Image generation using text

Abstract

The invention discloses image generation using text. Apparatuses, systems, and techniques for executing neural networks to generate images are disclosed. In at least one embodiment, for example, one or more neural networks generate one or more portions of one or more images and one or more subtitles. In at least one embodiment, as another example, one or more sensors are provided. A processor uses one or more neural networks to generate one or more images from text based at least in part on one or more first images of text not having content indicative of the one or more first images and one or more second images of text having content indicative of the one or more second images .

Description

Technical Field

[0001] At least one embodiment relates to a system that includes one or more neural networks for generating one or more captions (e.g., indicative information) for one or more portions of one or more images. For example, at least one embodiment relates to a processor or computing device that uses one or more neural networks to generate one or more images from text based at least in part on one or more first images (which do not have text indicating the content of the one or more first images) and one or more second images (which have text indicating the content of the one or more second images). As another example, one or more portions of one or more images are generated using one or more neural networks that are used to encode an image, generate one or more captions, and / or organize one or more captions based at least in part on one or more loss operations. Background Art

[0002] A neural network can generate an image from one or more masked pixels. The neural network can reason about what a pixel is by comparing the inferred pixel to surrounding pixels to reconstruct the image. The resulting image may be inaccurate relative to the original image. For example, a neural network performing optical character recognition (OCR) may be poor, which results in inaccurate image reconstruction, e.g., due to a lack of training data labeled for each task that the neural network must perform. Additionally, the amount of time and / or computational resources can be improved when using and / or training a neural network. Brief Description of the Drawings

[0003] Figure 1 is a block diagram showing a system including one or more neural network training systems according to at least one embodiment;

[0004] Figure 2 shows an exemplary system using one or more neural network training systems according to at least one embodiment;

[0005] Figure 3 shows an example of a system including an encoder system, a contrast loss system, and a caption generation system according to at least one embodiment;

[0006] Figure 4 is a block diagram showing a system using contrast loss according to at least one embodiment;

[0007] Figure 5 is a block diagram showing a processor and modules according to at least one embodiment;

[0008] Figure 6is a block diagram showing a driver and / or runtime including one or more libraries for providing one or more APIs according to at least one embodiment;

[0009] Figure 7A shows logic according to at least one embodiment;

[0010] Figure 7B shows logic according to at least one embodiment;

[0011] Figure 8 shows the training and deployment of a neural network according to at least one embodiment;

[0012] Figure 9 shows an example data center system according to at least one embodiment;

[0013] Figure 10A shows an example of an autonomous vehicle according to at least one embodiment;

[0014] Figure 10B shows according to at least one embodiment Figure 10A an example of the camera positions and fields of view of an autonomous vehicle;

[0015] Figure 10C is a block diagram showing according to at least one embodiment Figure 10A an example system architecture of an autonomous vehicle;

[0016] Figure 10D is a diagram showing according to at least one embodiment for communication between one or more cloud-based servers and Figure 10A an autonomous vehicle;

[0017] Figure 11 is a block diagram showing a computer system according to at least one embodiment;

[0018] Figure 12 is a block diagram showing a computer system according to at least one embodiment;

[0019] Figure 13 shows a computer system according to at least one embodiment;

[0020] Figure 14 shows a computer system according to at least one embodiment;

[0021] Figure 15A shows a computer system according to at least one embodiment;

[0022] Figure 15B shows a computer system according to at least one embodiment;

[0023] Figure 15CShows a computer system according to at least one embodiment;

[0024] Figure 15D Shows a computer system according to at least one embodiment;

[0025] Figure 15E And Figure 15F Shows a shared programming model according to at least one embodiment;

[0026] Figure 16 Shows an exemplary integrated circuit and associated graphics processor according to at least one embodiment;

[0027] Figures 17A - 17B Shows an exemplary integrated circuit and associated graphics processor according to at least one embodiment;

[0028] Figures 18A - 18B Shows additional exemplary graphics processor logic according to at least one embodiment;

[0029] Figure 19 Shows a computer system according to at least one embodiment;

[0030] Figure 20A Shows a parallel processor according to at least one embodiment;

[0031] Figure 20B Shows a partitioning unit according to at least one embodiment;

[0032] Figure 20C Shows a processing cluster according to at least one embodiment;

[0033] Figure 20D Shows a graphics multiprocessor according to at least one embodiment;

[0034] Figure 21 Shows a multi-graphics processing unit (GPU) system according to at least one embodiment;

[0035] Figure 22 Shows a graphics processor according to at least one embodiment;

[0036] Figure 23 Is a block diagram showing a processor microarchitecture for a processor according to at least one embodiment;

[0037] Figure 24 Shows a deep learning application processor according to at least one embodiment;

[0038] Figure 25 Is a block diagram showing an example neuromorphic processor according to at least one embodiment;

[0039] Figure 26 Shows at least a portion of a graphics processor in accordance with one or more embodiments;

[0040] Figure 27 Shows at least a portion of a graphics processor in accordance with one or more embodiments;

[0041] Figure 28 Shows at least a portion of a graphics processor in accordance with one or more embodiments;

[0042] Figure 29 Is a block diagram of a graphics processing engine of a graphics processor in accordance with at least one embodiment;

[0043] Figure 30 Is a block diagram of at least a portion of a graphics processor core in accordance with at least one embodiment;

[0044] Figures 31A - 31B Shows thread execution logic in accordance with at least one embodiment, which includes an array of processing elements of a graphics processor core.

[0045] Figure 32 Shows a parallel processing unit (“PPU”) in accordance with at least one embodiment;

[0046] Figure 33 Shows a general processing cluster (“GPC”) in accordance with at least one embodiment;

[0047] Figure 34 Shows a memory partition unit of a parallel processing unit (“PPU”) in accordance with at least one embodiment;

[0048] Figure 35 Shows a streaming multiprocessor in accordance with at least one embodiment;

[0049] Figure 36 Is an example data flow diagram of an advanced computing pipeline in accordance with at least one embodiment;

[0050] Figure 37 Is a system diagram of an example system for training, adapting, instantiating, and deploying a machine learning model in an advanced computing pipeline in accordance with at least one embodiment;

[0051] Figure 38 Includes an example illustration of an advanced computing pipeline for processing imaging data in accordance with at least one embodiment;

[0052] Figure 39A Includes an example data flow diagram of a virtual instrument supporting an ultrasound device in accordance with at least one embodiment;

[0053] Figure 39BExample data flow diagrams of virtual instruments supporting a CT scanner according to at least one embodiment;

[0054] Figure 40A Data flow diagrams illustrating a process for training a machine learning model according to at least one embodiment;

[0055] Figure 40B is an example illustration of a client - server architecture for enhancing an annotation tool using a pre - trained annotation model according to at least one embodiment; and

[0056] Figure 41 Illustrates components of a system for accessing a large language model according to at least one embodiment. Detailed Description

[0057] In the foregoing and following descriptions, various techniques are described. For purposes of explanation, specific configurations and details are set forth in order to provide a thorough understanding of the possible ways of implementing the techniques. However, it will also be apparent that the techniques described below can be practiced in different configurations without specific details. Additionally, well - known features may be omitted or simplified to avoid obscuring the described techniques.

[0058] Figure 1 is a block diagram showing a system 100 including one or more neural network training systems 112A - C according to at least one embodiment.

[0059] In at least one embodiment, the system 100 develops an image - based foundation neural network 110, which includes processing high - density information, such as text with more structure and larger datasets to facilitate training. In at least one embodiment, the system 100 includes one or more neural networks 110 that can generate highly informative representations for images in numerous tasks (e.g., semantic reasoning and / or text recognition) without fine - tuning. In at least one embodiment, the foundation neural network 110 is a model for performing various tasks within its domain. In at least one embodiment, as an example, a text model should be able to complete most text - based tasks. However, text - based foundation models can be large and difficult to train and have not been developed for operating on images.

[0060] In at least one embodiment, the system 100 includes a neural network 110, such as a vision foundation model. In at least one embodiment, the neural network 110 is trained by combining a first training system 112A, a second training system 112B, and a third training system 112C. In at least one embodiment, the first training system 112A is a pixel - masking encoder system (e.g., encoder system 212A, see Figure 2)。In at least one embodiment, the second training system 112B is a contrastive loss system (e.g., contrastive loss system 212B, see Figure 2 )。In at least one embodiment, the third training system 112C is a caption generation system (e.g., caption generation system 212C, see Figure 2 )。

[0061] In at least one embodiment, a pixel masking encoder system (e.g., the first training system 112A) masks a portion of the input image and provides it to a neural network that predicts the values of one or more masked pixels. In at least one embodiment, one or more predicted pixels are compared with the original ground truth image to determine the accuracy of the reconstructed (e.g., generated) one or more image portions.

[0062] In at least one embodiment, a contrastive loss system (e.g., the second training system 112B) compares the input image and associated labels (if any) with other images in the batch, placing semantically similar images close to each other (e.g., similar concepts are placed "near" each other). In at least one embodiment, for example, information indicating that one or more objects are apples is conceptually closer to oranges than to airplanes.

[0063] In at least one embodiment, a caption generation system (e.g., the third training system 112C) extracts information from the masked image and generates a caption for it before reconstructing one or more missing pixels. In at least one embodiment, the caption is then compared to the caption provided by the original image for similarity. In at least one embodiment, one or more captions indicate the content (e.g., information) of one or more images.

[0064] In at least one embodiment, these three systems 112A-C operate in parallel on the same input image and then combine one or more system results 114. In at least one embodiment, the neural network 110 includes the ability to recognize an image, a theme within the image, and reason about a description of the image. In at least one embodiment, the neural network 110 of the training system 112 uses both labeled training images and unlabeled training images. In at least one embodiment, the labeled training images include captions for one or more images and / or image portions.

[0065] In at least one embodiment, system 100 incorporates one or more training systems 112 to run in parallel on the same input image, giving it the ability to more comprehensively reason about the received image dataset and to utilize a larger training dataset, since images with and without captions can be used to discern semantically similar images. In at least one embodiment, by way of example, the processor uses one or more neural networks to generate one or more images from captions based at least in part on one or more images without captions (e.g., text indicating content) and one or more images with one or more embedded captions (e.g., text indicating content), such as by using one or more contrastive loss operations to compare the ground truth information with the generated information (shown further in Figure 4 ), and / or otherwise perform the operations described herein. In at least one embodiment, the processor generates an image that does not contain text indicating content (e.g., an embedded caption), such as a high-resolution image, based at least in part on being trained using more than one contrastive loss operation and / or otherwise performing the one or more operations.

[0066] In at least one embodiment, by way of example, system 100 uses processor 106 (e.g., Figure 5 processor 502) to generate an image or a portion thereof using neural network 110 and one or more training systems 112. In at least one embodiment, neural network 110 is a base neural network. In at least one embodiment, neural network 110 is a vision model. In at least one embodiment, one or more training systems 112 are transformer models for training neural network 110.

[0067] In at least one embodiment, system 100 includes a collection of one or more hardware and / or software computing resources having instructions that, when executed, perform one or more communication processes, such as the communication processes described herein. In at least one embodiment, system 100 is a software program executed on computer hardware, an application program executed on computer hardware, and / or variants thereof. In at least one embodiment, one or more processes of system 100 are performed by any suitable processing system or unit (e.g., a graphics processing unit (GPU), a general-purpose GPU (GPGPU), a parallel processing unit (PPU), a central processing unit (CPU), a data processing unit (DPU) (described below)) in any suitable manner, including sequentially, in parallel, and / or variants thereof. In at least one embodiment, system 100 uses a machine learning training framework (e.g., PYTORCH, TENSORFLOW, BOOST, CAFFE, MICROSOFT COGNITIVETOOLKIT / CNTK, MXNET, CHAINER, KERAS, DEEPLEARNING4J) and / or other training frameworks to implement and perform the operations described herein to generate one or more images from text at least in part based on one or more first images that do not have text indicating the content of the one or more first images and one or more second images that have text indicating the content of the one or more second images, and / or to otherwise perform the operations described herein. In at least one embodiment, by way of example, training a neural network model includes using a server (e.g., an NVIDIA DGX server) that further includes at least a GPU (e.g., an AMD MI200, VEGAL10, VEGO20, and ARCTURUS), an optimizer (e.g., an ADAM OPTIMIZER), and / or a discriminator architecture (e.g., a discriminator architecture from face-vid2vid for training using GAN loss).

[0068] In at least one embodiment, system 100 performs one or more processes. In at least one embodiment, part or all of the process (or any other process described herein, or variations and / or combinations thereof) is performed under the control of one or more computer systems configured with computer-executable instructions and is implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) to be executed jointly by hardware, software, or a combination thereof on one or more processors. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of a computer program that includes a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some of the computer-readable instructions for performing the process are not stored using only transient signals (e.g., propagated transient electrical or electromagnetic transmissions). In at least one embodiment, the non-transitory computer-readable medium does not necessarily include non-transitory data storage circuitry (e.g., buffers, caches, and queues) within a transceiver of a transient signal. In at least one embodiment, the process is performed at least in part on a computer system (e.g., the computer system described elsewhere in the present disclosure). In at least one embodiment, logic (e.g., hardware, software, or a combination of hardware and software) performs the process. In at least one embodiment, for example, a set of instructions is stored on a machine-readable medium that, if executed by one or more processors, causes the one or more processors to generate one or more images from text and / or otherwise perform the operations described herein using one or more neural networks based at least in part on one or more first images that do not have text indicating the content of the one or more first images and one or more second images that have text indicating the content of the one or more second images.

[0069] In at least one embodiment, system 100 includes one or more modules (e.g., as Figure 6modules 604-610) such that system 100 uses one or more neural networks to generate one or more images from text and / or otherwise perform the operations described herein based at least in part on one or more first images that do not have text indicating the content of the one or more first images and one or more second images that have text indicating the content of the one or more second images. In at least one embodiment, a module includes any combination of any type of logic (e.g., software, hardware, firmware) and / or circuitry configured to perform the functions. In at least one embodiment, a module includes one or more circuits that form part of a larger system (e.g., an integrated circuit (IC), a system on a chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), a data processing unit (DPU), etc.). In at least one embodiment, a controller includes any combination of any type of logic (e.g., software, hardware, firmware) and / or circuitry configured to perform the functions. In at least one embodiment, software includes a software package, code, a programming language, a driver, instructions, an instruction set, or some combination thereof. In at least one embodiment, hardware includes hardwired circuitry, programmable circuitry, state machine circuitry, fixed function circuitry, execution unit circuitry, firmware with stored instructions executed by programmable circuitry, or some combination thereof.

[0070] In at least one embodiment, system 100 includes a logic unit, such as a logic unit including firmware logic, hardware logic, or some combination thereof, configured to provide any of the functions further described herein. In at least one embodiment, the logic unit includes circuitry that forms part of a larger system (e.g., an IC, an SoC, a CPU, a GPU, a DPU). In at least one embodiment, the logic unit includes logic circuitry for implementing firmware and / or hardware for generating one or more images from text using one or more neural networks based at least in part on one or more first images that do not have text indicating the content of the one or more first images and one or more second images that have text indicating the content of the one or more second images, and / or otherwise performing the operations described herein.

[0071] In at least one embodiment, system 100 includes an engine that includes modules and / or logic units as further described herein. In at least one embodiment, a component includes modules and / or logic units as further described herein. In at least one embodiment, the engine includes software logic, firmware logic, hardware logic, or some combination thereof configured to provide any of the functions further described herein. In at least one embodiment, a component includes software logic, firmware logic, hardware logic, or some combination thereof configured to provide any of the functions further described herein. In at least one embodiment, operations performed by hardware and / or firmware may alternatively be implemented via software modules that may be embodied as software packages, code, and / or instruction sets. In at least one embodiment, a logic unit may also utilize a portion of software to implement its functionality.

[0072] In at least one embodiment, system 100 receives and / or uses input 102. In at least one embodiment, input 102 of system 100 includes images, captions, training data 104 (e.g., images with one or more captions, ground truth data, masked images), ground truth images, videos, video frames, sequence images, audio, text, symbols, previous inputs, neural networks, information represented as data, and / or other inputs described herein. In at least one embodiment, one or more inputs 102 are communicated to a processor via a signal. In at least one embodiment, one or more inputs 102 include information represented as one or more data packets. In at least one embodiment, input 102 is received by a hardware and / or software process, such as those associated with Figures 7A to 41 those described.

[0073] In at least one embodiment, system 100 includes one or more processors 106 (e.g., Figure 6of the processor 602). In at least one embodiment, the processor 106 executes one or more neural networks 110, for example to cause the processing of the input 102. In at least one embodiment, execution (e.g., executing a neural network, software program, API, etc.) is to cause, generate, transform, invoke, and / or initiate a software process to achieve a result. In at least one embodiment, processing (e.g., visual processing of an image) is the analysis and / or manipulation performed on an input, for example to improve quality and / or perform one or more operations on the image. In at least one embodiment, for example, processing includes masking an image and / or generating an image from the masked image. In at least one embodiment, an image can include a digital image, a photograph, a training image, a frame of a video, a frame of a video game, and / or a set of frames of a video or a video game. In at least one embodiment, an image is an assembly (compilation) of pixels, features, data, tensors, and / or other representational forms of the image. In at least one embodiment, a pixel is a point on an image that presents a shade, opacity, or color. In at least one embodiment, a pixel is represented in data form (e.g., grayscale, RGB, RGBA, or other variants). In at least one embodiment, image processing is performed by a processor composed of circuitry to analyze or manipulate the image. In at least one embodiment, the processor 106 performs processing at least in part by inferring its RGB value based on the surrounding pixels of the masked pixels. In at least one embodiment, the processing 108 is performed by the neural network 110. In at least one embodiment, examples of the processing 108 (e.g., the processing to be performed by one or more task neural networks (e.g., the first task neural network 110A)) include decoding, masking, encoding, text identification, object identification, text and / or object classification, depth identification, scaling, de-distortion, cropping, visualization, recognition, sharpening, restoration, pattern recognition, encoding, and / or retrieval of an image. In at least one embodiment, identifying one or more objects is using information to indicate one or more pixels. In at least one embodiment, for example, the information indicating one or more pixels as an object can be a bounding box, the coordinates of one or more pixels, features, and / or an object map, a cluster of pixels identified as masked, text, and / or symbols. In at least one embodiment, identifying an object includes identifying text, symbols, letters, and / or image segments. In at least one embodiment, as an example, one or more parts of a logo are identified as an object, where one or more objects include masked text, and one or more neural networks generate a part of the image associated with the masked text part. In at least one embodiment, as another example, the text of a logo is identified as an object, and the neural network generates masked and / or unmasked text of one or more image parts.

[0074] In at least one embodiment, neural network 110 generates the one or more portions based at least in part on one or more tasks of identifying one or more objects in one or more portions of one or more images, and / or otherwise performs the operations described herein. In at least one embodiment, neural network 110 is further shown in Figures 8 to 41 In at least one embodiment, system 100 includes neural network 110, such as one or more task neural networks (e.g., first task neural network 110A and / or second task neural network 110B) and / or a base neural network (e.g., Figure 2 and / or Figure 3 base neural networks 210 and / or 310). In at least one embodiment, one or more neural networks 110 are transformer neural networks, such as transformer neural networks trained for a particular task (e.g., processing, encoding, decoding, identifying, and / or masking). In at least one embodiment, training system 112 (e.g., an expert system) includes one or more task neural networks (e.g., task-specific neural networks). In at least one embodiment, processor 106 updates one or more weights of neural network 110 based at least in part on one or more training systems 112. In at least one embodiment, for example, processor 106 uses neural network 110 to generate output 116 based at least in part on input 102, wherein the output of one or more tasks is compared to the output of training systems 112A-C, and the weights of neural network 110 are adjusted towards the output of the task neural networks. In at least one embodiment, by way of example, before adjusting the weights of neural network 110, one or more outputs of training systems 112A-C are combined, such as by combining them into a data set and / or using each training system 112A-C to calculate the weight adjustment.

[0075] In at least one embodiment, system 100 generates output 116, which may include caption embeddings (e.g., text predictions), visual encoding embeddings, generated image 114, neural network with adjusted weights, and / or captions. In at least one embodiment, output 112 includes images, caption text, symbols, previous inputs, neural networks, information represented as data, and / or other outputs described herein. In at least one embodiment, output 112 is communicated to the processor via a signal. In at least one embodiment, output 112 includes information represented as one or more data packets. In at least one embodiment, output 112 is received by a hardware and / or software process, such as those described in connection with any one of Figures 7A to 41 above.

[0076] In at least one embodiment, system 100 that includes one or more processors uses one or more neural networks to generate one or more images from text and / or otherwise perform the operations described herein, at least in part based on one or more first images that do not have text indicative of the content of the one or more first images and one or more second images that have text indicative of the content of the one or more second images. In at least one embodiment, system 100 is Figures 1 to 6 the system shown in Figures 1 to 6 the system shown in and / or otherwise includes Figures 1 to 6 the system shown in, for using one or more neural networks to generate one or more images from text and / or otherwise perform the operations described herein, at least in part based on one or more first images that do not have text indicative of the content of the one or more first images and one or more second images that have text indicative of the content of the one or more second images. In at least one embodiment, system 100 performs Figures 1 to 6 one or more of the processes shown in, such as using one or more neural networks to generate one or more images from text, at least in part based on one or more first images that do not have text indicative of the content of the one or more first images and one or more second images that have text indicative of the content of the one or more second images, and / or otherwise perform the operations described herein. In at least one embodiment, system 100 includes Figures 7A to 41 one or more of the hardware shown in, for using one or more neural networks to generate one or more images from text, at least in part based on one or more first images that do not have text indicative of the content of the one or more first images and one or more second images that have text indicative of the content of the one or more second images, and / or otherwise perform the operations described herein.

[0077] Figure 2 FIG. shows an exemplary system 200 for training system 212 using one or more neural networks. In at least one embodiment, system 200 is an example of system 100. In at least one embodiment, system 200 includes a processor 206, a neural network 210, and one or more training systems 212 (e.g., an encoder system 212A, a contrast loss system 212B, and a caption generation system 212C).

[0078] In at least one embodiment, neural network 210 is a base neural network, such as a vision base neural network. In at least one embodiment, the base neural network uses one or more training systems 212 that include one or more task neural networks. In at least one embodiment, the task neural network is a task-specific neural network, a task expert, and / or an expert neural network. In at least one embodiment, the task neural network is used in an expert system (e.g., a differentiated specialized expert system), such as for performing processing functions. In at least one embodiment, the processing includes performing one or more operations to achieve a desired result, such as performing a task.

[0079] In at least one embodiment, system 100 includes system 200, such as for training neural network 210 using one or more training systems 212. In at least one embodiment, processor 206 trains base neural network 210 at least in part based on input 202 (e.g., input 102, see Figure 1 )(e.g., a ground truth image and / or caption). In at least one embodiment, processor 206 uses encoder system 212A, contrast loss system 212B, caption generation system 212C, or a combination thereof to train base neural network 210 to generate image parts and / or caption embeddings.

[0080] In at least one embodiment, the first training system 212 includes encoder system 212A. In at least one embodiment, encoder system 212A receives training data 204 as input 202. In at least one embodiment, pixel masking encoder system 212A (e.g., first training system 112A, see Figure 1 ) masks a portion of the input image and provides it to a neural network that predicts the values of one or more masked pixels. In at least one embodiment, one or more predicted pixels are compared to the original ground truth image to determine the accuracy of the reconstructed (e.g., generated) one or more image parts.

[0081] In at least one embodiment, the second training system 212 includes contrast loss system 212B. In at least one embodiment, contrast loss system 212B receives training data 204 as input 202. In at least one embodiment, contrast loss system 212B (e.g., second training system 112B, see Figure 1)Compare the input 202 image and associated labels (if any) with other images in the batch and place semantically similar images close to each other (e.g., similar concepts are placed "close" to each other). In at least one embodiment, for example, information indicating that one or more objects are apples will be conceptually closer to oranges than to airplanes.

[0082] In at least one embodiment, the third training system 212 includes a caption generation system 212C. In at least one embodiment, the caption generation system 212C receives the training data 204 as the input 202. In at least one embodiment, the caption generation system 212C (e.g., the third training system 112C, see Figure 1 )Extract information from the masked image and generate captions for it before reconstructing one or more missing pixels. In at least one embodiment, the captions are then compared for similarity with the captions provided by the original image. In at least one embodiment, the system 200 combines the system results 214 of the training system 212, compiles and combines (e.g., aggregates) them to generate the output 216. In at least one embodiment, the output 216 of the trained neural network (e.g., the output 116, see Figure 1 )Includes a neural network capable of reconstructing images, identifying themes, and / or descriptors 218.

[0083] In at least one embodiment, the processor 206 uses a neural network 210 that is at least partially based on the training system 212, and the training system 212 executes instructions to perform one or more tasks (e.g., the first task, the second task, and the third task corresponding to the encoder system 212A, the contrast loss system 212B, and the caption generation system 212C).

[0084] In at least one embodiment, one or more training systems 212 include one or more neural networks that are designed as web-scale knowledge bases, such as for reliably performing many downstream tasks. In at least one embodiment, for example, such a model can classify the main theme of a given image, find each person depicted in the image, and assign classifications to people and / or objects (e.g., classify a person as happy). In at least one embodiment, the training system 212 is trained on a wide range of training examples, such as to become a reasonably competent generalist model. In at least one embodiment, the input 402 is the caption of a document image, such as a "white paper", a paper title, a partial or full transcription of an image, and / or an uncaptioned image.

[0085] In at least one embodiment, the contrastive loss system 212B computes a loss correction (e.g., the generated caption loss) as a self-supervised task. In at least one embodiment, the processor 206 trains the neural network 210 (e.g., the base neural network) at least in part based on one or more training systems 212 that include one or more neural networks, such as to learn the semantics of captions while connecting the results of the visual encoder and the caption generator. In at least one embodiment, one or more training systems 212 include a text decoder, such as a transformer or sequence-to-sequence of a tension model. In at least one embodiment, the processor 506 executes one or more neural networks using features and / or vector spaces.

[0086] In at least one embodiment, a system 200 that includes one or more processors uses one or more neural networks to generate one or more images from text and / or otherwise perform the operations described herein, at least in part based on one or more first images that do not have text indicating the content of the one or more first images and one or more second images that have text indicating the content of the one or more second images. In at least one embodiment, the system 200 is Figures 1 to 6 the system shown in Figures 1 to 6 the system shown in and / or otherwise includes Figures 1 to 6 the system shown in, for using one or more neural networks to generate one or more images from text and / or otherwise perform the operations described herein, at least in part based on one or more first images that do not have text indicating the content of the one or more first images and one or more second images that have text indicating the content of the one or more second images. In at least one embodiment, the system 200 performs Figures 1 to 6 one or more of the processes shown in, such as using one or more neural networks to generate one or more images from text and / or otherwise perform the operations described herein, at least in part based on one or more first images that do not have text indicating the content of the one or more first images and one or more second images that have text indicating the content of the one or more second images. In at least one embodiment, the system 200 includes Figures 7A to 41 one or more of the hardware shown in, for using one or more neural networks to generate one or more images from text and / or otherwise perform the operations described herein, at least in part based on one or more first images that do not have text indicating the content of the one or more first images and one or more second images that have text indicating the content of the one or more second images.

[0087] Figure 3Shows an example of a system 300 according to at least one embodiment, the system 300 including an encoder system 306, a contrastive loss system 310, and a caption generation system 314. In at least one embodiment, the encoder system 306, the contrastive loss system 310, the caption generation system 314, or a combination thereof is a transformer neural network. In at least one embodiment, the encoder system 306, the contrastive loss system 310, the caption generation system 314, or a combination thereof includes a processor for executing the neural network (e.g., processors 106, 206, and / or 506). In at least one embodiment, by way of example, the pixel masking encoder system 306 executes the neural network in parallel with the contrastive loss system 310 and / or the caption generation system 314.

[0088] In at least one embodiment, some or all of processes 308, 312, 316, or a combination thereof (or any other processes described herein, or variations and / or combinations thereof) are executed under the control of one or more computer systems configured with computer-executable instructions and are implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) executed jointly on one or more processors by hardware, software, or a combination thereof. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of a computer program that includes a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some of the computer-readable instructions that can be used to execute processes 308, 312, 316, or a combination thereof are not stored using only transient signals (e.g., propagated transient electrical or electromagnetic transmissions). In at least one embodiment, the non-transitory computer-readable medium does not necessarily include non-transitory data storage circuits (e.g., buffers, caches, and queues) within a transceiver of a transient signal. In at least one embodiment, processes 308, 312, 316, or a combination thereof are executed at least in part on a computer system (e.g., the computer systems described elsewhere in the present disclosure). In at least one embodiment, logic (e.g., hardware, software, or a combination of hardware and software) executes processes 308, 312, 316, or a combination thereof.

[0089] In at least one embodiment, the pixel masking encoder system 306 includes a processor for performing process 308 using a neural network. In at least one embodiment, process 308 includes one or more steps: masking a portion of an image 308A, providing the masked portion to a neural network 308B, and / or evaluating the reconstruction of an image (e.g., one or more portions of an image) 308C. In at least one embodiment, the contrastive loss system 310 includes a processor for performing process 312 using a neural network. In at least one embodiment, process 312 includes one or more steps: determining whether one or more images 312A (e.g., one or more portions of image 304) have captions, semantically organizing one or more batches of captions 312B, and / or determining the placement of the original image relative to the captions 312C. In at least one embodiment, the caption generation system 314 includes a processor for performing process 316 using a neural network. In at least one embodiment, process 316 includes one or more steps: generating captions for an image 316A and / or calculating the similarity of the generated captions to the original captions 316B. In at least one embodiment, system 300 performs processes 308, 312, and 316 in parallel. In at least one embodiment, the outputs 320 of one or more of processes 308, 312, and / or 316 can be combined to obtain a combined system result 322, such as calculating an adjustment to the weights of one or more neural networks 210 (see Figure 2 ). In at least one embodiment, the pixel masking encoder system 306 is otherwise 212A and / or 112A. In at least one embodiment, the pixel masking encoder system 306 is system 212A and / or 112A, included in system 212A and / or 112A, or includes system 212A and / or 112A. In at least one embodiment, the contrastive loss system 310 is system 212B and / or 112B, included in system 212B and / or 112B, or includes system 212B and / or 112B. In at least one embodiment, the caption generation system 314 is system 212C and / or 112C, included in system 212C and / or 112C, or includes system 212C and / or 112C. In at least one embodiment, systems 306, 310, and / or 314 generate output 320 (e.g., output 116, see Figure 1 ).

[0090] In at least one embodiment, the contrast loss system 310 includes one or more processors for calculating a contrast loss of text (e.g., one or more captions). In at least one embodiment, the pixel masking encoder system 306 includes one or more processors for masking visual information (e.g., randomization of one or more pixel values). In at least one embodiment, the output 320 is generated using the neural networks of systems 306, 310, and / or 314, the output including one or more feature maps of a vector space, e.g., for performing a visual encoding task.

[0091] In at least one embodiment, the system 300 uses the image 304 to perform high-resolution training of a neural network. In at least one embodiment, the system 300 generates a metric associated with the performance of the neural network during training, e.g., for an image classification and / or optical character recognition (OCR) task. In at least one embodiment, the system 300 uses a processor to increase the resolution and / or masking of the image 304 for one or more inputs 302 (e.g., training data) of the neural network when it reaches a threshold of one or more training metrics (e.g., accuracy, percentage improvement, OCR ability, parity at a lower resolution, ability at a masking percentage, and / or consistency). In at least one embodiment, the pixel masking encoder system 306 randomly masks one or more portions of the image 304, e.g., by randomizing the pixel values of a percentage (e.g., 30%, 50%, 70%, or other percentage / ratio) of the image 304. In at least one embodiment, the system 300 does not require (but may include) adjusting one or more weights of a visual encoder for instance segmentation. In at least one embodiment, the system 300 performs label reconstruction at least in part based on the neural network being gradually scaled using different resolutions in combination with different percentages of image masking, e.g., for performing self-supervised and / or semi-supervised training, where the dataset may or may not be fully annotated.

[0092] In at least one embodiment, the system 300 including one or more processors uses one or more neural networks to generate one or more images from text and / or otherwise perform the operations described herein based at least in part on one or more first images that do not have text indicating the content of the one or more first images and one or more second images that have text indicating the content of the one or more second images. In at least one embodiment, the system 300 is Figures 1 to 6 the system shown in Figures 1 to 6 the system shown in and / or otherwise includes Figures 1 to 6The system shown in is for generating one or more images from text and / or otherwise performing the operations described herein using one or more neural networks based at least in part on one or more first images that do not have text indicating the content of the one or more first images and one or more second images that have text indicating the content of the one or more second images. In at least one embodiment, system 300 performs Figures 1 to 6 one or more of the processes shown in , such as generating one or more images from text using one or more neural networks based at least in part on one or more first images that do not have text indicating the content of the one or more first images and one or more second images that have text indicating the content of the one or more second images, and / or otherwise performing the operations described herein. In at least one embodiment, system 300 includes Figures 7A to 41 one or more of the hardware shown in , such as for generating one or more images from text using one or more neural networks based at least in part on one or more first images that do not have text indicating the content of the one or more first images and one or more second images that have text indicating the content of the one or more second images, and / or otherwise performing the operations described herein.

[0093] Figure 4 A block diagram of system 400 using contrastive loss is shown in accordance with at least one embodiment. In at least one embodiment, for example, a processor may execute process 400 to train a neural network without one or more fully annotated images (e.g., image portions). In at least one embodiment, system 400 using one or more processes (e.g., processes 308, 312, and / or 316) invokes processes, such as by using one or more processors (e.g., processor 106, see Figure 1 ). In at least one embodiment, system 400 includes using one or more steps to receive images, using a caption generator to generate captions 408, using contrastive loss to sort captions across one or more batches, and / or combinations thereof. In at least one embodiment, system 400 includes a visual encoder 406, a visual decoder 408, a text decoder 314, a joint image and text decoder 416, or combinations thereof.

[0094] In at least one embodiment, system 400 receives a ground truth image 402 as input. In at least one embodiment, a masked image 404 is received as input, or one or more operations perform masking on the ground truth image 402 (e.g., randomization of information, e.g., according to a distribution) to generate the masked image 404. In at least one embodiment, system 400 includes a pixel masking encoder system 306, a contrastive loss system 310, and a caption generation system 314 (see Figure 3 ), such as for performing one or more loss calculations (e.g., visual reconstruction loss 412, generative caption loss 418, contrastive caption loss 422, and / or combinations thereof). In at least one embodiment, system 400 using one or more processors performs the visual reconstruction loss 412 by comparing the generated image 410 (e.g., reconstructed to be the same or similar) with the ground truth image 402. In at least one embodiment, system 400 using one or more processors performs the contrastive caption loss 422 at least in part based on maximizing the likelihood of an image and its corresponding caption embedding 420 and minimizing the images and other captions in the batch. In at least one embodiment, the contrastive caption loss 422 is performed using one or more caption embeddings 420 of the ground truth image 402 and the generated embeddings (e.g., generated by the visual encoder 406) of the masked image 404. In at least one embodiment, system 400 using one or more processors performs the generative caption loss 418 at least in part based on comparing the generated caption from the visual encoder 406 with the ground truth caption embedding 420. In at least one embodiment, system 400 performs hybrid semi-supervised and generative objectives to build one or more visual foundation models. In at least one embodiment, system 400 uses one or more neural networks to generate an image 410, e.g., for training one or more neural networks. In at least one embodiment, a processor using a neural network is otherwise used to execute, generate, train, implement, call instructions, and / or implement the neural network. In at least one embodiment, for example, the generated image 410 is received as input to one or more neural networks for training.

[0095] In at least one embodiment, system 400 including one or more processors uses one or more neural networks to generate one or more images from text at least in part based on one or more first images that do not have text indicating the content of the one or more first images and one or more second images that have text indicating the content of the one or more second images, and / or otherwise perform the operations described herein. In at least one embodiment, system 400 is Figures 1 to 6 the system shown in Figures 1 to 6 the system shown in, and / or otherwise includes Figures 1 to 6The system shown in is for generating one or more images from text using one or more neural networks based at least in part on one or more first images that do not have text indicating the content of the one or more first images and one or more second images that have text indicating the content of the one or more second images, and / or for otherwise performing the operations described herein. In at least one embodiment, system 400 performs Figures 1 to 6 one or more of the processes shown in , such as generating one or more images from text using one or more neural networks based at least in part on one or more first images that do not have text indicating the content of the one or more first images and one or more second images that have text indicating the content of the one or more second images, and / or for otherwise performing the operations described herein. In at least one embodiment, system 400 includes Figures 7A to 41 one or more of the hardware shown in , such as for generating one or more images from text using one or more neural networks based at least in part on one or more first images that do not have text indicating the content of the one or more first images and one or more second images that have text indicating the content of the one or more second images, and / or for otherwise performing the operations described herein.

[0096] Figure 5 is a block diagram showing a processor 502 and modules 504 - 512 according to at least one embodiment. In at least one embodiment, system 500 includes a processor 502 and modules 504 - 512. In at least one embodiment, processor 502 performs one or more processes (such as the processes described herein) to generate one or more images using one or more neural networks and / or for otherwise performing the operations described herein. In at least one embodiment, processor 502 performs neural network training and / or image generation processes (such as the processes described above in connection with Figures 1 to 6 the processes described).

[0097] In at least one embodiment, processor 502 includes one or more circuits for performing one or more of the operations described below. In at least one embodiment, processor 502 is any suitable processing unit and / or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variants thereof (including those further described herein). In at least one embodiment, processor 502 includes a neural network training module 504, a loss calculation module 506, a base module 508, and / or a task neural network module 510.

[0098] In at least one embodiment, the neural network training module 504, the encoder module 506, the contrastive loss module 508, the caption generator module 510, and / or the result merging module 512 include one or more circuits of the processor 502 and / or one or more other processors. In at least one embodiment, the training module 504, the encoder module 506, the contrastive loss module 508, the caption generator module 510, and / or the result merging module 512 are distributed among multiple processors that communicate via a bus, a network, by writing to shared memory, and / or any suitable communication process (such as the communication processes described herein).

[0099] In at least one embodiment, as used in any implementation described herein, unless the context clearly dictates otherwise or is clearly contrary, a module refers to any combination of software logic, firmware logic, hardware logic, and / or circuits configured to provide the functions described herein. In at least one embodiment, software is embodied as a software package, code, and / or instruction set or instructions, and "hardware" as used in any implementation described herein includes, for example, hardwired circuitry, programmable circuitry, state machine circuitry, fixed function circuitry, execution unit circuitry, and / or firmware storing instructions executed by programmable circuitry, either individually or in any combination. In at least one embodiment, modules are collectively or individually embodied as circuitry forming part of a larger system (such as an integrated circuit (IC), a system on a chip (SoC), etc.). In at least one embodiment, modules execute one or more processes in conjunction with any suitable processing unit and / or combination of processing units (such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variants thereof, including those further described herein).

[0100] In at least one embodiment, the neural network training module 504 is a module that, if executed, causes one or more processors 502 to train one or more neural networks to perform one or more processing tasks, such as generating images. In at least one embodiment, the neural network training module 504 causes one or more processors 502 to execute one or more processes, such as those described herein, by at least including instructions or otherwise encoding instructions that cause the one or more processors 502 to execute the one or more processes or are otherwise available for the one or more processors 502 to execute the one or more processes. For example, in at least one embodiment, the neural network training module 504 causes one or more processors 502 to perform training of a neural network to generate images, videos, and / or image sequences. In at least one embodiment, the neural network training module 504 obtains or is otherwise provided with one or more instructions and / or identifiers of one or more instructions, including Figure 1instructions in it. For example, in at least one embodiment, the neural network training module 504 trains a neural network (e.g., a base model or a vision model) to generate one or more images from text and / or otherwise perform the operations described herein based at least in part on one or more first images that do not have text indicating the content of the one or more first images and one or more second images that have text indicating the content of the one or more second images.

[0101] In at least one embodiment, the encoder module 506 is a module that causes one or more processors to generate and / or execute one or more software instructions (e.g., software instructions of an executable software program that includes executable code) to use a base (e.g., vision) neural network. For example, in at least one embodiment, the encoder module 506 causes one or more processors 502 to encode information into one or more data sets (e.g., a data set representing an image) using one or more neural networks and / or otherwise perform the operations described herein. In at least one embodiment, the encoder module 506 causes one or more processors 502 to execute an encoding neural network, such as the pixel masking and encoding neural network used by the neural network training module 504 (e.g., to train a neural network or to be trained by a neural network). In at least one embodiment, the encoder module 506 causes one or more processors 502 to execute one or more processes, such as the processes described herein, by at least including instructions or otherwise encoding instructions that cause the execution of the one or more processes or are otherwise available for the execution of the one or more processes. As an example, in at least one embodiment, software causes one or more processors 502 to use an encoding neural network, such as a transformer.

[0102] In at least one embodiment, the contrast loss module 508 is a module that causes one or more processors 502 to perform a loss calculation, such as a loss calculation between the results of a task neural network obtained from a ground truth image and a reconstructed image. As an example, in at least one embodiment, the loss calculation is performed by the contrast loss module 508, such as in combination with Figures 1 to 6As described. In at least one embodiment, the contrast loss module 508 causes one or more processors 502 to perform one or more processes, such as the processes described herein, by at least including instructions or otherwise encoding instructions that cause the execution of the one or more processes or are otherwise available for the execution of the one or more processes. In at least one embodiment, by way of example, the contrast loss module 508 causes one or more processors 502 to calculate a loss between one or more results based at least in part on a base neural network and a training system of one or more neural networks (such as the encoder neural network of the encoder module 506 and / or the caption generator neural network of the caption generator module 510). In at least one embodiment, the contrast loss module 508 is a module that causes one or more processors to generate and / or execute one or more software instructions (such as software instructions of an executable software program that includes executable code) to perform the loss calculation.

[0103] In at least one embodiment, the caption generator module 510 is a module that causes one or more processors 502 to generate captions, such as in training a neural network in conjunction with the neural network training module 504. For example, in at least one embodiment, the processor uses the caption generator module 510 to generate captions, as Figures 1 - 6 shown. In at least one embodiment, the caption generator module 510 causes one or more processors 502 to execute one or more instructions to perform one or more processes, such as the processes described herein, by at least executing instructions that cause the execution of the one or more processes or are otherwise available for the execution of the one or more processes. In at least one embodiment, the caption generator module 510 causes one or more processors 502 to execute one or more instructions of a software program, such as to assign captions by embedding information of one or more portions of an image. In at least one embodiment, the caption generator module 510 causes one or more processors 502 to execute one or more instructions to perform one or more processes, such as in conjunction with Figures 1 to 6 the processes described. In at least one embodiment, the caption generator module 510 causes one or more processors 502 to generate captions using one or more neural networks, such as by embedding information related to a portion of an image and then performing a contrast loss operation using the contrast loss module 508.

[0104] In at least one embodiment, the result merging module 512 is a module that causes one or more processors 502 to merge one or more results of one or more neural networks, such as the results of training a neural network in conjunction with the neural network training module 504. For example, in at least one embodiment, the processor uses the result merging module 512 to merge the results of one or more neural networks (as shown in Figures 1 to 6 ) to, for example, calculate an adjustment to one or more neural network weights from the merged results. In at least one embodiment, the result merging module 512 causes one or more processors 502 to execute one or more instructions to perform one or more processes by at least executing the instructions, such as the processes described herein, where the instructions cause the performance of the one or more processes or are otherwise available for performing the one or more processes. In at least one embodiment, the result merging module 512 causes one or more processors 502 to execute one or more instructions of a software program, such as to merge the results of one or more neural networks used in conjunction with the encoder module 506, the contrastive loss module 508, and the caption generator module 510. In at least one embodiment, the result merging module 512 causes one or more processors 502 to execute one or more instructions to perform one or more processes, such as those processes described in conjunction with Figures 1 to 6 . In at least one embodiment, the result merging module 512 causes one or more processors 502 to merge the results of one or more neural networks, such as by combining the results into a data set and performing an aggregation operation.

[0105] In at least one embodiment, a system 500 including one or more processors uses one or more neural networks to generate one or more images from text and / or otherwise perform the operations described herein, at least in part based on one or more first images that do not have text indicating the content of the one or more first images and one or more second images that have text indicating the content of the one or more second images. In at least one embodiment, the system 500 is the system shown in Figures 1 to 6 , includes the system shown in Figures 1 to 6 , and / or otherwise includes the system shown in Figures 1 to 6 for using one or more neural networks to generate one or more images from text and / or otherwise perform the operations described herein, at least in part based on one or more first images that do not have text indicating the content of the one or more first images and one or more second images that have text indicating the content of the one or more second images. In at least one embodiment, the system 500 performs Figures 1 to 6One or more processes as shown, e.g., to generate one or more images from text using one or more neural networks based at least in part on one or more first images that do not have text indicative of the content of the one or more first images and one or more second images that have text indicative of the content of the one or more second images, and / or to otherwise perform the operations described herein. In at least one embodiment, system 500 includes Figures 7A to 41 One or more hardware as shown, e.g., for generating one or more images from text using one or more neural networks based at least in part on one or more first images that do not have text indicative of the content of the one or more first images and one or more second images that have text indicative of the content of the one or more second images, and / or to otherwise perform the operations described herein.

[0106] Figure 6 FIG. 600 is a block diagram showing a driver and / or runtime including one or more libraries for providing one or more application programming interfaces (APIs) according to at least one embodiment. In at least one embodiment, software program 602 is a software module. In at least one embodiment, software program 602 includes one or more software modules. In at least one embodiment, the software modules are as Figure 6 Further described non-exclusively as such. In at least one embodiment, one or more APIs 610 are software instruction sets that, if executed, cause one or more processors (e.g., Figure 5 processor 502 of ) to perform one or more computing operations. In at least one embodiment, one or more APIs 610 are distributed or otherwise provided as part of one or more libraries 606, driver / runtime 604, and / or any other grouping of software and / or executable code further described herein. In at least one embodiment, one or more APIs 610 perform one or more computing operations in response to a call from software program 602. In at least one embodiment, software program 602 is a collection of software code, commands, instructions, or other sequences of text for instructing a computing device to perform one or more computing operations and / or to call one or more other instruction sets (e.g., API 610 or API function 612) to be executed. In at least one embodiment, the functions provided by one or more APIs 610 include software functions 612, such as software functions that can be used to accelerate one or more portions of software program 602 using one or more parallel processing units (PPUs) (e.g., graphics processing units (GPUs)).

[0107] In at least one embodiment, the API 610 is a hardware interface of one or more circuits for performing one or more computing operations. In at least one embodiment, one or more of the software APIs 610 described herein are implemented as one or more circuits for performing one or more techniques described below in conjunction with Figures 1 - 8 In at least one embodiment, one or more software programs 602 include instructions that, if executed, cause one or more hardware devices and / or circuits to perform one or more techniques described in conjunction with Figures 1 - 6 further described.

[0108] In at least one embodiment, the software program 602 (e.g., a user-implemented software program) utilizes one or more application programming interfaces (APIs) 610 to perform various computing operations, such as memory reservation, matrix multiplication, arithmetic operations, or any computing operations performed by a parallel processing unit (PPU) (e.g., a graphics processing unit (GPU)), as further described herein. In at least one embodiment, one or more of the APIs 610 provide a set of callable functions 612 (referred to herein as APIs, API functions, and / or functions) that each perform one or more computing operations, such as computing operations related to parallel computing. For example, in one embodiment, one or more of the APIs 610 provide functions 612 to cause a neural network to generate one or more images using one or more images with or without captions and / or to otherwise perform the operations described herein.

[0109] In at least one embodiment, one or more software programs 602 interact with or otherwise communicate with one or more of the APIs 610 to perform one or more computing operations using one or more PPUs (e.g., GPUs). In at least one embodiment, one or more computing operations using one or more PPUs include at least one set or more of computing operations that are at least partially accelerated by being performed by the one or more PPUs. In at least one embodiment, one or more software programs 602 interact with one or more of the APIs 610 to perform audio-to-text processing.

[0110] In at least one embodiment, the interface is software instructions that, if executed, provide access to one or more functions 612 provided by one or more APIs 610. In at least one embodiment, when a software developer compiles one or more software programs 602 in conjunction with one or more libraries 606 that include or otherwise provide access to one or more APIs 610, the software programs 602 use a native interface. In at least one embodiment, one or more software programs 602 are statically compiled in conjunction with a pre-compiled library 606 that includes instructions for executing one or more APIs 610 or uncompiled source code. In at least one embodiment, one or more software programs 602 are dynamically compiled, and the one or more software programs are linked using a linker to one or more pre-compiled libraries 606 that include one or more APIs 610.

[0111] In at least one embodiment, when a software developer executes a software program that utilizes a library 606 that includes one or more APIs 610 or otherwise communicates with it over a network or other remote communication medium, the software program 602 uses a remote interface. In at least one embodiment, one or more libraries 606 that include one or more APIs 610 are executed by a remote computing service (e.g., a computing resource service provider). In another embodiment, one or more libraries 606 that include one or more APIs 610 are executed by any other computing host that provides the one or more APIs 610 to one or more software programs 602.

[0112] In at least one embodiment, a processor (e.g., processor 502) that executes or uses one or more software programs 602 invokes, uses, executes, or otherwise implements one or more APIs 610 to allocate and otherwise manage the memory 614 to be used by the software program 602. In at least one embodiment, one or more software programs 602 utilize one or more APIs 610 to allocate and otherwise manage the memory 614 to be used by one or more portions of the software program 602 that will be accelerated using one or more PPUs (e.g., a GPU or any other accelerator or processor further described herein). These software programs 602 request that a neural network perform signal processing using functions 612 provided by one or more APIs 610 in one embodiment.

[0113] In at least one embodiment, API 610 is an API for facilitating parallel computing. In at least one embodiment, API 610 is any other API further described herein. In at least one embodiment, API 610 is provided by driver and / or runtime 604. In at least one embodiment, API 610 is provided by the CUDA user mode driver. In at least one embodiment, API 610 is provided by the CUDA runtime. In at least one embodiment, the driver (e.g., driver / runtime 604) is data values and software instructions that, if executed, perform or otherwise facilitate the operation of one or more functions 612 of API 610 during the loading and execution of one or more portions of software program 602. In at least one embodiment, runtime 604 is data values and software instructions that, if executed, perform or otherwise facilitate the operation of one or more functions 612 of API 610 during the execution of software program 602. In at least one embodiment, one or more software programs 602 utilize one or more APIs 610 implemented or otherwise provided by driver and / or runtime 604 to perform combined arithmetic operations during execution by one or more PPUs (e.g., GPUs).

[0114] In at least one embodiment, one or more software programs 602 utilize one or more APIs 610 provided by driver and / or runtime 604 to perform combined arithmetic operations on one or more PPUs (e.g., GPUs). In at least one embodiment, one or more APIs 610 provide combined arithmetic operations through driver and / or runtime 604, as described above. In at least one embodiment, one or more software programs 602 utilize one or more APIs 610 provided by driver and / or runtime 604 to allocate or otherwise reserve one or more blocks of memory 614 of one or more PPUs (e.g., GPUs). In at least one embodiment, one or more software programs 602 utilize one or more APIs 610 provided by driver and / or runtime 604 to allocate or otherwise reserve blocks of memory 614. In at least one embodiment, one or more APIs 610 call a neural network to cause 616 the neural network, such as the neural network described in any of the figures Figures 1 to 6 described in connection with

[0115] To improve the availability of a software program 602 accelerated by one or more PPUs (e.g., GPUs) and / or the optimization of one or more portions of the software program 602, in one embodiment, one or more APIs 610 provide one or more API functions 612 to cause 616 a neural network as described herein, for example, in connection with Figures 1 - 6 the neural network described above. In at least one embodiment, the exemplary block diagram 600 depicts a processor (e.g., processor 106) that includes one or more circuits for causing one or more neural networks (e.g., a task neural network and / or a base neural network) to generate one or more images.

[0116] In the following description, numerous specific details are set forth to provide a more thorough understanding of at least one embodiment. However, it will be apparent to one of ordinary skill in the art that the inventive concepts may be practiced without one or more of these specific details.

[0117] Logic

[0118] Figure 7A Logic 715 is shown, which, as described elsewhere herein, can be used in one or more devices to perform operations such as those discussed herein according to at least one embodiment. In at least one embodiment, logic 715 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, logic 715 is inference and / or training logic. Details regarding logic 715 are provided below in connection with Figure 7A and / or Figure 7B In at least one embodiment, logic refers to any combination of software logic, hardware logic, and / or firmware logic for providing the functions or operations described herein, where the logic can be embodied jointly or separately as a circuit forming part of a larger system (e.g., an integrated circuit (IC), a system on a chip (SoC), or one or more processors (e.g., a CPU, a GPU)).

[0119] In at least one embodiment, logic 715 may include, but is not limited to, code and / or data storage 701 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network that is trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, logic 715 may include or be coupled to code and / or data storage 701 for storing graph code or other software to control timing and / or sequencing, where weight and / or other parameter information is loaded to configure the logic that includes integer and / or floating point units (collectively referred to as arithmetic logic unit (ALU)). In at least one embodiment, code (such as graph code) loads weight or other parameter information into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, code and / or data storage 701 stores weight parameters and / or input / output data for each layer of the neural network used in training and / or inference during forward propagation of input / output data and / or weight parameters in aspects of using one or more embodiments. In at least one embodiment, any portion of code and / or data storage 701 may be included within other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0120] In at least one embodiment, any portion of code and / or data storage 701 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 701 may be cache memory, dynamic random access memory (“DRAM”), static random access memory (“SRAM”), non-volatile memory (such as flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 701 is internal or external to the processor, e.g., or includes DRAM, SRAM, flash memory, or some other storage type, may depend on the available on-chip versus off-chip storage, latency requirements of the training and / or inference functions being performed, the batch size of the data used in inference and / or training of the neural network, or some combination of these factors.

[0121] In at least one embodiment, logic 715 may include, but is not limited to, code and / or data storage 705 for storing backward and / or output weights and / or input / output data corresponding to neurons or layers of a neural network that are trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, during training and / or inference using aspects of one or more embodiments, code and / or data storage 705 stores weight parameters and / or input / output data for each layer of the neural network that is trained or used in conjunction with one or more embodiments during backpropagation of the input / output data and / or weight parameters. In at least one embodiment, logic 715 may include or be coupled to code and / or data storage 705 for storing graph code or other software to control timing and / or sequencing, where weights and / or other parameter information are loaded to configure the logic, which includes integer and / or floating-point units (collectively referred to as arithmetic logic unit (ALU))

[0122] In at least one embodiment, the code (such as graph code) causes weight or other parameter information to be loaded into the processor ALU based on the architecture of the neural network corresponding to the code. In at least one embodiment, any portion of code and / or data storage 705 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 705 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 705 may be cache memory, DRAM, SRAM, non-volatile memory (such as flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 705 is internal or external to the processor, e.g., including DRAM, SRAM, flash memory, or some other storage type, may depend on the available on-chip versus off-chip storage, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0123] In at least one embodiment, code and / or data storage 701 and code and / or data storage 705 may be separate storage structures. In at least one embodiment, code and / or data storage 701 and code and / or data storage 705 may be the same storage structure. In at least one embodiment, code and / or data storage 701 and code and / or data storage 705 may be partially combined and partially separated. In at least one embodiment, any portion of code and / or data storage 701 and code and / or data storage 705 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0124] In at least one embodiment, logic 715 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 710 (including integer and / or floating point units) for performing logical and / or mathematical operations at least in part based on and / or as directed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values from layers or neurons within a neural network) stored in activation store 720, which are a function of input / output and / or weight parameter data stored in code and / or data store 701 and / or code and / or data store 705. In at least one embodiment, the activations stored in activation store 720 are generated according to linear algebra and / or matrix-based mathematics performed by ALU 710 in response to executing instructions or other code, where the weight values stored in code and / or data store 705 and / or code and / or data store 701 are used as operands along with other values such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data store 705 or code and / or data store 701 or other on-chip or off-chip storage.

[0125] In at least one embodiment, one or more ALUs 710 are included in one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 710 may be external to the processors or other hardware logic devices or circuits using them (e.g., coprocessors). In at least one embodiment, ALU 710 may be included within the execution units of a processor or otherwise included in an ALU bank accessible by the execution units of a processor, which execution units may be within the same processor or distributed among different types of different processors (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and / or data store 701, code and / or data store 705, and activation store 720 may share a processor or other hardware logic device or circuit, while in another embodiment, they may be in different processors or other hardware logic devices or circuits or some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation store 720 may be included with other on-chip or off-chip data storage, including the L1, L2, or L3 cache of a processor or system memory. Additionally, inference and / or training code may be stored along with other code accessible by the processor or other hardware logic or circuits and may be fetched and / or processed using the fetch, decode, schedule, execute, retire, and / or other logic circuits of the processor.

[0126] In at least one embodiment, the activation store 720 can be a cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the activation store 720 can be wholly or partially inside or outside one or more processors or other logic circuits. In at least one embodiment, the choice of whether the activation store 720 is internal or external to the processor, e.g., or includes DRAM, SRAM, flash memory, or some other storage type, can depend on the on-chip versus off-chip available storage, the latency requirements for performing training and / or inference functions, the batch size of the data used in inferring and / or training a neural network, or some combination of these factors.

[0127] In at least one embodiment, Figure 7A the logic 715 shown in can be used in conjunction with an application specific integrated circuit (“ASIC”), such as the processing unit from Google, the TM inference processing unit (IPU) from Graphcore, or the (e.g., “Lake Crest”) processor from Intel Corporation. In at least one embodiment, Figure 7A the logic 715 shown can be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware (e.g., field programmable gate array (“FPGA”)).

[0128] Figure 7B Logic 715 is shown in accordance with at least one embodiment. In at least one embodiment, the logic 715 is inference and / or training logic. In at least one embodiment, the logic 715 can include, but is not limited to, hardware logic where computing resources are dedicated or otherwise exclusively used with weight values or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Figure 7B the logic 715 shown in can be used in conjunction with an application specific integrated circuit (“ASIC”), such as the processing unit from Google, the TM inference processing unit (IPU) from Graphcore, or the (e.g., “Lake Crest”) processor from Intel Corporation. In at least one embodiment, Figure 7BThe logic 715 shown in [Figure] can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware (such as a field programmable gate array (FPGA)). In at least one embodiment, the logic 715 includes, but is not limited to, code and / or data storage 701 and code and / or data storage 705, which can be used to store code (such as graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. In Figure 7B In at least one embodiment shown in [Figure], each of code and / or data storage 701 and code and / or data storage 705 is respectively associated with dedicated computing resources (such as computing hardware 702 and computing hardware 706). In at least one embodiment, each of computing hardware 702 and computing hardware 706 includes one or more ALUs that respectively perform mathematical functions (such as linear algebra functions) only on the information stored in code and / or data storage 701 and code and / or data storage 705, and the results are stored in activation storage 720.

[0129] In at least one embodiment, each of code and / or data storage 701 and 705 and the corresponding computing hardware 702 and 706 respectively corresponds to different layers of a neural network, such that the activation obtained from one storage / computation pair 701 / 702 of code and / or data storage 701 and computing hardware 702 is provided as the input to the next storage / computation pair 705 / 706 of code and / or data storage 705 and computing hardware 706 in order to reflect the conceptual organization of the neural network. In at least one embodiment, each storage / computation pair 701 / 702 and 705 / 706 can correspond to more than one neural network layer. In at least one embodiment, additional storage / computation pairs (not shown) can be included in the logic 715 after or in parallel with the storage / computation pairs 701 / 702 and 705 / 706.

[0130] Neural Network Training and Deployment

[0131] Figure 8Illustrates the training and deployment of a deep neural network according to at least one embodiment. In at least one embodiment, a training dataset 802 is used to train an untrained neural network 806. In at least one embodiment, the training framework 804 is the PyTorch framework, while in other embodiments, the training framework 804 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 804 trains the untrained neural network 806 and allows it to be trained using the processing resources described herein to generate a trained neural network 808. In at least one embodiment, weights can be selected randomly or by pre-training using a deep belief network. In at least one embodiment, the training can be performed in a supervised, partially supervised, or unsupervised manner.

[0132] In at least one embodiment, supervised learning is used to train the untrained neural network 806, where the training dataset 802 includes inputs paired with desired outputs for the inputs, or where the training dataset 802 includes inputs with known outputs and the outputs of the neural network 806 are manually graded. In at least one embodiment, the untrained neural network 806 is trained in a supervised manner, processes inputs from the training dataset 802, and compares the resulting outputs with a set of desired or wanted outputs. In at least one embodiment, the error is then backpropagated through the untrained neural network 806. In at least one embodiment, the training framework 804 adjusts the weights that control the untrained neural network 806. In at least one embodiment, the training framework 804 includes tools for monitoring the degree to which the untrained neural network 806 converges to a model (such as the trained neural network 808) suitable for generating correct answers (such as result 814) based on input data (such as new dataset 812). In at least one embodiment, the training framework 804 repeatedly trains the untrained neural network 806 while adjusting the weights to refine the output of the untrained neural network 806 using a loss function and an adjustment algorithm (such as stochastic gradient descent). In at least one embodiment, the training framework 804 trains the untrained neural network 806 until the untrained neural network 806 reaches a desired accuracy. In at least one embodiment, the trained neural network 808 can then be deployed to implement any number of machine learning operations.

[0133] In at least one embodiment, unsupervised learning is used to train an untrained neural network 806, where the untrained neural network 806 attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised learning training dataset 802 will include input data without any associated output data or "ground truth" data. In at least one embodiment, the untrained neural network 806 can learn groupings within the training dataset 802 and can determine how individual inputs relate to the untrained dataset 802. In at least one embodiment, unsupervised training can be used to generate a self-organizing map in the trained neural network 808, which can perform operations useful for reducing the dimensionality of a new dataset 812. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows for the identification of data points in the new dataset 812 that deviate from the normal pattern of the new dataset 812.

[0134] In at least one embodiment, semi-supervised learning can be used, which is a technique in which a mixture of labeled and unlabeled data is included in the training dataset 802. In at least one embodiment, the training framework 804 can be used to perform incremental learning, such as through transfer learning techniques. In at least one embodiment, incremental learning enables the trained neural network 808 to adapt to a new dataset 812 without forgetting the knowledge injected into the trained neural network 808 during initial training.

[0135] In at least one embodiment, the training framework 804 is a framework that is processed in combination with a software development kit such as the OpenVINO (Open Visual Inference and Neural Network Optimization) toolkit. In at least one embodiment, the OpenVINO toolkit is a toolkit developed by Intel Corporation, Santa Clara, California, for example. In at least one embodiment, OpenVINO includes logic 715 or uses logic 715 to perform the operations described herein. In at least one embodiment, a SoC, integrated circuit, or processor uses OpenVINO to perform the operations described herein.

[0136] In at least one embodiment, OpenVINO is a toolkit for facilitating the development of applications (particularly neural network applications) for various tasks and operations, such as human vision emulation, speech recognition, natural language processing, recommendation systems, and / or variants thereof. In at least one embodiment, OpenVINO supports neural networks such as convolutional neural networks (CNNs), recurrent neural networks, and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries, such as OpenCV, OpenCL, and / or variants thereof.

[0137] In at least one embodiment, OpenVINO supports neural network models for various tasks and operations, such as classification, segmentation, object detection, face recognition, speech recognition, pose estimation (e.g., of a person and / or an object), monocular depth estimation, inpainting, style transfer, motion recognition, coloring, and / or variants thereof.

[0138] In at least one embodiment, OpenVINO includes one or more software tools and / or modules for model optimization, also referred to as the Model Optimizer. In at least one embodiment, the Model Optimizer is a command-line tool that facilitates the conversion between the training and deployment of a neural network model. In at least one embodiment, the Model Optimizer optimizes a neural network model for execution on various devices and / or processing units such as GPUs, CPUs, PPUs, GPGPUs, and / or variants thereof. In at least one embodiment, the Model Optimizer generates an internal representation of the model and optimizes the model to generate an intermediate representation. In at least one embodiment, the Model Optimizer reduces the number of layers of the model. In at least one embodiment, the Model Optimizer removes layers of the model used for training. In at least one embodiment, the Model Optimizer performs various neural network operations, such as modifying the input of the model (e.g., resizing the input of the model), modifying the size of the input of the model (e.g., modifying the batch size of the model), modifying the model structure (e.g., modifying the layers of the model), normalization, standardization, quantization (e.g., converting the weights of the model from a first representation such as floating point to a second representation such as integer), and / or variants thereof.

[0139] In at least one embodiment, OpenVINO includes one or more software libraries for inference, also referred to as the Inference Engine. In at least one embodiment, the Inference Engine is a C++ library or a library in any suitable programming language. In at least one embodiment, the Inference Engine is used to infer input data. In at least one embodiment, the Inference Engine implements various classes to infer input data and generate one or more results. In at least one embodiment, the Inference Engine implements one or more API functions to process the intermediate representation, set the input and / or output format, and / or execute the model on one or more devices.

[0140] In at least one embodiment, OpenVINO provides various capabilities for the heterogeneous execution of one or more neural network models. In at least one embodiment, heterogeneous execution or heterogeneous computing refers to one or more computing processes and / or systems that utilize one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions to execute programs on one or more devices. In at least one embodiment, OpenVINO provides various software functions to execute programs and / or portions of programs on different devices. In at least one embodiment, OpenVINO provides various software functions, for example, to run a first code portion on a CPU and a second code portion on a GPU and / or FPGA. In at least one embodiment, OpenVINO provides various software functions to execute one or more layers of a neural network on one or more devices (e.g., execute a first set of layers on a first device (e.g., GPU) and a second set of layers on a second device (e.g., CPU)).

[0141] In at least one embodiment, OpenVINO includes various functions similar to those associated with the CUDA programming model, such as various neural network model operations associated with frameworks such as TensorFlow, PyTorch, and / or their variants. In at least one embodiment, one or more CUDA programming model operations are performed using OpenVINO. In at least one embodiment, the various systems, methods, and / or techniques described herein are implemented using OpenVINO.

[0142] Data center

[0143] Figure 9 An exemplary data center 900 is shown in which at least one embodiment can be used. In at least one embodiment, data center 900 includes a data center infrastructure layer 910, a framework layer 920, a software layer 930, and an application layer 940.

[0144] In at least one embodiment, as Figure 9As shown, the data center infrastructure layer 910 may include a resource coordinator 912, grouped computing resources 914, and node computing resources ("node C.R.") 916(1)-916(N), where "N" represents a positive integer (which may be a different integer "N" from the integers used in other figures). In at least one embodiment, the node C.R. 916(1)-916(N) may include, but is not limited to, any number of central processing units ("CPU") or other processors (including accelerators, field programmable gate arrays (FPGA), graphics processors, etc.), memory storage devices 918(1)-918(N) (such as dynamic read-only memory, solid-state storage, or disk drivers), network input / output ("NW I / O") devices, network switches, virtual machines ("VM"), power modules, and cooling modules, etc. In at least one embodiment, one or more of the node C.R. 916(1)-916(N) may be servers having one or more of the above computing resources.

[0145] In at least one embodiment, the grouped computing resources 914 may include separate groupings of node C.R. housed within one or more racks (not shown), or many racks housed within data centers (also not shown) at various geographical locations. In at least one embodiment, the separate groupings of node C.R. within the grouped computing resources 914 may include grouped computing, network, memory, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node C.R. including CPUs or processors may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0146] In at least one embodiment, the resource coordinator 912 may configure or otherwise control one or more of the node C.R. 916(1)-916(N) and / or the grouped computing resources 914. In at least one embodiment, the resource coordinator 912 may include a software design infrastructure ("SDI") management entity for the data center 900. In at least one embodiment, the resource coordinator 912 may include hardware, software, or some combination thereof.

[0147] In at least one embodiment, as Figure 9As shown, the framework layer 920 includes a job scheduler 922, a configuration manager 924, a resource manager 926, and a distributed file system 928. In at least one embodiment, the framework layer 920 may include a framework that supports software 932 of the software layer 930 and / or one or more applications 942 of the application layer 940. In at least one embodiment, the software 932 or the application 942 may respectively include web-based service software or applications, such as service software or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 920 may be, but is not limited to, a type of free and open-source software web application framework, such as Apache Spark that can utilize the distributed file system 928 for large-scale data processing (e.g., "big data"). TM (hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 922 may include a Spark driver for facilitating the scheduling of workloads supported by the various layers of the data center 900. In at least one embodiment, the configuration manager 924 may be able to configure different layers, such as the software layer 930 and the framework layer 920 including Spark and the distributed file system 928 for supporting large-scale data processing. In at least one embodiment, the resource manager 926 may be able to manage the clustered or grouped computing resources mapped to or allocated for supporting the distributed file system 928 and the job scheduler 922. In at least one embodiment, the clustered or grouped computing resources may include the grouped computing resources 914 at the data center infrastructure layer 910. In at least one embodiment, the resource manager 926 may coordinate with the resource coordinator 912 to manage these mapped or allocated computing resources.

[0148] In at least one embodiment, the software 932 included in the software layer 930 may include software used by at least respective parts of the nodes C.R. 916(1)-916(N), the grouped computing resources 914, and / or the distributed file system 928 of the framework layer 920. In at least one embodiment, one or more types of software may include, but are not limited to, Internet web search software, email virus scanning software, database software, and streaming video content software.

[0149] In at least one embodiment, one or more applications 942 included in the application layer 940 may include one or more types of applications used by at least respective portions of nodes C.R. 916(1)-916(N), grouped computing resources 914, and / or the distributed file system 928 of the framework layer 920. In at least one embodiment, one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, applications, and machine learning applications, including training or inference software, machine learning framework software (such as PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0150] In at least one embodiment, any one of the configuration manager 924, the resource manager 926, and the resource coordinator 912 may implement any number and type of self-modifying actions based on any amount and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modifying actions may relieve data center operators of the data center 900 from making potentially bad configuration decisions and may avoid underutilization and / or poorly performing portions of the data center.

[0151] In at least one embodiment, the data center 900 may include tools, services, software, or other resources for training one or more machine learning models or using one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weight parameters according to a neural network architecture by using the software and computing resources described above with respect to the data center 900. In at least one embodiment, by using the weight parameters calculated by one or more training techniques described herein, the resources described above with respect to the data center 900 may be used to infer or predict information using the trained machine learning model corresponding to one or more neural networks.

[0152] In at least one embodiment, the data center may use a CPU, an application-specific integrated circuit (ASIC), a GPU, an FPGA, or other hardware to perform training and / or inference using the above resources. In addition, one or more of the above software and / or hardware resources may be configured as a service for allowing a user to train or perform information inference, such as image recognition, speech recognition, or other artificial intelligence services.

[0153] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. This is described in conjunction with Figure 7A and / or Figure 7BProvide details regarding logic 715. In at least one embodiment, logic 715 can be used in data center 900 for performing inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0154] In at least one embodiment, Figures 7A - 9 one or more of the systems depicted in are used to perform one or more operations described herein using one or more neural networks having various algorithms, formulas, and processes (such as those described in connection with Figure 1 those described) and / or otherwise. In at least one embodiment, Figures 7A - 9 one or more of the systems depicted in are used to implement one or more systems and / or processes (such as those described in connection with Figures 1 - 6 those described), such as to generate one or more images from text using one or more neural networks based at least in part on one or more first images that do not have text indicative of the content of the one or more first images and one or more second images that have text indicative of the content of the one or more second images and / or otherwise perform the operations described herein.

[0155] Autonomous vehicle

[0156] Figure 10A FIG. shows an example of an autonomous vehicle 1000 according to at least one embodiment. In at least one embodiment, autonomous vehicle 1000 (alternatively referred to herein as “vehicle 1000”) can be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle that accommodates one or more passengers. In at least one embodiment, vehicle 1000 can be a semi-trailer truck for hauling cargo. In at least one embodiment, vehicle 1000 can be an airplane, robotic vehicle, or other type of vehicle.

[0157] Autonomous vehicles can be described according to the automation levels defined by the National Highway Traffic Safety Administration (“NHTSA”) under the U.S. Department of Transportation and the Society of Automotive Engineers (“SAE”) “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016 - 201806 released on June 15, 2018, Standard No. J3016 - 201609 released on September 30, 2016, and previous and future versions of this standard). In at least one embodiment, vehicle 1000 may be capable of having functions according to one or more of Levels 1 to 5 of the autonomous driving levels. For example, in at least one embodiment, vehicle 1000 may be capable of having conditional automation (Level 3), highly automated (Level 4), and / or fully automated (Level 5), depending on the embodiment.

[0158] In at least one embodiment, vehicle 1000 may include, but is not limited to, components such as a chassis, a body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of the vehicle. In at least one embodiment, vehicle 1000 may include, but is not limited to, a propulsion system 1050, such as an internal combustion engine, a hybrid device, a fully electric motor, and / or another type of propulsion system. In at least one embodiment, propulsion system 1050 may be connected to the driveline of vehicle 1000, which may include, but is not limited to, a transmission for enabling the propulsion of vehicle 1000. In at least one embodiment, propulsion system 1050 may be controlled in response to receiving a signal from a throttle / accelerator 1052.

[0159] In at least one embodiment, when propulsion system 1050 is operating (e.g., when vehicle 1000 is in motion), a steering system 1054 (which may include, but is not limited to, a steering wheel) is used to steer vehicle 1000 (e.g., along a desired path or route). In at least one embodiment, steering system 1054 may receive a signal from a steering actuator 1056. In at least one embodiment, for fully automated (Level 5) functions, the steering wheel may be optional. In at least one embodiment, a brake sensor system 1046 may be used to operate vehicle brakes in response to receiving a signal from a brake actuator 1048 and / or a brake sensor.

[0160] In at least one embodiment, one or more controllers 1036, which may include, but is not limited to, one or more system - on - chips (“SoC”) Figure 10A(not shown) and / or a graphics processing unit (“GPU”) to provide signals (e.g., representative of commands) to one or more components and / or systems of the vehicle 1000. For example, in at least one embodiment, one or more controllers 1036 may send signals to operate vehicle brakes via a brake actuator 1048, operate a steering system 1054 via one or more steering actuators 1056, and operate a propulsion system 1050 via one or more throttle / accelerators 1052. In at least one embodiment, one or more controllers 1036 may include one or more on-vehicle (e.g., integrated) computing devices that process sensor signals and output operating commands (e.g., signals representative of commands) to effect autonomous driving and / or assist a human driver in driving the vehicle 1000. In at least one embodiment, one or more controllers 1036 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functions (e.g., computer vision), a fourth controller for infotainment functions, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the above functions, and two or more controllers may handle a single function and / or any combination thereof.

[0161] In at least one embodiment, one or more controllers 1036 provide signals for controlling one or more components and / or systems of the vehicle 1000 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data may be received from, for example but not limited to, the following sensors: one or more global navigation satellite system (“GNSS”) sensors 1058 (e.g., one or more global positioning system sensors), one or more RADAR sensors 1060, one or more ultrasonic sensors 1062, one or more LIDAR sensors 1064, one or more inertial measurement unit (IMU) sensors 1066 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1096, one or more stereo cameras 1068, one or more wide-angle cameras 1070 (e.g., fisheye cameras), one or more infrared cameras 1072, one or more surround cameras 1074 (e.g., 360-degree cameras), remote cameras ( Figure 10A (not shown), mid-range cameras ( Figure 10Anot shown), one or more speed sensors 1044 (e.g., for measuring the speed of vehicle 1000), one or more vibration sensors 1042, one or more steering sensors 1040, one or more braking sensors (e.g., as part of a braking sensor system 1046), and / or other sensor types.

[0162] In at least one embodiment, one or more controllers 1036 may receive inputs (e.g., represented by input data) from the instrument panel 1032 of vehicle 1000 and provide outputs (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 1034, a sound annunciator, a speaker, and / or via other components of vehicle 1000. In at least one embodiment, the output may include information such as vehicle speed, speed, time, map data (e.g., a high-definition map ( Figure 10A not shown), location data (e.g., the location of vehicle 1000, e.g., on a map), direction, the locations of other vehicles (e.g., occupied grids), information about objects, and the status of objects sensed by one or more controllers 1036, etc. For example, in at least one embodiment, the HMI display 1034 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic signal changes, etc.) and / or information about driving maneuvers the vehicle has made, is making, or will make (e.g., changing lanes now, reaching exit 34B in two miles, etc.).

[0163] In at least one embodiment, vehicle 1000 further includes a network interface 1024, which may communicate via one or more networks using one or more wireless antennas 1026 and / or one or more modems. For example, in at least one embodiment, the network interface 1024 may be capable of communicating via Long-Term Evolution (“LTE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile Communications (“GSM”), IMT-CDMA Multi-Carrier (“CDMA2000”) networks, etc. In at least one embodiment, one or more wireless antennas 1026 may also enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using one or more local area networks (such as Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low-power wide area networks (“LPWAN”) (such as protocols like LoRaWAN, SigFox, etc.).

[0164] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. This is described in conjunction with Figure 7A and / or Figure 7BDetails regarding logic 715 are provided. In at least one embodiment, logic 715 can be used in vehicle 1000 for performing inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0165] In at least one embodiment, Figure 10A one or more of the systems depicted in are used to perform operations described herein using one or more neural networks having various algorithms, formulas, and procedures (such as those associated with Figure 1 those described) and / or otherwise. In at least one embodiment, Figure 10A one or more of the systems depicted in are used to implement one or more systems and / or processes (such as those associated with Figures 1 - 6 those described), such as to generate one or more images from text using one or more neural networks based at least in part on one or more first images that do not have text indicative of the content of the one or more first images and one or more second images that have text indicative of the content of the one or more second images and / or otherwise perform operations described herein.

[0166] Figure 10B An example of the camera positions and fields of view of autonomous vehicle 1000 according to at least one embodiment is shown. In at least one embodiment, the cameras and respective fields of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras can be included and / or the cameras can be located at different positions on vehicle 1000. Figure 10A

[0167] ​In at least one embodiment, the camera type for a camera may include, but is not limited to, a digital camera that may be adapted to be used with components and / or systems of vehicle 1000. In at least one embodiment, one or more cameras may operate at an Automotive Safety Integrity Level (“ASIL”) B and / or other ASIL. In at least one embodiment, the camera type may be capable of any image capture rate, such as 60 frames per second (fps), 120 fps, 240 fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, other types of shutters, or a combination thereof. In at least one embodiment, the color filter array may include a Red Clear Clear Clear (“RCCC”) color filter array, a Red Clear Clear Blue (“RCCB”) color filter array, a Red Blue Green Clear (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer (RGGB) sensor color filter array, a monochrome sensor color filter array, and / or other types of color filter arrays. In at least one embodiment, transparent pixel cameras, such as cameras having RCCC, RCCB, and / or RBGC color filter arrays, may be used to attempt to improve photosensitivity.

[0168] In at least one embodiment, one or more cameras may be used to perform Advanced Driver Assistance System (“ADAS”) functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-functional monocular camera may be installed to provide functions including lane departure warning, traffic sign assistance, and smart headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) may simultaneously record and provide image data (e.g., video).

[0169] In at least one embodiment, one or more cameras may be mounted in a mounting component, such as a custom-designed (three-dimensional (“3D”) printed) component, in order to remove stray light and reflected light from within vehicle 1000 (e.g., reflected light from the dashboard that is reflected in the windshield mirror) that may interfere with the camera's image data capture ability. Regarding the rearview mirror mounting component, in at least one embodiment, the rearview mirror component may be 3D printed custom such that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras may be integrated into the rearview mirror. In at least one embodiment, for side view cameras, one or more cameras may also be integrated within four pillars at each corner of the cabin.

[0170] In at least one embodiment, a camera (e.g., a forward camera) having a field of view of portions of the environment in front of the vehicle 1000 can be used for surround view to help identify the forward path and obstacles, and to assist in providing information crucial for generating an occupancy grid and / or determining a preferred vehicle path with the help of one or more controllers 1036 and / or a control SoC. In at least one embodiment, the forward camera can be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward camera can also be used for ADAS functions and systems, including but not limited to lane departure warning (“LDW”), adaptive cruise control (“ACC”), and / or other functions such as traffic sign recognition.

[0171] In at least one embodiment, a variety of cameras can be used in a forward configuration, including for example a monocular camera platform including a CMOS (“complementary metal oxide semiconductor”) color imager. In at least one embodiment, a wide-angle camera 1070 can be used to sense objects entering the view from the periphery (e.g., pedestrians, intersection traffic, or bicycles). Although only one wide-angle camera 1070 is shown in Figure 10B , in other embodiments, any number (including zero) of wide-angle cameras can be on the vehicle 1000. In at least one embodiment, any number of long-range cameras 1098 (e.g., a long-range stereo camera pair) can be used for depth-based object detection, especially for objects for which a neural network has not been trained. In at least one embodiment, one or more long-range cameras 1098 can also be used for object detection and classification and basic object tracking.

[0172] In at least one embodiment, any number of stereo cameras 1068 can also be included in the forward configuration. In at least one embodiment, one or more stereo cameras 1068 can include an integrated control unit that includes a scalable processing unit that can provide programmable logic (“FPGA”) and a multi-core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit can be used to generate a 3D map of the environment of the vehicle 1000, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1068 can include but are not limited to a compact stereo vision sensor that can include but is not limited to two camera lenses (one on the left and one on the right) and an image processing chip that can measure the distance from the vehicle 1000 to a target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1068 can be used in addition to or in place of those described herein.

[0173] In at least one embodiment, a camera (e.g., a side view camera) having a view of portions of the environment including the sides of the vehicle 1000 can be used for surround view, which provides information for creating and updating an occupancy grid, and for generating side impact collision warnings. For example, in at least one embodiment, the surround cameras 1074 (e.g., four surround cameras as shown Figure 10B can be positioned on the vehicle 1000. In at least one embodiment, one or more of the surround cameras 1074 can include, but are not limited to, any number and combination of wide-angle cameras, one or more fisheye cameras, one or more 360-degree cameras, and / or similar cameras. For example, in at least one embodiment, four fisheye cameras can be located at the front, rear, and sides of the vehicle 1000. In at least one embodiment, the vehicle 1000 can use three surround cameras 1074 (e.g., left, right, and rear), and can utilize one or more other cameras (e.g., a forward camera) as the fourth surround view camera.

[0174] In at least one embodiment, a camera (e.g., a rear view camera) having a view of portions of the environment including the rear of the vehicle 1000 can be used for parking assistance, surround view, rear collision warnings, and for creating and updating an occupancy grid. In at least one embodiment, a variety of cameras can be used, including but not limited to cameras that are also suitable as forward view cameras (e.g., the tele camera 1098 and / or the mid-range camera 1076, the stereo camera 1068, the infrared camera 1072, etc.), as described herein.

[0175] In at least one embodiment, Figure 10B one or more of the systems depicted in are used to perform the operations described herein using one or more neural networks having various algorithms, formulas, and processes (such as those incorporated Figure 1 and / or otherwise perform the operations described herein. In at least one embodiment, Figure 10B one or more of the systems depicted in are used to implement one or more systems and / or processes (such as those incorporated Figures 1 - 6 such as to generate one or more images from text using one or more neural networks based at least in part on one or more first images that do not have text indicating the content of the one or more first images and one or more second images that have text indicating the content of the one or more second images and / or otherwise perform the operations described herein.

[0176] Figure 10C is a block diagram showing an exemplary system architecture of an autonomous vehicle 1000 according to at least one embodiment. In at least one embodiment, Figure 10A In at least one embodiment, Figure 10CEach of the components, features, and systems of the vehicle 1000 therein is shown as being connected via a bus 1002. In at least one embodiment, the bus 1002 may include, but is not limited to, a CAN data interface (alternatively referred to herein as the "CAN bus"). In at least one embodiment, the CAN may be a network inside the vehicle 1000 for assisting in controlling various features and functions of the vehicle 1000, such as actuation of brakes, acceleration, braking, steering, windshield wipers, etc. In at least one embodiment, the bus 1002 may be configured to have dozens or even hundreds of nodes, each node having its own unique identifier (e.g., CAN ID). In at least one embodiment, the bus 1002 can be read to find the steering wheel angle, ground speed, engine revolutions per minute ("RPM"), button positions, and / or other vehicle state indicators. In at least one embodiment, the bus 1002 may be a CAN bus compliant with ASIL B.

[0177] In at least one embodiment, in addition to or instead of CAN, FlexRay and / or Ethernet protocols may also be used. In at least one embodiment, there can be any number of buses forming the bus 1002, which may include, but are not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using different protocols. In at least one embodiment, two or more buses can be used to perform different functions, and / or can be used for redundancy. For example, a first bus can be used for collision avoidance functions, and a second bus can be used for actuation control. In at least one embodiment, each bus in the bus 1002 can communicate with any component of the vehicle 1000, and two or more buses in the bus 1002 can communicate with corresponding components. In at least one embodiment, each of any number of system-on-chips ("SoC") 1004 (e.g., SoC 1004(A) and SoC 1004(B)), each of one or more controllers 1036, and / or each computer in the vehicle can access the same input data (e.g., input from sensors of the vehicle 1000), and can be connected to a common bus, such as a CAN bus.

[0178] In at least one embodiment, the vehicle 1000 may include one or more controllers 1036, such as those described herein with respect to Figure 10A In at least one embodiment, the controller 1036 can be used for a variety of functions. In at least one embodiment, the controller 1036 can be coupled to any of the various other components and systems of the vehicle 1000, and can be used to control the vehicle 1000, the artificial intelligence of the vehicle 1000, the infotainment of the vehicle 1000, and / or other functions.

[0179] In at least one embodiment, vehicle 1000 may include any number of SoCs 1004. In at least one embodiment, each of the SoCs 1004 may include, but is not limited to, a central processing unit (“one or more CPUs”) 1006, a graphics processing unit (“one or more GPUs”) 1008, one or more processors 1010, one or more caches 1012, one or more accelerators 1014, one or more data stores 1016, and / or other components and features not shown. In at least one embodiment, one or more SoCs 1004 may be used to control vehicle 1000 in a variety of platforms and systems. For example, in at least one embodiment, one or more SoCs 1004 may be combined with a high-definition (“HD”) map 1022 in a system (e.g., the system of vehicle 1000), and the HD map 1022 may obtain map refreshes and / or updates from one or more servers ( Figure 10C not shown in the figure) via network interface 1024.

[0180] In at least one embodiment, one or more CPUs 1006 may include a CPU cluster or CPU complex (alternatively referred to herein as “CCPLEX”). In at least one embodiment, one or more CPUs 1006 may include multiple cores and / or secondary (“L2”) caches. For example, in at least one embodiment, one or more CPUs 1006 may include eight cores in a coherent multi-processor configuration. In at least one embodiment, one or more CPUs 1006 may include four dual-core clusters, each with a dedicated L2 cache (e.g., a 2 megabyte (MB) L2 cache). In at least one embodiment, one or more CPUs 1006 (e.g., CCPLEX) may be configured to support simultaneous cluster operations, which allows any combination of the clusters of one or more CPUs 1006 to be active at any given time.

[0181] In at least one embodiment, one or more CPUs 1006 may implement power management functions, which may include, but are not limited to, one or more of the following features: automatically clock-gating individual hardware blocks during idle to save dynamic power; clock-gating each core clock when the core is not actively executing instructions due to execution of a wait-for-interrupt ("WFI") / wait-for-event ("WFE") instruction; each core may be independently power-gated; each core cluster may be independently clock-gated when all cores are clock-gated or power-gated; and / or each core cluster may be independently power-gated when all cores are power-gated. In at least one embodiment, one or more CPUs 1006 may further implement an enhanced algorithm for managing power states, where allowed power states and expected wake-up times are specified, and the hardware / microcode determines the optimal power state to enter for the core, cluster, and CCPLEX. In at least one embodiment, the processing core may support a simplified power state entry sequence in software, where the work is offloaded to the microcode.

[0182] In at least one embodiment, one or more GPUs 1008 may include an integrated GPU (alternatively referred to herein as "iGPU"). In at least one embodiment, one or more GPUs 1008 may be programmable and efficient for parallel workloads. In at least one embodiment, one or more GPUs 1008 may use an enhanced tensor instruction set. In at least one embodiment, one or more GPUs 1008 may include one or more streaming microprocessors, where each streaming microprocessor may include a level-1 ("L1") cache (e.g., an L1 cache having a storage capacity of at least 96 KB), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache having a storage capacity of 512 KB). In at least one embodiment, one or more GPUs 1008 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1008 may use one or more compute application programming interfaces (APIs). In at least one embodiment, one or more GPUs 1008 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0183] In at least one embodiment, one or more GPUs 1008 may be power optimized to achieve optimal performance in automotive and embedded use cases. For example, in at least one embodiment, one or more GPUs 1008 may be fabricated on fin field-effect transistor ("FinFET") circuitry. In at least one embodiment, each streaming microprocessor may include multiple mixed-precision processing cores partitioned into multiple blocks. By way of example and not limitation, 64 FP32 cores and 32 FP64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA tensor cores for deep learning matrix arithmetic, a level zero ("L0") instruction cache, a scheduler (e.g., a warp scheduler), or an orderer, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor may include separate parallel integer and floating-point data paths for efficient execution of workloads with a mix of computational and addressing operations. In at least one embodiment, the streaming microprocessor may include separate thread scheduling capabilities to enable finer-grained synchronization and cooperation between parallel threads. In at least one embodiment, the streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0184] In at least one embodiment, one or more GPUs 1008 may include high bandwidth memory ("HBM") and / or a 16GB HBM2 memory subsystem, which in some examples is used to provide a peak memory bandwidth of approximately 900GB / second. In at least one embodiment, synchronous graphics random access memory ("SGRAM"), such as fifth generation graphics double data rate type synchronous random access memory ("GDDR5"), may be used in addition to or in place of HBM memory.

[0185] In at least one embodiment, one or more GPUs 1008 may include unified memory technology. In at least one embodiment, address translation service (“ATS”) support may be used to allow one or more GPUs 1008 to directly access the page tables of one or more CPUs 1006. In at least one embodiment, when a memory management unit (“MMU”) of a GPU in one or more GPUs 1008 experiences a miss, an address translation request may be sent to one or more CPUs 1006. In response, in at least one embodiment, two CPUs in one or more CPUs 1006 may look up the virtual-physical mapping of the address in their page tables and send the translation back to one or more GPUs 1008. In at least one embodiment, unified memory technology may allow a single unified virtual address space for the memories of both one or more CPUs 1006 and one or more GPUs 1008, thus simplifying the programming of one or more GPUs 1008 and the porting of applications to one or more GPUs 1008.

[0186] In at least one embodiment, one or more GPUs 1008 may include any number of access counters that may track the frequency of access by one or more GPUs 1008 to the memories of other processors. In at least one embodiment, one or more access counters may help ensure that memory pages are moved to the physical memory of the processor that most frequently accesses the pages, thereby improving the efficiency of sharing memory ranges among processors.

[0187] In at least one embodiment, one or more SoCs 1004 may include any number of caches 1012, including those described herein. For example, in at least one embodiment, one or more caches 1012 may include a level three (“L3”) cache that may be available to both one or more CPUs 1006 and one or more GPUs 1008 (e.g., connected to one or more CPUs 1006 and one or more GPUs 1008). In at least one embodiment, one or more caches 1012 may include a write-back cache that may track the state of each line, such as by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, depending on the embodiment, the L3 cache may include 4MB of memory or more, although smaller cache sizes may be used.

[0188] In at least one embodiment, one or more SoCs 1004 may include one or more accelerators 1014 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, one or more SoCs 1004 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memories. In at least one embodiment, a large on-chip memory (e.g., 4MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1008 and offload some tasks of one or more GPUs 1008 (e.g., to free up more cycles of one or more GPUs 1008 to perform other tasks). In at least one embodiment, one or more accelerators 1014 may be used for target workloads that are stable enough to withstand acceleration (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.). In at least one embodiment, CNNs may include region-based or region convolutional neural networks (“RCNNs”) and fast RCNNs (e.g., as used for object detection) or other types of CNNs.

[0189] In at least one embodiment, one or more accelerators 1014 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators (“DLAs”). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more tensor processing units (“TPUs”), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, a TPU may be an accelerator configured and optimized to perform image processing functions (e.g., for CNN, RCNN, etc.). In at least one embodiment, one or more DLAs may be further optimized for a particular set of neural network types and floating-point operations as well as inference. In at least one embodiment, the design of one or more DLAs may provide higher performance per millimeter than a typical general-purpose GPU and generally far exceed the performance of a CPU. In at least one embodiment, one or more TPUs may perform several functions, including supporting, for example, INT8, INT16, and FP16 data types for single-instance convolution functions of features and weights as well as post-processor functions. In at least one embodiment, one or more DLAs may execute a neural network, especially a CNN, quickly and efficiently on processed or unprocessed data for any of a variety of functions, including, for example, but not limited to: a CNN for object recognition and detection using data from a camera sensor; a CNN for distance estimation using data from a camera sensor; a CNN for emergency vehicle detection and identification and detection using data from a microphone; a CNN for face recognition and vehicle owner identification using data from a camera sensor; and / or a CNN for protection and / or security-related events.

[0190] In at least one embodiment, one or more DLAs may perform any function of one or more GPUs 1008, and by using an inference accelerator, for example, a designer may target one or more DLAs or one or more GPUs 1008 for any function. For example, in at least one embodiment, a designer may concentrate the processing and floating-point operations of a CNN on one or more DLAs and leave other functions to one or more GPUs 1008 and / or one or more accelerators 1014.

[0191] In at least one embodiment, one or more accelerators 1014 may include a Programmable Vision Accelerator (“PVA”), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA may be designed and configured to accelerate computer vision algorithms for Advanced Driver Assistance Systems (“ADAS”) 1038, autonomous driving, Augmented Reality (“AR”) applications, and / or Virtual Reality (“VR”) applications. In at least one embodiment, the PVA may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may include, for example but not limited to, any number of Reduced Instruction Set Computing (“RISC”) cores, Direct Memory Access (“DMA”), and / or any number of vector processors.

[0192] In at least one embodiment, the RISC cores may interact with an image sensor (e.g., the image sensor of any of the cameras described herein), an image signal processor, etc. In at least one embodiment, each RISC core may include any number of memories. In at least one embodiment, depending on the embodiment, the RISC cores may use any one of a variety of protocols. In at least one embodiment, the RISC cores may execute a Real-Time Operating System (“RTOS”). In at least one embodiment, one or more integrated circuit devices, Application-Specific Integrated Circuits (“ASICs”), and / or memory devices may be used to implement the RISC cores. For example, in at least one embodiment, the RISC cores may include an instruction cache and / or tightly coupled RAM.

[0193] In at least one embodiment, the DMA may enable the components of the PVA to access system memory independently of one or more CPUs 1006. In at least one embodiment, the DMA may support any number of features for optimizing the delivery to the PVA, including but not limited to, supporting multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA may support up to six or more dimensions of addressing, which may include but are not limited to block width, block height, block depth, horizontal block step, vertical block step, and / or depth step.

[0194] In at least one embodiment, the vector processor may be a programmable processor that may be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, one or more DMA engines (e.g., two DMA engines) and / or other peripherals. In at least one embodiment, the vector processing subsystem may operate as the main processing engine of the PVA and may include a vector processing unit (“VPU”), an instruction cache and / or a vector memory (e.g., “VMEM”). In at least one embodiment, the VPU core may include a digital signal processor, such as, for example, a single instruction multiple data (“SIMD”), very long instruction word (“VLIW”) digital signal processor. In at least one embodiment, the combination of SIMD and VLIW may improve throughput and speed.

[0195] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. Thus, in at least one embodiment, each vector processor may be configured to execute independently of other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute a general computer vision algorithm, but on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may simultaneously execute different computer vision algorithms on one image, or even execute different algorithms on a sequence of images or portions of an image. In at least one embodiment, any number of PVAs may be included in a hardware acceleration cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error correction code (“ECC”) memory for enhancing overall system security.

[0196] In at least one embodiment, one or more accelerators 1014 may include an on-chip computer vision network and static random access memory (“SRAM”) to provide high-bandwidth, low-latency SRAM for the one or more accelerators 1014. In at least one embodiment, the on-chip memory may include at least 4MB SRAM, which includes, for example but not limited to, eight field-configurable memory blocks that can be accessed by both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and the DLA may access the memory via a backbone that provides high-speed access to the memory for the PVA and the DLA. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and the DLA to the memory (e.g., using APB).

[0197] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and the DLA provide ready and valid signals before transmitting any control signals / address / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / address / data, as well as burst-type communication for continuous data transfer. In at least one embodiment, although other standards and protocols may be used, the interface may conform to the International Organization for Standardization (“ISO”) 26262 or the International Electrotechnical Commission (“IEC”) 61508 standard.

[0198] In at least one embodiment, one or more SoCs 1004 may include a real-time ray tracing hardware accelerator. In at least one embodiment, the real-time ray tracing hardware accelerator may be used to quickly and efficiently determine the position and extent of an object (e.g., within a world model) to generate a real-time visualization simulation for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for SONAR system simulation, for general wave propagation simulation, for comparison with LIDAR data for positioning and / or other functions, and / or for other uses.

[0199] In at least one embodiment, one or more accelerators 1014 can have a wide range of uses for autonomous driving. In at least one embodiment, PVA can be used in critical processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of PVA at low power and low latency match well with algorithm domains that require predictable processing. In other words, PVA excels in semi-dense or dense general-purpose computing, even on small data sets that may require predictable runtimes with low latency and low power. In at least one embodiment, such as in vehicle 1000, PVA can be designed to run classical computer vision algorithms as they can be efficient in object detection and integer math operations.

[0200] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, algorithms based on semi-global matching can be used in some examples, but this is not meant to be limiting. In at least one embodiment, applications for level 3 - 5 autonomous driving use motion estimation / stereo matching in operation (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA can perform computer stereo vision functions on inputs from two monocular cameras.

[0201] In at least one embodiment, PVA can be used to perform dense optical flow. For example, in at least one embodiment, PVA can process raw RADAR data (e.g., using 4D fast Fourier transform) to provide processed RADAR data. In at least one embodiment, for example, PVA is used for time-of-flight depth processing by processing raw time-of-flight data to provide processed time-of-flight data.

[0202] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, for example but not limited to, a neural network, the output of which is a measure of the confidence for each object detection. In at least one embodiment, the confidence can be represented or interpreted as a probability, or as providing a relative "weight" of each detection compared to other detections. In at least one embodiment, the confidence measure enables the system to make further decisions, i.e., regarding which detections should be considered true positive detections rather than false positive detections. In at least one embodiment, the system can set a threshold for the confidence, and only consider detections that exceed the threshold as true positive detections. In embodiments using an automatic emergency braking ("AEB") system, false positive detections will cause the vehicle to automatically perform emergency braking, which is clearly undesirable. In at least one embodiment, highly confident detections can be considered as triggers for AEB. In at least one embodiment, the DLA can run a neural network for regressing confidence values. In at least one embodiment, the neural network can take as its input at least some subset of parameters, such as bounding box dimensions, a ground plane estimate obtained (e.g., from another subsystem), and the outputs of one or more IMU sensors 1066 related to the vehicle 1000 direction, distance, and 3D position estimate of the object obtained from the neural network and / or other sensors (e.g., one or more LIDAR sensors 1064 or one or more RADAR sensors 1060).

[0203] In at least one embodiment, one or more SoCs 1004 can include one or more data stores 1016 (e.g., memories). In at least one embodiment, one or more data stores 1016 can be on-chip memories of one or more SoCs 1004, which can store neural networks to be executed on one or more GPUs 1008 and / or the DLA. In at least one embodiment, one or more data stores 1016 can have a large enough capacity to store multiple instances of neural networks for redundancy and safety. In at least one embodiment, one or more data stores 1016 can include one or more L2 or L3 caches.

[0204] In at least one embodiment, one or more SoCs 1004 may include any number of processors 1010 (e.g., embedded processors). In at least one embodiment, one or more processors 1010 may include a boot and power management processor, which may be a dedicated processor and subsystem for handling boot power and management functions and related secure execution. In at least one embodiment, the boot and power management processor may be part of the boot sequence of one or more SoCs 1004 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in system low-power state transitions, manage one or more SoC 1004 thermal and temperature sensors, and / or manage the power state of one or more SoCs 1004. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and one or more SoCs 1004 may use the ring oscillator to detect the temperature of one or more CPUs 1006, one or more GPUs 1008, and / or one or more accelerators 1014. In at least one embodiment, if it is determined that the temperature exceeds a threshold, the boot and power management processor may enter a temperature fault routine and place one or more SoCs 1004 in a lower power state and / or place the vehicle 1000 in the driver's safe parking mode (e.g., safely park the vehicle 1000).

[0205] In at least one embodiment, one or more processors 1010 may further include a set of embedded processors, which may be used as an audio processing engine. The audio processing engine may be an audio subsystem that provides full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core that has a digital signal processor with dedicated RAM.

[0206] In at least one embodiment, one or more processors 1010 may further include an always-on processor engine, which may provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0207] In at least one embodiment, one or more processors 1010 may further include a security cluster engine, which includes but is not limited to a dedicated processor subsystem for handling security management of automotive applications. In at least one embodiment, the security cluster engine may include but is not limited to two or more processor cores, tightly coupled RAM, supporting peripherals (such as timers, interrupt controllers, etc.) and / or routing logic. In the security mode, in at least one embodiment, two or more cores may operate in a lockstep mode and may be used as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, one or more processors 1010 may further include a real-time camera engine, which may include but is not limited to a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 1010 may further include a high dynamic range signal processor, which may include but is not limited to an image signal processor, which is a hardware engine as part of the camera processing pipeline.

[0208] In at least one embodiment, one or more processors 1010 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements the video post-processing functions required for a video playback application to produce a final image for a player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1070, one or more surround cameras 1074, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, preferably, the in-cabin monitoring camera sensors are monitored by a neural network running on another instance of the SoC 1004, which is configured to identify in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform but is not limited to lip reading to activate cellular services and make calls, indicate emails, change the destination of the vehicle, activate or change the vehicle's infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode and are otherwise disabled.

[0209] In at least one embodiment, the video image synthesizer may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, in the case of motion occurring in the video, the noise reduction appropriately weights the spatial information, thereby reducing the weight of the information provided by adjacent frames. In at least one embodiment, in the case where an image or a part of the image does not include motion, the temporal noise reduction performed by the video image synthesizer may use information from a previous image to reduce the noise in the current image.

[0210] In at least one embodiment, the video image synthesizer may also be configured to perform stereoscopic correction on the input stereoscopic shot frames. In at least one embodiment, when the operating system desktop is in use, the video image synthesizer may also be used for user interface synthesis and does not require one or more GPUs 1008 to continuously render new surfaces. In at least one embodiment, when one or more GPUs 1008 are powered and active for 3D rendering, the video image synthesizer may be used to offload one or more GPUs 1008 to improve performance and responsiveness.

[0211] In at least one embodiment, one or more of the SoCs 1004 may further include a Mobile Industry Processor Interface ("MIPI") camera serial interface, a high-speed interface, and / or a video input block for receiving video and inputs from cameras, which can be used for camera and related pixel input functions. In at least one embodiment, one or more of the SoCs 1004 may further include an input / output controller that can be software-controlled and can be used to receive I / O signals not committed to a specific role.

[0212] In at least one embodiment, one or more of the SoCs 1004 may further include a wide range of peripheral interfaces for enabling communication with peripheral devices, audio encoder / decoders ("codecs"), power management, and / or other devices. In at least one embodiment, one or more of the SoCs 1004 can be used to process data from cameras (e.g., connected via Gigabit Multimedia Serial Link and Ethernet channels), sensors (e.g., one or more LIDAR sensors 1064, one or more RADAR sensors 1060, etc., which can be connected via Ethernet channels), data from the bus 1002 (e.g., the speed, steering wheel position, etc. of the vehicle 1000), data from one or more GNSS sensors 1058 (e.g., connected via Ethernet bus or CAN bus), etc. In at least one embodiment, one or more of the SoCs 1004 may further include dedicated high-performance mass storage controllers, which may include their own DMA engines and can be used to free one or more CPUs 1006 from routine data management tasks.

[0213] In at least one embodiment, one or more SoCs 1004 can be an end-to-end platform with a flexible architecture that spans automation levels 3 - 5, thereby providing an integrated functional safety architecture for a platform that leverages and effectively uses computer vision and ADAS technologies to achieve diversity and redundancy, and provides a flexible and reliable driving software stack as well as deep learning tools. In at least one embodiment, one or more SoCs 1004 can be faster, more reliable, and even more energy - efficient and space - efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 1014, when combined with one or more CPUs 1006, one or more GPUs 1008, and one or more data stores 1016, can provide a fast and efficient platform for level 3 - 5 autonomous vehicles.

[0214] In at least one embodiment, computer vision algorithms can be executed on a CPU, which can be configured using a high - level programming language (such as C) to execute various processing algorithms on various visual data. However, in at least one embodiment, a CPU generally cannot meet the performance requirements of many computer vision applications, for example, performance requirements related to execution time and power consumption. In at least one embodiment, many CPUs cannot execute complex object detection algorithms in real - time, which are used in in - vehicle ADAS applications and actual level 3 - 5 autonomous vehicles.

[0215] The embodiments described herein allow multiple neural networks to be executed simultaneously and / or sequentially, and allow the results to be combined together to achieve level 3 - 5 autonomous driving functions. For example, in at least one embodiment, a CNN executed on a DLA or a discrete GPU (e.g., one or more GPUs 1020) can include text and word recognition, thereby allowing traffic signs to be read and understood, including signs that the neural network has not been specifically trained for. In at least one embodiment, the DLA can also include a neural network that is capable of recognizing, interpreting, and providing semantic understanding of the signs, and passing that semantic understanding to a path - planning module running on a CPU complex.

[0216] In at least one embodiment, for level 3, 4, or 5 driving, multiple neural networks can be run simultaneously. For example, in at least one embodiment, a warning sign that states "Caution: flashing lights indicate icy conditions", along with the electric lights, can be interpreted independently or jointly by several neural networks. In at least one embodiment, the warning sign itself can be recognized as a traffic sign by a first deployed neural network (e.g., a neural network that has been trained), and the text "flashing lights indicate icy conditions" can be interpreted by a second deployed neural network, which notifies the vehicle's path planning software (preferably executed on the CPU complex) that when flashing lights are detected, there is an icy condition. In at least one embodiment, the flashing lights can be recognized by operating a third deployed neural network on multiple frames, and the vehicle's path planning software can be notified of the presence (or absence) of the flashing lights. In at least one embodiment, all three neural networks can run simultaneously, e.g., within the DLA and / or on one or more GPUs 1008.

[0217] In at least one embodiment, a CNN for face recognition and vehicle owner recognition can use data from a camera sensor to recognize the presence of an authorized driver and / or the owner of the vehicle 1000. In at least one embodiment, a normally open sensor processing engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and in a security mode, can be used to disable the vehicle when the owner leaves the vehicle. In this way, one or more SoCs 1004 provide protection against theft and / or carjacking.

[0218] In at least one embodiment, a CNN for emergency vehicle detection and recognition can use data from a microphone 1096 to detect and recognize an emergency vehicle siren. In at least one embodiment, one or more SoCs 1004 use a CNN to classify environmental and urban sounds, as well as visual data. In at least one embodiment, a CNN running on the DLA is trained to recognize the relative approach speed of an emergency vehicle (e.g., by using the Doppler effect). In at least one embodiment, a CNN can also be trained to recognize emergency vehicles specific to the local area in which the vehicle is operating, as identified by one or more GNSS sensors 1058. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while in North America, the CNN will seek to recognize only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used, with the assistance of one or more ultrasonic sensors 1062, to execute an emergency vehicle safety routine, slow down the vehicle, drive the vehicle to the side of the road, park the vehicle, and / or idle the vehicle until the emergency vehicle has passed.

[0219] In at least one embodiment, vehicle 1000 may include one or more CPUs 1018 (e.g., one or more discrete CPUs or one or more dCPUs), which may be coupled to one or more SoCs 1004 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, one or more CPUs 1018 may include, for example, X86 processors. One or more CPUs 1018 can be used to perform any of a variety of functions, such as arbitrating potentially inconsistent results between ADAS sensors and one or more SoCs 1004, and / or monitoring the status and health of one or more controllers 1036 and / or on-chip infotainment system (“Infotainment SoC”) 1030. In at least one embodiment, one or more SoCs 1004 include one or more interconnects, and the interconnects may include Peripheral Component Interconnect Express (PCIe).

[0220] In at least one embodiment, vehicle 1000 may include one or more GPUs 1020 (e.g., one or more discrete GPUs or one or more dGPUs), which may be coupled to one or more SoCs 1004 via a high-speed interconnect (e.g., NVIDIA's NVLINK channel). In at least one embodiment, one or more GPUs 1020 may provide additional artificial intelligence capabilities, such as by executing redundant and / or different neural networks, and may be used to train and / or update neural networks at least in part based on inputs from sensors of vehicle 1000 (e.g., sensor data).

[0221] In at least one embodiment, vehicle 1000 may further include a network interface 1024, which may include, but is not limited to, one or more wireless antennas 1026 (e.g., one or more wireless antennas for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, network interface 1024 may be used to implement a wireless connection to an Internet cloud service (e.g., with a server and / or other network devices), to other vehicles, and / or to computing devices (e.g., a passenger's client device). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 1000 and another vehicle and / or an indirect link may be established (e.g., through a network and the Internet). In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide the direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1000 with information about vehicles in the vicinity of vehicle 1000 (e.g., vehicles in front of, to the side of, and / or behind vehicle 1000). In at least one embodiment, the foregoing function may be part of the cooperative adaptive cruise control function of vehicle 1000.

[0222] In at least one embodiment, network interface 1024 may include a SoC that provides modulation and demodulation functions and enables one or more controllers 1036 to communicate over a wireless network. In at least one embodiment, network interface 1024 may include a radio frequency front end for upconverting from baseband to radio frequency and downconverting from radio frequency to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed by known processes and / or using a super-heterodyne process. In at least one embodiment, the radio frequency front end functions may be provided by a separate chip. In at least one embodiment, the network interface may include wireless capabilities for communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0223] In at least one embodiment, vehicle 1000 may further include one or more data stores 1028, which may include but are not limited to off-chip (e.g., one or more off-chip SoCs 1004) storage. In at least one embodiment, one or more data stores 1028 may include but are not limited to one or more storage elements, including RAM, SRAM, dynamic random access memory (“DRAM”), video random access memory (“VRAM”), flash memory, hard disks, and / or other components and / or devices capable of storing at least one bit of data.

[0224] In at least one embodiment, vehicle 1000 may further include one or more GNSS sensors 1058 (e.g., GPS and / or assisted GPS sensors) to assist in mapping, perception, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1058 may be used, including for example but not limited to a GPS using a USB connector with an Ethernet to serial interface (e.g., RS-232) bridge.

[0225] In at least one embodiment, vehicle 1000 may further include one or more RADAR sensors 1060. In at least one embodiment, one or more RADAR sensors 1060 may be used by vehicle 1000 for remote vehicle detection, even in dark and / or adverse weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. In at least one embodiment, one or more RADAR sensors 1060 may use the CAN bus and / or bus 1002 (e.g., for transmitting data generated by one or more RADAR sensors 1060) to control and access object tracking data and, in some examples, may access an Ethernet channel to access raw data. In at least one embodiment, a variety of RADAR sensor types may be used. For example but not limited to, one or more RADAR sensors 1060 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more of the one or more RADAR sensors 1060 is a pulsed Doppler RADAR sensor.

[0226] In at least one embodiment, one or more RADAR sensors 1060 may include different configurations, such as long range with a narrow field of view, short range with a wide field of view, short range side coverage, etc. In at least one embodiment, long range RADAR may be used for adaptive cruise control functions. In at least one embodiment, the long range RADAR system may provide a wide field of view achieved through two or more independent scans (e.g., within a range of 250 m (meters)). In at least one embodiment, one or more RADAR sensors 1060 may assist in differentiating between static and moving objects and may be used by ADAS system 1038 for emergency braking assistance and forward collision warning. In at least one embodiment, one or more sensors 1060 included in the long range RADAR system may include but are not limited to a monostatic multimodal RADAR having multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, with six antennas, the central four antennas may create a focused beam pattern designed to record the surrounding environment of vehicle 1000 at a relatively high speed with minimal traffic interference from adjacent lanes. In at least one embodiment, the other two antennas may widen the field of view, enabling it to quickly detect vehicles entering or leaving the lane of vehicle 1000.

[0227] In at least one embodiment, by way of example, a mid-range RADAR system may include a range of up to 160 m (front) or 80 m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 1060 designed to be mounted at both ends of the rear bumper. When mounted at both ends of the rear bumper, in at least one embodiment, the RADAR sensor system may generate two beams that continuously monitor the rear direction of the vehicle and the blind spots in the vicinity. In at least one embodiment, the short-range RADAR system may be used in the ADAS system 1038 for blind spot detection and / or lane change assistance.

[0228] In at least one embodiment, the vehicle 1000 may further include one or more ultrasonic sensors 1062. In at least one embodiment, one or more ultrasonic sensors 1062 that may be positioned at the front, rear, and / or side positions of the vehicle 1000 may be used for parking assistance and / or creating and updating an occupancy grid. In at least one embodiment, a variety of ultrasonic sensors 1062 may be used, and different ultrasonic sensors 1062 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensor 1062 may operate at a functional safety level of ASIL B.

[0229] In at least one embodiment, the vehicle 1000 may include one or more LIDAR sensors 1064. In at least one embodiment, one or more LIDAR sensors 1064 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, one or more LIDAR sensors 1064 may operate at a functional safety level of ASIL B. In at least one embodiment, the vehicle 1000 may include multiple (e.g., two, four, six, etc.) LIDAR sensors 1064 that may use an Ethernet channel (e.g., to provide data to a gigabit Ethernet switch).

[0230] In at least one embodiment, one or more LIDAR sensors 1064 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available one or more LIDAR sensors 1064 may, for example, have an advertised range of approximately 100 m, an accuracy of 2 cm - 3 cm, and support an Ethernet connection of 100 Mbps. In at least one embodiment, one or more non-protruding LIDAR sensors may be used. In such an embodiment, one or more LIDAR sensors 1064 may include small devices that can be embedded in the front, rear, sides, and / or corner positions of the vehicle 1000. In at least one embodiment, one or more LIDAR sensors 1064, in such an embodiment, may provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, and have a range of 200 m, even for low-reflectivity objects. In at least one embodiment, the one or more forward-mounted LIDAR sensors 1064 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0231] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate up to approximately 200 m around the vehicle 1000. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and the reflected light on each pixel, which in turn corresponds to the range from the vehicle 1000 to the object. In at least one embodiment, flash LIDAR may allow for the generation of highly accurate and distortion-free images of the surrounding environment using each laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, with one on each side of the vehicle 1000. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D staring array LIDAR camera that has no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device may use a Class I (eye-safe) laser pulse of 5 nanoseconds per frame and may capture the reflected laser as a 3D range point cloud and co-registered intensity data.

[0232] In at least one embodiment, vehicle 1000 may further include one or more IMU sensors 1066. In at least one embodiment, one or more IMU sensors 1066 may be located at the center of the rear axle of vehicle 1000. In at least one embodiment, one or more IMU sensors 1066 may include, for example but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, one or more magnetic compasses, and / or other sensor types. In at least one embodiment, for example in a six-axis application, one or more IMU sensors 1066 may include but are not limited to accelerometers and gyroscopes. In at least one embodiment, for example in a nine-axis application, one or more IMU sensors 1066 may include but are not limited to accelerometers, gyroscopes, and magnetometers.

[0233] In at least one embodiment, one or more IMU sensors 1066 may be implemented as a miniature high-performance GPS-aided inertial navigation system (“GPS / INS”) that combines microelectromechanical system (“MEMS”) inertial sensors, a high-sensitivity GPS receiver, and an advanced Kalman filtering algorithm, for providing estimates of position, velocity, and attitude. In at least one embodiment, one or more IMU sensors 1066 may enable vehicle 1000 to estimate its heading by directly observing and correlating the speed changes from GPS to one or more IMU sensors 1066, without input from a magnetic sensor. In at least one embodiment, one or more IMU sensors 1066 and one or more GNSS sensors 1058 may be combined in a single integrated unit.

[0234] In at least one embodiment, vehicle 1000 may include one or more microphones 1096 placed inside and / or around vehicle 1000. In at least one embodiment, one or more microphones 1096 may be used for emergency vehicle detection and identification.

[0235] In at least one embodiment, vehicle 1000 may further include any number of camera types, including one or more stereo cameras 1068, one or more wide-angle cameras 1070, one or more infrared cameras 1072, one or more surround cameras 1074, one or more long-range cameras 1098, one or more mid-range cameras 1076, and / or other camera types. In at least one embodiment, the cameras can be used to capture image data around the entire periphery of vehicle 1000. In at least one embodiment, the type of cameras used depends on vehicle 1000. In at least one embodiment, any combination of camera types can be used to provide the necessary coverage around vehicle 1000. In at least one embodiment, the number of cameras deployed can vary according to the embodiment. For example, in at least one embodiment, vehicle 1000 can include six cameras, seven cameras, ten cameras, twelve cameras, or other numbers of cameras. In at least one embodiment, the cameras can support, by way of example but not limitation, Gigabit Multimedia Serial Link (“GMSL”) and / or Gigabit Ethernet communications. In at least one embodiment, each camera was previously described in more detail with reference to Figure 10A and Figure 10B Each camera is described in more detail.

[0236] In at least one embodiment, vehicle 1000 may further include one or more vibration sensors 1042. In at least one embodiment, one or more vibration sensors 1042 can measure the vibration of components of vehicle 1000 (e.g., the axle). For example, in at least one embodiment, a change in vibration can indicate a change in the road surface. In at least one embodiment, when two or more vibration sensors 1042 are used, the difference between the vibrations can be used to determine the friction or slippage of the road surface (e.g., when there is a vibration difference between a power-driven axle and a freely rotating axle).

[0237] In at least one embodiment, vehicle 1000 may include an ADAS system 1038. In at least one embodiment, the ADAS system 1038 may include, in some examples, but not be limited to, a SoC. In at least one embodiment, the ADAS system 1038 may include, but not be limited to, any number and any combination of autonomous / adaptive / automatic cruise control (“ACC”) systems, cooperative adaptive cruise control (“CACC”) systems, forward collision warning (“FCW”) systems, automatic emergency braking (“AEB”) systems, lane departure warning (“LDW”) systems, lane keeping assist (“LKA”) systems, blind spot warning (“BSW”) systems, rear cross traffic warning (“RCTW”) systems, collision warning (“CW”) systems, lane centering (“LC”) systems, and / or other systems, features, and / or functions.

[0238] In at least one embodiment, the ACC system may use one or more RADAR sensors 1060, one or more LIDAR sensors 1064, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle immediately in front of vehicle 1000 and automatically adjusts the speed of vehicle 1000 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system performs distance keeping and advises vehicle 1000 to change lanes when needed. In at least one embodiment, the lateral ACC is related to other ADAS applications, such as LC and CW.

[0239] In at least one embodiment, the CACC system uses information from other vehicles, which may be received indirectly from other vehicles via the network interface 1024 and / or one or more wireless antennas 1026 via a wireless link or through a network connection (e.g., via the Internet). In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle (“V2V”) communication link, while the indirect link may be provided by an infrastructure-to-vehicle (“I2V”) communication link. Generally, V2V communication provides information about the vehicle immediately ahead (e.g., the vehicle immediately in front of and in the same lane as vehicle 1000), while I2V communication provides information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, given information about the vehicles ahead of a given vehicle 1000, the CACC system may be more reliable and has the potential to improve the smoothness of traffic flow and reduce road congestion.

[0240] In at least one embodiment, the FCW system is designed to warn the driver of a hazard so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward camera and / or one or more RADAR sensors 1060, which are coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration component. In at least one embodiment, the FCW system may provide warnings, such as in the form of a sound, visual warning, vibration, and / or a rapid braking pulse.

[0241] In at least one embodiment, the AEB system detects an impending forward collision with another vehicle or other object and can automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system can use one or more forward cameras and / or one or more RADAR sensors 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid the collision, and, if the driver does not take corrective action, the AEB system can automatically apply the brakes in an attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system can include technologies such as dynamic brake support and / or collision imminent braking.

[0242] In at least one embodiment, when vehicle 1000 crosses a lane marking, the LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibration, to warn the driver. In at least one embodiment, the LDW system does not activate when the driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system can use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback such as a display, speaker, and / or vibration component. In at least one embodiment, the LKA system is a variant of the LDW system. In at least one embodiment, if vehicle 1000 begins to leave its lane, the LKA system provides steering input or braking to correct vehicle 1000.

[0243] In at least one embodiment, the BSW system detects and warns the driver that the vehicle is in the blind spot of an automobile. In at least one embodiment, the BSW system can provide visual, audible, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide additional warnings when the driver uses a turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to driver feedback such as a display, speaker, and / or vibration component.

[0244] In at least one embodiment, when the vehicle 1000 detects an object outside the rear camera range while reversing, the RCTW system can provide visual, audible, and / or tactile notifications. In at least one embodiment, the RCTW system includes an AEB system for ensuring that vehicle braking is applied to avoid a collision. In at least one embodiment, the RCTW system can use one or more rear-facing RADAR sensors 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback such as a display, speaker, and / or vibration component.

[0245] In at least one embodiment, conventional ADAS systems may be prone to producing false positive results, which may annoy and distract the driver, but are generally not catastrophic because conventional ADAS systems will warn the driver and allow the driver to decide whether a safety situation truly exists and take action accordingly. In at least one embodiment, in the case of conflicting results, the vehicle 1000 itself decides whether to follow the result of the main computer or the auxiliary computer (e.g., the first controller or the second controller in the controller 1036). For example, in at least one embodiment, the ADAS system 1038 can be a backup and / or auxiliary computer for providing perception information to the backup computer rationality module. In at least one embodiment, the backup computer rationality monitor can run various software redundantly on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, the output from the ADAS system 1038 can be provided to the supervisory MCU. In at least one embodiment, if the output from the main computer and the output from the auxiliary computer conflict, the supervisory MCU decides how to reconcile the conflict to ensure safe operation.

[0246] In at least one embodiment, the main computer can be configured to provide a confidence score to the supervisory MCU, which indicates the main computer's confidence in the selected result. In at least one embodiment, if this confidence score exceeds a threshold, the supervisory MCU can follow the instructions of the main computer, regardless of whether the auxiliary computer provides conflicting or inconsistent results. In at least one embodiment, in the case where the confidence score does not meet the threshold and the main computer and the auxiliary computer indicate different results (e.g., conflict), the supervisory MCU can arbitrate between the computers to determine an appropriate result.

[0247] In at least one embodiment, the supervisory MCU can be configured to run a neural network that is trained and configured to determine conditions under which the auxiliary computer provides an error alert based at least in part on outputs from the host computer and outputs from the auxiliary computer. In at least one embodiment, one or more neural networks in the supervisory MCU can learn when the output of the auxiliary computer can be trusted and when it cannot be trusted. For example, in at least one embodiment, when the auxiliary computer is a RADAR-based FCW system, one or more neural networks in the supervisory MCU can learn when the FCW system is identifying a metallic object that is not actually a hazard, such as a drainage grate or manhole cover that would trigger an alert. In at least one embodiment, when the auxiliary computer is a camera-based LDW system, the neural network in the supervisory MCU can learn to override the LDW when there is a bicyclist or pedestrian present and lane departure is actually the safest course of action. In at least one embodiment, the supervisory MCU can include at least one of a DLA or GPU suitable for running one or more neural networks with associated memory. In at least one embodiment, the supervisory MCU can be included as and / or included in components of one or more SoCs 1004.

[0248] In at least one embodiment, the ADAS system 1038 can include an auxiliary computer that performs ADAS functions using traditional computer vision rules. In at least one embodiment, the auxiliary computer can use classical computer vision rules (if-then), and the presence of one or more neural networks in the supervisory MCU can improve reliability, safety, and performance. For example, in at least one embodiment, the diverse implementation and intentional non-identity make the overall system more fault-tolerant, especially for faults caused by software (or software-hardware interface) functions. For example, in at least one embodiment, if there is a software vulnerability or error in the software running on the host computer and the not-identical software code running on the auxiliary computer provides a consistent overall result, the supervisory MCU can have greater confidence that the overall result is correct, and the vulnerability in the software or hardware on the host computer will not result in a major error.

[0249] In at least one embodiment, the output of the ADAS system 1038 can be fed into the perception block of the host computer and / or the dynamic driving task block of the host computer. For example, in at least one embodiment, if the ADAS system 1038 indicates a forward collision warning due to an object directly ahead, the perception block can use that information when the object is identified. In at least one embodiment, as described herein, the auxiliary computer can have its own neural network that is trained to reduce the risk of false alarms.

[0250] In at least one embodiment, vehicle 1000 may further include an infotainment SoC 1030 (e.g., in-vehicle infotainment (IVI)). Although shown and described as an SoC, in at least one embodiment, infotainment system SoC 1030 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, infotainment SoC 1030 may include, but is not limited to, a combination of hardware and software that may be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., television, movies, streaming, etc.), telephone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total covered distance, brake fuel level, oil level, door open / closed, air filter information, etc.) to vehicle 1000. For example, infotainment SoC 1030 may include a radio, disk player, navigation system, video player, USB and Bluetooth connectivity, in-vehicle computer, in-vehicle entertainment system, WiFi, steering wheel audio control, hands-free voice control, head-up display (“HUD”), HMI display 1034, telematics device, control panel (e.g., for controlling various components, features, and / or systems and / or interacting therewith), and / or other components. In at least one embodiment, infotainment SoC 1030 may further be used to provide information (e.g., visual and / or auditory information) to one or more users of vehicle 1000, such as information from ADAS system 1038, autonomous driving information (such as planned vehicle maneuvers), trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0251] In at least one embodiment, infotainment SoC 1030 may include any number and type of GPU functionality. In at least one embodiment, infotainment SoC 1030 may communicate with other devices, systems, and / or components of vehicle 1000 via bus 1002. In at least one embodiment, infotainment SoC 1030 may be coupled to a supervisory MCU such that the GPU of the infotainment system may perform some autonomous driving functions in the event of a failure of one or more main controllers 1036 (e.g., the main computer and / or backup computer of vehicle 1000). In at least one embodiment, infotainment SoC 1030 may place vehicle 1000 into a driver-to-safe parking mode as described herein.

[0252] In at least one embodiment, vehicle 1000 may further include a dashboard 1032 (e.g., a digital dashboard, an electronic dashboard, a digital instrument panel, etc.). In at least one embodiment, the dashboard 1032 may include, but is not limited to, a controller and / or a supercomputer (e.g., a discrete controller or supercomputer). In at least one embodiment, the dashboard 1032 may include, but is not limited to, any number and combination of a set of gauges, such as a speedometer, a fuel level, an oil pressure, a tachometer, an odometer, a turn indicator, a shift position indicator, one or more seatbelt warning lights, one or more parking brake warning lights, one or more engine malfunction lights, auxiliary restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between the infotainment SoC 1030 and the dashboard 1032. In at least one embodiment, the dashboard 1032 may be included as part of the infotainment SoC 1030, and vice versa.

[0253] In at least one embodiment, Figure 10C one or more of the systems depicted therein are used to perform the operations described herein using one or more neural networks with various algorithms, formulas, and processes (such as those incorporated Figure 1 with those described) and / or otherwise. In at least one embodiment, Figure 10C one or more of the systems depicted therein are used to implement one or more systems and / or processes (such as those incorporated Figures 1 - 6 with those described), such as to generate one or more images from text and / or otherwise perform the operations described herein using one or more neural networks based at least in part on one or more first images that do not have text indicating the content of one or more first images and one or more second images that have text indicating the content of one or more second images.

[0254] Figure 10D is according to at least one embodiment between one or more cloud-based servers and Figure 10A1000. In at least one embodiment, the system may include, but is not limited to, one or more servers 1078, one or more networks 1090, and any number and type of vehicles, including vehicle 1000. In at least one embodiment, one or more servers 1078 may include, but are not limited to, multiple GPUs 1084(A)-1084(H) (collectively referred to herein as GPUs 1084), PCIe switches 1082(A)-1082(D) (collectively referred to herein as PCIe switches 1082), and / or CPUs 1080(A)-1080(B) (collectively referred to herein as CPUs 1080). In at least one embodiment, GPUs 1084, CPUs 1080, and PCIe switches 1082 may be interconnected with a high-speed interconnect, such as, for example, but not limited to, NVLink interface 1088 and / or PCIe connection 1086 developed by NVIDIA. In at least one embodiment, the GPUs 1084 are connected via NVLink and / or NVSwitch SoCs, and the GPUs 1084 and PCIe switches 1082 are connected via PCIe interconnects. Although eight GPUs 1084, two CPUs 1080, and four PCIe switches 1082 are shown, this is not intended to be limiting. In at least one embodiment, each of the one or more servers 1078 may include, but is not limited to, any number of GPUs 1084, CPUs 1080, and / or PCIe switches 1082 in any combination. For example, in at least one embodiment, one or more servers 1078 may each include eight, sixteen, thirty-two, and / or more GPUs 1084.

[0255] In at least one embodiment, the one or more servers 1078 may receive image data representing an image from a vehicle via one or more networks 1090 that shows an unexpected or changed road condition, such as a recently started road project. In at least one embodiment, the one or more servers 1078 may send an updated neural network 1092 and / or map information 1094 to the vehicle via one or more networks 1090, including, but not limited to, information about traffic and road conditions. In at least one embodiment, updates to the map information 1094 may include, but are not limited to, updates to the HD map 1022, such as information about construction sites, potholes, access roads, flooding, and / or other obstacles. In at least one embodiment, the neural network 1092 and / or map information 1094 may have been generated by new training and / or experience represented in data received from any number of vehicles in the environment, and / or based at least on training performed at a data center (e.g., using one or more servers 1078 and / or other servers).

[0256] In at least one embodiment, one or more servers 1078 may be used to train a machine learning model (e.g., a neural network) at least in part based on training data. In at least one embodiment, the training data may be generated by a vehicle and / or may be generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is labeled (e.g., in cases where the associated neural network benefits from supervised learning) and / or undergoes other preprocessing. In at least one embodiment, no amount of training data is labeled and / or preprocessed (e.g., in cases where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model may be used by the vehicle (e.g., sent to the vehicle via one or more networks 1090), and / or the machine learning model may be used by one or more servers 1078 to remotely monitor the vehicle.

[0257] In at least one embodiment, one or more servers 1078 may receive data from a vehicle and apply the data to a latest real-time neural network for real-time intelligent inference. In at least one embodiment, one or more servers 1078 may include a deep learning supercomputer powered by one or more GPUs 1084 and / or a dedicated AI computer, such as DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1078 may include a deep learning infrastructure of a data center powered by a CPU.

[0258] In at least one embodiment, the deep learning infrastructure of one or more servers 1078 may be capable of performing fast, real-time inference and may use this ability to evaluate and verify the health of the processors, software, and / or associated hardware in vehicle 1000. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1000, such as an image sequence and / or objects located in the image sequence by vehicle 1000 (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify the objects and compare them with the objects identified by vehicle 1000, and if the results do not match and the deep learning infrastructure determines that the AI in vehicle 1000 is malfunctioning, one or more servers 1078 may send a signal to vehicle 1000 that instructs the fail-safe computer of vehicle 1000 to take control, notify the passengers, and complete a safe parking operation.

[0259] In at least one embodiment, one or more servers 1078 may include one or more GPUs 1084 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3 device). In at least one embodiment, the combination of GPU-driven servers and inference acceleration can enable real-time response. In at least one embodiment, in cases where performance is less critical, servers driven by CPUs, FPGAs, and other processors can be used for inference. In at least one embodiment, one or more hardware structures 715 are used to execute one or more embodiments. This document combines Figure 7A and / or Figure 7B to provide details about the hardware structure 715.

[0260] Computer system

[0261] Figure 11 is a block diagram showing an exemplary computer system according to at least one embodiment. The exemplary computer system can be a system with interconnected devices and components, a system-on-chip (SOC), or some combination thereof formed with a processor that can include execution units for executing instructions. In at least one embodiment, according to the present disclosure, such as in the embodiments described herein, the computer system 1100 may include, but is not limited to, components such as a processor 1102 for executing algorithms for processing data using execution units (including logic). In at least one embodiment, the computer system 1100 may include a processor, such as those available from Intel Corporation of Santa Clara, California, processor families, Xeon TM , XScale TM and / or StrongARM TM , Core TM or Nervana TM microprocessors, although other systems (including PCs, engineering workstations, set-top boxes, etc. with other microprocessors) can also be used. In at least one embodiment, the computer system 1100 can execute versions of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces can also be used.

[0262] Embodiments can be used in other devices such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, an embedded application can include a microcontroller, a digital signal processor (“DSP”), a system-on-chip, a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0263] In at least one embodiment, computer system 1100 can include, but is not limited to, a processor 1102, which can include, but is not limited to, one or more execution units 1108 for performing machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, computer system 1100 is a single-processor desktop or server system, but in another embodiment, computer system 1100 can be a multi-processor system. In at least one embodiment, processor 1102 can include, but is not limited to, for example, a complex instruction set computer (“CISC”) microprocessor, a reduced instruction set computing (“RISC”) microprocessor, a very long instruction word (“VLIW”) microprocessor, a processor implementing an instruction set combination, or any other processor device such as a digital signal processor. In at least one embodiment, processor 1102 can be coupled to a processor bus 1110, which can transfer data signals between processor 1102 and other components in computer system 1100.

[0264] In at least one embodiment, processor 1102 can include, but is not limited to, a level 1 (“L1”) internal cache memory (“cache”) 1104. In at least one embodiment, processor 1102 can have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory can reside external to processor 1102. Depending on the particular implementation and requirements, other embodiments can also include a combination of internal and external caches. In at least one embodiment, register file 1106 can store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0265] In at least one embodiment, execution unit 1108, which includes but is not limited to logic for performing integer and floating point operations, is also located within processor 1102. In at least one embodiment, processor 1102 may also include a microcode (“ucode”) read-only memory (“ROM”) that stores microcode for certain macroinstructions. In at least one embodiment, execution unit 1108 may include logic for processing a packed instruction set 1109. In at least one embodiment, by including the packed instruction set 1109 in the instruction set of a general-purpose processor and the associated circuitry that is to execute the instructions, operations used by many multimedia applications can be performed using packed data in processor 1102. In at least one embodiment, many multimedia applications can be accelerated and executed more efficiently by performing operations on packed data using the full width of the processor's data bus, which can eliminate the need to transfer smaller data units on the processor's data bus to perform one or more operations on one data element at a time.

[0266] In at least one embodiment, execution unit 1108 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1100 may include but is not limited to memory 1120. In at least one embodiment, memory 1120 may be a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, or other memory device. In at least one embodiment, memory 1120 may store one or more instructions 1119 and / or data 1121 represented by data signals that may be executed by processor 1102.

[0267] In at least one embodiment, a system logic chip may be coupled to a processor bus 1110 and a memory 1120. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 1116, and a processor 1102 may communicate with the MCH 1116 via the processor bus 1110. In at least one embodiment, the MCH 1116 may provide a high-bandwidth memory path 1118 to the memory 1120 for instruction and data storage and for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1116 may direct data signals among the processor 1102, the memory 1120, and other components in the computer system 1100, and may bridge data signals among the processor bus 1110, the memory 1120, and the system I / O interface 1122. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1116 may be coupled to the memory 1120 via the high-bandwidth memory path 1118, and a graphics / video card 1112 may be coupled to the MCH 1116 via an Accelerated Graphics Port (“AGP”) interconnect 1114.

[0268] In at least one embodiment, the computer system 1100 may use the system I / O interface 1122 as a proprietary hub interface bus to couple the MCH 1116 to an I / O controller hub (“ICH”) 1130. In at least one embodiment, the ICH 1130 may provide a direct connection to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 1120, the chipset, and the processor 1102. Examples may include, but are not limited to, an audio controller 1129, a firmware hub (“flash BIOS”) 1128, a wireless transceiver 1126, a data storage 1124, a legacy I / O controller 1123 that includes a user input and keyboard interface 1125, a serial expansion port 1127 (such as a Universal Serial Bus (“USB”) port), and a network controller 1134. In at least one embodiment, the data storage 1124 may include a hard disk driver, a floppy disk driver, a CD-ROM device, a flash device, or other mass storage devices.

[0269] In at least one embodiment, Figure 11 a system including interconnected hardware devices or “chips” is shown, while in other embodiments, Figure 11 an exemplary SoC may be shown. In at least one embodiment, Figure 11The devices shown in [the figure] can be interconnected using proprietary interconnections, standardized interconnections (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 1100 are interconnected using Compute Express Link (CXL) interconnections.

[0270] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 715 are provided herein in connection with Figure 7A and / or Figure 7B In at least one embodiment, logic 715 can be used in computer system 1100 to perform inference or prediction operations at least in part based on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0271] In at least one embodiment, Figure 11 one or more of the systems depicted in [the figure] are used to perform one or more operations described herein using one or more neural networks having various algorithms, formulas, and procedures (such as those described in connection with Figure 1 ). In at least one embodiment, Figure 11 one or more of the systems depicted in [the figure] are used to implement one or more systems and / or processes (such as those described in connection with Figures 1 - 6 ), such as to generate one or more images from text using one or more neural networks based at least in part on one or more first images that do not have text indicating the content of the one or more first images and one or more second images that have text indicating the content of the one or more second images and / or otherwise perform the operations described herein.

[0272] Figure 12 is a block diagram showing an electronic device 1200 for utilizing a processor 1210 according to at least one embodiment. In at least one embodiment, the electronic device 1200 can be, for example but not limited to, a laptop computer, a tower server, a rack server, a blade server, a laptop, a desktop computer, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0273] In at least one embodiment, the electronic device 1200 can include, but is not limited to, a processor 1210 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor 1210 is coupled using a bus or interface, such as I 2C bus, System Management Bus (“SMBus”), Low Pin Count (LPC) bus, Serial Peripheral Interface (“SPI”), High Definition Audio (“HDA”) bus, Serial Advanced Technology Attachment (“SATA”) bus, Universal Serial Bus (“USB”) (versions 1, 2, 3, etc.) or Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, Figure 12 a system is shown that includes interconnected hardware devices or “chips”, and in other embodiments, Figure 12 an exemplary SoC may be shown. In at least one embodiment, Figure 12 the devices shown therein may be interconnected using a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 12 one or more components of are interconnected using Compute Express Link (CXL) interconnects.

[0274] In at least one embodiment, Figure 12 may include a display 1224, a touch screen 1225, a touchpad 1230, a Near Field Communication unit (“NFC”) 1245, a sensor hub 1240, a thermal sensor 1246, an Embedded Controller (“EC”) 1235, a Trusted Platform Module (“TPM”) 1238, BIOS / Firmware / Flash (“BIOS, FW Flash”) 1222, a DSP 1260, drivers 1220 (such as Solid State Disk (“SSD”) or Hard Disk Driver (“HDD”)), a Wireless Local Area Network unit (“WLAN”) 1250, a Bluetooth unit 1252, a Wireless Wide Area Network unit (“WWAN”) 1256, a Global Positioning System (GPS) unit 1255, a camera (“USB 3.0 camera”) 1254 (such as a USB 3.0 camera) and / or a Low Power Double Data Rate (“LPDDR”) memory unit (“LPDDR3”) 1215 implemented, for example, to the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0275] In at least one embodiment, other components may be communicatively coupled to the processor 1210 via the components described herein. In at least one embodiment, the accelerometer 1241, ambient light sensor (“ALS”) 1242, compass 1243, and gyroscope 1244 may be communicatively coupled to the sensor hub 1240. In at least one embodiment, the thermal sensor 1239, fan 1237, keyboard 1236, and touchpad 1230 may be communicatively coupled to the EC 1235. In at least one embodiment, the speaker 1263, headphones 1264, and microphone (“mic”) 1265 may be communicatively coupled to the audio unit (“audio codec and class-D amplifier”) 1262, which may in turn be communicatively coupled to the DSP 1260. In at least one embodiment, the audio unit 1262 may include, for example but not limited to, an audio encoder / decoder (“codec”) and a class-D amplifier. In at least one embodiment, the SIM card (“SIM”) 1257 may be communicatively coupled to the WWAN unit 1256. In at least one embodiment, components such as the WLAN unit 1250, the Bluetooth unit 1252, and the WWAN unit 1256 may be implemented in a next-generation form factor (“NGFF”).

[0276] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the logic 715 are provided herein in connection with Figure 7A and / or Figure 7B In at least one embodiment, the logic 715 may be used in the electronic device 1200 to perform inference or prediction operations at least in part based on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0277] In at least one embodiment, Figure 12 one or more of the systems depicted in Figure 1 are used to perform the operations described herein using one or more neural networks having various algorithms, formulas, and procedures (such as those described in connection with Figure 12 one or more of the systems depicted in Figures 1 - 6 are used to implement one or more systems and / or processes (such as those described in connection with

[0278] Figure 13FIG. 1300 shows a computer system in accordance with at least one embodiment. In at least one embodiment, the computer system 1300 is configured to implement the various processes and methods described throughout this disclosure.

[0279] In at least one embodiment, the computer system 1300 includes, but is not limited to, at least one central processing unit (“CPU”) 1302, which is connected to a communication bus 1310 implemented using any suitable protocol, such as PCI (“Peripheral Component Interconnect”), Peripheral Component Interconnect Express (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, the computer system 1300 includes, but is not limited to, a main memory 1304 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in the main memory 1304, which may take the form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“network interface”) 1322 provides an interface to other computing devices and networks for receiving data from other systems and transmitting data to other systems using the computer system 1300.

[0280] In at least one embodiment, the computer system 1300 includes, but is not limited to, an input device 1308, a parallel processing system 1312, and a display device 1306 in at least one embodiment, which may be implemented using a conventional cathode ray tube (“CRT”), liquid crystal display (“LCD”), light emitting diode (“LED”) display, plasma display, or other suitable display technology. In at least one embodiment, user input is received from the input device 1308, such as a keyboard, mouse, touchpad, microphone, etc. In at least one embodiment, each module described herein may be located on a single semiconductor platform to form a processing system.

[0281] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 715 are provided herein in connection with Figure 7A and / or Figure 7B In at least one embodiment, the logic 715 may be used in the computer system 1300 to perform inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0282] In at least one embodiment, Figure 13 one or more of the systems depicted in Figure 1 are used to perform the operations described herein using one or more neural networks with various algorithms, formulas, and processes (such as those described in connection withFigure 13 One or more systems depicted are used to implement one or more systems and / or processes (such as those associated with Figures 1 - 6 those described), such as to generate one or more images from text using one or more neural networks based at least in part on one or more first images that do not have text indicating the content of the one or more first images and one or more second images that have text indicating the content of the one or more second images and / or to otherwise perform the operations described herein.

[0283] Figure 14 FIG. 1400 shows a computer system 1400 according to at least one embodiment. In at least one embodiment, computer system 1400 includes, but is not limited to, computer 1410 and USB drive 1420. In at least one embodiment, computer 1410 may include, but is not limited to, any number and type of processors (not shown) and memories (not shown). In at least one embodiment, computer 1410 includes, but is not limited to, servers, cloud instances, laptop computers, and desktop computers.

[0284] In at least one embodiment, USB drive 1420 includes, but is not limited to, processing unit 1430, USB interface 1440, and USB interface logic 1450. In at least one embodiment, processing unit 1430 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, processing unit 1430 may include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, processing unit 1430 includes an application specific integrated circuit (“ASIC”) that is optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, processing unit 1430 is a tensor processing unit (“TPC”) that is optimized to perform machine learning inference operations. In at least one embodiment, processing unit 1430 is a vision processing unit (“VPU”) that is optimized to perform machine vision and machine learning inference operations.

[0285] In at least one embodiment, USB interface 1440 can be any type of USB connector or USB socket. For example, in at least one embodiment, USB interface 1440 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, USB interface 1440 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1450 may include any number and type of logic that enables processing unit 1430 to interface with a device (such as computer 1410) via USB connector 1440.

[0286] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. This is described herein in connection with Figure 7A and / or Figure 7B which provide details regarding Logic 715. In at least one embodiment, Logic 715 may be used in a computer system 1400 to perform inference or prediction operations at least in part based on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0287] In at least one embodiment, Figure 14 one or more of the systems depicted in are used to perform operations described herein using one or more neural networks having various algorithms, formulas, and procedures (such as those described in connection with Figure 1 and / or otherwise). In at least one embodiment, Figure 14 one or more of the systems depicted in are used to implement one or more systems and / or processes (such as those described in connection with Figures 1 - 6 such as to generate one or more images from text using one or more neural networks at least in part based on one or more first images that do not have text indicating the content of the one or more first images and one or more second images that have text indicating the content of the one or more second images and / or otherwise perform operations described herein.

[0288] Figure 15A An exemplary architecture is shown where multiple GPUs 1510(1)-1510(N) are communicatively coupled to multiple multi-core processors 1505(1)-1505(M) via high-speed links 1540(1)-1540(N) (e.g., buses, point-to-point interconnects, etc.). In at least one embodiment, the high-speed links 1540(1)-1540(N) support a communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or higher. In at least one embodiment, various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, "N" and "M" represent positive integers, whose values may vary from figure to figure. In at least one embodiment, one or more of the multiple GPUs 1510(1)-1510(N) include as Figure 18A and Figure 18BOne or more graphics cores (also simply referred to as "cores") 1800 are disclosed. In at least one embodiment, one or more graphics cores 1800 may be referred to as a streaming multiprocessor ("SM"), stream processor ("SP"), stream processing unit ("SPU"), compute unit ("CU"), execution unit ("EU"), and / or slice, where a slice in this context may refer to a portion of the processing resources in a processing unit (e.g., 16 cores, ray tracing units, thread directors or schedulers).

[0289] In addition, in at least one embodiment, two or more GPUs 1510 are interconnected by high-speed links 1529(1)-1529(2), and the high-speed links may be implemented using a protocol / link similar to or different from the protocol / link used for high-speed links 1540(1)-1540(N). Similarly, two or more multi-core processors 1505 may be connected by a high-speed link 1528, and the high-speed link may be a symmetric multiprocessor (SMP) bus operating at a speed of 20 GB / s, 30 GB / s, 120 GB / s or higher. Alternatively, similar protocols / links (e.g., through a common interconnect structure) may be used to complete Figure 15A all communications between the various system components shown.

[0290] In at least one embodiment, each multi-core processor 1505 is communicatively coupled to a processor memory 1501(1)-1501(M) via a memory interconnect 1526(1)-1526(M) respectively, and each GPU 1510(1)-1510(N) is communicatively coupled to a GPU memory 1520(1)-1520(N) through a GPU memory interconnect 1550(1)-1550(N) respectively. In at least one embodiment, the memory interconnects 1526 and 1550 may utilize similar or different memory access techniques. By way of example and not limitation, the processor memories 1501(1)-1501(M) and the GPU memory 1520 may be volatile memories such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memories such as 3D XPoint or Nano-Ram. In at least one embodiment, some portions of the processor memory 1501 may be volatile memories while another portion may be non-volatile memories (e.g., using a two-level memory (2LM) hierarchy).

[0291] As described herein, although each multi-core processor 1505 and GPU 1510 may be physically coupled to specific memories 1501, 1520, respectively, and / or a unified memory architecture may be implemented, where a virtual system address space (also referred to as the "effective address" space) is distributed among the respective physical memories. For example, processor memories 1501(1)-1501(M) may each include 64 GB of system memory address space, and GPU memories 1520(1)-1520(N) may each include 32 GB of system memory address space, such that when M = 2 and N = 4, a total of 256 GB of addressable memory results. Other values of N and M are possible.

[0292] Figure 15B Additional details of the interconnection between multi-core processor 1507 and graphics acceleration module 1546 are shown in accordance with one exemplary embodiment. In at least one embodiment, graphics acceleration module 1546 may include one or more GPU chips integrated on a line card that is coupled to processor 1507 via a high-speed link 1540 (e.g., PCIe bus, NVLink, etc.). In at least one embodiment, graphics acceleration module 1546 may alternatively be integrated on a package or chip with processor 1507.

[0293] In at least one embodiment, processor 1507 includes multiple cores 1560A-1560D (which may be referred to as "execution units"), each core having a translation lookaside buffer ("TLB") 1561A-1561D and one or more caches 1562A-1562D. In at least one embodiment, cores 1560A-1560D may include various other components (not shown) for executing instructions and processing data. In at least one embodiment, caches 1562A-1562D may include level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 1556 may be included within caches 1562A-1562D and shared by groups of cores 1560A-1560D. For example, one embodiment of processor 1507 includes 24 cores, each having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, processor 1507 and graphics acceleration module 1546 are connected to system memory 1514, which may include Figure 15A processor memories 1501(1)-1501(M) therein.

[0294] In at least one embodiment, cache coherence for data and instructions stored in respective caches 1562A - 1562D, 1556, and system memory 1514 is maintained via an inter - core communication through coherence bus 1564. In at least one embodiment, for example, each cache may have cache coherence logic / circuit associated therewith to communicate through coherence bus 1564 in response to detecting a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented via coherence bus 1564 to snoop cache accesses.

[0295] In at least one embodiment, proxy circuit 1525 communicatively couples graphics acceleration module 1546 to coherence bus 1564, thereby allowing graphics acceleration module 1546 to participate in the cache coherence protocol as a peer to cores 1560A - 1560D. In particular, in at least one embodiment, interface 1535 provides a connection to proxy circuit 1525 via high - speed link 1540, and interface 1537 connects graphics acceleration module 1546 to high - speed link 1540.

[0296] In at least one embodiment, accelerator integrated circuit 1536 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 1531(1)-1531(N) of graphics acceleration module 1546. In at least one embodiment, graphics processing engines 1531(1)-1531(N) may each include a separate graphics processing unit (GPU). In at least one embodiment, the multiple graphics processing engines 1531(1)-1531(N) of graphics acceleration module 1546 include one or more graphics cores 1800, as discussed in conjunction with Figure 18A and Figure 18B as discussed. In at least one embodiment, graphics processing engines 1531(1)-1531(N) may alternatively include different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoder / decoder), samplers, and blit engines. In at least one embodiment, graphics acceleration module 1546 may be a GPU having multiple graphics processing engines 1531(1)-1531(N), or graphics processing engines 1531(1)-1531(N) may be individual GPUs integrated on a common package, line card, or chip.

[0297] In at least one embodiment, the accelerator integrated circuit 1536 includes a memory management unit (MMU) 1539 for performing various memory management functions such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and also includes a memory access protocol for accessing system memory 1514. In at least one embodiment, the MMU 1539 may also include a translation lookaside buffer ("TLB") (not shown) for caching virtual / effective-to-physical / real address translations. In at least one embodiment, the cache 1538 may store commands and data for efficient access by the graphics processing engines 1531(1)-1531(N). In at least one embodiment, an acquisition unit 1544 may be used to keep the data stored in the cache 1538 and the graphics memories 1533(1)-1533(M) consistent with the core caches 1562A-1562D, 1556, and the system memory 1514. As previously described, this may be representative of the cache 1538 and the memories 1533(1)-1533(M) being implemented via the proxy circuit 1525 (e.g., sending updates related to modifications / accesses of cache lines on the processor caches 1562A-1562D, 1556 to the cache 1538 and receiving updates from the cache 1538).

[0298] In at least one embodiment, a set of registers 1545 stores context data for threads executed by the graphics processing engines 1531(1)-1531(N), and a context management circuit 1548 manages thread contexts. For example, the context management circuit 1548 may perform save and restore operations to save and restore the contexts of individual threads during a context switch (e.g., where the first thread is saved and the second thread is stored so that the second thread can be executed by the graphics processing engine). For example, the context management circuit 1548 may store the current register values into a specified area in memory (e.g., identified by a context pointer) during a context switch. Then, the register values can be restored when returning to the context. In at least one embodiment, an interrupt management circuit 1547 receives and processes interrupts received from system devices.

[0299] In at least one embodiment, the MMU 1539 converts virtual / valid addresses from the graphics processing engine 1531 into real / physical addresses in the system memory 1514. In at least one embodiment, the accelerator integrated circuit 1536 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1546 and / or other accelerator devices. In at least one embodiment, the graphics accelerator module 1546 can be dedicated to a single application executing on the processor 1507 or can be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented where the resources of the graphics processing engines 1531(1)-1531(N) are shared among multiple applications or virtual machines (VMs). In at least one embodiment, the resources can be subdivided into "slices" based on the processing requirements and priorities associated with the VMs and / or applications and assigned to different VMs and / or applications.

[0300] In at least one embodiment, the accelerator integrated circuit 1536 functions as a bridge for the system of the graphics accelerator modules 1546 and provides address translation and system memory cache services. Additionally, in at least one embodiment, the accelerator integrated circuit 1536 can provide virtualization facilities for the host processor to manage the virtualization, interrupts, and memory management of the graphics processing engines 1531(1)-1531(N).

[0301] In at least one embodiment, since the hardware resources of the graphics processing engines 1531(1)-1531(N) are explicitly mapped to the real address space seen by the host processor 1507, any host processor can directly address these resources using valid address values. In at least one embodiment, one function of the accelerator integrated circuit 1536 is the physical separation of the graphics processing engines 1531(1)-1531(N) such that they appear as independent units to the system.

[0302] In at least one embodiment, one or more graphics memories 1533(1)-1533(M) are coupled to each of the graphics processing engines 1531(1)-1531(N), and N = M. In at least one embodiment, the graphics memories 1533(1)-1533(M) store the instructions and data being processed by each of the graphics processing engines 1531(1)-1531(N). In at least one embodiment, the graphics memories 1533(1)-1533(M) can be volatile memories such as DRAM (including stacked DRAM), GDDR memories (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memories such as 3D XPoint or Nano-Ram.

[0303] In at least one embodiment, to reduce data traffic on the high-speed link 1540, a biasing technique can be used to ensure that the data stored in the graphics memories 1533(1)-1533(M) is the data most frequently used by the graphics processing engines 1531(1)-1531(N), and preferably is data not used (at least not frequently used) by the cores 1560A-1560D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep the data needed by the cores (and preferably not needed by the graphics processing engines 1531(1)-1531(N)) in the caches 1562A-1562D, 1556, and the system memory 1514.

[0304] Figure 15C Another exemplary embodiment is shown in which the accelerator integrated circuit 1536 is integrated within the processor 1507. In this embodiment, the graphics processing engines 1531(1)-1531(N) communicate directly with the accelerator integrated circuit 1536 via the interfaces 1537 and 1535 (again, which can be any form of bus or interface protocol) over the high-speed link 1540. In at least one embodiment, the accelerator integrated circuit 1536 may perform operations similar to those described with respect to Figure 15B but may have higher throughput due to its close proximity to the coherence bus 1564 and the caches 1562A-1562D, 1556. In at least one embodiment, the accelerator integrated circuit supports different programming models, which include a process-specific programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), and the programming models may include a programming model controlled by the accelerator integrated circuit 1536 and a programming model controlled by the graphics acceleration module 1546.

[0305] In at least one embodiment, the graphics processing engines 1531(1)-1531(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to the graphics processing engines 1531(1)-1531(N), thereby providing virtualization within the VM / partition.

[0306] In at least one embodiment, the graphics processing engines 1531(1)-1531(N) can be shared by multiple VM / application partitions. In at least one embodiment, a sharing model can use a hypervisor to virtualize the graphics processing engines 1531(1)-1531(N) to allow each operating system to access them. In at least one embodiment, for a single-partition system without a hypervisor, the operating system owns the graphics processing engines 1531(1)-1531(N). In at least one embodiment, the operating system can virtualize the graphics processing engines 1531(1)-1531(N) to provide access to each process or application.

[0307] In at least one embodiment, the graphics acceleration module 1546 or individual graphics processing engines 1531(1)-1531(N) use a process handle to select process elements. In at least one embodiment, the process elements are stored in the system memory 1514 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle can be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engines 1531(1)-1531(N) (i.e., calling the system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle can be the offset of the process element in the process element linked list.

[0308] Figure 15D An exemplary accelerator integration slice 1590 is shown. In at least one embodiment, a "slice" includes a specified portion of the processing resources of the accelerator integrated circuit 1536. In at least one embodiment, an application is an effective address space 1582 in the system memory 1514 that stores process elements 1583. In at least one embodiment, in response to a GPU call 1581 from an application 1580 executing on the processor 1507, the process element 1583 is stored. In at least one embodiment, the process element 1583 contains the process state of the corresponding application 1580. In at least one embodiment, the work descriptor (WD) 1584 contained in the process element 1583 can be a single job requested by the application or can contain a pointer to a job queue. In at least one embodiment, the WD 1584 is a pointer to a job request queue in the effective address space 1582 of the application.

[0309] In at least one embodiment, the graphics acceleration module 1546 and / or each of the graphics processing engines 1531(1)-1531(N) may be shared by all processes or a subset of processes in the system. In at least one embodiment, an infrastructure may be included for setting process states and sending a WD 1584 to the graphics acceleration module 1546 to start a job in a virtualized environment.

[0310] In at least one embodiment, the process-specific programming model is implementation-specific. In at least one embodiment, in this model, a single process owns the graphics acceleration module 1546 or an individual graphics processing engine 1531. In at least one embodiment, when the graphics acceleration module 1546 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 1536 for the owned partition, and when the graphics acceleration module 1546 is assigned, the operating system initializes the accelerator integrated circuit 1536 for the owned process.

[0311] In at least one embodiment, in operation, the WD fetch unit 1591 in the accelerator integration slice 1590 fetches the next WD 1584, which includes an indication of work to be completed by one or more of the graphics processing engines of the graphics acceleration module 1546. In at least one embodiment, data from the WD 1584 may be stored in the register 1545 and used by the MMU 1539, the interrupt management circuit 1547, and / or the context management circuit 1548, as shown. For example, one embodiment of the MMU 1539 includes a segment / page walk circuit for accessing the segment / page table 1586 within the OS virtual address space 1585. In at least one embodiment, the interrupt management circuit 1547 may process the interrupt event 1592 received from the graphics acceleration module 1546. In at least one embodiment, when performing a graphics operation, the virtual address 1593 generated by the graphics processing engines 1531(1)-1531(N) is converted to a physical address by the MMU 1539.

[0312] In at least one embodiment, the register 1545 is replicated for each of the graphics processing engines 1531(1)-1531(N) and / or the graphics acceleration module 1546, and the register 1545 may be initialized by the hypervisor or the operating system. In at least one embodiment, each of these replicated registers may be included in the accelerator integration slice 1590. Exemplary registers that may be initialized by the hypervisor are shown in Table 1.

[0313] Table 1 - Registers Initialized by the Hypervisor

[0314]

[0315] Exemplary registers that can be initialized by the operating system are shown in Table 2.

[0316] Table 2 - Registers Initialized by the Operating System

[0317]

[0318] In at least one embodiment, each WD 1584 is specific to a particular graphics acceleration module 1546 and / or graphics processing engine 1531(1)-1531(N). In at least one embodiment, it contains all the information required for the graphics processing engine 1531(1)-1531(N) to complete its work, or it can be a pointer to a memory location where the application has set up a command queue for the work to be done.

[0319] Figure 15E Additional details of an exemplary embodiment of the shared model are shown. This embodiment includes a hypervisor real address space 1598 in which a list of process elements 1599 is stored. In at least one embodiment, the hypervisor real address space 1598 can be accessed via the hypervisor 1596, which virtualizes the graphics acceleration module engine for the operating system 1595.

[0320] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 1546. In at least one embodiment, there are two programming models in which the graphics acceleration module 1546 is shared by multiple processes and partitions, namely time-slicing sharing and graphics-directed sharing.

[0321] In at least one embodiment, in this model, the system hypervisor 1596 owns the graphics acceleration module 1546 and makes its functions available to all operating systems 1595. In at least one embodiment, for the graphics acceleration module 1546 to support virtualization through the system hypervisor 1596, the graphics acceleration module 1546 may have to comply with certain requirements, such as (1) the job requests of the application must be autonomous (i.e., do not require maintaining state between jobs), or the graphics acceleration module 1546 must provide a context save and restore mechanism, (2) the graphics acceleration module 1546 guarantees that the job requests of the application are completed within a specified amount of time, including any translation errors, or the graphics acceleration module 1546 provides the ability to preempt job processing, and (3) when operating in the directed sharing programming model, it must be ensured that the graphics acceleration module 1546 is fair among processes.

[0322] In at least one embodiment, application 1580 is required to use a graphics acceleration module type, a work descriptor (WD), a permission mask register (AMR) value, and a context save / restore area pointer (CSRP) for an operating system 1595 system call. In at least one embodiment, the graphics acceleration module type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1546 and can take the form of a graphics acceleration module 1546 command, a valid address pointer to a user-defined structure, a valid address pointer to a command queue, or any other data structure that describes the work to be done by the graphics acceleration module 1546.

[0323] In at least one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to the application that sets the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1536 (not shown) and the graphics acceleration module 1546 does not support the user permission mask override register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in a hypervisor call. In at least one embodiment, the hypervisor 1596 can selectively apply the current permission mask override register (AMOR) value before placing the AMR in the process element 1583. In at least one embodiment, the CSRP is one of the registers 1545 that contains the valid address of a region in the valid address space 1582 of the application for the graphics acceleration module 1546 to save and restore the context state. In at least one embodiment, this pointer is optional if state saving between jobs is not required or when a job is preempted. In at least one embodiment, the context save / restore area can be a fixed system memory.

[0324] Upon receiving the system call, the operating system 1595 can verify that the application 1580 has been registered and granted permission to use the graphics acceleration module 1546. Then, in at least one embodiment, the operating system 1595 uses the information shown in Table 3 to call the hypervisor 1596.

[0325] Table 3 - Operating System to Hypervisor Call Parameters

[0326]

[0327] In at least one embodiment, upon receiving a hypervisor call, the hypervisor 1596 verifies that the operating system 1595 is registered and has been granted permission to use the graphics acceleration module 1546. Then, in at least one embodiment, the hypervisor 1596 places the process element 1583 into a process element linked list corresponding to the type of the graphics acceleration module 1546. In at least one embodiment, the process element may include the information shown in Table 4.

[0328] Table 4 - Process Element Information

[0329]

[0330] In at least one embodiment, the hypervisor initializes the registers 1545 of the multiple accelerator integration slices 1590.

[0331] As Figure 15F shown, in at least one embodiment, a unified memory is used, and the unified memory can be addressed via a common virtual memory address space for accessing the physical processor memories 1501(1)-1501(N) and the GPU memories 1520(1)-1520(N). In this implementation, operations executed on the GPUs 1510(1)-1510(N) utilize the same virtual / effective memory address space to access the processor memories 1501(1)-1501(M), and vice versa, thus simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to the processor memory 1501(1), a second portion is allocated to the second processor memory 1501(N), a third portion is allocated to the GPU memory 1520(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of the processor memories 1501 and the GPU memories 1520, allowing any processor or GPU to access the memory using a virtual address mapped to any physical memory.

[0332] In at least one embodiment, the bias / coherency management circuits 1594A-1594E within one or more MMUs 1539A-1539E ensure cache coherency between one or more host processors (e.g., 1505) and the caches of the GPUs 1510, and implement a bias technique for indicating the physical memory in which certain types of data should be stored. In at least one embodiment, although multiple instances of the bias / coherency management circuits 1594A-1594E are shown in Figure 15F , the bias / coherency circuits may be implemented within the MMUs of one or more host processors 1505 and / or within the accelerator integrated circuit 1536.

[0333] One embodiment allows the GPU memory 1520 to be mapped as part of the system memory and accessed using shared virtual memory (SVM) technology, without suffering from the performance drawbacks associated with full-system cache coherence. In at least one embodiment, the ability of the GPU memory 1520 to be accessed as system memory without heavy cache coherence overhead provides a favorable operating environment for GPU offloading. In at least one embodiment, this arrangement allows the software of the host processor 1505 to set operands and access computation results without the overhead of traditional I / O DMA data copying. In at least one embodiment, such traditional copying includes driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, which are all less efficient than simple memory accesses. In at least one embodiment, the ability to access the GPU memory 1520 without cache coherence overhead can be critical to the execution time of offloaded computations. In at least one embodiment, for example, in the case of a large amount of streaming write memory traffic, the cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPU 1510. In at least one embodiment, the efficiency of operand setting, the efficiency of result access, and the efficiency of GPU computation may play a role in determining the effectiveness of GPU offloading.

[0334] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table may be used, which may be a page-granularity structure (e.g., controlled at the granularity of memory pages), and this page-granularity structure includes 1 or 2 bits per GPU-attached memory page. In at least one embodiment, with or without a bias cache in the GPU 1510 (e.g., for caching frequently / most recently used entries of the bias table), the bias table may be implemented in the stolen memory ranges of one or more GPU memories 1520. Alternatively, in at least one embodiment, the entire bias table may be maintained within the GPU.

[0335] In at least one embodiment, before actually accessing the GPU memory, the bias table entry associated with each access to the GPU attached memory 1520 is accessed, thereby causing the following operations. In at least one embodiment, a local request from the GPU 1510 that finds its page in the GPU bias is directly forwarded to the corresponding GPU memory 1520. In at least one embodiment, a local request from the GPU that finds its page in the host bias is forwarded to the processor 1505 (e.g., via the high-speed link described herein). In at least one embodiment, a request from the processor 1505 that finds the requested page in the host processor bias completes a request similar to a normal memory read. Alternatively, a request pointing to a GPU bias page can be forwarded to the GPU 1510. In at least one embodiment, if the GPU is not currently using a page, the GPU can migrate the page to the host processor bias. In at least one embodiment, the bias state of a page can be changed by a software-based mechanism, a software mechanism assisted by hardware, or in a limited set of cases by a purely hardware-based mechanism.

[0336] In at least one embodiment, a mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn calls the device driver of the GPU, which in turn sends a message (or enqueues a command descriptor) to the GPU, instructing the GPU to change the bias state and perform a cache flush operation in the host in certain migrations. In at least one embodiment, the cache flush operation is used for migrating from the host processor 1505 bias to the GPU bias, but not for the reverse migration.

[0337] In at least one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that cannot be cached by the host processor 1505. In at least one embodiment, to access these pages, the processor 1505 can request access from the GPU 1510, and the GPU 1510 may or may not immediately grant access. Thus, in at least one embodiment, to reduce communication between the processor 1505 and the GPU 1510, it is beneficial to ensure that GPU bias pages are pages required by the GPU rather than the host processor 1505, and vice versa.

[0338] One or more hardware structures 715 are used to execute one or more embodiments. Details regarding one or more hardware structures 715 may be provided herein in conjunction with Figure 7A and / or Figure 7B provide details about one or more hardware structures 715.

[0339] Figure 16An exemplary integrated circuit and associated graphics processor in accordance with various embodiments described herein are shown, which may be fabricated using one or more IP cores. In addition to those illustrated, other logic and circuitry may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0340] Figure 16 is a block diagram of an exemplary system on a chip integrated circuit 1600 that may be fabricated using one or more IP cores. In at least one embodiment, integrated circuit 1600 includes one or more application processors 1605 (e.g., CPUs), at least one graphics processor 1610, and may additionally include an image processor 1615 and / or a video processor 1620, any of which may be a modular IP core. In at least one embodiment, integrated circuit 1600 includes peripheral or bus logic, which includes a USB controller 1625, a UART controller 1630, an SPI / SDIO controller 1635, and an 2 S / I 2 C controller 1640. In at least one embodiment, integrated circuit 1600 may include a display device 1645 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1650 and a mobile industry processor interface (MIPI) display interface 1655. In at least one embodiment, storage may be provided by a flash memory subsystem 1660, which includes flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1665 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1670.

[0341] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 715 are provided herein in connection with Figure 7A and / or Figure 7B In at least one embodiment, logic 715 may be in integrated circuit 1600 for inferring or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0342] In at least one embodiment, Figures 15A - 16 one or more of the systems depicted in Figure 1 are used to perform the operations described herein using one or more neural networks having various algorithms, formulas, and procedures (such as those described in connection with Figures 15A - 16One or more systems depicted herein are used to implement one or more systems and / or processes (such as those associated with Figures 1 - 6 described), such as to generate one or more images from text using one or more neural networks based at least in part on one or more first images that do not have text indicating the content of the one or more first images and one or more second images that have text indicating the content of the one or more second images and / or to otherwise perform the operations described herein.

[0343] Figures 17A - 17B An exemplary integrated circuit and associated graphics processor in accordance with various embodiments described herein are shown, which may be fabricated using one or more IP cores. In addition to those illustrated, other logic and circuitry may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general processor cores.

[0344] Figures 17A - 17B is a block diagram showing an exemplary graphics processor used within a SoC in accordance with embodiments described herein. Figure 17A An exemplary graphics processor 1710 of a system-on-chip integrated circuit in accordance with at least one embodiment is shown, which may be fabricated using one or more IP cores. Figure 17B An additional exemplary graphics processor 1740 of a system-on-chip integrated circuit in accordance with at least one embodiment is shown, which may be fabricated using one or more IP cores. In at least one embodiment, Figure 17A the graphics processor 1710 is a low-power graphics processor core. In at least one embodiment, Figure 17B the graphics processor 1740 is a higher-performance graphics processor core. In at least one embodiment, each graphics processor 1710, 1740 may be a Figure 16 variant of the graphics processor 1610.

[0345] In at least one embodiment, the graphics processor 1710 includes a vertex processor 1705 and one or more fragment processors 1715A - 1715N (e.g., 1715A, 1715B, 1715C, 1715D to 1715N - 1, and 1715N). In at least one embodiment, the graphics processor 1710 can execute different shader programs via separate logic such that the vertex processor 1705 is optimized to perform operations for vertex shader programs, while the one or more fragment processors 1715A - 1715N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 1705 executes the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the one or more fragment processors 1715A - 1715N use the primitives and vertex data generated by the vertex processor 1705 to produce a frame buffer for display on a display device. In at least one embodiment, the one or more fragment processors 1715A - 1715N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to pixel shader programs provided in the Direct 3D API.

[0346] In at least one embodiment, the graphics processor 1710 additionally includes one or more memory management units (MMUs) 1720A - 1720B, one or more caches 1725A - 1725B, and one or more circuit interconnects 1730A - 1730B. In at least one embodiment, the one or more MMUs 1720A - 1720B provide virtual - to - physical address mapping for the graphics processor 1710 (including for the vertex processor 1705 and / or the fragment processors 1715A - 1715N), and in addition to vertex or image / texture data stored in the one or more caches 1725A - 1725B, it can also reference vertex or image / texture data stored in memory. In at least one embodiment, the one or more MMUs 1720A - 1720B can be synchronized with other MMUs within the system, including one or more MMUs associated with Figure 16 one or more application processors 1605, image processors 1615, and / or video processors 1620 such that each processor 1605 - 1620 can participate in a shared or unified virtual memory system. In at least one embodiment, the one or more circuit interconnects 1730A - 1730B enable the graphics processor 1710 to interface with other IP cores within the SoC via the internal bus of the SoC or via a direct connection.

[0347] In at least one embodiment, the graphics processor 1740 includes asFigure 17B One or more shader cores 1755A - 1755N (e.g., 1755A, 1755B, 1755C, 1755D, 1755E, 1755F to 1755N - 1, and 1755N) as shown, which provide a unified shader core architecture where a single core or type of core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1740 includes an inter - core task manager 1745, which acts as a thread dispatcher for dispatching execution threads to one or more shader cores 1755A - 1755N and a tiling unit 1758 to accelerate tiling operations for tile - based rendering, where the rendering operation of a scene is subdivided in the image space, e.g., to take advantage of local spatial coherence within the scene or optimize the use of internal caches.

[0348] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the logic 715 are provided herein in conjunction with Figure 7A and / or Figure 7B In at least one embodiment, the logic 715 can be used in the graphics processor 1710 and / or 1740 to perform inference or prediction operations at least in part based on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0349] In at least one embodiment, Figures 17A - 17B One or more of the systems depicted in are used to perform one or more operations described herein using one or more neural networks having various algorithms, formulas, and procedures (such as those described in conjunction with Figure 1 and / or otherwise. In at least one embodiment, Figures 17A - 17B One or more of the systems depicted in are used to implement one or more systems and / or processes (such as those described in conjunction with Figures 1 - 6 such as to generate one or more images from text using one or more neural networks at least in part based on one or more first images that do not have text indicating the content of the one or more first images and one or more second images that have text indicating the content of the one or more second images and / or otherwise perform the operations described herein.

[0350] Figures 18A - 18B Additional exemplary graphics processor logic according to embodiments described herein is shown. In at least one embodiment, as shown in and in conjunction with Figures 18A - 18B shown in and in conjunction with Figures 18A - 18BThe described components are integrated into a single system, such as a graphics processing unit (GPU), a system on a chip (SoC), or another type of processor. In at least one embodiment, Figure 18A illustrates a graphics core 1800 that may be included in Figure 16 the graphics processor 1610 in at least one embodiment, and in at least one embodiment, the graphics core 1800 may be a unified shader core 1755A-1755N as Figure 17B shown. Figure 18B illustrates a highly parallel general purpose graphics processing unit (“GPGPU,” which may also be referred to as a “graphics processing unit”) 1830 suitable for deployment on a multi-chip module in at least one embodiment. In at least one embodiment, the graphics processing unit 1830 is a GPGPU that includes a graphics processor. In at least one embodiment, the integrated circuit 1600 includes the graphics core 1800, e.g., for forming the integrated circuit and / or forming an SoC, where such integrated circuit and / or such SoC performs the operations described herein.

[0351] In at least one embodiment, the graphics core 1800 includes a shared instruction cache 1802, texture units 1818, and cache / shared memory 1820 (e.g., which includes L1, L2, L3, last level cache, or other caches), which are shared for execution resources within the graphics core 1800. In at least one embodiment, the graphics core 1800 may include a plurality of slices 1801A - 1801N or partitions per core, and the graphics processor may include multiple instances of the graphics core 1800. In at least one embodiment, each of the slices 1801A - 1801N refers to the graphics core 1800. In at least one embodiment, the slices 1801A - 1801N have sub - slices that are part of the slices 1801A - 1801N. In at least one embodiment, the slices 1801A - 1801N are independent of or dependent on other slices. In at least one embodiment, the slices 1801A - 1801N may include support logic including local instruction caches 1804A - 1804N, thread schedulers (orderers) 1806A - 1806N, thread dispatchers 1807A - 1808N, and a set of registers 1810A - 1810N. In at least one embodiment, the slices 1801A - 1801N may include a set of additional functional units (AFU 1812A - 1812N), floating - point units (FPU1814A - 1814N), integer arithmetic logic units (ALU 1816A - 1816N), address calculation units (ACU 1813A - 1813N), double - precision floating - point units (DPFPU 1815A - 1815N), and matrix processing units (MPU 1817A - 1817N). In at least one embodiment, the MPU 1817A - 1817N is referred to as a matrix engine.

[0352] In at least one embodiment, each of the slices 1801A - 1801N includes one or more engines for floating - point and integer vector operations, and one or more engines for accelerating convolution and matrix operations in AI, machine learning, or large - dataset workloads. In at least one embodiment, one or more of the slices 1801A - 1801N includes one or more vector engines for computing vectors (e.g., performing mathematical operations on vectors). In at least one embodiment, the vector engines can compute vector operations in 16 - bit floating - point (also known as "FP16"), 32 - bit floating - point (also known as "FP32"), or 64 - bit floating - point (also known as "FP64"). In at least one embodiment, one or more of the slices 1801A - 1801N includes 16 vector engines paired with 16 matrix math units to compute matrix / tensor operations, where the vector engines and math units are exposed via matrix expansion. In at least one embodiment, a slice is a designated portion of the processing resources of a processing unit, e.g., 16 cores and ray - tracing units or 8 cores, a thread scheduler, a thread dispatcher, and additional functional units of the processor. In at least one embodiment, the graphics core 1800 includes one or more matrix engines for computing matrix operations, e.g., when computing tensor operations.

[0353] In at least one embodiment, one or more of the slices 1801A - 1801N includes one or more ray - tracing units for computing ray - tracing operations (e.g., 16 ray - tracing units per slice 1801A - 1801N). In at least one embodiment, the ray - tracing units compute ray traversal, triangle intersection, bounding - box intersection, or other ray - tracing operations.

[0354] In at least one embodiment, one or more of the slices 1801A - 1801N includes a media slice that encodes, decodes, and / or transcodes data; scales and / or converts the format of data; and / or performs video - quality operations on video data.

[0355] In at least one embodiment, one or more slices 1801A - 1801N are linked to an L2 cache and memory structure, a link connector, a high - bandwidth memory (HBM) (e.g., HBM2e, HDM3) stack, and a media engine. In at least one embodiment, one or more slices 1801A - 1801N include multiple cores (e.g., 16 cores) paired with each core and multiple ray - tracing units (e.g., 16). In at least one embodiment, one or more slices 1801A - 1801N have one or more L1 caches. In at least one embodiment, one or more slices 1801A - 1801N include one or more vector engines; one or more instruction caches for storing instructions; one or more L1 caches for caching data; one or more shared local memories (SLM) (e.g., corresponding to instructions) for storing data; one or more samplers for sampling data; one or more ray - tracing units for performing ray - tracing operations; one or more geometry units for performing operations in a geometry pipeline and / or applying geometric transformations to vertices or polygons; one or more rasterizers for describing an image in a vector - graphics format (e.g., shape) and converting it into a raster image (e.g., a series of pixels, points, or lines that, when displayed together, create an image represented by the shape); one or more hierarchical depth buffers (Hiz) for caching data; and / or one or more pixel back - ends. In at least one embodiment, slices 1801A - 1801N include a memory structure, e.g., an L2 cache.

[0356] In at least one embodiment, FPU 1814A - 1814N can perform single - precision (32 - bit) and half - precision (16 - bit) floating - point operations, while DPFPU 1815A - 1815N performs double - precision (64 - bit) floating - point operations. In at least one embodiment, ALU1816A - 1816N can perform variable - precision integer operations with 8 - bit, 16 - bit, and 32 - bit precision and can be configured for mixed - precision operations. In at least one embodiment, MPU 1817A - 1817N can also be configured for mixed - precision matrix operations, including half - precision floating - point operations and 8 - bit integer operations. In at least one embodiment, MPU 1817A - 1817N can perform various matrix operations to accelerate machine - learning application frameworks, including enabling support for accelerated general matrix - to - matrix multiplication (GEMM). In at least one embodiment, AFU 1812A - 1812N can perform additional logical operations not supported by a floating - point unit or an integer unit, including trigonometric operations (e.g., sine, cosine, etc.).

[0357] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. As described herein in connection withFigure 7A and / or Figure 7B Provide details about logic 715. In at least one embodiment, logic 715 may be used in graphics core 1800 for performing inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0358] In at least one embodiment, graphics core 1800 includes an interconnect and link structure sub-layer attached to a switch and a GPU-GPU bridge that enables multiple graphics processors 1800 (e.g., 8) to be linked to each other using load / store units (LSUs), data transfer units, and synchronization semantics across multiple graphics processors 1800 without glue. In at least one embodiment, the interconnect includes a standardized interconnect (e.g., PCIe) or some combination thereof.

[0359] In at least one embodiment, graphics core 1800 includes multiple tiles. In at least one embodiment, a tile is an individual die or one or more dies, where each die can be connected using an interconnect (e.g., Embedded Multi-Die Interconnect Bridge (EMIB)). In at least one embodiment, graphics core 1800 includes a compute tile, a memory tile (e.g., where the memory tile can be exclusively accessed by different tiles or different chip sets, such as a Rambo tile), a base tile, a foundation tile, an HMB tile, a link tile, and an EMIB tile, where all tiles are encapsulated together in graphics core 1800 as part of the GPU. In at least one embodiment, graphics core 1800 may include multiple tiles (also referred to as a "multi-tile package") in a single package. In at least one embodiment, the compute tile may have 8 graphics cores 1800, an L1 cache; and the base tile may have a host interface using PCIe 5.0, HBM2e, MDFI, and EMIB, a link tile with 8 links, and 8 ports with an embedded switch. In at least one embodiment, each tile is connected to a face-to-face (F2F) chip bond using fine-pitch 36-micron microbumps (e.g., copper pillars). In at least one embodiment, graphics core 1800 includes a memory structure that includes memory and is accessible by multiple tiles. In at least one embodiment, graphics core 1800 stores, accesses, or loads its own hardware context in memory, where the hardware context is a set of data loaded from registers before process restoration, and where the hardware context may indicate the state of the hardware (e.g., the state of the GPU).

[0360] In at least one embodiment, graphics core 1800 includes serializer / deserializer (SERDES) circuitry that converts a serial data stream to a parallel data stream or a parallel data stream to a serial data stream.

[0361] In at least one embodiment, the graphics core 1800 includes a high-speed coherent unified fabric (GPU-to-GPU), load / store units, large data transfer and synchronization semantics, and GPUs connected by an embedded switch, where the GPU-GPU bridge is controlled by a controller.

[0362] In at least one embodiment, the graphics core 1800 executes an API, where the API abstracts the hardware of the graphics core 1800 and utilizes instruction access libraries to perform mathematical operations (e.g., math kernel libraries), deep neural network operations (e.g., deep neural network libraries), vector operations, collective communications, thread building blocks, video processing, data analysis libraries, and / or ray tracing operations.

[0363] In at least one embodiment, Figure 18A one or more of the systems depicted herein are used to perform operations described herein using one or more neural networks having various algorithms, formulas, and procedures (such as those incorporated Figure 1 with). In at least one embodiment, Figure 18A one or more of the systems depicted herein are used to implement one or more systems and / or processes (such as those incorporated Figures 1 - 6 with), such as to generate one or more images from text using one or more neural networks based at least in part on one or more first images that do not have text indicative of the content of the one or more first images and one or more second images that have text indicative of the content of the one or more second images and / or to perform operations described herein in other ways.

[0364] Figure 18BIllustrated is the GPGPU 1830 in at least one embodiment, which can be configured such that highly parallel computing operations can be performed by an array of graphics processing units. In at least one embodiment, the GPGPU 1830 can be directly linked to other instances of the GPGPU 1830 to create a multi-GPU cluster to increase the training speed for deep neural networks. In at least one embodiment, the GPGPU 1830 includes a host interface 1832 for enabling connection to a host processor. In at least one embodiment, the host interface 1832 is a PCI Express interface. In at least one embodiment, the host interface 1832 can be a vendor-specific communication interface or communication fabric. In at least one embodiment, the GPGPU 1830 receives commands from the host processor and uses a global scheduler 1834 (which can be referred to as a thread sequencer and / or asynchronous compute engine) to allocate execution threads associated with those commands to a set of compute clusters 1836A - 1836H. In at least one embodiment, the compute clusters 1836A - 1836H share a cache memory 1838. In at least one embodiment, the cache memory 1838 can be used as a higher-level cache for the cache memories within the compute clusters 1836A - 1836H. In at least one embodiment, the compute clusters 1836A - 1836H include slices or are referred to as "slices". In at least one embodiment, the GPGPU1830 is part of a SoC, such as part of the integrated circuit 1600( Figure 16 ) part.

[0365] In at least one embodiment, the GPGPU 1830 includes memories 1844A - 1844B, which are coupled to the compute clusters 1836A - 1836H via a set of memory controllers 1842A - 1842B (e.g., one or more controllers of HBM2e). In at least one embodiment, the memories 1844A - 1844B can include various types of memory devices, which include dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), which includes graphics double data rate (GDDR) memory.

[0366] In at least one embodiment, each of the compute clusters 1836A - 1836H includes a set of graphics cores, such as [[ID=26The graphics core 1800, which can include various types of integer and floating-point logic units that can perform computational operations over a range of precisions suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each of the compute clusters 1836A - 1836H can be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units can be configured to perform 64-bit floating-point operations.

[0367] In at least one embodiment, multiple instances of the GPGPU 1830 can be configured to operate as compute clusters. In at least one embodiment, the communication for synchronization and data exchange in the compute clusters 1836A - 1836H varies between embodiments. In at least one embodiment, multiple instances of the GPGPU 1830 communicate via the host interface 1832. In at least one embodiment, the GPGPU 1830 includes an I / O hub 1839 that couples the GPGPU 1830 to a GPU link 1840 that enables a direct connection to other instances of the GPGPU 1830. In at least one embodiment, the GPU link 1840 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of the GPGPU 1830. In at least one embodiment, the GPU link 1840 is coupled to a high-speed interconnect to send and receive data to and from other GPGPUs or parallel processors. In at least one embodiment, multiple instances of the GPGPU 1830 are located in separate data processing systems and communicate via network devices accessible via the host interface 1832. In at least one embodiment, in addition to or as an alternative to the host interface 1832, the GPU link 1840 can also be configured to enable a connection to a host processor.

[0368] In at least one embodiment, the GPGPU 1830 can be configured to train a neural network. In at least one embodiment, the GPGPU 1830 can be used within an inference platform. In at least one embodiment, in the case of using the GPGPU 1830 for inference, the GPGPU 1830 can include fewer compute clusters 1836A - 1836H compared to when using the GPGPU 1830 to train a neural network. In at least one embodiment, the memory technology associated with the memories 1844A - 1844B can differ between the inference and training configurations, with higher bandwidth memory technology dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 1830 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions that can be used during the inference operations of a deployed neural network.

[0369] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. As described herein in connection with ​ and / or ​ details regarding Logic 715 are provided. In at least one embodiment, Logic 715 may be used in GPGPU 1830 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0370] In at least one embodiment, ​ one or more of the systems depicted in are used to perform one or more of the operations described herein using one or more neural networks having various algorithms, formulas, and processes (such as those described in connection with Figure 1 ). In at least one embodiment, Figure 18B one or more of the systems depicted in are used to implement one or more systems and / or processes (such as those described in connection with Figures 1-6 ), such as to generate one or more images from text using one or more neural networks based at least in part on one or more first images that do not have text indicating the content of the one or more first images and one or more second images that have text indicating the content of the one or more second images and / or to otherwise perform the operations described herein.

[0371] Figure 19 is a block diagram illustrating a computing system 1900 according to at least one embodiment. In at least one embodiment, the computing system 1900 includes a processing subsystem 1901 having one or more processors 1902 and system memory 1904 communicating via an interconnect path that may include a memory hub 1905. In at least one embodiment, the memory hub 1905 may be a separate component within a chipset component or may be integrated within one or more processors 1902. In at least one embodiment, the memory hub 1905 is coupled to an I / O subsystem 1911 via a communication link 1906. In at least one embodiment, the I / O subsystem 1911 includes an I / O hub 1907 that may enable the computing system 1900 to receive input from one or more input devices 1908. In at least one embodiment, the I / O hub 1907 may enable a display controller, which may be included in one or more processors 1902, to provide output to one or more display devices 1910A. In at least one embodiment, one or more display devices 1910A coupled to the I / O hub 1907 may include local, internal, or embedded display devices.

[0372] In at least one embodiment, the processing subsystem 1901 includes one or more parallel processors 1912 coupled to the memory hub 1905 via a bus or other communication link 1913. In at least one embodiment, the communication link 1913 may use any number of standards based on communication link technologies or protocols (such as but not limited to PCI Express), or may be a vendor-specific communication interface or communication fabric. In at least one embodiment, the one or more parallel processors 1912 form a parallel or vector processing system in a computing center, which may include a large number of processing cores and / or processing clusters, such as an integrated many-core (MIC) processor. In at least one embodiment, some or all of the one or more parallel processors 1912 form a graphics processing subsystem, which may output pixels to one of the one or more display devices 1910A coupled via the I / O hub 1907. In at least one embodiment, the one or more parallel processors 1912 may also include a display controller and a display interface (not shown) for implementing a direct connection to one or more display devices 1910B. In at least one embodiment, the parallel processor 1912 includes one or more cores, such as the graphics core 1800 discussed herein.

[0373] In at least one embodiment, the system storage unit 1914 may be connected to the I / O hub 1907 to provide a storage mechanism for the computing system 1900. In at least one embodiment, the I / O switch 1916 may be used to provide an interface mechanism for implementing connections between the I / O hub 1907 and other components, which may include, for example, a network adapter 1918 and / or a wireless network adapter 1919 integrated into the platform, as well as various other devices that may be added via one or more additional devices 1920. In at least one embodiment, the network adapter 1918 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 1919 may include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more radio devices.

[0374] In at least one embodiment, the computing system 1900 may include other components not explicitly shown that may also be connected to the I / O hub 1907, and the other components include USB or other port connections, optical storage drivers, video capture devices, etc. In at least one embodiment, any suitable protocol (such as a PCI (Peripheral Component Interconnect)-based protocol (such as PCI-Express) or other bus or point-to-point communication interface and / or protocol (such as NV-Link high-speed interconnect or interconnect protocol)) may be used to implement the communication paths of the various components. Figure 19 in the middle.

[0375] In at least one embodiment, one or more parallel processors 1912 include circuitry optimized for graphics and video processing, the circuitry including, for example, video output circuitry and constituting a graphics processing unit (GPU), e.g., one or more parallel processors 1912 include a graphics core 1800. In at least one embodiment, one or more parallel processors 1912 include circuitry optimized for general-purpose processing. In at least one embodiment, the components of computing system 1900 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1912, memory hub 1905, one or more processors 1902, and I / O hub 1907 may be integrated into a system-on-a-chip (SoC) integrated circuit. In at least one embodiment, the components of computing system 1900 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 1900 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules into a modular computing system.

[0376] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 715 are provided herein in connection with Figure 7A and / or Figure 7B In at least one embodiment, logic 715 may be used in computing system 1900 to perform inference or prediction operations at least in part based on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0377] In at least one embodiment, Figure 19 one or more of the systems depicted in Figure 1 are used to perform one or more of the operations described herein using one or more neural networks having various algorithms, formulas, and procedures (such as those described in connection with Figure 19 one or more of the systems depicted in Figures 1-6 are used to implement one or more systems and / or processes (such as those described in connection with

[0378] Processor

[0379] Figure 20A FIG. 2000 shows a parallel processor according to at least one embodiment. In at least one embodiment, the various components of the parallel processor 2000 may be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits (ASICs), or field programmable gate arrays (FPGAs). In at least one embodiment, the illustrated parallel processor 2000 is a variant of one or more of the parallel processors 1912 shown in accordance with an exemplary embodiment. Figure 19 In at least one embodiment, the parallel processor 2000 includes one or more graphics cores 1800.

[0380] In at least one embodiment, the parallel processor 2000 includes a parallel processing unit 2002. In at least one embodiment, the parallel processing unit 2002 includes an I / O unit 2004 that enables communication with other devices, including other instances of the parallel processing unit 2002. In at least one embodiment, the I / O unit 2004 may be directly connected to other devices. In at least one embodiment, the I / O unit 2004 is connected to other devices via a hub or switch interface (e.g., a memory hub 2005). In at least one embodiment, the connection between the memory hub 2005 and the I / O unit 2004 forms a communication link 2013. In at least one embodiment, the I / O unit 2004 is connected to a host interface 2006 and a memory crossbar 2016, where the host interface 2006 receives commands for performing processing operations and the memory crossbar 2016 receives commands for performing memory operations.

[0381] In at least one embodiment, when the host interface 2006 receives a command buffer via the I / O unit 2004, the host interface 2006 may direct the work operations for executing those commands to the front end 2008. In at least one embodiment, the front end 2008 is coupled to a scheduler 2010 (which may be referred to as an ordinalizer), and the scheduler 2010 is configured to allocate commands or other work items to the array of processing clusters 2012. In at least one embodiment, the scheduler 2010 ensures that the array of processing clusters 2012 is properly configured and in an active state before tasks are allocated to the clusters in the array of processing clusters 2012. In at least one embodiment, the scheduler 2010 is implemented via firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2010 may be configured to perform complex scheduling and work allocation operations at both a coarse-grained and a fine-grained level, enabling fast preemption and context switching of the threads executing on the array of processing clusters 2012. In at least one embodiment, the host software may attest to the workload to be scheduled on the array of processing clusters 2012 via one of the multiple graphics processing paths. In at least one embodiment, the workload may then be automatically allocated on the array of processing clusters 2012 by the scheduler 2010 logic within the microcontroller including the scheduler 2010.

[0382] In at least one embodiment, the array of processing clusters 2012 may include up to "N" processing clusters (e.g., cluster 2014A, cluster 2014B to cluster 2014N), where "N" represents a positive integer (which may be a different integer "N" from the integers used in other figures). In at least one embodiment, each of the clusters 2014A - 2014N of the array of processing clusters 2012 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 2010 may use various scheduling and / or work allocation algorithms to allocate work to the clusters 2014A - 2014N in the array of processing clusters 2012, and these algorithms may vary according to the workload generated for each type of program or computation. In at least one embodiment, the scheduling may be handled dynamically by the scheduler 2010, or may be assisted in part by compiler logic during the compilation of the program logic configured to be executed by the array of processing clusters 2012. In at least one embodiment, different clusters 2014A - 2014N in the array of processing clusters 2012 may be assigned to process different types of programs or to perform different types of computations.

[0383] In at least one embodiment, the processing cluster array 2012 can be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster array 2012 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing cluster array 2012 can include logic for performing processing tasks that include filtering of video and / or audio data, performing modeling operations, including physics operations, and performing data transformations.

[0384] In at least one embodiment, the processing cluster array 2012 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2012 can include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, and tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2012 can be configured to execute shader programs related to graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2002 can transfer data from the system memory via the I / O unit 2004 for processing. In at least one embodiment, during processing, the transferred data can be stored in on-chip memory (e.g., parallel processor memory 2022) during processing and then written back to the system memory.

[0385] In at least one embodiment, when the parallel processing unit 2002 is used to perform graphics processing, the scheduler 2010 can be configured to divide the processing workload into tasks of approximately equal size to better enable the distribution of graphics processing operations to the multiple clusters 2014A - 2014N in the processing cluster array 2012. In at least one embodiment, various parts of the processing cluster array 2012 can be configured to perform different types of processing. For example, in at least one embodiment, the first part can be configured to perform vertex shading and topology generation, the second part can be configured to perform tessellation and geometry shading, and the third part can be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 2014A - 2014N can be stored in a buffer to allow the transfer of intermediate data between the clusters 2014A - 2014N for further processing.

[0386] In at least one embodiment, the processing cluster array 2012 may receive processing tasks to be executed via a scheduler 2010 that receives commands defining the processing tasks from a front end 2008. In at least one embodiment, the processing tasks may include an index of data to be processed, such as surface (patch) data, raw data, vertex data, and / or pixel data, as well as status parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, the scheduler 2010 may be configured to obtain an index corresponding to the task or may receive the index from the front end 2008. In at least one embodiment, the front end 2008 may be configured to ensure that the processing cluster array 2012 is configured in a valid state before starting a workload specified by an incoming command buffer (e.g., a batch-buffer, a push buffer, etc.).

[0387] In at least one embodiment, each of one or more instances of the parallel processing units 2002 may be coupled to a parallel processor memory 2022. In at least one embodiment, the parallel processor memory 2022 may be accessed via a memory crossbar 2016 that may receive memory requests from the processing cluster array 2012 as well as an I / O unit 2004. In at least one embodiment, the memory crossbar 2016 may access the parallel processor memory 2022 via a memory interface 2018. In at least one embodiment, the memory interface 2018 may include a plurality of partitioning units (e.g., partitioning unit 2020A, partitioning unit 2020B to partitioning unit 2020N), each of which may be coupled to a portion (e.g., a memory unit) of the parallel processor memory 2022. In at least one embodiment, the number of partitioning units 2020A-2020N is configured to be equal to the number of memory units such that the first partitioning unit 2020A has a corresponding first memory unit 2024A, the second partitioning unit 2020B has a corresponding second memory unit 2024B, and the Nth partitioning unit 2020N has a corresponding Nth memory unit 2024N. In at least one embodiment, the number of partitioning units 2020A-2020N may not be equal to the number of memory units.

[0388] In at least one embodiment, the memory units 2024A - 2024N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, the memory units 2024A - 2024N may further include 3D stacked memory, including but not limited to high bandwidth memory (HBM), HBM2e, HBM3. In at least one embodiment, render targets such as frame buffers or texture maps may be stored across the memory units 2024A - 2024N, allowing the partition units 2020A - 2020N to write portions of each render target in parallel to efficiently utilize the available bandwidth of the parallel processor memory 2022. In at least one embodiment, local instances of the parallel processor memory 2022 may be excluded in favor of a unified memory design that utilizes system memory and local cache memory.

[0389] In at least one embodiment, any one of the clusters 2014A - 2014N in the cluster array 2012 of processing clusters may process data to be written into any of the memory units 2024A - 2024N within the parallel processor memory 2022. In at least one embodiment, the memory crossbar 2016 may be configured to transfer the output of each cluster 2014A - 2014N to any of the partition units 2020A - 2020N or to another cluster 2014A - 2014N, and the other cluster 2014A - 2014N may perform additional processing operations on the output. In at least one embodiment, each cluster 2014A - 2014N may communicate with the memory interface 2018 through the memory crossbar 2016 to read from or write to various external memory devices. In at least one embodiment, the memory crossbar 2016 has connections to the memory interface 2018 for communicating with the I / O unit 2004 and to a local instance of the parallel processor memory 2022, which enables processing units within different processing clusters 2014A - 2014N to communicate with system memory or other memory that is not local to the parallel processing units 2002. In at least one embodiment, the memory crossbar 2016 may use virtual channels to separate the traffic flow between the clusters 2014A - 2014N and the partition units 2020A - 2020N.

[0390] In at least one embodiment, multiple instances of the parallel processing unit 2002 can be provided on a single add-in card, or multiple add-in cards can be interconnected. In at least one embodiment, different instances of the parallel processing unit 2002 can be configured to operate with each other even if the different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 2002 can include floating-point units with higher precision relative to other instances. In at least one embodiment, a system that includes one or more instances of the parallel processing unit 2002 or the parallel processor 2000 can be implemented in various configurations and form factors, including but not limited to desktop computers, laptop computers, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0391] Figure 20B is a block diagram of a partitioning unit 2020 according to at least one embodiment. In at least one embodiment, the partitioning unit 2020 is Figure 20A an instance of one of the partitioning units 2020A - 2020N. In at least one embodiment, the partitioning unit 2020 includes an L2 cache 2021, a frame buffer interface 2025, and a ROP 2026 (raster operation unit). In at least one embodiment, the L2 cache 2021 is a read / write cache that is configured to perform load and store operations received from the memory crossbar 2016 and the ROP 2026. In at least one embodiment, the L2 cache 2021 outputs read misses and urgent write-back requests to the frame buffer interface 2025 for processing. In at least one embodiment, updates can also be sent to the frame buffer via the frame buffer interface 2025 for processing. In at least one embodiment, the frame buffer interface 2025 interfaces with one of the memory units (such as Figure 20A the memory units 2024A - 2024N (e.g., within the parallel processor memory 2022)) of

[0392] In at least one embodiment, the ROP 2026 is a processing unit that performs raster operations such as stencil, z-test, blending, etc. In at least one embodiment, the ROP 2026 then outputs the processed graphics data stored in the graphics memory. In at least one embodiment, the ROP 2026 includes compression logic for compressing depth or color data written to the memory and decompressing depth or color data read from the memory. In at least one embodiment, the compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by the ROP 2026 can vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed on depth and color data per tile.

[0393] In at least one embodiment, the ROP 2026 is included within each processing cluster (e.g., Figure 20A clusters 2014A - 2014N), rather than within the partitioning unit 2020. In at least one embodiment, read and write requests for pixel data rather than pixel fragment data are transmitted through the memory crossbar 2016. In at least one embodiment, the processed graphics data can be displayed on a display device (such as Figure 19 one of one or more display devices 1910), routed by the processor 1902 for further processing, or routed by Figure 20A one of the processing entities within the parallel processor 2000 of

[0394] Figure 20C is a block diagram of a processing cluster 2014 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is Figure 20A an instance of one of the processing clusters 2014A - 2014N. In at least one embodiment, the processing cluster 2014 can be configured to execute a number of threads in parallel, where a "thread" refers to an instance of a particular program executed on a particular set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issue techniques are used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) techniques are used to support the parallel execution of a large number of generally synchronized threads using a common instruction unit that is configured to issue instructions to a set of processing engines within each processing cluster.

[0395] In at least one embodiment, the operation of the processing cluster 2014 can be controlled via a pipeline manager 2032 that assigns processing tasks to the SIMT parallel processor. In at least one embodiment, the pipeline manager 2032 receives from Figure 20AThe scheduler 2010 receives instructions and manages the execution of these instructions via the graphics multiprocessor 2034 and / or the texture unit 2036. In at least one embodiment, the graphics multiprocessor 2034 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures may be included within the processing cluster 2014. In at least one embodiment, one or more instances of the graphics multiprocessor 2034 may be included within the processing cluster 2014. In at least one embodiment, the graphics multiprocessor 2034 may process data, and the data crossbar 2040 may be used to distribute the processed data to one of multiple possible destinations (including other shader units). In at least one embodiment, the pipeline manager 2032 may facilitate the distribution of the processed data by specifying the destination of the processed data to be distributed via the data crossbar 2040.

[0396] In at least one embodiment, each graphics multiprocessor 2034 within the processing cluster 2014 may include the same set of functional execution logic (e.g., arithmetic logic units, load-store units, etc.). In at least one embodiment, the functional execution logic may be configured in a pipelined manner, where new instructions may be issued before the completion of previous instructions. In at least one embodiment, the functional execution logic supports various operations, including integer and floating-point arithmetic, comparison operations, boolean operations, bit shifts, and the calculation of various algebraic...

Claims

1. A processor, comprising: One or more circuits configured to generate one or more images from text using one or more neural networks based at least in part on the one or more first images that do not have text indicating the content of the one or more first images and the one or more second images that have text indicating the content of the one or more second images.

2. The processor according to claim 1, wherein the text indicating the content is a caption embedded using one or more encoders.

3. The processor according to claim 1, wherein the one or more first images that do not have text indicating the content of the one or more first images are compared with the one or more second images based at least in part on the one or more neural networks performing one or more loss operations.

4. The processor according to claim 1, wherein the one or more neural networks generate the one or more images based at least in part on one or more captions of one or more parts of the one or more second images.

5. The processor according to claim 1, wherein the one or more second images include one or more ground truth images, and the one or more ground truth images are compared with the one or more first images based at least in part on one or more loss operations.

6. The processor according to claim 5, wherein the one or more loss operations include a visual reconstruction loss, a contrastive caption loss, or a generative caption loss.

7. The processor according to claim 1, wherein the one or more circuits are configured to cause the one or more neural networks to be trained based at least in part on embedding one or more captions using one or more visual encoders and comparing the one or more captions with one or more ground truth captions.

8. A system, comprising: One or more processors configured to generate one or more images from text using one or more neural networks based at least in part on the one or more first images that do not have text indicating the content of the one or more first images and the one or more second images that have text indicating the content of the one or more second images.

9. The system according to claim 8, wherein the text indicating the content is a caption embedded using one or more encoders.

10. The system according to claim 8, wherein the one or more first images that do not have text indicating the content of the one or more first images are compared with the one or more second images based at least in part on the one or more neural networks performing one or more loss operations.

11. The system according to claim 8, wherein the one or more neural networks generate the one or more images based at least in part on one or more captions of one or more parts of the one or more second images.

12. The system according to claim 8, wherein the one or more second images include one or more ground truth images, and the one or more ground truth images are compared with the one or more first images at least in part based on one or more loss operations.

13. The system according to claim 12, wherein the one or more loss operations include a visual reconstruction loss, a contrastive caption loss, or a generative caption loss.

14. The system according to claim 8, wherein the one or more processors are configured to cause the one or more neural networks to be trained at least in part based on embedding one or more captions using one or more visual encoders and comparing the one or more captions with one or more ground truth captions.

15. A method comprising: generating, using one or more neural networks, one or more images from text based at least in part on the one or more first images that do not have text indicating the content of the one or more first images and the one or more second images that have text indicating the content of the one or more second images.

16. The method according to claim 15, wherein the text indicating the content is captions embedded using one or more encoders.

17. The method according to claim 15, wherein the one or more first images that do not have text indicating the content of the one or more first images are compared with the one or more second images at least in part based on the one or more neural networks performing one or more loss operations.

18. The method according to claim 15, wherein the one or more neural networks generate the one or more images at least in part based on one or more captions of one or more portions of the one or more second images.

19. The method according to claim 15, wherein the one or more second images include one or more ground truth images, and the one or more ground truth images are compared with the one or more first images at least in part based on one or more loss operations.

20. The method according to claim 15 further comprises: causing the one or more neural networks to be trained at least in part based on embedding one or more captions using one or more visual encoders and comparing the one or more captions with one or more ground truth captions.

Images