Video compression method and device, equipment and storage medium

Abstract

The invention provides a video compression method and device, equipment and a storage medium. The method comprises the following steps: acquiring a t-th frame to-be-compressed image; segmenting the t-th frame of image to be compressed into m slices; the coding result of the t-th frame of to-be-compressed image is an I frame; coding the nth slice based on the first processing core to obtain a coding result of the nth slice; coding the (n + 1) th slice based on the second processing core to obtain a coding result of the (n + 1) th slice; acquiring a (t + 1) th frame of to-be-compressed image; the first processing core refers to a slice coding result to code a first first coding unit to obtain a first first coding result; and the second processing core encodes the (n + 2) th slice to obtain an encoding result of the (n + 2) th slice. According to the technical scheme provided by the invention, the to-be-compressed images with different coding result types can be processed differently, so that the multi-core processing capability of the video coder is improved.

Description

Technical Field

[0001] This application relates to the field of video processing technologies, and particularly relates to a video compression method, apparatus, device, and storage medium. Background Art

[0002] Currently, video resolutions are getting larger and larger, and people have a demand for higher-performance video compression. Software encoders implemented by a Central Processing Unit (CPU) can no longer meet the requirements for high-performance video compression.

[0003] To solve this problem, related technologies hardwareize video encoding functions through a System on Chip (SoC). Among them, the processing cores of video encoders are generally in the forms of single-core, dual-core, and multi-core.

[0004] However, the above method adopts the same processing scheme for all images to be compressed, thus unable to process different images to be compressed differently, and further reducing the multi-core processing ability of the video encoder. Summary of the Invention

[0005] An embodiment of this application provides a video compression method, which can process images to be compressed with different encoding result types differently, thereby improving the multi-core processing ability of the video encoder. The technical solution is as follows:

[0006] According to a first aspect of an embodiment of this application, a video compression method is provided. The method includes:

[0007] Obtain the t-th frame of the image to be compressed; the t-th frame of the image to be compressed is a part of the video to be compressed;

[0008] Divide the t-th frame of the image to be compressed into m slices; the encoding result of the t-th frame of the image to be compressed is an I-frame; t and m are integers greater than or equal to 1;

[0009] Encode the n-th slice based on a first processing core to obtain an encoding result of the n-th slice; encode the (n + 1)-th slice based on a second processing core to obtain an encoding result of the (n + 1)-th slice; each encoding result of the slice is a part of the I-frame; the first processing core and the second processing core are parts of the video encoder; n is an integer greater than or equal to 1;

[0010] Obtain the (t + 1)-th frame of the image to be compressed; the encoding result of the (t + 1)-th frame of the image to be compressed is the first P-frame;

[0011] The first processing core encodes the first first coding unit with reference to one of the slice coding results, obtaining a first first coding result; each of the first coding units is a part of the (t + 1)-th frame of the image to be compressed; each of the first coding results is a part of the first P frame; the second processing core encodes the (n + 2)-th slice, obtaining the (n + 2)-th slice coding result; (n + 2) is an integer less than or equal to m.

[0012] In a possible implementation, before the first processing core encodes the first first coding unit with reference to one of the slice coding results to obtain a first first coding result, it further includes:

[0013] The first processing core accesses the synchronization control module. If the synchronization control module indicates that the first slice coding result is stored in the memory, the first processing core obtains the first slice coding result from the memory; or

[0014] If the synchronization control module indicates that the first slice coding result does not exist in the memory, the first processing core is in a waiting state;

[0015] When the first processing core receives a wake-up signal, the first processing core obtains the first slice coding result from the memory; the wake-up signal is generated by the synchronization control module based on the write state of the memory.

[0016] In a possible implementation, the method further includes:

[0017] Obtain the (t + j)-th frame of the image to be compressed; the coding result of the (t + j)-th frame of the image to be compressed is the j-th P frame;

[0018] The first processing core encodes the first j-th coding unit with reference to the first (j - 1)-th coding result, obtaining a first j-th coding result; each of the j-th coding units is a part of the (t + j + 1)-th frame of the image to be compressed; each of the j-th coding results is a part of the j-th P frame; j is an integer greater than or equal to 2; (t + j + 1) is an integer less than or equal to m;

[0019] Obtain the (t + j + 1)-th frame of the image to be compressed; the coding result of the (t + j + 1)-th frame of the image to be compressed is the (j + 1)-th P frame;

[0020] The second processing core encodes the first (j + 1)-th coding unit with reference to the first j-th coding result to obtain the first (j + 1)-th coding result; each (j + 1)-th coding unit is a part of the image to be compressed in the (t + j + 1)-th frame; each (j + 1)-th coding result is a part of the (j + 1)-th P frame.

[0021] In a possible implementation, before the first processing core encodes the first j-th coding unit with reference to the first (j - 1)-th coding result to obtain the first j-th coding result, it further includes:

[0022] The first processing core accesses the synchronization control module. If the synchronization control module indicates that the first (j - 1)-th coding result is stored in the memory, the first processing core obtains the first (j - 1)-th coding result from the memory; or

[0023] If the synchronization control module indicates that the first (j - 1)-th coding result does not exist in the memory, the first processing core is in a waiting state;

[0024] When the first processing core receives a wake-up signal, the first processing core obtains the first (j - 1)-th coding result from the memory; the wake-up signal is generated by the synchronization control module based on the write state of the memory.

[0025] In a possible implementation, before the second processing core encodes the first (j + 1)-th coding unit with reference to the first j-th coding result to obtain the first (j + 1)-th coding result, it further includes:

[0026] The second processing core accesses the synchronization control module. If the synchronization control module indicates that the first j-th coding result is stored in the memory, the second processing core obtains the first j-th coding result from the memory; or

[0027] If the synchronization control module indicates that the first j-th coding result does not exist in the memory, the second processing core is in a waiting state;

[0028] When the second processing core receives the wake-up signal, the second processing core obtains the first j-th coding result from the memory.

[0029] In a possible implementation, the method further includes:

[0030] The first processing core accesses the synchronization control module. If the synchronization control module indicates that the k-th (j - 1)-th encoding result is stored in the memory, the first processing core obtains the k-th (j - 1)-th encoding result from the memory; k is an integer greater than or equal to 1.

[0031] The first processing core encodes the k-th j-th encoding unit with reference to the k-th (j - 1)-th encoding result to obtain the k-th j-th encoding result.

[0032] The second processing core accesses the synchronization control module. If the synchronization control module indicates that the k-th j-th encoding result is stored in the memory, the second processing core obtains the k-th j-th encoding result from the memory; the second processing core encodes the k-th (j + 1)-th encoding unit with reference to the k-th j-th encoding result to obtain the k-th (j + 1)-th encoding result.

[0033] In a possible implementation, the method further includes:

[0034] Encoding the first slice by the first processing core to obtain the first slice encoding result; encoding the second slice by the second processing core to obtain the second slice encoding result; encoding the i-th slice by the i-th processing core to obtain the i-th slice encoding result; i is an integer greater than or equal to 3 and less than m.

[0035] Obtaining the (t + 1)-th frame of the image to be compressed.

[0036] The i-th processing core encodes the first first encoding unit with reference to the first slice encoding result to obtain the first first encoding result; the first processing core encodes the (i + 1)-th slice to obtain the (i + 1)-th slice encoding result; the (i - 1)-th processing core encodes the (2i - 1)-th slice to obtain the (2i - 1)-th slice encoding result; the i-th processing core and the (i - 1)-th processing core are part of the video encoder; i is an integer greater than or equal to 3 and less than m.

[0037] In a possible implementation, the method further includes:

[0038] Obtaining the (t + 2)-th frame of the image to be compressed; the encoding result of the (t + 2)-th frame of the image to be compressed is the second P frame.

[0039] The (i - 1)-th processing core encodes the first second coding unit with reference to the first first coding result to obtain the first second coding result; each second coding unit is a part of the image to be compressed in the (t + 2)-th frame; each second coding result is a part of the second P frame; the i-th processing core encodes the second first coding unit with reference to the second slice coding result to obtain the second first coding result; the first processing core encodes the 2i-th slice to obtain the 2i-th slice coding result; the (i - 2)-th processing core encodes the (3i - 3)-th slice to obtain the (3i - 3)-th slice coding result.

[0040] In a possible implementation, before the i-th processing core encodes the first first coding unit with reference to the first slice coding result to obtain the first first coding result, it further includes:

[0041] The i-th processing core accesses the synchronization control module. If the synchronization control module indicates that the first slice coding result is stored in the memory, the i-th processing core obtains the first slice coding result from the memory; or

[0042] If the synchronization control module indicates that the first slice coding result does not exist in the memory, the i-th processing core is in a waiting state;

[0043] When the i-th processing core receives a wake-up signal, the i-th processing core obtains the first slice coding result from the memory.

[0044] In a possible implementation, the method further includes:

[0045] The i-th processing core accesses the synchronization control module. If the synchronization control module indicates that the p-th slice coding result is stored in the memory, the i-th processing core obtains the p-th slice coding result from the memory; p is an integer greater than or equal to 1 and less than m;

[0046] The first processing core encodes the p-th first coding unit with reference to the i-th slice coding result to obtain the p-th first coding result;

[0047] The (i-1)th processing core accesses the synchronization control module. If the synchronization control module indicates that the qth first encoding result is stored in the memory, the (i-1)th processing core obtains the qth first encoding result from the memory; the (i-1)th processing core encodes the qth second encoding unit with reference to the qth first encoding result to obtain the qth second encoding result; q is an integer greater than or equal to 1 and less than m.

[0048] According to a second aspect of the embodiments of the present application, there is provided a video compression device, including:

[0049] An acquisition module, configured to acquire the t-th frame of the image to be compressed; the t-th frame of the image to be compressed is a part of the video to be compressed;

[0050] A slicing module, configured to slice the t-th frame of the image to be compressed into m slices; the encoding result of the t-th frame of the image to be compressed is an I frame; t and m are integers greater than or equal to 1;

[0051] An encoding module, configured to encode the nth slice based on a first processing core to obtain the encoding result of the nth slice; encode the (n+1)th slice based on a second processing core to obtain the encoding result of the (n+1)th slice; each slice encoding result is a part of the I frame; the first processing core and the second processing core are parts of a video encoder; n is an integer greater than or equal to 1;

[0052] The acquisition module is further configured to acquire the (t+1)th frame of the image to be compressed; the encoding result of the (t+1)th frame of the image to be compressed is the first P frame;

[0053] The encoding module is further configured to the first processing core encodes the first first encoding unit with reference to an encoding result of a slice to obtain the first first encoding result; each first encoding unit is a part of the (t+1)th frame of the image to be compressed; each first encoding result is a part of the first P frame; the second processing core encodes the (n+2)th slice to obtain the encoding result of the (n+2)th slice; (n+2) is an integer less than or equal to m.

[0054] According to a third aspect of the embodiments of the present application, there is provided a computer device, where the computer device includes a processor and a memory, and the memory is used to store at least one segment of program, and the at least one segment of program is loaded and executed by the processor to perform the video compression method described above.

[0055] According to a fourth aspect of the embodiments of the present application, there is provided a computer-readable storage medium, in which at least one segment of program is stored, and the at least one segment of program is loaded and executed by a processor to implement the video compression method described above.

[0056] In the embodiments of the present application, a video compression method is provided. The to-be-compressed image with an I-frame coding result is sliced into multiple slices, and multiple processing cores are controlled to encode one slice respectively, that is, multiple processing cores encode one to-be-compressed image in parallel, thereby reducing the delay in the I-frame encoding process and further improving the encoding performance. In addition, the to-be-compressed image with a P-frame coding result is not sliced in the present application, thereby reducing the problem of image boundary quality fragmentation caused by excessive slices. Therefore, the embodiments of the present application realize the selection of different encoding methods for to-be-compressed images with different types of coding results, thereby greatly improving the encoding ability of multiple processing cores. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0058] Figure 1 is a schematic diagram of an implementation environment provided according to an embodiment of the present application;

[0059] Figure 2 is a schematic flowchart of a video compression method provided according to an embodiment of the present application;

[0060] Figure 3 is a schematic diagram of the structure of a group of pictures provided according to an embodiment of the present application;

[0061] Figure 4 is a schematic diagram of the structure after slicing a to-be-compressed image provided according to an embodiment of the present application;

[0062] Figure 5 is a schematic diagram of the principle of parallel I-frame encoding and P-frame encoding provided according to an embodiment of the present application;

[0063] Figure 6 is a schematic diagram of the principle of a synchronization control module provided according to an embodiment of the present application;

[0064] Figure 7 is a schematic diagram of the principle of parallel encoding of two P-frames provided according to an embodiment of the present application;

[0065] Figure 8It is a schematic diagram of the principle of parallel operation of multiple processing cores provided according to an embodiment of the present application;

[0066] Figure 9 It is a schematic structural diagram of a video compression device provided according to an embodiment of the present application;

[0067] Figure 10 It is a schematic structural diagram of a terminal provided according to an embodiment of the present application;

[0068] Figure 11 It is a schematic structural diagram of a server provided according to an embodiment of the present application. Detailed implementation manners

[0069] To make the objectives, technical solutions and advantages of the present application clearer, the following will further describe the embodiments of the present application in detail with reference to the accompanying drawings.

[0070] Here, the exemplary embodiments will be described in detail, and the examples are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application.

[0071] In the present application, terms such as "first" and "second" are used to distinguish the same items or similar items with basically the same functions and effects. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor are the quantity and execution order limited. It should also be understood that although the following description uses terms such as first and second to describe various elements, these elements should not be limited by the terms.

[0072] These terms are only used to distinguish one element from another. For example, without departing from the scope of various examples, the first action can be called the second action, and similarly, the second action can also be called the first action. Both the first action and the second action can be actions, and in some cases, they can be separate and different actions.

[0073] Among them, at least one means one or more than one. For example, at least one action can be one action, two actions, three actions, etc., any integer greater than or equal to one. And multiple means two or more than two. For example, multiple actions can be two actions, three actions, etc., any integer greater than or equal to two.

[0074] Figure 1 It is a schematic diagram of an implementation environment provided according to an embodiment of the present application. This implementation environment may include a terminal 101 and a server 102.

[0075] In the terminal 101, a video encoder is provided. For example, the terminal 101 can be a smart phone with a video encoder, a wearable device, a personal computer, a laptop computer, a tablet computer, a smart TV, a vehicle-mounted terminal, etc.

[0076] The server 102 can be a single server, a server cluster composed of multiple servers, or a cloud processing center.

[0077] The terminal 101 is connected to the server 102 through a wired or wireless network.

[0078] In some embodiments, the wireless network or the wired network uses standard communication technologies and / or protocols. The network is usually the Internet, but can also be any network, including but not limited to any combination of a Local Area Network (LAN), a Metropolitan Area Network (MAN), a Wide Area Network (WAN), a mobile, wired or wireless network, a private network or a virtual private network. In some embodiments, technologies and / or formats including Hyper Text Mark-up Language (HTML), Extensible Markup Language (XML), etc. are used to represent the data exchanged through the network. In addition, conventional encryption technologies such as Secure Socket Layer (SSL), Transport Layer Security (TLS), Virtual Private Network (VPN), Internet Protocol Security (IPsec), etc. can be used to encrypt all or some of the links. In other embodiments, customized and / or dedicated data communication technologies can be used to replace or supplement the above data communication technologies.

[0079] In the related art, in order to hardwareize the video encoding function, the processing core of the video encoder can include forms such as a single core, a dual core, and multiple cores. Correspondingly, the working modes include single-core time-sharing multiplexing, multi-core collaborative processing, multi-core parallel processing, etc.

[0080] Optionally, to increase the main frequency of the hardware to achieve the purpose of single-core processing ability, for example, real-time processing of 8K@30fps can be achieved, but the corresponding power consumption will increase. For high-frame-rate videos, since the single core can only process one frame at a time, it does not have the ability of multi-channel parallel processing. Among them, 8K@30fps is a specification description in video or display technology; the 8K resolution is usually 7680×4320 pixels (about 33 million pixels); 30fps means playing 30 frames per second, which belongs to the medium-high smoothness standard.

[0081] Optionally, to improve the processing ability of large-resolution and high-frame-rate video images, a multi-core collaborative encoding processing scheme is mostly adopted. Specifically, multiple hardware cores with slightly lower processing capabilities cooperate in terms of algorithms or processing processes, which not only enhances the processing ability of a single-channel large-resolution and high-frame-rate video stream, but also increases the actual physical cores, thus improving the true parallel processing ability of multiple video streams. For example, the large-resolution input image is sliced into multiple parts by rows or columns, and different hardware cores are responsible for processing different image slices. The bitstreams after processing by all cores are merged to finally obtain the compressed bitstream of the entire frame image. However, the method implemented through software and hardware synchronization is very complex. Special control and cache designs are required for the synchronization of different image slices to ensure performance and image compression quality; moreover, the same processing scheme is adopted for all compressed frame types (Intra-coded Frame (I-frame), Predictive-coded Frame (P-frame), and Bidirectional Predictive-coded Frame (B-frame)), without targeted processing according to the different bitstream sizes of I-frames, P-frames, and B-frames, so that the multi-core processing ability of the video encoder cannot be maximally utilized.

[0082] To solve the above technical problems, an embodiment of the present application provides a video compression method, which includes: slicing the to-be-compressed image with the encoding result of an I-frame into multiple slices, and different processing cores process different slices. For the to-be-compressed image with the encoding result of a P-frame, each processing core processes one frame and does not slice the to-be-compressed image.

[0083] For the to-be-compressed image with the encoding result of an I-frame, in the H.264 / H.265 compression protocol, the bitstream of I-frame encoding is larger than that of P-frame encoding. Then, the encoding of I-frames takes a longer time, resulting in a larger encoding delay, which causes performance jitter. Also, since I-frame encoding is intra-frame prediction, it is more suitable for multi-core parallel slicing processing; therefore, the present application adopts multi-processing cores to collaboratively encode I-frames.

[0084] For the to-be-compressed image with the coding result being a P frame, different from the related art which slices the input image and sends it to different cores for parallel coding, the present application removes the dependencies formed due to the reference frame; that is, when coding the current to-be-compressed image, another processing core may be writing the reference frame on which the current frame depends; this is because motion estimation has a certain search range, so as long as the reference frame has completed the image reconstruction within the search range, the coding task of this frame can be started without waiting for the completion of the reconstructed image of the entire frame, thereby improving the coding efficiency.

[0085] Figure 2 is a schematic flowchart of a video compression method provided by an embodiment of the present application. As Figure 2 shown, in the embodiment of the present application, it is applied to a terminal with a video encoder, taking a video encoder with two processing cores and a high-frame-rate video stream as an example for illustration. The method includes the following steps:

[0086] In step 201, the terminal acquires the t-th frame to-be-compressed image.

[0087] Wherein, the t-th frame to-be-compressed image is a part of the to-be-compressed video.

[0088] Figure 3 is a schematic structural diagram of a Group of Pictures (GOP) according to an embodiment of the present application.

[0089] Next, in combination with Figure 3 an exemplary illustration of step 201 will be given.

[0090] Before step 201, the terminal acquires information such as the coding GOP structure information and the bitrate control parameters, and then initializes the video encoder. Creates an encoding channel and enables the encoding channel to start receiving the to-be-compressed images. During the encoding process, it is necessary to refer to the adjacent previous I frame or P frame to encode the next P frame. For example, the to-be-compressed image is generated by a video input (VIN) module or a video process system (VPS) module.

[0091] In some embodiments, the terminal acquires the t-th frame to-be-compressed image and adds the t-th frame to-be-compressed image to the input buffer queue of the encoding channel. For example, the to-be-compressed image is an image in YUV color encoding format. YUV is a color encoding method that separates the luminance information and the chrominance information for processing.

[0092] It can be understood that when the encoding result of a frame of image to be compressed is an I-frame, the frame of image to be compressed does not need to refer to the encoder result of the previous frame during encoding. When the encoding result of a frame of image to be compressed is a P-frame, the frame of image to be compressed needs to refer to the encoding result of the previous frame of image to be compressed during encoding.

[0093] In step 202, the terminal divides the t-th frame of image to be compressed into m slices; the encoding result of the t-th frame of image to be compressed is an I-frame.

[0094] Wherein, t and m are integers greater than or equal to 1.

[0095] Figure 4 is a schematic diagram of the structure after dividing a frame of image to be compressed provided by an embodiment of the present application.

[0096] The following combines Figure 4 to give an exemplary illustration of the slices.

[0097] In some embodiments, while adding the t-th frame of image to be compressed to the input buffer queue of the encoding channel, determine the frame type after encoding this frame of image to be compressed, and based on this frame type, determine the slicing strategy. Wherein, the slicing strategy is to slice or not to slice.

[0098] In one example, based on the encoding GOP structure information, determine the frame type corresponding to the encoding result of each frame of image to be compressed; wherein, the frame type is an I-frame or a P-frame. Optionally, when the frame type is an I-frame, divide this frame of image to be compressed into multiple slices. Optionally, when the frame type is a P-frame, there is no need to slice this image to be compressed. Optionally, when the frame type is an I-frame, slice this frame of image to be compressed horizontally. The value of m is set according to actual needs. For example: the height of each slice is at least 16 pixels or 64 pixels. The number of slices is 4, 6, 8 or 10. Wherein, when the number of slices is 4, this frame of image to be compressed includes the first slice, the second slice, the third slice and the fourth slice.

[0099] It should be noted that the method for slicing the image to be compressed involved in the present application can be directly obtained from related technologies, and the embodiments of the present application will not be elaborated.

[0100] Figure 5 is a schematic diagram of the principle of parallel I-frame encoding and P-frame encoding provided by an embodiment of the present application.

[0101] The following combines Figure 5 to give an exemplary illustration of the principle of parallel I-frame encoding and P-frame encoding.

[0102] In step 203, the terminal encodes the nth slice based on the first processing core to obtain the encoding result of the nth slice, and encodes the (n + 1)th slice based on the second processing core to obtain the encoding result of the (n + 1)th slice.

[0103] Wherein, each slice encoding result is a part of an I-frame; the first processing core and the second processing core are parts of a video encoder. n is an integer greater than or equal to 1.

[0104] In some embodiments, before the terminal obtains the (t + 1)th frame of the image to be compressed, the first processing core and the second processing core parallelly encode two adjacent slices of the tth frame of the image to be compressed. For example: the first processing core encodes the first slice while the second processing core encodes the second slice.

[0105] From the above analysis, it can be seen that since the encoding result of the previous frame is not required during the process of encoding a frame of the image to be compressed into an I-frame, therefore, the frame of the image to be compressed is sliced into multiple slices, and multiple processing cores are controlled to encode one slice respectively, that is, multiple processing cores parallelly encode a frame of the image to be compressed, thereby reducing the latency in the I-frame encoding process and further improving the encoding performance.

[0106] In step 204, the terminal obtains the (t + 1)th frame of the image to be compressed; the encoding result of the (t + 1)th frame of the image to be compressed is the first P-frame.

[0107] In some embodiments, when the first processing core is encoding the nth slice and the second processing core is encoding the (n + 1)th slice, and the (t + 1)th frame of the image to be compressed is obtained, the first processing core continues to encode the nth slice, and the second processing core continues to encode the (n + 1)th slice until the first processing core completes the encoding of the nth slice and the second processing core completes the encoding of the (n + 1)th slice, and then the CPU controls the second processing core to process the (t + 1)th frame of the image to be compressed. Optionally, after the first processing core completes the encoding of the nth slice and the second processing core completes the encoding of the (n + 1)th slice, the CPU controls the first processing core to process the (t + 1)th frame of the image to be compressed. Wherein, the CPU controls the first processing core and the second processing core through instructions.

[0108] In some embodiments, when the first processing core is about to encode the nth slice and the second processing core is about to encode the (n + 1)th slice, and the (t + 1)th frame of the image to be compressed is obtained, the CPU controls the first processing core to encode the nth slice and the second processing core to process the (t + 1)th frame of the image to be compressed. Optionally, the CPU controls the second processing core to encode the nth slice and the first processing core to process the (t + 1)th frame of the image to be compressed.

[0109] In step 205, the first processing core encodes the first first coding unit with reference to a slice coding result to obtain the first first coding result. The second processing core encodes the (n + 2)-th slice to obtain the (n + 2)-th slice coding result.

[0110] Among them, (n + 2) is an integer less than or equal to m. Each first coding unit is a part of the (t + 1)-th frame of the image to be compressed. Each first coding result is a part of the first P frame.

[0111] In one example, after the second processing core finishes encoding the (n + 2)-th slice, it encodes the remaining slices until the encoding of the (t)-th frame of the image to be compressed is completed. After the first processing core finishes encoding the first first coding unit, it continues to encode the remaining part of the (t + 1)-th frame of the image to be compressed until the encoding of the (t + 1)-th frame of the image to be compressed is completed.

[0112] In some embodiments, the size of the first coding unit is the same as the size of the slice.

[0113] Figure 6 It is a schematic diagram of the principle of a synchronization control module 602 provided according to an embodiment of the present application.

[0114] The following combines Figure 6 to make an exemplary description of the synchronization control module 602.

[0115] In some embodiments, before step 205, before the first processing core 6011 encodes the first coding unit, it first determines whether the first slice coding result that the first coding unit needs to refer to has been stored in the memory 603. Among them, the memory 603 includes a plurality of synchronization buffers, and the synchronization buffers correspond to the processing cores one by one. For example, the memory 603 is a Double Data Rate Synchronous Dynamic Random Access Memory (DDR). The first processing core 6011 is matched with the first synchronization buffer 6031; the first processing core 6012 is matched with the second synchronization buffer 6032.

[0116] In some embodiments, the first processing core 6011 accesses the synchronization control module 602. If the synchronization control module 602 indicates that the first slice coding result is stored in the memory 603, the first processing core 6011 obtains the first slice coding result from the memory 603. Or if the synchronization control module 602 indicates that the first slice coding result does not exist in the memory 603, the first processing core 6011 is in a waiting state; when the first processing core 6011 receives a wake-up signal, the first processing core 6011 obtains the first slice coding result from the memory 603; the wake-up signal is generated by the synchronization control module 602 based on the write state of the memory 603.

[0117] In one example, after the first processing core 6011 encodes a slice coding result, it writes the slice coding result into the first synchronization buffer 6031. The synchronization control module 602 accesses the first synchronization buffer 6031 to obtain the current write state of the first synchronization buffer 6031; the write state includes parameter information such as the height of the slice corresponding to the latest stored slice coding result. For example, the synchronization control module 602 detects the write state of the coding result in the memory 603 through a polling or interrupt mechanism, and generates a wake-up signal when it detects that the required coding result has been stored.

[0118] In one example, the first processing core 6012 of the video encoder 601 accesses the synchronization control module 602 to obtain parameter information such as the height of the slice corresponding to the latest stored slice coding result, and determines the storage situation of the slice coding result in the first synchronization buffer 6031. When there is at least the minimum number of slice coding results that need to be referenced, the first processing core 6012 obtains the slice coding results that need to be referenced, and encodes a first coding unit based on the slice coding results that need to be referenced to obtain a first coding result, and stores the first coding result in the second synchronization buffer 6032. It can be understood that the minimum number of slice coding results that need to be referenced means that there is at least one slice coding result that needs to be referenced by at least one first coding unit to be encoded.

[0119] In one example, the first processing core 6012 accesses the synchronization control module 602 to obtain parameter information such as the height of the slice corresponding to the latest stored slice coding result, determines the storage situation of the slice coding result in the first synchronization buffer 6031. When there is no least slice coding result to be referenced, the first processing core 6012 enters a waiting state. Then, the synchronization control module 602 accesses the first synchronization buffer 6031 based on a preset frequency, obtains the current writing state of the first synchronization buffer 6031, and determines whether the least slice coding result to be referenced has been stored in the first synchronization buffer 6031. If the least slice coding result to be referenced has been stored, the synchronization control module 602 generates a wake-up signal and sends the wake-up signal to the first processing core 6012. After receiving the wake-up signal, the first processing core 6012 obtains the slice coding result to be referenced from the first buffer, encodes a first coding unit based on the slice coding result to be referenced, obtains a first coding result, and stores the first coding result in the second synchronization buffer 6032.

[0120] The above steps 201 to 205 encode two frames of images to be compressed in parallel. After one frame is divided into multiple slices, it is encoded as an I frame; the other frame is encoded as the first P frame with reference to the previous frame. It should be noted that the I frame, the first P frame, and the second P frame involved in the embodiments of the present application are for a common GOP. For example, the first P frame is the first P frame in the GOP.

[0121] In some embodiments, after step 205, the terminal further processes the I frame and the P frame based on a preset algorithm to obtain a compressed bitstream. After the CPU receives an interrupt indicating that a complete frame has been encoded, it obtains the compressed bitstream data from the storage and saves the compressed bitstream data to the output buffer queue of the encoding channel. For example, the preset algorithm includes motion estimation, discrete cosine transform, quantization, and entropy coding, etc.

[0122] Through the above analysis, it can be seen that the present application does not divide the image to be compressed with a P frame coding result, thereby reducing the problem of image boundary quality fragmentation caused by excessive slices. Therefore, the embodiments of the present application implement different coding methods for images to be compressed with different types of coding results, thereby greatly improving the coding ability of the multi-processing core.

[0123] Figure 7 It is a schematic diagram of the principle of parallel encoding of two P frames according to an embodiment of the present application.

[0124] The following combines Figure 7 to give an exemplary illustration of the principle of parallel encoding of two P frames.

[0125] In some embodiments, when the encoding of the t-th frame of the image to be compressed is completed, an I-frame is obtained, and then the first processing core and the second processing core respectively encode a frame of the image to be compressed into a P-frame, that is, the encoding of two P-frames is parallel.

[0126] In one example, the terminal obtains the (t + j)-th frame of the image to be compressed; the encoding result of the (t + j)-th frame of the image to be compressed is the j-th P-frame. The first processing core encodes the first j-th encoding unit with reference to the encoding result of the first (j - 1)-th frame, and obtains the encoding result of the first j-th frame; each j-th encoding unit is a part of the (t + j + 1)-th frame of the image to be compressed; each encoding result of the j-th frame is a part of the j-th P-frame; j is an integer greater than or equal to 2; (t + j + 1) is an integer less than or equal to m;

[0127] The (t + j + 1)-th frame of the image to be compressed is obtained; the encoding result of the (t + j + 1)-th frame of the image to be compressed is the (j + 1)-th P-frame; the second processing core encodes the first (j + 1)-th encoding unit with reference to the encoding result of the first j-th frame, and obtains the encoding result of the first (j + 1)-th frame; each (j + 1)-th encoding unit is a part of the (t + j + 1)-th frame of the image to be compressed; each encoding result of the (j + 1)-th frame is a part of the (j + 1)-th P-frame. In this embodiment, the first processing core and the second processing core encode two frames of the image to be compressed in parallel, one of which is encoded into the j-th P-frame; the other frame is encoded into the (j + 1)-th P-frame with reference to the previous frame.

[0128] In some embodiments, since when encoding the image to be compressed into a P-frame, the encoding result of the previous frame of the image to be compressed needs to be referred to, and in the process of encoding the image to be compressed into a P-frame, it is encoded part by part, that is, one encoding unit is encoded each time. Therefore, it is necessary to determine whether the encoding result to be referred to is stored in the memory before encoding each encoding unit.

[0129] In one example, the second processing core accesses the synchronization control module. If the synchronization control module indicates that the encoding result of the first j-th frame is stored in the memory, the second processing core obtains the encoding result of the first j-th frame from the memory. Or if the synchronization control module indicates that the encoding result of the first j-th frame does not exist in the memory, the second processing core is in a waiting state; when the second processing core receives a wake-up signal, the second processing core obtains the encoding result of the first j-th frame from the memory.

[0130] In one example, before the first processing core encodes the first j-th coding unit with reference to the first (j - 1)-th coding result and obtains the first j-th coding result, it further includes: the first processing core accesses the synchronization control module. If the synchronization control module indicates that the first (j - 1)-th coding result is stored in the memory, the first processing core obtains the first (j - 1)-th coding result from the memory. Or if the synchronization control module indicates that the first (j - 1)-th coding result does not exist in the memory, the first processing core is in a waiting state; when the first processing core receives a wake-up signal, the first processing core obtains the first (j - 1)-th coding result from the memory; the wake-up signal is generated by the synchronization control module based on the write state of the memory.

[0131] Optionally, the first processing core accesses the synchronization control module. If the synchronization control module indicates that the k-th (j - 1)-th coding result is stored in the memory, the first processing core obtains the k-th (j - 1)-th coding result from the memory; k is an integer greater than or equal to 1; based on the first processing core encoding the k-th j-th coding unit with reference to the k-th (j - 1)-th coding result, the k-th j-th coding result is obtained; the second processing core accesses the synchronization control module. If the synchronization control module indicates that the k-th j-th coding result is stored in the memory, the second processing core obtains the k-th j-th coding result from the memory; based on the second processing core encoding the k-th (j + 1)-th coding unit with reference to the k-th j-th coding result, the k-th (j + 1)-th coding result is obtained.

[0132] Figure 8 It is a schematic diagram of the principle of parallel operation of multiple processing cores provided according to an embodiment of the present application.

[0133] The following combines Figure 8 to exemplarily illustrate the principle of parallel operation of multiple processing cores.

[0134] In some embodiments, when multiple processing cores operate in parallel, in some of the processing cores, each processing core encodes a slice; in some other processing cores, each processing core encodes a P-frame respectively.

[0135] In one example, the i-th processing core accesses the synchronization control module. If the synchronization control module indicates that the first slice coding result is stored in the memory, the i-th processing core obtains the first slice coding result from the memory. Or if the synchronization control module indicates that the first slice coding result does not exist in the memory, the i-th processing core is in a waiting state. When the i-th processing core receives a wake-up signal, the i-th processing core obtains the first slice coding result from the memory.

[0136] In one example, the first slice is encoded based on the first processing core to obtain the encoding result of the first slice; the second slice is encoded based on the second processing core to obtain the encoding result of the second slice; the i-th slice is encoded based on the i-th processing core to obtain the encoding result of the i-th slice, where i is an integer greater than or equal to 3 and less than m; the (t + 1)-th frame of the image to be compressed is obtained; the i-th processing core encodes the first first coding unit with reference to the encoding result of the first slice to obtain the first first encoding result; the first processing core encodes the (i + 1)-th slice to obtain the encoding result of the (i + 1)-th slice; the (i - 1)-th processing core encodes the (2i - 1)-th slice to obtain the encoding result of the (2i - 1)-th slice; the i-th processing core and the (i - 1)-th processing core are part of the video encoder.

[0137] In one example, the (t + 2)-th frame of the image to be compressed is obtained; the encoding result of the (t + 2)-th frame of the image to be compressed is the second P frame. The (i - 1)-th processing core encodes the first second coding unit with reference to the first first encoding result to obtain the first second encoding result; each second coding unit is part of the (t + 2)-th frame of the image to be compressed; each second encoding result is part of the second P frame; the i-th processing core encodes the second first coding unit with reference to the encoding result of the second slice to obtain the second first encoding result; the 2i-th slice is encoded based on the first processing core to obtain the encoding result of the 2i-th slice; the (3i - 3)-th slice is encoded based on the (i - 2)-th processing core to obtain the encoding result of the (3i - 3)-th slice.

[0138] Optionally, the i-th processing core accesses the synchronization control module. If the synchronization control module indicates that the encoding result of the p-th slice is stored in the memory, the i-th processing core obtains the encoding result of the p-th slice from the memory, where p is an integer greater than or equal to 1 and less than m. The first processing core encodes the p-th first coding unit with reference to the encoding result of the i-th slice to obtain the p-th first encoding result. The (i - 1)-th processing core accesses the synchronization control module. If the synchronization control module indicates that the q-th first encoding result is stored in the memory, the (i - 1)-th processing core obtains the q-th first encoding result from the memory; the (i - 1)-th processing core encodes the q-th second coding unit with reference to the q-th first encoding result to obtain the q-th second encoding result, where q is an integer greater than or equal to 1 and less than m.

[0139] In an embodiment of the present application, the to-be-compressed image with an I-frame coding result is sliced into multiple slices, and multiple processing cores are controlled to encode one slice respectively, that is, multiple processing cores encode one to-be-compressed image in parallel, thereby reducing the latency in the I-frame encoding process and improving the encoding performance. In addition, the to-be-compressed image with a P-frame coding result in the present application is not sliced, thereby reducing the problem of image boundary quality fragmentation caused by excessive slices. Therefore, the embodiment of the present application realizes selecting different encoding methods for to-be-compressed images with different types of coding results, thereby greatly improving the encoding ability of multiple processing cores.

[0140] Figure 9 FIG. 4 is a schematic structural diagram of a video compression device 900 provided according to an embodiment of the present application. The device includes:

[0141] An acquisition module 901, configured to acquire the t-th frame of to-be-compressed image; the t-th frame of to-be-compressed image is a part of the to-be-compressed video.

[0142] A slicing module 902, configured to slice the t-th frame of to-be-compressed image into m slices; the coding result of the t-th frame of to-be-compressed image is an I-frame. t and m are integers greater than or equal to 1.

[0143] An encoding module 903, configured to encode the n-th slice based on the first processing core to obtain the n-th slice encoding result; encode the (n + 1)-th slice based on the second processing core to obtain the (n + 1)-th slice encoding result; each slice encoding result is a part of the I-frame; the first processing core and the second processing core are parts of the video encoder. n is an integer greater than or equal to 1.

[0144] The acquisition module 904 is further configured to acquire the (t + 1)-th frame of to-be-compressed image; the coding result of the (t + 1)-th frame of to-be-compressed image is the first P-frame.

[0145] The encoding module 905 is further configured to encode the first first coding unit by the first processing core with reference to one slice encoding result to obtain the first first coding result; each first coding unit is a part of the (t + 1)-th frame of to-be-compressed image; each first coding result is a part of the first P-frame; the second processing core encodes the (n + 2)-th slice to obtain the (n + 2)-th slice encoding result; (n + 2) is an integer less than or equal to m.

[0146] In some embodiments, before the first processing core encodes the first first coding unit with reference to one slice encoding result to obtain the first first coding result, it further includes:

[0147] The first processing core accesses the synchronization control module. If the synchronization control module indicates that the first slice encoding result is stored in the memory, the first processing core obtains the first slice encoding result from the memory; or

[0148] If the synchronization control module indicates that the first slice coding result does not exist in the memory, the first processing core is in a waiting state;

[0149] When the first processing core receives a wake-up signal, the first processing core obtains the first slice coding result from the memory; the wake-up signal is generated by the synchronization control module based on the write state of the memory.

[0150] In some embodiments, the apparatus is further configured to:

[0151] Obtain the (t + j)-th frame of the image to be compressed; the coding result of the (t + j)-th frame of the image to be compressed is the j-th P frame;

[0152] The first processing core encodes the first j-th coding unit with reference to the first (j - 1)-th coding result to obtain the first j-th coding result; each j-th coding unit is a part of the (t + j + 1)-th frame of the image to be compressed; each j-th coding result is a part of the j-th P frame; j is an integer greater than or equal to 2; (t + j + 1) is an integer less than or equal to m;

[0153] Obtain the (t + j + 1)-th frame of the image to be compressed; the coding result of the (t + j + 1)-th frame of the image to be compressed is the (j + 1)-th P frame;

[0154] The second processing core encodes the first (j + 1)-th coding unit with reference to the first j-th coding result to obtain the first (j + 1)-th coding result; each (j + 1)-th coding unit is a part of the (t + j + 1)-th frame of the image to be compressed; each (j + 1)-th coding result is a part of the (j + 1)-th P frame.

[0155] In some embodiments, before the first processing core encodes the first j-th coding unit with reference to the first (j - 1)-th coding result to obtain the first j-th coding result, it further includes:

[0156] The first processing core accesses the synchronization control module. If the synchronization control module indicates that the first (j - 1)-th coding result is stored in the memory, the first processing core obtains the first (j - 1)-th coding result from the memory; or

[0157] If the synchronization control module indicates that the first (j - 1)-th coding result does not exist in the memory, the first processing core is in a waiting state;

[0158] When the first processing core receives a wake-up signal, the first processing core obtains the first (j - 1)-th coding result from the memory; the wake-up signal is generated by the synchronization control module based on the write state of the memory.

[0159] In some embodiments, before the second processing core encodes the first (j + 1)-th coding unit with reference to the first j-th coding result to obtain the first (j + 1)-th coding result, it further includes:

[0160] The second processing core accesses the synchronization control module. If the synchronization control module indicates that the first j-th coding result is stored in the memory, the second processing core obtains the first j-th coding result from the memory; or

[0161] If the synchronization control module indicates that the first j-th coding result does not exist in the memory, the second processing core is in a waiting state;

[0162] When the second processing core receives a wake-up signal, the second processing core obtains the first j-th coding result from the memory.

[0163] In some embodiments, the apparatus is further configured to:

[0164] The first processing core accesses the synchronization control module. If the synchronization control module indicates that the k-th (j - 1)-th coding result is stored in the memory, the first processing core obtains the k-th (j - 1)-th coding result from the memory; k is an integer greater than or equal to 1;

[0165] Based on the first processing core encoding the k-th j-th coding unit with reference to the k-th (j - 1)-th coding result to obtain the k-th j-th coding result;

[0166] The second processing core accesses the synchronization control module. If the synchronization control module indicates that the k-th j-th coding result is stored in the memory, the second processing core obtains the k-th j-th coding result from the memory; based on the second processing core encoding the k-th (j + 1)-th coding unit with reference to the k-th j-th coding result to obtain the k-th (j + 1)-th coding result.

[0167] In some embodiments, the apparatus is further configured to:

[0168] Based on the first processing core encoding the first slice to obtain the first slice coding result; based on the second processing core encoding the second slice to obtain the second slice coding result; based on the i-th processing core encoding the i-th slice to obtain the i-th slice coding result; i is an integer greater than or equal to 3 and less than m;

[0169] Obtain the (t + 1)-th frame of the image to be compressed;

[0170] The i-th processing core encodes the first first coding unit with reference to the coding result of the first slice, obtaining the first first coding result; the first processing core encodes the (i + 1)-th slice, obtaining the coding result of the (i + 1)-th slice; the (i - 1)-th processing core encodes the (2i - 1)-th slice, obtaining the coding result of the (2i - 1)-th slice; the i-th processing core and the (i - 1)-th processing core are part of a video encoder.

[0171] In some embodiments, the apparatus is further configured to:

[0172] Obtain the image to be compressed for the (t + 2)-th frame; the coding result of the image to be compressed for the (t + 2)-th frame is the second P-frame;

[0173] The (i - 1)-th processing core encodes the first second coding unit with reference to the first first coding result, obtaining the first second coding result; each second coding unit is part of the image to be compressed for the (t + 2)-th frame; each second coding result is part of the second P-frame; the i-th processing core encodes the second first coding unit with reference to the coding result of the second slice, obtaining the second first coding result; based on the first processing core, the 2i-th slice is encoded, obtaining the coding result of the 2i-th slice; based on the (i - 2)-th processing core, the (3i - 3)-th slice is encoded, obtaining the coding result of the (3i - 3)-th slice.

[0174] In some embodiments, before the i-th processing core encodes the first first coding unit with reference to the coding result of the first slice and obtains the first first coding result, it further includes:

[0175] The i-th processing core accesses the synchronization control module. If the synchronization control module indicates that the coding result of the first slice is stored in the memory, the i-th processing core obtains the coding result of the first slice from the memory; or

[0176] If the synchronization control module indicates that the coding result of the first slice does not exist in the memory, the i-th processing core is in a waiting state;

[0177] When the i-th processing core receives a wake-up signal, the i-th processing core obtains the coding result of the first slice from the memory.

[0178] In some embodiments, the apparatus is further configured to:

[0179] The i-th processing core accesses the synchronization control module. If the synchronization control module indicates that the coding result of the p-th slice is stored in the memory, the i-th processing core obtains the coding result of the p-th slice from the memory; p is an integer greater than or equal to 1 and less than m;

[0180] The first processing core encodes the p-th first coding unit with reference to the coding result of the i-th slice, obtaining the p-th first coding result;

[0181] The (i - 1)th processing core accesses the synchronization control module. If the synchronization control module indicates that the qth first encoding result is stored in the memory, the (i - 1)th processing core obtains the qth first encoding result from the memory; the (i - 1)th processing core encodes the qth second encoding unit with reference to the qth first encoding result to obtain the qth second encoding result; q is an integer greater than or equal to 1 and less than m.

[0182] It should be noted that when the video compression device provided in the above embodiment executes the corresponding steps, only the division of the above - mentioned functional modules is used for illustration. In practical applications, the above - mentioned functions can be allocated to different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the video compression device provided in the above embodiment and the embodiment of the video compression method belong to the same concept. For the specific implementation process, please refer to the method embodiment, which will not be elaborated here.

[0183] In the embodiment of the present application, the I - frame image to be compressed with the encoding result is sliced into multiple slices, and multiple processing cores are controlled to encode one slice respectively, that is, multiple processing cores encode one frame of the image to be compressed in parallel, thereby reducing the delay in the I - frame encoding process and improving the encoding performance. In addition, the present application does not slice the image to be compressed with the encoding result being a P - frame, thereby reducing the problem of image boundary quality fragmentation caused by too many slices. Therefore, the embodiment of the present application realizes selecting different encoding methods for images to be compressed with different types of encoding results, thereby greatly improving the encoding ability of multiple processing cores.

[0184] The embodiment of the present application also provides a computer device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor. When the processor executes the computer program, the above - mentioned method is implemented.

[0185] Taking the computer device as a terminal as an example, Figure 10 is a schematic structural diagram of a terminal provided by an embodiment of the present application. Refer to Figure 10 , the terminal 1000 can be: a smart phone, a tablet computer, an MP3 player (Moving Picture Experts Group Audio Layer III), an MP4 (Moving Picture Experts Group Audio Layer IV) player, a notebook computer, or a desktop computer. The terminal 1000 may also be referred to by other names such as user equipment, portable terminal, laptop terminal, desktop terminal, etc.

[0186] Generally, the terminal 1000 includes a processor 1001 and a memory 1002.

[0187] The processor 1001 may include one or more processing cores, such as a 4-core processor, a 5-core processor, etc. The processor 1001 may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), or PLA (Programmable Logic Array). The processor 1001 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the wake state, also known as the CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 1001 may be integrated with a GPU (Graphics Processing Unit), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 1001 may further include an AI (Artificial Intelligence) processor, and the AI processor is used to process computational operations related to machine learning.

[0188] The memory 1002 may include one or more computer-readable storage media, and the computer-readable storage media may be non-transitory. The memory 1002 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 1002 is used to store at least one program code, and the at least one program code is used to be executed by the processor 1001 to implement the process executed by the terminal in the method embodiments provided in this application for the above-mentioned method.

[0189] In some embodiments, the terminal 1000 may further optionally include a peripheral device interface 1003 and at least one peripheral device. The processor 1001, the memory 1002, and the peripheral device interface 1003 may be connected through a bus or signal lines. Each peripheral device may be connected to the peripheral device interface 1003 through a bus, signal lines, or a circuit board. Specifically, the peripheral devices include at least one of a display screen 1004, a camera assembly 1005, an audio circuit 1006, and a power supply 1007.

[0190] The peripheral device interface 1003 can be used to connect at least one I / O (Input / Output) related peripheral device to the processor 1001 and the memory 1002. In some embodiments, the processor 1001, the memory 1002, and the peripheral device interface 1003 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 1001, the memory 1002, and the peripheral device interface 1003 can be implemented on a separate chip or circuit board, and the embodiments of the present application do not limit this.

[0191] The display screen 1004 is used to display a UI (User Interface). The UI may include graphics, text, icons, videos, and any combination thereof. When the display screen 1004 is a touch display screen, the display screen 1004 also has the ability to collect touch signals on or above the surface of the display screen 1004. The touch signals can be input to the processor 1001 as control signals for processing. At this time, the display screen 1004 can also be used to provide virtual buttons and / or a virtual keyboard, also known as soft buttons and / or a soft keyboard. In some embodiments, there can be one display screen 1004, which is set on the front panel of the terminal 1000; in some other embodiments, there can be at least two display screens 1004, which are respectively set on different surfaces of the terminal 1000 or in a folding design; in some other embodiments, the display screen 1004 can be a flexible display screen, which is set on the curved surface or the folding surface of the terminal 1000. Even, the display screen 1004 can also be set to an irregular non-rectangular shape, that is, a special-shaped screen. The display screen 1004 can be prepared using materials such as LCD (Liquid Crystal Display) and OLED (Organic Light-Emitting Diode).

[0192] The camera module 1005 is used to collect images or videos. In some embodiments, the camera module 1005 includes a front camera and a rear camera. Generally, the front camera is set on the front panel of the terminal, and the rear camera is set on the back of the terminal. In some embodiments, there are at least two rear cameras, which are any one of a main camera, a depth-of-field camera, a wide-angle camera, and a telephoto camera respectively, to realize the function of background blurring by fusing the main camera and the depth-of-field camera, the function of panoramic shooting by fusing the main camera and the wide-angle camera, and the VR (Virtual Reality) shooting function or other fusion shooting functions. In some embodiments, the camera module 1005 can also include a flash. The flash can be a single-color-temperature flash or a dual-color-temperature flash. A dual-color-temperature flash refers to the combination of a warm-light flash and a cold-light flash, which can be used for light compensation under different color temperatures.

[0193] The audio circuit 1006 may include a microphone and a speaker. The microphone is used to collect sound waves of the user and the environment, and convert the sound waves into electrical signals for input to the processor 1001 for processing. For the purpose of stereo collection or noise reduction, there may be multiple microphones, which are respectively arranged at different parts of the terminal 1000. The microphone may also be an array microphone or an omnidirectional collection microphone. The speaker is used to convert the electrical signal from the processor 1001 into sound waves. The speaker may be a traditional thin film speaker or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, it can not only convert the electrical signal into sound waves audible to humans, but also convert the electrical signal into sound waves inaudible to humans for uses such as ranging. In some embodiments, the audio circuit 1006 may also include a headphone jack.

[0194] The power supply 1007 is used to supply power to each component in the terminal 1000. The power supply 1007 may be alternating current, direct current, a disposable battery or a rechargeable battery. When the power supply 1007 includes a rechargeable battery, the rechargeable battery may support wired charging or wireless charging. The rechargeable battery may also be used to support fast charging technology.

[0195] Those skilled in the art can understand that Figure 10 the structure shown in does not limit the terminal 1000, and may include more or fewer components than shown in the figure, or combine some components, or adopt different component arrangements.

[0196] Taking a computer device as a server as an example, Figure 11 FIG. is a schematic structural diagram of a server provided by an embodiment of the present application. The server 1100 may vary greatly due to different configurations or performances, and may include one or more processors (Central Processing Units, CPUs) 1101 and one or more memories 1102. Among them, at least one computer program is stored in the one or more memories 1102, and the at least one computer program is loaded and executed by the one or more processors 1101 to implement the above video compression method. Of course, the server 1100 may also have components such as a wired or wireless network interface, a keyboard, and an input / output interface for input / output. The server 1100 may also include other components for implementing device functions, which will not be elaborated here.

[0197] Embodiments of the present application also provide a computer-readable storage medium. The computer-readable storage medium includes a stored computer program. When the computer program runs, it controls the device where the computer-readable storage medium is located to execute the method described above. Optionally, the computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), magnetic tape, a floppy disk, an optical data storage device, etc.

[0198] Those of ordinary skill in the art can understand that all or part of the steps to implement the above embodiments can be completed by hardware or by a program instructing relevant hardware. The program can be stored in a computer-readable storage medium. The storage medium mentioned above can be a read-only memory, a magnetic disk, an optical disc, etc.

[0199] The above are only optional embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A video compression method, characterized in that, Including: Obtain the t-th frame of the image to be compressed; The t-th frame of the image to be compressed is a part of the video to be compressed; Divide the t-th frame of the image to be compressed into m slices; the encoding result of the t-th frame of the image to be compressed is an I-frame; t and m are integers greater than or equal to 1; Encode the n-th slice based on the first processing core to obtain the encoding result of the n-th slice; Encode the (n + 1)-th slice based on the second processing core to obtain the encoding result of the (n + 1)-th slice; each slice encoding result is a part of the I-frame; The first processing core and the second processing core are parts of a video encoder; n is an integer greater than or equal to 1; Obtain the (t + 1)-th frame of the image to be compressed; the encoding result of the (t + 1)-th frame of the image to be compressed is the first P-frame; The first processing core encodes the first first encoding unit with reference to one slice encoding result to obtain the first first encoding result; each first encoding unit is a part of the (t + 1)-th frame of the image to be compressed; each first encoding result is a part of the first P-frame; The second processing core encodes the (n + 2)-th slice to obtain the encoding result of the (n + 2)-th slice; (n + 2) is an integer less than or equal to m.

2. The method according to claim 1, wherein Before the first processing core encodes the first first encoding unit with reference to one slice encoding result to obtain the first first encoding result, it further includes: The first processing core accesses the synchronization control module. If the synchronization control module indicates that the first slice encoding result is stored in the memory, the first processing core obtains the first slice encoding result from the memory; or If the synchronization control module indicates that the first slice encoding result does not exist in the memory, the first processing core is in a waiting state; When the first processing core receives a wake-up signal, the first processing core obtains the first slice encoding result from the memory; the wake-up signal is generated by the synchronization control module based on the write state of the memory.

3. The method according to claim 2, wherein The method further includes: Obtain the (t + j)-th frame of the image to be compressed; the encoding result of the (t + j)-th frame of the image to be compressed is the j-th P-frame; The first processing core encodes the first j-th encoding unit with reference to the first (j - 1) encoding result to obtain the first j-th encoding result; each j-th encoding unit is a part of the (t + j + 1)-th frame of the image to be compressed; each j-th encoding result is a part of the j-th P-frame; j is an integer greater than or equal to 2; (t + j + 1) is an integer less than or equal to m; Obtain the (t + j + 1)-th frame of the image to be compressed; the encoding result of the (t + j + 1)-th frame of the image to be compressed is the (j + 1)-th P-frame; The second processing core encodes the first (j + 1)-th coding unit with reference to the first j-th coding result, to obtain the first (j + 1)-th coding result; each (j + 1)-th coding unit is a part of the image to be compressed in the (t + j + 1)-th frame; each (j + 1)-th coding result is a part of the (j + 1)-th P frame.

4. The method according to claim 3, wherein Before the first processing core encodes the first j-th coding unit with reference to the first (j - 1)-th coding result to obtain the first j-th coding result, it further includes: The first processing core accesses the synchronization control module. If the synchronization control module indicates that the first (j - 1)-th coding result is stored in the memory, the first processing core obtains the first (j - 1)-th coding result from the memory; or If the synchronization control module indicates that the first (j - 1)-th coding result does not exist in the memory, the first processing core is in the waiting state; When the first processing core receives the wake-up signal, the first processing core obtains the first (j - 1)-th coding result from the memory.

5. The method according to claim 4, characterized in that Before the second processing core encodes the first (j + 1)-th coding unit with reference to the first j-th coding result to obtain the first (j + 1)-th coding result, it further includes: The second processing core accesses the synchronization control module. If the synchronization control module indicates that the first j-th coding result is stored in the memory, the second processing core obtains the first j-th coding result from the memory; or If the synchronization control module indicates that the first j-th coding result does not exist in the memory, the second processing core is in the waiting state; When the second processing core receives the wake-up signal, the second processing core obtains the first j-th coding result from the memory.

6. The method according to claim 5, characterized in that, The method further includes: The first processing core accesses the synchronization control module. If the synchronization control module indicates that the k-th (j - 1)-th coding result is stored in the memory, the first processing core obtains the k-th (j - 1)-th coding result from the memory; k is an integer greater than or equal to 1; The first processing core encodes the k-th j-th coding unit with reference to the k-th (j - 1)-th coding result, to obtain the k-th j-th coding result; The second processing core accesses the synchronization control module. If the synchronization control module indicates that the k-th j-th coding result is stored in the memory, the second processing core obtains the k-th j-th coding result from the memory; the second processing core encodes the k-th (j + 1)-th coding unit with reference to the k-th j-th coding result, to obtain the k-th (j + 1)-th coding result.

7. The method according to claim 6, characterized in that The method further includes: Encode the first slice based on a first processing core to obtain an encoding result of the first slice; encode the second slice based on a second processing core to obtain an encoding result of the second slice; encode the i-th slice based on an i-th processing core to obtain an encoding result of the i-th slice, where i is an integer greater than or equal to 3 and less than m; Obtain the (t + 1)-th frame of the image to be compressed; The i-th processing core encodes the first first coding unit with reference to the encoding result of the first slice to obtain a first first encoding result; the first processing core encodes the (i + 1)-th slice to obtain an encoding result of the (i + 1)-th slice; the (i - 1)-th processing core encodes the (2i - 1)-th slice to obtain an encoding result of the (2i - 1)-th slice; the i-th processing core and the (i - 1)-th processing core are part of a video encoder.

8. The method according to claim 7, wherein The method further includes: Obtain the (t + 2)-th frame of the image to be compressed; the encoding result of the (t + 2)-th frame of the image to be compressed is the second P frame; The (i - 1)-th processing core encodes the first second coding unit with reference to the first first encoding result to obtain a first second encoding result; each second coding unit is part of the (t + 2)-th frame of the image to be compressed; each second encoding result is part of the second P frame; the i-th processing core encodes the second first coding unit with reference to the encoding result of the second slice to obtain a second first encoding result; the first processing core encodes the 2i-th slice to obtain an encoding result of the 2i-th slice; the (i - 2)-th processing core encodes the (3i - 3)-th slice to obtain an encoding result of the (3i - 3)-th slice.

9. The method according to claim 7, wherein Before the i-th processing core encodes the first first coding unit with reference to the encoding result of the first slice to obtain a first first encoding result, it further includes: The i-th processing core accesses a synchronization control module. If the synchronization control module indicates that the encoding result of the first slice is stored in a memory, the i-th processing core obtains the encoding result of the first slice from the memory; or If the synchronization control module indicates that the encoding result of the first slice does not exist in the memory, the i-th processing core is in the waiting state; When the i-th processing core receives a wake-up signal, the i-th processing core obtains the encoding result of the first slice from the memory.

10. The method according to claim 8, wherein The method further includes: The i-th processing core accesses the synchronization control module. If the synchronization control module indicates that the encoding result of the p-th slice is stored in the memory, the i-th processing core obtains the encoding result of the p-th slice from the memory, where p is an integer greater than or equal to 1 and less than m; The first processing core encodes the p-th first coding unit with reference to the encoding result of the i-th slice to obtain a p-th first encoding result; The (i - 1)-th processing core accesses the synchronization control module. If the synchronization control module indicates that the q-th first encoding result is stored in the memory, the (i - 1)-th processing core obtains the q-th first encoding result from the memory; the (i - 1)-th processing core encodes the q-th second encoding unit with reference to the q-th first encoding result to obtain the q-th second encoding result; q is an integer greater than or equal to 1 and less than m.

11. A video compression device, characterized in that, Including: An acquisition module, configured to acquire the t-th frame of the image to be compressed; The t-th frame of the image to be compressed is a part of the video to be compressed; A slicing module, configured to slice the t-th frame of the image to be compressed into m slices; The encoding result of the t-th frame of the image to be compressed is an I-frame; t and m are integers greater than or equal to 1; An encoding module, configured to encode the n-th slice based on a first processing core to obtain the encoding result of the n-th slice; Encode the (n + 1)-th slice based on a second processing core to obtain the encoding result of the (n + 1)-th slice; each encoding result of the slice is a part of the I-frame; The first processing core and the second processing core are parts of a video encoder; n is an integer greater than or equal to 1; The acquisition module is further configured to acquire the (t + 1)-th frame of the image to be compressed; the encoding result of the (t + 1)-th frame of the image to be compressed is the first P-frame; The encoding module is further configured to encode the first first encoding unit with reference to an encoding result of one slice by the first processing core to obtain the first first encoding result; each first encoding unit is a part of the (t + 1)-th frame of the image to be compressed; each first encoding result is a part of the first P-frame; The second processing core encodes the (n + 2)-th slice to obtain the encoding result of the (n + 2)-th slice; (n + 2) is an integer less than or equal to m.

12. A computer device, characterized in that, The computer device includes a processor and a memory, and the memory is used to store at least one program, and the at least one program is loaded and executed by the processor to perform the video compression method according to any one of claims 1 to 10.

13. A computer-readable storage medium, characterized in that, At least one program is stored in the computer-readable storage medium, and the at least one program is loaded and executed by a processor to implement the video compression method according to any one of claims 1 to 10.

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