Semiconductor device

Abstract

A semiconductor device may include: a pass transistor on a first surface of a substrate; a pull-down transistor sharing an active region with the pass transistor; a pull-up transistor sharing a gate with the pull-down transistor; a word line connected to a gate of the pass transistor; a bit line connected to a drain of the pass transistor; a first power supply wiring on the second surface of the substrate and connected to a source of the pull-down transistor; and a second power supply wiring connected to a source of the pull-up transistor. The source of the pass transistor and the drains of the pull-down transistor and the pull-up transistor may be connected by a node. A word line, a bit line, and a second power wiring may be on the first surface of the substrate. A first portion of the first power supply wiring may extend in a direction parallel to a gate of the pass transistor.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices. Background Art

[0002] SRAM (Static Random Access Memory) is a memory device that typically has a high operation speed and requires low operation power because data does not need to be refreshed. A typical application of SRAM is as a memory element of a mobile device such as a mobile phone. Generally, an SRAM memory cell includes two transfer transistors and two inverters that form a flip-flop circuit.

[0003] When forming an SRAM cell using a CMOS process, it may be difficult to reduce the size of the SRAM cell because six transistors are provided in a single SRAM cell. In particular, as the process is miniaturized, the margin between metal wirings and contacts for connecting a large number of transistors and applying signals is decreasing, which becomes an obstacle to the miniaturization of the SRAM cell. Summary of the Invention

[0004] Aspects of the present disclosure provide a semiconductor device having improved reliability.

[0005] However, aspects of the present disclosure are not limited to the aspects described herein. By referring to the detailed description of the present disclosure given below, the above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains.

[0006] According to an exemplary embodiment of the present disclosure, a semiconductor device may include: a substrate including a first surface and a second surface opposite to each other in a first direction; a first active pattern on the first surface and extending in a second direction that intersects the first direction; a second active pattern on the first surface and spaced apart from the first active pattern in a third direction that intersects the first direction and the second direction, the second active pattern extending in the second direction; a first gate electrode intersecting the first active pattern and extending in the third direction; a second gate electrode spaced apart from the first gate electrode in the second direction, the second gate electrode intersecting the first active pattern and the second active pattern; a first source / drain pattern on the first active pattern, the first source / drain pattern being disposed between the first gate electrode and the second gate electrode; a second source / drain pattern on the first active pattern, the second gate electrode being located between the first source / drain pattern and the second source / drain pattern; a third source / drain pattern on the second active pattern and spaced apart from the first source / drain pattern in the third direction; and a first power supply wiring on the second surface and electrically connected to the second source / drain pattern. The first source / drain pattern and the third source / drain pattern may be electrically shared through the same node. A first portion of the first power supply wiring may extend in the third direction under the second source / drain pattern.

[0007] According to an exemplary embodiment of the present disclosure, a semiconductor device may include: a substrate including a first surface and a second surface opposite to each other in a first direction; a transfer transistor on the first surface of the substrate; a pull-down transistor sharing an active region with the transfer transistor; a pull-up transistor sharing a gate electrode with the pull-down transistor; a word line electrically connected to the gate electrode of the transfer transistor; a bit line electrically connected to the drain pattern of the transfer transistor; a first power supply wiring electrically connected to the source pattern of the pull-down transistor; and a second power supply wiring electrically connected to the source pattern of the pull-up transistor. The source pattern of the transfer transistor, the drain pattern of the pull-down transistor, and the drain pattern of the pull-up transistor may be electrically connected through a single node. The first power supply wiring may be on the second surface. The word line, the bit line, and the second power supply wiring may be on the first surface. A first portion of the first power supply wiring may extend in a direction parallel to an extending direction of the gate electrode of the transfer transistor.

[0008] According to an exemplary embodiment of the present disclosure, a semiconductor device may include: a substrate including a first NMOS region, a second NMOS region, and a PMOS region between the first NMOS region and the second NMOS region, the substrate including a first surface and a second surface opposite to each other in a first direction; a first transfer transistor and a first pull-down transistor on the first surface of the substrate in the first NMOS region; a second transfer transistor and a second pull-down transistor on the first surface of the substrate in the second NMOS region; a first pull-up transistor on the first surface of the substrate in the PMOS region, the first pull-up transistor sharing a gate electrode with the first pull-down transistor; a second pull-up transistor on the first surface of the substrate in the PMOS region and sharing a gate electrode with the second pull-down transistor; a first power supply wiring configured to apply a negative voltage to each of the source patterns of the first pull-down transistor and the second pull-down transistor; and a second power supply wiring configured to apply a positive voltage to each of the source patterns of the first pull-up transistor and the second pull-up transistor. The first transfer transistor and the first pull-down transistor may share an active region. The second transfer transistor and the second pull-down transistor may share an active region. The source pattern of the first transfer transistor, the drain pattern of the first pull-down transistor, and the drain pattern of the first pull-up transistor may be electrically connected through a first node. The source pattern of the second transfer transistor, the drain pattern of the second pull-down transistor, and the drain pattern of the second pull-up transistor may be electrically connected through a second node. The first power supply wiring may be on the second surface of the substrate. The second power supply wiring may be on the first surface of the substrate. The first power supply wiring may extend in a direction parallel to an extending direction of the gate electrode of the first transfer transistor and an extending direction of the gate electrode of the second transfer transistor. The second power supply wiring may extend in a direction parallel to an extending direction of the active pattern of the first transfer transistor and an extending direction of the active pattern of the second transfer transistor. Description of the Drawings

[0009] The above and other aspects and features of the present disclosure will become more apparent by describing in detail example embodiments of the present disclosure with reference to the accompanying drawings, wherein:

[0010] Figure 1 is an example circuit diagram for illustrating a semiconductor device according to some embodiments.

[0011] Figure 2 is an example layout diagram for illustrating a semiconductor device according to some embodiments of the present disclosure.

[0012] Figure 3 is Figure 2 an enlarged view of region C1 of

[0013] Figure 4 is Figure 3 an example cross-sectional view taken along line A1-A1 of

[0014] Figure 5 is Figure 3 an example cross-sectional view taken along line A2-A2 of

[0015] Figure 6 is Figure 3 an example cross-sectional view taken along line A3-A3 of

[0016] Figure 7 is Figure 3 an example cross-sectional view taken along line A4-A4 of

[0017] Figure 8 is an example layout diagram for illustrating a semiconductor device according to some other embodiments of the present disclosure.

[0018] Figure 9 is Figure 8 an example cross-sectional view taken along line B1-B1 of

[0019] Figure 10 and Figure 11 is Figure 8 an example cross-sectional view taken along line B2-B2 of

[0020] Figures 12 to 16 is an example diagram for illustrating a semiconductor device according to some other embodiments of the present disclosure. Detailed Description of Specific Embodiments

[0021] Although the drawings of the semiconductor device according to some embodiments show transistors and MBCFETs including nanowires or nanosheets TMA (multi-bridge trench field effect transistor) is taken as an example, but the example implementation is not limited thereto. The semiconductor device according to some embodiments may of course include a tunneling transistor (tunneling FET) or a three-dimensional (3D) transistor. The semiconductor device according to some embodiments may of course include a planar transistor. In addition, the technical idea of the present disclosure can be applied to transistors based on two-dimensional materials and their heterostructures (2D material-based FETs).

[0022] In addition, the semiconductor device according to some embodiments may further include a bipolar junction transistor, a laterally diffused metal oxide semiconductor (LDMOS), etc.

[0023] Embodiments according to the technical idea of the present disclosure will be described below with reference to the accompanying drawings. First, reference will be made to Figures 1 to 3 Describe a semiconductor device according to some embodiments of the present disclosure.

[0024] Figure 1 is an example circuit diagram for illustrating a semiconductor device according to some embodiments.

[0025] Refer to Figure 1 , a semiconductor device according to some embodiments may include at least one or more units. Each unit may include a first bit line BL1 and a second bit line BL2, a word line WL, and a plurality of transistors. That is, Figure 1 may be a circuit diagram of one of the multiple units of the display semiconductor device.

[0026] Specifically, the semiconductor device may include a first transfer transistor PG1, a second transfer transistor PG2, a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, and a second pull-down transistor PD2.

[0027] The first pull-up transistor PU1 and the second pull-up transistor PU2 may be P-type MOSFETs (metal oxide semiconductor field effect transistors). The first transfer transistor PG1, the second transfer transistor PG2, the first pull-down transistor PD1, and the second pull-down transistor PD2 may be N-type MOSFETs. That is, the semiconductor device may include six transistors, including four NMOS transistors and two PMOS transistors.

[0028] The switching electrodes (e.g., gate electrodes) of the first transfer transistor PG1 and the second transfer transistor PG2 can be connected to the word line WL. The drain pattern of the first transfer transistor PG1 can be connected to the first bit line BL1. The drain pattern of the second transfer transistor PG2 can be connected to the second bit line BL2. A positive voltage VDD can be applied to the source pattern of the first pull-up transistor PU1. A positive voltage VDD can be applied to the source pattern of the second pull-up transistor PU2. A negative voltage VSS can be applied to the source pattern of the first pull-down transistor PD1. A negative voltage VSS can be applied to the source pattern of the second pull-down transistor PD2.

[0029] The source pattern of the first transfer transistor PG1, the drain pattern of the first pull-up transistor PU1, and the drain pattern of the first pull-down transistor PD1 can be commonly connected to the first node N1.

[0030] The source pattern of the second transfer transistor PG2, the drain pattern of the second pull-up transistor PU2, and the drain pattern of the second pull-down transistor PD2 can be commonly connected to the second node N2.

[0031] The switching electrodes (e.g., gate electrodes) of the first pull-up transistor PU1 and the first pull-down transistor PD1 can be commonly connected to the second node N2. The switching electrodes (e.g., gate electrodes) of the second pull-up transistor PU2 and the second pull-down transistor PD2 can be commonly connected to the first node N1. Thus, the first and second pull-up transistors PU1 and PU2 and the first and second pull-down transistors PD1 and PD2 can form a latch circuit including a pair of CMOS inverters.

[0032] When a high signal is applied to the first node N1, the second pull-up transistor PU2 is turned off, the second pull-down transistor PD2 is turned on, and a low signal is applied to the second node N2. When a low signal is applied to the second node N2, the first pull-up transistor PU1 is turned on, the second pull-down transistor PD2 is turned off, and the first node N1 maintains a high signal.

[0033] When a high signal is applied to the second node N2, the first pull-up transistor PU1 is turned off, the first pull-down transistor PD1 is turned on, and a low signal is applied to the first node N1. When a low signal is applied to the first node N1, the second pull-up transistor PU2 is turned on, the second pull-down transistor PD2 is turned off, and the second node N2 maintains a high signal.

[0034] Accordingly, the first and second transfer transistors PG1 and PG2 are turned on in response to a switching signal applied to the word line WL. At this time, data signals supplied to the first bit line BL1 and the second bit line BL2 can be latched to the first node N1 and the second node N2 through the first transfer transistor PG1 and the second transfer transistor PG2. When the first and second transfer transistors PG1 and PG2 are turned on, the data latched to the first and second nodes N1 and N2 can be provided to the first and second bit lines BL1 and BL2 through the first and second transfer transistors PG1 and PG2. The data latched to the first and second nodes N1 and N2 can be read by sensing the signals provided to the first and second bit lines BL1 and BL2 with the help of a sense amplifier.

[0035] The first transfer transistor PG1 may share an active region with the first pull-down transistor PD1. The second transfer transistor PG2 may share an active region with the second pull-down transistor PD2. The first pull-down transistor PD1 may share a gate electrode with the first pull-up transistor PU1. The second pull-down transistor PD2 may share a gate electrode with the second pull-up transistor PU2. The gate electrodes of each of the first transfer transistor PG1 and the second transfer transistor PG2 are not shared with the gate electrodes of other transistors.

[0036] In some embodiments, a first power supply wiring (e.g., Figure 4 PL1) for applying a negative voltage to the source patterns of the first pull-down transistor PD1 and the second pull-down transistor PD2 may be disposed under the substrate. A second power supply wiring (e.g., Figure 5 PL2) for applying a positive voltage to the source patterns of the first pull-up transistor PU1 and the second pull-up transistor PU2 may be disposed above the substrate. In addition, the word line WL and the first bit line BL1 and the second bit line BL2 may be disposed above the substrate. This will be described in detail using Figures 3 to 7 This will be described in detail using

[0037] In some embodiments, the first pull-down transistor PD1 and the second pull-down transistor PD2 may be N-type MOSFETs (metal-oxide-semiconductor field-effect transistors). The first transfer transistor PG1, the second transfer transistor PG2, the first pull-up transistor PU1, and the second pull-up transistor PU2 may be P-type MOSFETs. That is, the semiconductor device may include six transistors composed of four PMOS transistors and two NMOS transistors.

[0038] The first transfer transistor PG1 may share an active region with the first pull-up transistor PU1. The second transfer transistor PG2 may share an active region with the second pull-up transistor PU2. The first pull-down transistor PD1 may share a gate electrode with the first pull-up transistor PU1. The second pull-down transistor PD2 may share a gate electrode with the second pull-up transistor PU2. The gate electrodes of each of the first transfer transistor PG1 and the second transfer transistor PG2 are not shared with the gate electrodes of other transistors.

[0039] In some embodiments, a power supply wiring for applying a positive voltage to the source patterns of the first pull-up transistor PU1 and the second pull-up transistor PU2 may be disposed under the substrate. A power supply wiring for applying a negative voltage to the source patterns of the first pull-down transistor PD1 and the second pull-down transistor PD2 may be disposed above the substrate. In addition, word lines WL and first bit lines BL1 and second bit lines BL2 may be disposed above the substrate.

[0040] Figure 2 is an exemplary layout diagram for explaining a semiconductor device according to some embodiments of the present disclosure.

[0041] Referring to Figure 2 , a semiconductor device according to some embodiments may include a first unit region C1, a second unit region C2, a third unit region C3, and a fourth unit region C4.

[0042] In Figure 2 , although the semiconductor device is shown as including four unit regions C1, C2, C3, and C4, the technical idea of the present disclosure is not limited thereto. The semiconductor device of the present disclosure may include five or more unit regions.

[0043] The first unit region C1 may be adjacent to the second unit region C2 and the third unit region C3. The first unit region C1 and the second unit region C2 may be adjacent to each other in a second direction D2. The first unit region C1 and the third unit region C3 may be adjacent to each other in a third direction D3. In the present specification, the first direction D1, the second direction D2, and the third direction D3 may intersect each other. The first direction D1 may be a direction substantially perpendicular to the upper surface of the substrate, and each of the second direction D2 and the third direction D3 may be substantially parallel to the upper surface of the substrate.

[0044] Based on the third direction D3, the layout structure of the first unit region C1 may be symmetric with the layout structure of the second unit region C2. Based on the second direction D2, the layout structure of the first unit region C1 may be symmetric with the layout structure of the third unit region C3.

[0045] Similarly, the fourth unit region C4 can be adjacent to the second unit region C2 and the third unit region C3. The fourth unit region C4 and the second unit region C2 can be adjacent to each other in the third direction D3. The fourth unit region C4 and the third unit region C3 can be adjacent to each other in the second direction D2. Based on the second direction D2, the layout structure of the fourth unit region C4 can be symmetrical to the layout structure of the second unit region C2. Based on the third direction D3, the layout structure of the fourth unit region C4 can be symmetrical to the layout structure of the third unit region C3.

[0046] Since the first unit region C1, the second unit region C2, the third unit region C3, and the fourth unit region C4 can be substantially the same, only the first unit region C1 will be described below.

[0047] For example, the first unit region C1 can include first and second transfer transistors PG1 and PG2, first and second pull - down transistors PD1 and PD2, and first and second pull - up transistors PU1 and PU2.

[0048] In addition, the first unit region C1 can include a first gate electrode G1, a second gate electrode G2, a third gate electrode G3, and a fourth gate electrode G4. The first unit region C1 can include a first active pattern AP1, a second active pattern AP2, a third active pattern AP3, and a fourth active pattern AP4.

[0049] The first transfer transistor PG1 and the first pull - down transistor PD1 can share the first active pattern AP1. The gate electrode of the first transfer transistor PG1 can be the first gate electrode G1. The first pull - down transistor PD1 and the first pull - up transistor PU1 can share the second gate electrode G2. The active pattern of the first pull - up transistor PU1 can be the second active pattern AP2.

[0050] The second transfer transistor PG2 and the second pull - down transistor PD2 can share the fourth active pattern AP4. The gate electrode of the second transfer transistor PG2 can be the third gate electrode G3. The second pull - down transistor PD2 and the second pull - up transistor PU2 can share the fourth gate electrode G4. The active pattern of the second pull - up transistor PU2 can be the third active pattern AP3.

[0051] The semiconductor device according to some embodiments can include a first power supply wiring PL1. The first power supply wiring PL1 can be electrically connected to the source pattern of the first pull - down transistor PD1 and the source pattern of the second pull - down transistor PD2. The source pattern of the first pull - down transistor PD1 and the source pattern of the second pull - down transistor PD2 can each be electrically connected to the first power supply wiring PL1 through a first via VA1. The first power supply wiring PL1 can apply a negative voltage VSS to the source pattern of the first pull - down transistor PD1 and the source pattern of the second pull - down transistor PD2.

[0052] The first power supply wiring PL1 may extend along the third direction D3. The first power supply wiring PL1 may extend in the same direction as the extending direction of the gate electrodes G1, G2, G3, and G4. In addition, the first power supply wiring PL1 may be disposed under the transistors. That is, the first power supply wiring PL1 may be disposed under the substrate. In addition, the first power supply wiring PL1 may be arranged to overlap each of two adjacent cells in the second direction D2 in the first direction D1. This will be described in more detail using Figures 3 to 7 be described in more detail.

[0053] Figure 3 is Figure 2 an enlarged view of the region C1 in Figure 4 is along Figure 3 an example cross-sectional view taken along the line A1-A1 of Figure 5 is along Figure 3 an example cross-sectional view taken along the line A2-A2 of Figure 6 is along Figure 3 an example cross-sectional view taken along the line A3-A3 of Figure 7 is along Figure 3 an example cross-sectional view taken along the line A4-A4 of

[0054] Referring to Figures 3 to 7 , a semiconductor device according to some embodiments may include a first active pattern AP1, a second active pattern AP2, a third active pattern AP3, a fourth active pattern AP4, a first gate electrode G1, a second gate electrode G2, a third gate electrode G3, and a fourth gate electrode G4.

[0055] First, a substrate 100 may be provided. The substrate 100 may include a plurality of active regions and field regions. Each of the plurality of active regions may be a region in which the first active pattern AP1, the second active pattern AP2, the third active pattern AP3, or the fourth active pattern AP4 is disposed. The field regions may be formed directly adjacent to the plurality of active regions. The field regions may form a boundary with the plurality of active regions.

[0056] The plurality of active regions are spaced apart from each other. The plurality of active regions may be separated by the field regions. In other words, an element isolation film may be disposed around the plurality of active regions spaced apart from each other. At this time, a portion of the element isolation film between the plurality of active regions may be the field region. For example, a portion where a channel region of a transistor (which may be an example of a semiconductor device) is formed may be an active region, and a portion that divides the channel region of the transistor formed in the active region may be a field region. Alternatively, the active region may be a portion where a fin pattern or a nanosheet used as a channel region of a transistor is formed, and the field region may be a region where a fin pattern or a nanosheet used as a channel region is not formed.

[0057] The substrate 100 may include a first surface 100a and a second surface 100b that face each other in a first direction D1. The substrate 100 may be a silicon substrate or silicon-on-insulator (SOI). Alternatively, the substrate 100 may include, but is not limited to, silicon germanium, silicon-germanium-on-insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0058] The substrate 100 may include a first region R1, a second region R2, and a third region R3. The third region R3 may be interposed between the first region R1 and the second region R2. A first active pattern AP1 is disposed on the substrate 100 of the first region R1. Two transistors may be disposed on the substrate 100 of the first region R1. A fourth active pattern AP4 is disposed on the substrate 100 of the second region R2. Two transistors may be disposed on the substrate 100 of the second region R2. A second active pattern AP2 and a third active pattern AP3 are disposed on the substrate 100 of the third region R3. Two transistors may be disposed on the substrate 100 of the third region R3.

[0059] In some embodiments, the first region R1 and the second region R2 may be a first NMOS region and a second NMOS region, respectively. In this case, the third region R3 may be a PMOS region. A first transfer transistor and a first pull-down transistor are disposed on the substrate 100 of the first NMOS region. A second transfer transistor and a second pull-down transistor are disposed on the substrate 100 of the second NMOS region. A first pull-up transistor and a second pull-up transistor are disposed on the substrate 100 of the PMOS region.

[0060] In another embodiment, the first region R1 and the second region R2 may be a first PMOS region and a second PMOS region, respectively. In this case, the third region R3 may be an NMOS region. A first transfer transistor and a first pull-up transistor are disposed on the substrate 100 of the first PMOS region. A second transfer transistor and a second pull-up transistor are disposed on the substrate 100 of the second PMOS region. A first pull-down transistor and a second pull-down transistor are disposed on the substrate 100 of the NMOS region.

[0061] Hereinafter, a description will be provided based on the assumption that the first region R1 and the second region R2 are each of the first and second NMOS regions and the third region R3 is a PMOS region.

[0062] The first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4 may each be disposed on the first surface 100a of the substrate 100. The first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4 may extend on the substrate 100 along the second direction D2. The first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4 may be spaced apart from each other in the third direction D3.

[0063] From the perspective of a plan view, the first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4 may each include a long surface extending along the second direction D2 and a short surface extending along the third direction D3. Here, the second direction D2 may intersect the third direction D3 and the first direction D1. In addition, the third direction D3 may intersect the first direction D1. The first direction D1 may be the thickness direction of the substrate 100.

[0064] Each of the first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4 may be a multi-channel active pattern. The first active pattern AP1 may include a first lower pattern BP1 and a plurality of first sheet patterns SP1. The second active pattern AP2 may include a second lower pattern BP2 and a plurality of second sheet patterns SP2. Although not shown, the third active pattern AP3 may include a third lower pattern and a plurality of third sheet patterns. The fourth active pattern AP4 may include a fourth lower pattern and a plurality of fourth sheet patterns. For ease of explanation, the description of the third active pattern AP3 and the fourth active pattern AP4 will be omitted.

[0065] The first lower pattern BP1 may protrude from the substrate 100 along the first direction D1. The first lower pattern BP1 may extend longer in the second direction D2. The first lower pattern BP1 may be a fin pattern. The plurality of first sheet patterns SP1 may be disposed on the first lower pattern BP1. The plurality of first sheet patterns SP1 may be spaced apart from the first lower pattern BP1 in the first direction D1. In addition, the plurality of first sheet patterns SP1 may be spaced apart from each other in the first direction D1. Although three first sheet patterns SP1 are shown as being disposed in the first direction D1, this is merely for ease of explanation and the embodiments are not limited thereto.

[0066] The second lower pattern BP2 may protrude from the substrate 100 in the first direction D1. The second lower pattern BP2 may extend longer in the second direction D2. The second lower pattern BP2 may be a fin pattern. Although not shown, a plurality of second sheet patterns SP2 may be provided on the second lower pattern BP2. The plurality of second sheet patterns SP2 may be spaced apart from the second lower pattern BP2 in the first direction D1. In addition, the plurality of second sheet patterns SP2 may be spaced apart from each other in the first direction D1.

[0067] Both the first lower pattern BP1 and the second lower pattern BP2 may be formed by etching a part of the substrate 100, or may include an epitaxial layer grown from the substrate 100. The first lower pattern BP1 and the second lower pattern BP2 may each include silicon or germanium as an elemental semiconductor material. In addition, the first lower pattern BP1 and the second lower pattern BP2 may each include a compound semiconductor, such as a Group-IV / IV compound semiconductor or a Group-III / V compound semiconductor.

[0068] The Group-IV / IV compound semiconductor may be, for example, a binary compound or a ternary compound including at least two or more of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound obtained by doping these elements with a Group-IV element.

[0069] The Group-III / V compound semiconductor may be, for example, one of a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In) as a Group-III element with one of phosphorus (P), arsenic (As), and antimony (Sb) as a Group-V element.

[0070] The first sheet pattern SP1 and the second sheet pattern SP2 may each include one of silicon or germanium as an elemental semiconductor material, a Group-IV / IV compound semiconductor, or a Group-III / V compound semiconductor. Each first sheet pattern SP1 may include the same material as the first lower pattern BP1, or may include a material different from the first lower pattern BP1. Each second sheet pattern SP2 may include the same material as the second lower pattern BP2, or may include a material different from the second lower pattern BP2.

[0071] In a semiconductor device according to some embodiments, the first lower pattern BP1 and the second lower pattern BP2 may be silicon lower patterns including silicon, and the first sheet pattern SP1 and the second sheet pattern may be silicon sheet patterns including silicon.

[0072] A field insulating film 105 may be formed on the first substrate 100. The field insulating film 105 may be formed on the first surface 100a of the first substrate 100.

[0073] The field insulating film 105 may cover sidewalls of the first lower pattern BP1 and sidewalls of the second lower pattern BP2. Each of the first sheet patterns SP1 and each of the second sheet patterns are disposed higher than an upper surface of the field insulating film 105. The field insulating film 105 may include, for example, an oxide film, a nitride film, a oxynitride film, or a combination thereof. Although the field insulating film 105 is shown as a single film, embodiments are not limited thereto. Different from the illustrated example, the field insulating film 105 may include a field liner extending along sidewalls and a bottom surface of a trench defining the first and second lower patterns BP1 and BP2 and a field fill film on the field liner.

[0074] The first to fourth gate electrodes G1, G2, G3, and G4 may be disposed on a first surface 100a of the substrate 100. The first to fourth gate electrodes G1, G2, G3, and G4 may be disposed on the field insulating film 105. The first to fourth gate electrodes G1, G2, G3, and G4 may each extend in a third direction D3.

[0075] The first gate electrode G1 may be disposed on the first active pattern AP1. The first gate electrode G1 may cross the first active pattern AP1. The first gate electrode G1 may surround the first sheet pattern SP1. The second gate electrode G2 may be disposed on the first active pattern AP1, the second active pattern AP2, and the third active pattern AP3. The second gate electrode G2 may cross each of the first active pattern AP1, the second active pattern AP2, and the third active pattern AP3. The second gate electrode G2 may surround the first sheet pattern SP1, the second sheet pattern SP2, and the third sheet pattern. The third gate electrode G3 may be disposed on the fourth active pattern AP4. The fourth gate electrode G4 may be disposed on the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4.

[0076] In Figure 4 , although upper surfaces of the first gate electrode G1 and the second gate electrode G2 may each be convex surfaces recessed toward an upper surface of the first lower pattern BP1, embodiments are not limited thereto. That is, different from the illustrated example, upper surfaces of the first gate electrode G1 and the second gate electrode G2 may be flat planes.

[0077] The first to fourth gate electrodes G1, G2, G3, and G4 may each include, for example, at least one of titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbon nitride (TiAlCN), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbon nitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof.

[0078] The first to fourth gate electrodes G1, G2, G3, and G4 may each include a conductive metal oxide, a conductive metal oxynitride, etc., and may include an oxidized form of the foregoing materials.

[0079] The first gate electrode G1 may be disposed between the first source / drain pattern SDP1 and the third source / drain pattern SDP3, which will be described hereinafter. The second gate electrode G2 may be disposed between the first source / drain pattern SDP1 and the second source / drain pattern SDP2.

[0080] In some embodiments, the first gate electrode G1 may be the gate electrode of the first transfer transistor PG1. The second gate electrode G2 may be the gate electrode of the first pull-down transistor PD1 and the first pull-up transistor PU1.

[0081] The first gate spacer GS1 may be disposed on the sidewalls of the first gate electrode G1. The first gate spacer GS1 does not contact the first gate electrode G1. The first gate insulating film GI1 may be disposed between the first gate electrode G1 and the first gate spacer GS1.

[0082] The second gate spacer GS2 may be disposed on the sidewalls of the second gate electrode G2. The second gate spacer GS2 does not contact the second gate electrode G2. The second gate insulating film GI2 may be disposed between the second gate electrode G2 and the second gate spacer GS2.

[0083] Each of the first gate spacer GS1 and the second gate spacer GS2 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon carbon oxide (SiOC), and combinations thereof.

[0084] The first gate insulating film GI1 may extend between the upper surface of the first gate electrode G1 and the first lower pattern BP1 and between the first gate electrode G1 and the first sheet pattern SP1. In addition, the first gate insulating film GI1 may be formed between the first gate electrode G1 and the first gate spacer GS1.

[0085] The second gate insulating film GI2 may be formed between the second gate electrode G2 and the upper surface of the first lower pattern BP1, between the second gate electrode G2 and the upper surface of the second lower pattern BP2, between the second gate electrode G2 and the first sheet pattern SP1, and between the second gate electrode G2 and the second sheet pattern SP2. In addition, the second gate insulating film GI2 may be formed between the second gate electrode G2 and the second gate spacer GS2.

[0086] Each of the first gate insulating film GI1 and the second gate insulating film GI2 may include silicon oxide, silicon oxynitride, silicon nitride, or a high-k material having a dielectric constant higher than that of silicon oxide. The high-k material may include, for example, one or more of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0087] Although each of the first and second gate insulating films GI1 and GI2 is shown as a single film, this is for illustrative purposes only and the embodiments are not limited thereto. Each of the first and second gate insulating films GI1 and GI2 may include a plurality of films.

[0088] A semiconductor device according to some embodiments may include an NC (negative capacitance) FET using a negative capacitor. For example, each of the first and second gate insulating films GI1 and GI2 may include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0089] A ferroelectric material film can have a negative capacitance, and a paraelectric material film can have a positive capacitance. For example, if two or more capacitors are connected in series and each capacitor has a positive capacitance value, the total capacitance decreases from the capacitance of each individual capacitor. On the other hand, if at least one of the capacitances of two or more capacitors connected in series has a negative value, the total capacitance can be greater than the absolute value of each individual capacitance while having a positive value.

[0090] When a ferroelectric material film having a negative capacitance and a paraelectric material film having a positive capacitance are connected in series, the total capacitance value of the series-connected ferroelectric material film and paraelectric material film can increase. By using the increased total capacitance value, a transistor including the ferroelectric material film can have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0091] The ferroelectric material film can have ferroelectric properties. The ferroelectric material film can include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanate, barium titanate, and lead zirconium titanate. Here, as an example, hafnium zirconium oxide can be a material obtained by doping hafnium oxide with zirconium (Zr). As another example, hafnium zirconium oxide can be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0092] The ferroelectric material film can further include a doped dopant. For example, the dopant can include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant included in the ferroelectric material film can vary according to the type of ferroelectric material included in the ferroelectric material film.

[0093] When the ferroelectric material film includes hafnium oxide, the dopant included in the ferroelectric material film can include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0094] When the dopant is aluminum (Al), the ferroelectric material film can contain 3 to 8 at% (atomic percentage) of aluminum. Here, the ratio of the dopant can be the ratio of aluminum to the sum of hafnium and aluminum.

[0095] When the dopant is silicon (Si), the ferroelectric material film can include 2 to 10 at% of silicon. When the dopant is yttrium (Y), the ferroelectric material film can include 2 to 10 at% of yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film can include 1 to 7 at% of gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film can include 50 to 80 at% of zirconium.

[0096] The paraelectric material film can have paraelectric properties. The paraelectric material film can include at least one of, for example, silicon oxide and metal oxides with a high dielectric constant. The metal oxide contained in the paraelectric material film can include at least one of, for example but not limited to, hafnium oxide, zirconium oxide, and aluminum oxide.

[0097] The ferroelectric material film and the paraelectric material film can contain the same materials. The ferroelectric material film has ferroelectric properties, but the paraelectric material film may not have ferroelectric properties. For example, when the ferroelectric material film and the paraelectric material film contain hafnium oxide, the crystal structure of the hafnium oxide contained in the ferroelectric material film is different from the crystal structure of the hafnium oxide contained in the paraelectric material film.

[0098] The ferroelectric material film can have a thickness with ferroelectric properties. The thickness of the ferroelectric material film can be, for example, 0.5 to 10 nm, but is not limited thereto. Since the critical thickness for exhibiting ferroelectric properties may be different for each ferroelectric material, the thickness of the ferroelectric material film can vary depending on the ferroelectric material.

[0099] As an example, each of the first and second gate insulating films GI1 and GI2 can include a ferroelectric material film. As another example, each of the first and second gate insulating films GI1 and GI2 can include a plurality of ferroelectric material films spaced apart from each other. Each of the first and second gate insulating films GI1 and GI2 can have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0100] The first gate capping film GC1 can be disposed on the upper surface of the first gate electrode G1 and the upper surface of the first gate spacer GS1. The second gate capping film GC2 can be disposed on the upper surface of the second gate electrode G2 and the upper surface of the second gate spacer GS2. Each of the first gate capping film GC1 and the second gate capping film GC2 can include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and combinations thereof.

[0101] The first source / drain pattern SDP1 can be disposed on the first active pattern AP1. The first source / drain pattern SDP1 can be disposed on the first lower pattern BP1. The first source / drain pattern SDP1 can be disposed between the first gate electrode G1 and the second gate electrode G2.

[0102] The second source / drain pattern SDP2 may be disposed on the first active pattern AP1. The second source / drain pattern SDP2 may be disposed on the first lower pattern BP1. The second source / drain pattern SDP2 may be opposite to the first source / drain pattern SDP1, and the second gate electrode G2 is located therebetween. That is, the first source / drain pattern SDP1 may be disposed on one side of the second gate electrode G2, and the second source / drain pattern SDP2 may be disposed on the other side of the second gate electrode G2.

[0103] The third source / drain pattern SDP3 may be disposed on the first active pattern AP1. The third source / drain pattern SDP1 may be disposed on the first lower pattern BP1. The third source / drain pattern SDP3 may be opposite to the first source / drain pattern SDP1, and the first gate electrode G1 is located therebetween. That is, the first source / drain pattern SDP1 may be disposed on one side of the first gate electrode G1, and the third source / drain pattern SDP3 may be disposed on the other side of the first gate electrode G1.

[0104] The fourth source / drain pattern SDP4 may be disposed on the second active pattern AP2. The fourth source / drain pattern SDP4 may be disposed on the second lower pattern BP2. The fourth source / drain pattern SDP4 may be spaced apart from the first source / drain pattern SDP1 in the third direction D3. The fourth source / drain pattern SDP4 may be disposed on one side of the second gate electrode G2.

[0105] The fifth source / drain pattern SDP5 may be disposed on the second active pattern AP2. The fifth source / drain pattern SDP5 may be disposed on the second lower pattern BP2. The fifth source / drain pattern SDP5 may be spaced apart from the second source / drain pattern SDP2 in the third direction D3. The fifth source / drain pattern SDP5 may be disposed on the other side of the second gate electrode G2. That is, the fourth source / drain pattern SDP4 and the fifth source / drain pattern SDP5 may be opposite to each other, and the second gate electrode G2 is located therebetween.

[0106] In some embodiments, the first source / drain pattern SDP1 may be the source pattern of the first transfer transistor PG1, while the first source / drain pattern SDP1 may be the drain pattern of the first pull-down transistor PD1. The second source / drain pattern SDP2 may be the source pattern of the first pull-down transistor PD1. The third source / drain pattern SDP3 may be the drain pattern of the first transfer transistor PG1. The fourth source / drain pattern SDP4 may be the drain pattern of the first pull-up transistor PU1. The fifth source / drain pattern SDP5 may be the source pattern of the first pull-up transistor PU1.

[0107] Each of the first to fifth source / drain patterns SDP1, SDP2, SDP3, SDP4, and SDP5 may include an epitaxial pattern. Each of the first to fifth source / drain patterns SDP1, SDP2, SDP3, SDP4, and SDP5 may include a semiconductor material. The first to fifth source / drain patterns SDP1, SDP2, SDP3, SDP4, and SDP5 may be included in the source / drain of a transistor using the first sheet pattern SP1 or the second sheet pattern SP2 as a channel region.

[0108] The first source / drain pattern SDP1, the second source / drain pattern SDP2, and the third source / drain pattern SDP3 may be connected to the channel region of the first active pattern AP1 serving as a channel. For example, the first source / drain pattern SDP1, the second source / drain pattern SDP2, and the third source / drain pattern SDP3 may be connected to the first sheet pattern SP1.

[0109] The fourth source / drain pattern SDP4 and the fifth source / drain pattern SDP5 may be connected to the channel region of the second active pattern AP2 serving as a channel. For example, the fourth source / drain pattern SDP4 and the fifth source / drain pattern SDP5 may be connected to the second sheet pattern SP2.

[0110] The etch stop film 160 may extend along the upper surface of the field insulating film 105, the sidewalls of the first and second spacers GS1 and GS2, and the contours of the first source / drain pattern SDP1, the second source / drain pattern SDP2, the third source / drain pattern SDP3, the fourth source / drain pattern SDP4, and the fifth source / drain pattern SDP5. In some embodiments, the etch stop film 160 is not provided on the sidewalls of the first and second gate capping films GC1 and GC2. That is, each of the first and second gate capping films GC1 and GC2 may be provided on the upper surface of the etch stop film 160. In addition, the sidewalls of the etch stop film 160 may be connected to the outer walls of the first and second gate capping films GC1 and GC2. Different from the illustrated example, the etch stop film 160 may be provided on the sidewalls of the first and second gate capping films GC1 and GC2.

[0111] The etch stop film 160 may include a material having an etch selectivity with respect to the first interlayer insulating film 190, which will be described below. The etch stop film 160 may include a nitride-based insulating material. For example, it may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), and combinations thereof.

[0112] The first interlayer insulating film 190 is disposed on the etch stop film 160. The first interlayer insulating film 190 may be formed on the field insulating film 105. The first interlayer insulating film 190 may be disposed on the first source / drain pattern SDP1, the second source / drain pattern SDP2, the third source / drain pattern SDP3, the fourth source / drain pattern SDP4, and the fifth source / drain pattern SDP5. The first interlayer insulating film 190 may not cover the upper surfaces of the first and second gate capping films GC1 and GC2. For example, the upper surface of the first interlayer insulating film 190 may be coplanar with the upper surfaces of the first and second gate capping films GC1 and GC2.

[0113] The first interlayer insulating film 190 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. The low dielectric constant material may include, for example, but not limited to, tetraethyl orthosilicate fluoride (FTEOS), hydrogen silsesquioxane (HSQ), benzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxyditert-butoxysilane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), TOSZ (Tonen SilaZen), FSG (fluorosilicate glass), polyimide nanofoams such as polypropylene oxide, CDO (carbon-doped silicon oxide), OSG (organic silicate glass), SiLK, amorphous fluorocarbon, silica aerogel, silica xerogel, mesoporous silica, or a combination thereof.

[0114] The first gate contact CB1 may be disposed on the first gate electrode G1. The first gate contact CB1 may be electrically connected to the first gate electrode G1. The first gate contact CB1 may be electrically connected to the word line WL, which will be described below. That is, the word line WL may be electrically connected to the first gate electrode G1 through the first gate contact CB1. In addition, a gate contact may also be disposed on the third gate electrode G3. Another word line and the third gate electrode G3 may be electrically connected through the gate contact.

[0115] The second gate contact CB2 is disposed on the second gate electrode G2. The second gate contact CB2 may be electrically connected to the second gate electrode G2. The second gate contact CB2 may be electrically connected to the first source / drain contact CA1 through the node pattern ND. That is, the same signal may be applied to the second gate electrode G2, the first source / drain pattern SDP1, and the fourth source / drain pattern SDP4 through the node pattern ND.

[0116] The first source / drain contact CA1 can be disposed on the first source / drain pattern SDP1 on the first active pattern AP1. The first source / drain contact CA1 can be disposed on the fourth source / drain pattern SDP4 on the second active pattern AP2. That is, the first source / drain pattern SDP1 and the fourth source / drain pattern SDP4 can be electrically connected to each other through the first source / drain contact CA1.

[0117] The third source / drain contact CA3 can be disposed on the third source / drain pattern SDP3 on the first active pattern AP1. The fifth source / drain contact CA5 can be disposed on the fifth source / drain pattern SDP5 on the second active pattern AP2.

[0118] The first source / drain contact CA1 passes through the etch stop film 160 and can be connected to the first source / drain pattern SDP1 and the fourth source / drain pattern SDP4. The first source / drain contact CA1 can be disposed inside the first interlayer insulating film 190. The first source / drain contact CA1 can be surrounded by the first interlayer insulating film 190.

[0119] The third source / drain contact CA3 passes through the etch stop film 160 and can be connected to the third source / drain pattern SDP3. The third source / drain contact CA3 can be disposed inside the first interlayer insulating film 190. The third source / drain contact CA3 can be surrounded by the first interlayer insulating film 190.

[0120] The fifth source / drain contact CA5 passes through the etch stop film 160 and can be connected to the fifth source / drain pattern SDP5. The fifth source / drain contact CA5 can be disposed inside the first interlayer insulating film 190. The fifth source / drain contact CA5 can be surrounded by the first interlayer insulating film 190.

[0121] The first contact silicide film 151 can be disposed between the first source / drain contact CA1 and the first source / drain pattern SDP1. Although the first contact silicide film 151 is shown as being formed along the contour of the interface between the first source / drain pattern SDP1 and the first source / drain contact CA1, the embodiments are not limited thereto.

[0122] Similarly, the fourth contact silicide film 154 can be disposed between the first source / drain contact CA1 and the fourth source / drain pattern SDP4. The third contact silicide film 153 can be disposed between the third source / drain contact CA3 and the third source / drain pattern SDP3. The fifth contact silicide film 155 can be disposed between the fifth source / drain contact CA5 and the fifth source / drain pattern SDP5.

[0123] Each of the first contact silicide film 151, the third contact silicide film 153, the fourth contact silicide film 154, and the fifth contact silicide film 155 may include, for example, a metal silicide material.

[0124] The first interlayer insulating film 190 does not cover the upper surfaces of the first source / drain contact CA1, the third source / drain contact CA3, and the fifth source / drain contact CA5. As an example, the upper surfaces of the first source / drain contact CA1, the third source / drain contact CA3, and the fifth source / drain contact CA5 do not protrude above the upper surfaces of the first and second gate capping films GC1 and GC2. The upper surfaces of the first source / drain contact CA1, the third source / drain contact CA3, and the fifth source / drain contact CA5 may be coplanar with the upper surfaces of the first and second gate capping films GC1 and GC2.

[0125] In some embodiments, the first source / drain contact CA1 may include a first source / drain barrier film CA1a and a first source / drain fill film CA1b on the first source / drain barrier film CA1a. The third source / drain contact CA3 may include a third source / drain barrier film CA3a and a third source / drain fill film CA3b on the third source / drain barrier film CA3a. The fifth source / drain contact CA5 may include a fifth source / drain barrier film CA5a and a fifth source / drain fill film CA5b on the fifth source / drain barrier film CA5a.

[0126] Since the first source / drain barrier film CA1a, the third source / drain barrier film CA3a, and the fifth source / drain barrier film CA5a are substantially the same, and the first source / drain fill film CA1b, the third source / drain fill film CA3b, and the fifth source / drain fill film CA5b are substantially the same, only the first source / drain barrier film CA1a and the first source / drain fill film CA1b will be described below.

[0127] The first source / drain blocking film CA1a may include, for example, at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), tungsten carbon nitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), and two-dimensional (2D) materials. In a semiconductor device according to some embodiments, the 2D material may be a metal material and / or a semiconductor material. The 2D material may include 2D allotropes or 2D compounds, and may include, but is not limited to, at least one of graphene, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten diselenide (WSe2), and tungsten disulfide (WS2). That is, since the above 2D materials are only listed as examples, the 2D materials that can be included in the semiconductor device of the present disclosure are not limited by the above materials.

[0128] The first source / drain filling film CA1b may include, for example, at least one of aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn), and molybdenum (Mo).

[0129] Although the first source / drain filling film CA1b is shown as including a plurality of conductive films, the embodiments are not limited thereto. Different from the shown example, the first source / drain contact CA1 may be a single film.

[0130] In some embodiments, the second gate contact CB2 may include a second gate contact blocking film CB2a and a second gate contact filling film CB2b. The material included in the second gate contact blocking film CB2a may be the same as the material included in the first source / drain blocking film CA1a. The material included in the second gate contact filling film CB2b may be the same as the material included in the first source / drain filling film CA1b.

[0131] A semiconductor device according to some embodiments may include a first power supply wiring PL1, a second power supply wiring PL2, a first bit line BL1, a word line WL, and a second bit line BL2.

[0132] The first power supply wiring PL1 may be disposed on the second surface 100b of the substrate 100. The first power supply wiring PL1 may be disposed under the transfer transistor, the pull-down transistor, and the pull-up transistor. The first power supply wiring PL1 may be electrically connected to the second source / drain pattern SDP2. The first power supply wiring PL1 may apply a negative voltage VSS to the second source / drain pattern SDP2.

[0133] Specifically, the first via VA1 can be disposed between the first power supply wiring PL1 and the second source / drain pattern SDP2. The first via VA1 can extend toward the substrate 100 on the upper surface of the first power supply wiring PL1. The upper surface of the first power supply wiring PL1 can face the second surface 100b of the substrate 100.

[0134] The first via VA1 can penetrate the substrate 100 and the first lower pattern BP1 and be directly connected to the second source / drain pattern SDP2. The second contact silicide film 152 can be formed between the first via VA1 and the second source / drain pattern SDP2.

[0135] The first via VA1 can include a first via barrier film VA1a and a first via filling film VA1b on the first via barrier film VA1a. The material included in the first via barrier film VA1a can be the same as the material included in the first source / drain barrier film CA1a. The material included in the first via filling film VA1b can be the same as the material included in the first source / drain filling film CA1b.

[0136] The first power supply wiring PL1 can extend along the third direction D3. The first power supply wiring PL1 can extend in the same direction as the extension direction of the gate electrodes G1, G2, G3, and G4. The first power supply wiring PL1 can be electrically connected to the source pattern of the pull-down transistor included in the plurality of cells. Since the first power supply wiring PL1 is disposed on the second surface 100b of the substrate 100, the design freedom of other wirings can be increased. Therefore, a semiconductor device with improved reliability can be manufactured.

[0137] The first power supply wiring PL1 can include a first power supply wiring barrier film PL1a and a first power supply wiring filling film PL1b on the first power supply wiring barrier film PL1a. The material included in the first power supply wiring barrier film PL1a can be the same as the material included in the first source / drain barrier film CA1a. The material included in the first power supply wiring filling film PL1b can be the same as the material included in the first source / drain filling film CA1b.

[0138] The first power supply wiring PL1 may be surrounded by the lower insulating film 102. The lower insulating film 102 may be disposed on the second surface 100b of the substrate 100. The lower insulating film 102 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. The low dielectric constant material may include, for example but not limited to, tetraethyl orthosilicate fluoride (FTEOS), hydrogen silsesquioxane (HSQ), benzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxyditert-butoxysilane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), TOSZ (Tonen SilaZen), FSG (fluorosilicate glass), polyimide nanofoams such as polypropylene oxide, CDO (carbon-doped silicon oxide), OSG (organic silicate glass), SiLK, amorphous fluorocarbon, silica aerogel, silica xerogel, mesoporous silica, or a combination thereof.

[0139] The second power supply wiring PL2 may be disposed on the first surface 100a of the substrate 100. From the perspective of a plan view, the second power supply wiring PL2 may be disposed between the second active pattern AP2 and the third active pattern AP3. The second power supply wiring PL2 may be disposed above the transfer transistor, the pull-down transistor, and the pull-up transistor. The second power supply wiring PL2 may be electrically connected to the fifth source / drain pattern SDP5. The second power supply wiring PL2 may apply a positive voltage VDD to the fifth source / drain pattern SDP5.

[0140] Specifically, the third via VA3 may be disposed between the second power supply wiring PL2 and the fifth source / drain pattern SDP5. The third via VA3 may extend from the lower surface of the second power supply wiring PL2 toward the substrate 100. The lower surface of the second power supply wiring PL2 may face the first surface 100a of the substrate 100. The third via VA3 may pass through the upper stop film 191 and the second interlayer insulating film 192, and be directly connected to the fifth source / drain contact CA5.

[0141] The third via VA3 may include a third via barrier film VA3a and a third via filling film VA3b on the third via barrier film VA3a. The material contained in the third via barrier film VA3a may be the same as the material contained in the first source / drain barrier film CA1a. The material contained in the third via filling film VA3b may be the same as the material contained in the first source / drain filling film CA1b.

[0142] The second power supply wiring PL2 may extend along the second direction D2. The second power supply wiring PL2 may extend in a direction different from that of the first power supply wiring PL1. The second power supply wiring PL2 may extend in the same direction as the extending direction of the active pattern. The second power supply wiring PL2 may be electrically connected to the source pattern of the pull-up transistor included in the plurality of cells.

[0143] The second power supply wiring PL2 may include a second power supply wiring blocking film PL2a and a second power supply wiring filling film PL2b on the second power supply wiring blocking film PL2a. The material included in the second power supply wiring blocking film PL2a may be the same as the material included in the first source / drain blocking film CA1a. The material included in the second power supply wiring filling film PL2b may be the same as the material included in the first source / drain filling film CA1b.

[0144] The upper stop film 191 is provided on the first interlayer insulating film 190. The second interlayer insulating film 192 is provided on the upper stop film 191. The upper stop film 191 may include a material having an etching selectivity with respect to the second interlayer insulating film 192. The upper stop film 191 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon carbon oxide (SiOC), aluminum oxide (AlO), aluminum nitride (AlN), aluminum carbon oxide (AlOC), and combinations thereof. Although the upper stop film 191 is shown as a single film, the embodiments are not limited thereto. Different from the illustrated example, the upper stop film 191 may not be formed. The second interlayer insulating film 192 may include at least one of, for example, silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, and a low dielectric constant material.

[0145] The first bit line BL1 may be provided on the first surface 100a of the substrate 100. The first bit line BL1 may be provided above the transfer transistor, the pull-down transistor, and the pull-up transistor. The first bit line BL1 may be electrically connected to the third source / drain pattern SDP3. The first bit line BL1 may apply a signal to the third source / drain pattern SDP3.

[0146] Specifically, the second via VA2 may be provided between the first bit line BL1 and the third source / drain pattern SDP3. The second via VA2 may extend toward the substrate 100 on the lower surface of the first bit line BL1. The lower surface of the first bit line BL1 may face the first surface 100a of the substrate 100. The second via VA2 may pass through the upper stop film 191 and the second interlayer insulating film 192, and may be directly connected to the third source / drain contact CA3.

[0147] The second via VA2 may include a second via blocking film VA2a and a second via filling film VA2b on the second via blocking film VA2a. The material included in the second via blocking film VA2a may be the same as the material included in the first source / drain blocking film CA1a. The material included in the second via filling film VA2b may be the same as the material included in the first source / drain filling film CA1b.

[0148] The first bit line BL1 may extend along the second direction D2. The first bit line BL1 may extend in a direction different from that of the first power supply wiring PL1. The first bit line BL1 may extend in the same direction as the second power supply wiring PL2. The first bit line BL1 and the second power supply wiring PL2 may be provided at the same vertical level. The first bit line BL1 and the second power supply wiring PL2 may be spaced apart from each other in the third direction D3. The first bit line BL1 may extend in the same direction as the extending direction of the active pattern.

[0149] The first bit line BL1 may include a first bit line blocking film BL1a and a first bit line filling film BL1b on the first bit line blocking film BL1a. The material included in the first bit line blocking film BL1a may be the same as the material included in the first source / drain blocking film CA1a. The material included in the first bit line filling film BL1b may be the same as the material included in the first source / drain filling film CA1b.

[0150] In some embodiments, the first bit line BL1 is provided on the first active pattern AP1. The second bit line BL2 is provided on the fourth active pattern AP4. The first bit line BL1 may be electrically connected to the drain pattern of the first transfer transistor included in the plurality of cells. The second bit line BL2 may be electrically connected to the drain pattern of the second transfer transistor included in the plurality of cells.

[0151] The first bit line BL1 and the second power supply wiring PL2 may be surrounded by a third interlayer insulating film 193. The third interlayer insulating film 193 may include at least one of, for example, silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, and a low dielectric constant material.

[0152] The word line WL may extend in the third direction D3. The word line WL may extend in a direction different from that of the first bit line BL1 and the second bit line BL2. Based on the first surface 100a of the substrate 100, the word line WL may be provided at a higher vertical level than the first bit line BL1 and the second bit line BL2. The word line WL may be connected to the first gate electrode G1 through the first gate contact CB1. The word line WL may apply a signal to the gate electrode of the first transfer transistor. Although not shown, the word line WL may also be connected to the third gate electrode G3. The word line WL may apply a signal to the gate electrode of the second transfer transistor through another gate contact.

[0153] The word line WL may include a word line blocking film WLa and a word line filling film WLb on the word line blocking film WLa. The material included in the word line blocking film WLa may be the same as the material included in the first source / drain blocking film CA1a. The material included in the word line filling film WLb may be the same as the material included in the first source / drain filling film CA1b.

[0154] The word line WL may be surrounded by a fourth interlayer insulating film 194. The fourth interlayer insulating film 194 may include at least one of, for example, silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, and a low dielectric constant material.

[0155] The semiconductor device according to some embodiments may further include a node pattern ND. The node pattern ND may be disposed on the first source / drain contact CA1 and the second gate contact CB2. A signal may be applied to the first source / drain pattern SDP1, the fourth source / drain pattern SDP4, and the fourth gate electrode G4 through the node pattern ND, the first source / drain contact CA1, and the second gate contact CB2. The node pattern ND may pass through the second interlayer insulating film 192 and the upper stop film 191 and be connected to the first source / drain contact CA1 and the second gate contact CB2.

[0156] The node pattern ND may include a node pattern blocking film NDa and a node pattern filling film NDb on the node pattern blocking film NDa. The material included in the node pattern blocking film NDa may be the same as the material included in the first source / drain blocking film CA1a. The material included in the node pattern filling film NDb may be the same as the material included in the first source / drain filling film CA1b.

[0157] Although the transistors included in the semiconductor device according to some embodiments are shown as MBCFETs, the technical idea of the present disclosure is not limited thereto. The transistors may be FinFETs or GAAFETs including nanowires.

[0158] Hereinafter, reference will be made to Figures 8 to 11 to describe semiconductor devices according to some other embodiments of the present disclosure. For ease of explanation, repeated content described using Figures 3 to 7 will be briefly described or omitted.

[0159] Figure 8 is an example layout diagram for explaining semiconductor devices according to some other embodiments of the present disclosure. Figure 9 is Figure 8 an example cross-sectional view taken along line B1 - B1. Figure 10 and Figure 11 is along Figure 8An exemplary cross-sectional view taken along line B2-B2.

[0160] First, referring to Figures 8 to 10 , in a semiconductor device according to some embodiments, the first via VA1 may not be directly connected to the second source / drain pattern SDP2. A semiconductor device according to some embodiments may include a second source / drain contact CA2.

[0161] The second source / drain contact CA2 may be disposed on the second source / drain pattern SDP2 on the first active pattern AP1. The second source / drain contact CA2 may pass through the etch stop film 160 and the first interlayer insulating film 190 and be connected to the second source / drain pattern SDP2. The second contact silicide film 152 may be disposed between the second source / drain contact CA2 and the second source / drain pattern SDP2.

[0162] The second source / drain contact CA2 may include a second source / drain barrier film CA2a and a second source / drain fill film CA2b on the second source / drain barrier film CA2a. The material included in the second source / drain barrier film CA2a may be the same as the material included in the first source / drain barrier film CA1a. The material included in the second source / drain fill film CA2b may be the same as the material included in the first source / drain fill film CA1b.

[0163] The first via VA1 is not directly connected to the second source / drain pattern SDP2. The first via VA1 may be directly connected to the second source / drain contact CA2. That is, the first power supply wiring PL1 and the second source / drain pattern SDP2 may be electrically connected through the first via VA1 and the second source / drain contact CA2.

[0164] The first via VA1 may pass through the substrate 100, the field insulating film 105, and the etch stop film 160 and be connected to the lower surface of the second source / drain contact CA2. The lower surface of the second source / drain contact CA2 may face the first surface 100a of the substrate 100.

[0165] Referring to Figure 11 , a semiconductor device according to some embodiments may further include a wiring contact CT and a fifth via VA5.

[0166] The fifth via VA5 may be disposed on the second source / drain contact CA2. The fifth via VA5 may be electrically connected to the second source / drain contact CA2 and may be electrically connected to the wiring contact CT. The wiring contact CT may pass through the first interlayer insulating film 190, the etch stop film 160, and the field insulating film 105 from the lower surface of the fifth via VA5 and may be connected to the first via VA1.

[0167] That is, the first power supply wiring PL1 can be electrically connected to the second source / drain pattern SDP2 through the first via VA1, the wiring contact CT, the fifth via VA5, and the second source / drain contact CA2.

[0168] The fifth via VA5 can include a fifth via barrier film VA5a and a fifth via fill film VA5b on the fifth via barrier film VA5a. The material included in the fifth via barrier film VA5a can be the same as the material included in the first source / drain barrier film CA1a. The material included in the fifth via fill film VA5b can be the same as the material included in the first source / drain fill film CA1b.

[0169] The wiring contact CT can include a wiring contact barrier film CTa and a wiring contact fill film CTb on the wiring contact barrier film CTa. The material included in the wiring contact barrier film CTa can be the same as the material included in the first source / drain barrier film CA1a. The material included in the wiring contact fill film CTb can be the same as the material included in the first source / drain fill film CA1b.

[0170] Hereinafter, a semiconductor device according to some other embodiments of the present disclosure will be described with reference to Figures 12 to 16 For ease of explanation, repeated content described using Figures 3 to 7 will be briefly described or omitted.

[0171] Figures 12 to 16 is an example diagram for explaining a semiconductor device according to some other embodiments of the present disclosure.

[0172] With reference to Figure 12 the first power supply wiring PL1 can include a first portion PL1_1 and a second portion PL1_2.

[0173] The first portion PL1_1 of the first power supply wiring PL1 can extend along the third direction D3, and the second portion PL1_2 of the first power supply wiring PL1 can extend along the second direction D2. The second portion PL1_2 of the first power supply wiring PL1 can extend along the second direction D2 between a pair of first portions PL1_1 of the first power supply wiring PL1. The second portion PL1_2 of the first power supply wiring PL1 can be connected to each of the pair of first portions PL1_1 of the first power supply wiring PL1.

[0174] That is, from the perspective of a plan view, the first power supply wiring PL1 can be formed as a rectangular closed curve.

[0175] With reference to Figure 13 the first power supply wiring PL1 can include a first portion PL1_1 and a second portion PL1_2.

[0176] Although the first part PL1_1 of the first power supply wiring PL1 extends in the third direction D3, the second part PL1_2 of the first power supply wiring PL1 can be arranged in an island shape. That is, the second part PL1_2 of the first power supply wiring PL1 can be spaced apart from the first part PL1_1 of the first power supply wiring PL1.

[0177] A part of the second part PL1_2 of the first power supply wiring PL1 can be arranged in an island shape at a position overlapping with the source patterns of the first pull-down transistors PD1 in the first unit region C1 and the source patterns of the first pull-down transistors PD1 in the second unit region C2 in the first direction D1.

[0178] Another part of the second part PL1_2 of the first power supply wiring PL1 can be arranged in an island shape at a position overlapping with the source patterns of the second pull-down transistors PD2 in the third unit region C3 and the source patterns of the second pull-down transistors PD2 in the fourth unit region C4 in the first direction D1.

[0179] Refer to Figure 14 , the first power supply wiring PL1 can extend in the second direction D2. The first power supply wiring PL1 can extend in the same direction as the extending direction of the active pattern of the transfer transistor. The first power supply wirings PL1 can be spaced apart from each other in the third direction D3.

[0180] A part of the first power supply wiring PL1 overlaps with the source patterns of the first pull-down transistors PD1 in the first unit region C1 and the source patterns of the first pull-down transistors PD1 in the second unit region C2 in the first direction D1.

[0181] Another part of the first power supply wiring PL1 overlaps with the source patterns of the second pull-down transistors PD2 in the first unit region C1 and the source patterns of the second pull-down transistors PD2 in the second unit region C2 in the first direction D1.

[0182] Another part of the first power supply wiring PL1 overlaps with the source patterns of the first pull-down transistors PD1 in the third unit region C3 and the source patterns of the first pull-down transistors PD1 in the fourth unit region C4 in the first direction D1.

[0183] Another part of the first power supply wiring PL1 overlaps with the source patterns of the second pull-down transistors PD2 in the third unit region C3 and the source patterns of the second pull-down transistors PD2 in the fourth unit region C4 in the first direction D1.

[0184] Refer to Figure 15, the first power supply wiring PL1 can extend along the second direction D2. The first power supply wiring PL1 can extend in the same direction as the extending direction of the active pattern of the transfer transistor. The first power supply wirings PL1 can be spaced apart from each other in the third direction D3.

[0185] The first power supply wiring PL1 can overlap with all four adjacent cells C1, C2, C3, and C4 in the first direction D1.

[0186] Refer to Figure 16 , all the first power supply wirings PL1 can be arranged in an island shape. The first power supply wiring PL1 can include a first portion PL1_1 and a second portion PL1_2.

[0187] The first portion PL1_1 of the first power supply wiring PL1 can extend along the third direction D3, and the second portion PL1_2 of the first power supply wiring PL1 can extend along the second direction D2. The first portion PL1_1 of the first power supply wiring PL1 is connected to the source patterns of the second pull-down transistor and the first pull-down transistor of a pair of adjacent cells in the third direction D3. The second portion PL1_2 of the first power supply wiring PL1 is connected to the source patterns of the first pull-down transistor and the second pull-down transistor of a pair of adjacent cells in the second direction D2.

[0188] Although the embodiments of the present disclosure have been described with reference to the accompanying drawings, the inventive concept in the present disclosure is not limited to the above embodiments, but can be implemented in various different forms. Those of ordinary skill in the art to which the present disclosure pertains will be able to understand that the present disclosure can be implemented in other specific forms without changing the technical idea or essential characteristics of the present disclosure. Therefore, it should be understood that the above-described embodiments are illustrative in all aspects rather than restrictive.

[0189] Cross-reference to related applications

[0190] This application claims the priority of Korean Patent Application No. 10-2024-0000305, filed with the Korean Intellectual Property Office on January 2, 2024, and all the rights arising therefrom, the entire content of which is incorporated herein by reference.

Claims

1. A semiconductor device, comprising: A substrate including a first surface and a second surface opposite to each other in a first direction; A first active pattern on the first surface and extending in a second direction that intersects the first direction; A second active pattern on the first surface and spaced apart from the first active pattern in a third direction that intersects the first direction and the second direction, the second active pattern extending in the second direction; A first gate electrode intersecting the first active pattern and extending in the third direction; A second gate electrode spaced apart from the first gate electrode in the second direction, the second gate electrode intersecting the first active pattern and the second active pattern; A first source / drain pattern on the first active pattern, the first source / drain pattern being disposed between the first gate electrode and the second gate electrode; A second source / drain pattern on the first active pattern, the second gate electrode being located between the first source / drain pattern and the second source / drain pattern; A third source / drain pattern on the second active pattern and spaced apart from the first source / drain pattern in the third direction; And A first power supply wiring on the second surface and electrically connected to the second source / drain pattern, wherein The first source / drain pattern and the third source / drain pattern are electrically shared through the same node, and A first portion of the first power supply wiring extends along the third direction under the second source / drain pattern.

2. The semiconductor device according to claim 1, wherein A second portion of the first power supply wiring extends along the second direction under the second source / drain pattern, and The first portion of the first power supply wiring and the second portion of the first power supply wiring are electrically connected to each other.

3. The semiconductor device according to claim 1, further comprising: A first via extending from an upper surface of the first power supply wiring to the substrate.

4. The semiconductor device according to claim 3, wherein The first via passes through the substrate and the first active pattern, and The first via is directly connected to the second source / drain pattern.

5. The semiconductor device according to claim 3, further comprising: A second source / drain contact on the second source / drain pattern, Wherein the first via is connected to the second source / drain contact.

6. The semiconductor device according to claim 1, Wherein the first gate electrode is not on the second active pattern.

7. The semiconductor device according to claim 1, further comprising: A fourth source / drain pattern separated from the first source / drain pattern, the first gate electrode being located between the first source / drain pattern and the fourth source / drain pattern; A bit line connected to the fourth source / drain pattern; And A word line connected to the first gate electrode.

8. The semiconductor device according to claim 7, further comprising: A fifth source / drain pattern, on the second active pattern and separated from the third source / drain pattern, with the second gate electrode therebetween the fifth source / drain pattern and the third source / drain pattern; And A second power supply wiring on the first surface, wherein The second power supply wiring is electrically connected to the fifth source / drain pattern.

9. The semiconductor device according to claim 8, wherein The first power supply wiring is configured to apply a negative voltage to the second source / drain pattern, and The second power supply wiring is configured to apply a positive voltage to the fifth source / drain pattern.

10. The semiconductor device according to claim 8, wherein The first power supply wiring is configured to apply a positive voltage to the second source / drain pattern, and The second power supply wiring is configured to apply a negative voltage to the fifth source / drain pattern.

11. The semiconductor device according to claim 1, wherein The first active pattern includes a first lower pattern and a plurality of first sheet patterns, The first lower pattern extends in the second direction, The plurality of first sheet patterns are spaced apart from the first lower pattern in the first direction, and The plurality of first sheet patterns are connected to the first source / drain pattern, the second source / drain pattern, and the third source / drain pattern.

12. A semiconductor device, comprising: A substrate including a first surface and a second surface opposite to each other in a first direction; A transfer transistor on the first surface of the substrate; A pull-down transistor sharing an active region with the transfer transistor; A pull-up transistor sharing a gate electrode with the pull-down transistor; A word line electrically connected to the gate electrode of the transfer transistor; A bit line electrically connected to the drain pattern of the transfer transistor; A first power supply wiring electrically connected to the source pattern of the pull-down transistor; And A second power supply wiring electrically connected to the source pattern of the pull-up transistor, wherein The source pattern of the transfer transistor, the drain pattern of the pull-down transistor, and the drain pattern of the pull-up transistor are electrically connected through a node, The first power supply wiring is on the second surface, The word line, the bit line, and the second power supply wiring are on the first surface, and A first portion of the first power supply wiring extends in a direction parallel to the extending direction of the gate electrode of the transfer transistor.

13. The semiconductor device according to claim 12, wherein A second portion of the first power supply wiring extends in a direction parallel to the extending direction of the active pattern of the transfer transistor, and The first portion of the first power supply wiring and the second portion of the first power supply wiring are electrically connected.

14. The semiconductor device according to claim 12, In a plan view, the shape of the first power supply wiring includes a rectangular closed curve.

15. The semiconductor device according to claim 12, Wherein the bit line and the second power supply wiring extend in the same direction.

16. The semiconductor device according to claim 12, wherein The first power supply wiring is configured to apply a negative voltage to the source pattern of the pull-down transistor, and The second power supply wiring is configured to apply a positive voltage to the source pattern of the pull-up transistor.

17. A semiconductor device, comprising: A substrate including a first NMOS region, a second NMOS region, and a PMOS region between the first NMOS region and the second NMOS region, the substrate including a first surface and a second surface opposite to each other in a first direction; A first transfer transistor and a first pull-down transistor on the first surface of the substrate in the first NMOS region; A second transfer transistor and a second pull-down transistor on the first surface of the substrate in the second NMOS region; A first pull-up transistor on the first surface of the substrate in the PMOS region, the first pull-up transistor sharing a gate electrode with the first pull-down transistor; A second pull-up transistor on the first surface of the substrate in the PMOS region and sharing a gate electrode with the second pull-down transistor; A first power supply wiring configured to apply a negative voltage to each of the source patterns of the first pull-down transistor and the second pull-down transistor; And A second power supply wiring configured to apply a positive voltage to each of the source patterns of the first pull-up transistor and the second pull-up transistor, wherein The first transfer transistor and the first pull-down transistor share an active region, The second transfer transistor and the second pull-down transistor share an active region, The source pattern of the first transfer transistor, the drain pattern of the first pull-down transistor, and the drain pattern of the first pull-up transistor are electrically connected through a first node, The source pattern of the second transfer transistor, the drain pattern of the second pull-down transistor, and the drain pattern of the second pull-up transistor are electrically connected through a second node, The first power supply wiring is on the second surface of the substrate, The second power supply wiring is on the first surface of the substrate, The first power supply wiring extends in a direction parallel to the extending direction of the gate electrode of the first transfer transistor and the extending direction of the gate electrode of the second transfer transistor, and The second power supply wiring extends in a direction parallel to the extending direction of the active pattern of the first transfer transistor and the extending direction of the active pattern of the second transfer transistor.

18. The semiconductor device according to claim 17, wherein The first transfer transistor, the second transfer transistor, the first pull-down transistor, the second pull-down transistor, the first pull-up transistor, and the second pull-up transistor are all MBCFETs.

19. The semiconductor device according to claim 17, wherein A first portion of the first power supply wiring is connected to the source pattern of the first pull-down transistor, A second portion of the first power supply wiring is connected to the source pattern of the second pull-down transistor, and The first portion of the first power supply wiring and the second portion of the first power supply wiring are spaced apart from each other.

20. The semiconductor device according to claim 17, further comprising: A word line is connected to the gate electrodes of each of the first transfer transistor and the second transfer transistor, wherein the word line is on the first surface of the substrate, and relative to the first surface of the substrate, the level of the word line is a vertical level higher than the level of the second power supply wiring.

Images