Preparation method of SRAM (Static Random Access Memory) device

Abstract

The invention provides a preparation method of an SRAM (Static Random Access Memory) device, which comprises the following steps of: providing a substrate, etching the substrate to form a groove so as to define a plurality of active regions which are arranged at intervals in the substrate, forming an oxide layer on the substrate, filling the groove with the oxide layer so as to form a shallow groove isolation structure, forming an amorphous silicon shielding layer covering the shallow groove isolation structure, and performing channel doping on the active region, removing the oxide layer on the active region and the amorphous silicon shielding layer on the shallow trench isolation structure, and forming a gate electrode on the active region. According to the preparation method of the SRAM device, the saturation leakage current of the pull-up transistor can be reduced to be within the specification range, and the power consumption of the SRAM device is reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor integrated circuit manufacturing and relates to a method for preparing a SRAM device. Background Art

[0002] Static random access memory (SRAM) is a volatile memory used to store data. An SRAM cell usually includes a pull-up transistor (PU), a pull-down transistor (PD) and a pass-gate transistor (PG), wherein the pull-up transistor (PU) is a P-type metal oxide semiconductor (PMOS) transistor. In the 90nm high-voltage display drive platform, when manufacturing the PU device of the SRAM cell, the substrate needs to be heavily ion doped (such as phosphorus ions or arsenic ions) to form the required N-type active area. However, the heavy ion doping process will destroy part of the structure in the shallow trench isolation (STI) structure, resulting in the upper surface of the STI structure being lower than the upper surface of the N-type active area of ​​the substrate after the PU device is manufactured, thereby affecting the electrical performance of the PU device, causing its saturated drain current (Idsat) to exceed the specified specification range, thereby causing the power consumption of the SRAM device to increase.

[0003] Therefore, how to provide a method for preparing an SRAM device to reduce the Idsat of the PU device to within the specification range and reduce the power consumption of the SRAM device has become an important problem that needs to be solved urgently by those skilled in the art.

[0004] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for preparing an SRAM device, which is used to solve the problem in the prior art that the Idsat of the PU device exceeds the prescribed specification range, resulting in increased power consumption of the SRAM device.

[0006] To achieve the above object and other related objects, the present invention provides a method for preparing a SRAM device, comprising the following steps:

[0007] providing a substrate;

[0008] Etch the substrate to form trenches to define a plurality of spaced-apart active regions in the substrate;

[0009] Form an oxide layer on the substrate, and the oxide layer fills the trenches to form a shallow trench isolation structure;

[0010] Form an amorphous silicon masking layer covering the shallow trench isolation structure, and perform channel doping on the active regions;

[0011] Remove the oxide layer on the active regions and the amorphous silicon masking layer on the shallow trench isolation structure, and form gate electrodes on the active regions.

[0012] Optionally, the plurality of active regions include N-type active regions and P-type active regions. The N-type active regions are used to fabricate pull-up transistors. The P-type active regions include a first P-type active region and a second P-type active region. The first P-type active region is used to fabricate pull-down transistors, and the second P-type active region is used to fabricate pass transistors.

[0013] Optionally, performing channel doping on the active regions includes the following steps:

[0014] Perform N-type ion doping on at least one of the active regions to form the N-type active regions;

[0015] Perform P-type ion doping on at least one of the active regions to form the P-type active regions.

[0016] Optionally, the doping ions of the N-type active regions include one of phosphorus ions and arsenic ions.

[0017] Optionally, the doping ions of the P-type active regions include boron ions.

[0018] Optionally, forming gate electrodes on the active regions includes the following steps:

[0019] Form a gate oxide layer on the N-type active regions, the first P-type active regions, and the second P-type active regions;

[0020] Form a first gate on the gate oxide layers of the N-type active regions and the first P-type active regions, and form a second gate on the gate oxide layer of the second P-type active regions.

[0021] Optionally, forming the amorphous silicon masking layer covering the shallow trench isolation structure includes the following steps:

[0022] Form an amorphous silicon layer on the oxide layer;

[0023] Use in-situ steam generation oxidation to oxidize the amorphous silicon layer on the active regions to obtain a silicon oxide layer covering the active regions;

[0024] The silicon oxide layer is removed by wet etching to obtain the amorphous silicon shielding layer.

[0025] Optionally, the thickness range of the gate oxide layer is 20 nm to 30 nm.

[0026] Optionally, the material of the first electrode includes polysilicon, and the material of the second electrode includes polysilicon.

[0027] Optionally, the method for removing the oxide layer and the amorphous silicon shielding layer on the active region includes wet etching.

[0028] As described above, the method for manufacturing the SRAM device of the present invention introduces an amorphous silicon shielding layer as an ion implantation mask layer for the shallow trench isolation structure, thereby protecting the shallow trench isolation structure from being affected by ion implantation. When using wet etching to remove the oxide layer on the substrate surface, it can prevent the upper surface of the STI structure from being lower than the upper surface of the substrate active region, thereby reducing the saturation drain current of the pull-up transistor to within the specification range and reducing the power consumption of the SRAM device. Description of the Drawings

[0029] Figure 1 It shows a schematic diagram of the structure obtained after providing a substrate and forming a shallow trench isolation structure in a method for manufacturing an SRAM device.

[0030] Figure 2 It shows a schematic diagram of the structure obtained after forming an N-type active region and the P-type active region in a method for manufacturing an SRAM device.

[0031] Figure 3 It shows a schematic diagram of the structure obtained after removing the oxide layer on the N-type active region and the P-type active region in a method for manufacturing an SRAM device.

[0032] Figure 4 It shows a schematic diagram of the structure obtained after forming a polysilicon layer in a method for manufacturing an SRAM device.

[0033] Figure 5 It shows a depth distribution diagram of the nuclear energy loss of different implanted ions.

[0034] Figure 6 It shows Figure 4 a cross-sectional electron microscope picture of region A in

[0035] Figure 7 It shows a process flow diagram of the method for manufacturing the SRAM device of the present invention.

[0036] Figure 8 It shows a schematic diagram of the structure of providing a substrate in the method for manufacturing the SRAM device of the present invention.

[0037] Figure 9 Schematic cross-sectional view of the structure obtained after forming a trench in the method for manufacturing an SRAM device according to the present invention (along the Figure 8 section B-B' in

[0038] Figure 10 Schematic cross-sectional view of the structure obtained after forming a shallow trench isolation structure in the method for manufacturing an SRAM device according to the present invention (along the Figure 8 section B-B' in

[0039] Figure 11 Schematic cross-sectional view of the structure obtained after forming an amorphous silicon mask layer and performing channel doping in the method for manufacturing an SRAM device according to the present invention (along the Figure 8 section B-B' in

[0040] Figure 12 Schematic cross-sectional view of the structure obtained after forming an amorphous silicon layer in the method for manufacturing an SRAM device according to the present invention (along the Figure 8 section B-B' in

[0041] Figure 13 Schematic cross-sectional view of the structure obtained after removing the amorphous silicon mask layer and forming a gate electrode in the method for manufacturing an SRAM device according to the present invention (along the Figure 8 section B-B' in

[0042] Figure 14 Shown as Figure 13 top view of the structure shown.

[0043] Description of reference numerals

[0044] 101 Substrate

[0045] 102, 202 N-type active region

[0046] 103, 203 P-type active region

[0047] 2031 First P-type active region

[0048] 2032 Second P-type active region

[0049] 104, 205 Oxide layer

[0050] 105, 206 Shallow trench isolation structure

[0051] 106 Polysilicon layer

[0052] 107 Step

[0053] 201 Substrate

[0054] 204 Shallow trench

[0055] 207 Amorphous silicon blocking layer

[0056] 208 Amorphous silicon layer

[0057] 209 Gate oxide layer

[0058] 210 Gate electrode

[0059] 2101 First gate

[0060] 2102 Second gate

[0061] Step height in H1 PU device

[0062] Step height in H2 PD device

[0063] Steps S1 - S6 Specific implementation manner

[0064] Please refer to Figures 1 to 4 , which shows a schematic structural diagram presented by each step of a preparation method of an SRAM device. Among them, at least the following steps are included:

[0065] (1) As Figure 1 shown, first provide a substrate 101, in which an N-type active region 102 and a P-type active region 103 are provided. Etch the substrate 101 to form a shallow groove, and deposit an oxide layer 104 on the substrate 101. The oxide layer 104 fills the shallow groove to form a shallow trench isolation structure 105;

[0066] (2) As Figure 2 shown, perform N-type ion implantation on one of the active regions to form an N-type active region 102, and perform P-type ion implantation on the other active region to form a P-type active region 103;

[0067] (3) As Figure 3 shown, use wet etching to remove the oxide layer 104 on the N-type active region 102 and the P-type active region 103;

[0068] (4) As Figure 4 shown, form a polysilicon layer 106 on the substrate 101.

[0069] In the above preparation method of the SRAM device, the oxide layer 104 used to form the shallow trench isolation structure 105 is usually silicon oxide. When performing ion implantation on the N-type active region 102 and the P-type active region 103, the collision of the implanted ions with the silicon oxide will cause some silicon-oxygen bonds to be broken. As a result, when using wet etching to remove the oxide layer 104, the wet etching rate of the shallow trench isolation structure 105 will increase, making the upper surface of the shallow trench isolation structure 105 lower than the upper surface of the substrate 101 (asFigure 3 as shown, thereby generating a step 107 in the SRAM device.

[0070] Please refer to Figure 5 , which shows the depth distribution of nuclear energy loss of different implanted ions. Nuclear deposition energy is used to characterize the damage of implanted ions to materials. Nuclear deposition energy refers to the energy lost when ions undergo elastic collisions with the nuclei of the target material (i.e., Figure 5 the nuclear energy loss in Figure 5 ). This energy is positively correlated with the implantation dose. Nuclear deposition energy needs to be calculated and characterized through a simulation model because it is related to the kinetic energy of ions after acceleration in the implanter (i.e., the implantation energy), but is not exactly equal. As

[0071] To more clearly show the step height in the PU device and the step height in the PD device, please refer to Figure 6 , which shows Figure 4 a cross-sectional electron microscope picture of region A in . The step height H1 in the PU device is more than

[0072] The inventors of the present application provide a method for manufacturing an SRAM device. By introducing an amorphous silicon masking layer as an ion implantation masking layer for the shallow trench isolation structure in the SRAM device, it is possible to avoid damage to the structure of the shallow trench isolation structure and prevent the upper surface of the STI structure from being lower than the upper surface of the substrate active region, thereby reducing the Idsat of the PU device to within the specification range and reducing the power consumption of the SRAM device.

[0073] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0074] It should be emphasized that the term "comprising / including" as used herein refers to the presence of features, whole units, steps or components, but does not exclude the presence or addition of one or more other features, whole units, steps or components.

[0075] Features described and / or illustrated for one embodiment can be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or replace features in other embodiments.

[0076] When detailing the embodiments of the present invention, for ease of illustration, the schematic diagrams showing the device structure are enlarged locally not in accordance with the general scale, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention herein. In addition, in actual production, three-dimensional spatial dimensions including length, width and depth should be included.

[0077] For convenience of description, spatial relationship terms such as "beneath", "below", "lower", "under", "above", "on" etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relationship terms are intended to encompass other directions of the device in use or operation in addition to the directions depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers.

[0078] In the context of the present application, the structure in which the first feature is "above" the second feature described may include embodiments where the first and second features are in direct contact, and may also include embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0079] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape and size of the components in actual implementation. The type, quantity and proportion of each component in its actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0080] Please refer to Figure 7 , which shows a process flow diagram of the method for preparing the SRAM device of the present invention, including the following steps:

[0081] S1: Provide a substrate;

[0082] S2: Etch the substrate to form trenches to define a plurality of spaced-apart active regions in the substrate;

[0083] S3: Form an oxide layer on the substrate, and the oxide layer fills the trenches to form a shallow trench isolation structure;

[0084] S4: Form an amorphous silicon masking layer covering the shallow trench isolation structure, and perform channel doping on the active regions;

[0085] S5: Remove the oxide layer on the active regions and the amorphous silicon masking layer on the shallow trench isolation structure, and form gate electrodes on the active regions.

[0086] Next, in conjunction with Figures 8 to 14 , each step of the manufacturing method of the SRAM device of the present invention will be described in detail.

[0087] First, please refer to Figure 8 , and perform step S1: Provide a substrate 201.

[0088] As an example, the substrate 201 is a single-crystalline silicon substrate or a silicon-on-insulator substrate (SOI substrate).

[0089] As an example, the plurality of active regions include an N-type active region 202 and a P-type active region 203. The N-type active region 202 is used to fabricate a pull-up transistor. The P-type active region 203 includes a first P-type active region 2031 and a second P-type active region 2032. The first P-type active region 2031 is used to fabricate a pull-down transistor, and the second P-type active region 2032 is used to fabricate a pass transistor. In some embodiments, the pull-up transistor is typically a P-type metal-oxide-semiconductor transistor, and the pull-down transistor and the pass transistor are typically N-type metal-oxide-semiconductor transistors.

[0090] It should be noted that in the SRAM device, the pass transistor has an independently provided gate, and the pull-up transistor and the pull-down transistor share a gate, and they need to be adjacent to each other during manufacturing. For the sake of easy illustration, the structure shown in the subsequent Figures 9 to 13 is a schematic cross-sectional view corresponding to the cross-section along B-B' in Figure 8 .

[0091] Please refer to Figure 9 again, and perform step S2: Etch the substrate 201 to form trenches 204 to define a plurality of spaced-apart active regions in the substrate 201.

[0092] As an example, the method of forming the trenches 204 includes one of wet etching and dry etching.

[0093] Please refer to again Figure 10 and perform step S3: Form an oxide layer 205 on the substrate 201, and the oxide layer 205 fills the trench 204 to form a shallow trench isolation structure 206. By means of the shallow trench isolation structure 206, isolation between the pull-up transistor, the pull-down transistor, and the pass transistor and other devices can be achieved, avoiding short circuits and other situations.

[0094] Please refer to again Figure 11 and perform step S4: Form an amorphous silicon masking layer 207 covering the shallow trench isolation structure 206, and perform channel doping on the active region.

[0095] Specifically, the amorphous silicon masking layer 207 serves as an ion implantation masking layer for the shallow trench isolation structure 206, which can block doping ions from entering the shallow trench isolation structure 206, thereby effectively preventing the shallow trench isolation structure 206 from being collided by implanted ions and protecting the silicon-oxygen bonds inside it from being damaged. When subsequently removing the oxide layer 205 on the surface of the substrate 201 by wet etching, it can avoid the increase in the wet etching rate of the shallow trench isolation structure 206, prevent the upper surface of the STI structure from being lower than the upper surface of the substrate active region, thereby reducing the Idsat of the PU device to within the specification range and reducing the power consumption of the SRAM device.

[0096] As an example, forming the amorphous silicon masking layer 207 covering the shallow trench isolation structure 206 includes the following steps:

[0097] (1) Please refer to Figure 12 and form an amorphous silicon layer 208 on the oxide layer 205;

[0098] (2) Use the in-situ steam generation (ISSG) oxidation method to oxidize the amorphous silicon layer 208 on the active region to obtain a silicon oxide layer covering the active region;

[0099] (3) Please refer to again Figure 11 and use wet etching to remove the silicon oxide layer to obtain the amorphous silicon masking layer 207.

[0100] Among them, Figure 12 shows a cross-sectional schematic diagram of the structure obtained after forming the amorphous silicon masking layer 207 in the preparation method of the SRAM device of the present invention (along the Figure 8 B-B' section in

[0101] As an example, channel doping of the active region includes the following steps:

[0102] (1) Perform N-type ion doping on at least one of the active regions to form an N-type active region 202;

[0103] (2) Perform P-type ion doping on at least one of the active regions to form a P-type active region 203.

[0104] As an example, the doping ions of the N-type active region 202 include one of phosphorus ions and arsenic ions.

[0105] As an example, the doping ions of the P-type active region 203 include boron ions.

[0106] Refer to again Figure 13 , perform step S5: Remove the oxide layer 205 on the active region and the amorphous silicon blocking layer 207 on the shallow trench isolation structure 206, and form a gate electrode 210 on the active region. Among them, after channel doping of the active region, generally, annealing treatment is required for the device. After annealing, the amorphous silicon blocking layer 207 will turn into conductive polysilicon. To avoid its influence on the isolation effect of the shallow trench isolation structure 206, before forming the gate electrode 210, the amorphous silicon blocking layer 207 needs to be removed to ensure the structure of the device remains unchanged.

[0107] As an example, forming a gate electrode 210 on the active region includes the following steps:

[0108] (1) Refer to again Figure 13 , form a gate oxide layer 209 on the N-type active region 202, the first P-type active region 2031, and the second P-type active region 2032;

[0109] (2) Refer to Figure 14 , form a first gate 2101 on the gate oxide layer 209 of the N-type active region 202 and the first P-type active region 2031, and form a second gate 2102 on the gate oxide layer 209 of the second P-type active region 2032. Among them, Figure 14 Shown as Figure 13 The top view of the structure shown.

[0110] As an example, the gate oxide layer 209 can be a silicon dioxide layer. Through an oxidation process, the upper surfaces of the N-type active region 202, the first P-type active region 2031, and the second P-type active region 2032 are oxidized to form the gate oxide layer 209. Then, the gate electrode 210 is fabricated. For example, polysilicon can be deposited as the gate electrode 210.

[0111] As an example, the thickness range of the gate oxide layer 209 is 20 nm to 30 nm.

[0112] As an example, the material of the first electrode 2091 includes polysilicon, and the material of the second electrode 2092 includes polysilicon.

[0113] As an example, the method for removing the oxide layer 205 on the active region and the amorphous silicon shielding layer 207 includes wet etching. In this embodiment, the amorphous silicon shielding layer 207 serves as an ion implantation masking layer for the shallow trench isolation structure 206, which can not only prevent the wet etching rate of the shallow trench isolation structure 206 from increasing, but also isolate the etching solution, thereby preventing the upper surface of the STI structure from being lower than the upper surface of the substrate active region and reducing the saturation drain current of the pull-up transistor to within the specification range.

[0114] In summary, the method for manufacturing the SRAM device of the present invention includes the following steps: providing a substrate, etching the substrate to form trenches to define a plurality of spaced-apart active regions in the substrate, forming an oxide layer on the substrate, and filling the trenches with the oxide layer to form a shallow trench isolation structure, forming an amorphous silicon shielding layer covering the shallow trench isolation structure, performing channel doping on the active regions, removing the oxide layer on the active regions and the amorphous silicon shielding layer on the shallow trench isolation structure, and forming gate electrodes on the active regions. The method for manufacturing the SRAM device of the present invention introduces an amorphous silicon shielding layer as an ion implantation masking layer for the shallow trench isolation structure to protect the shallow trench isolation structure from being affected by ion implantation. When using wet etching to remove the oxide layer on the surface of the substrate 201, it can prevent the wet etching rate of the shallow trench isolation structure from increasing, avoid the upper surface of the STI structure from being lower than the upper surface of the substrate active region, thereby reducing the saturation drain current of the pull-up transistor to within the specification range and reducing the power consumption of the SRAM device. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0115] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for manufacturing an SRAM device, characterized in that, It includes the following steps: Provide a substrate; Etch the substrate to form trenches to define a plurality of spaced-apart active regions in the substrate; Form an oxide layer on the substrate, and the oxide layer fills the trenches to form a shallow trench isolation structure; Form an amorphous silicon masking layer covering the shallow trench isolation structure, and perform channel doping on the active regions; Remove the oxide layer on the active regions and the amorphous silicon masking layer on the shallow trench isolation structure, and form gate electrodes on the active regions.

2. The manufacturing method of the SRAM device according to claim 1, wherein: The plurality of active regions include N-type active regions and P-type active regions. The N-type active regions are used to fabricate pull-up transistors. The P-type active regions include a first P-type active region and a second P-type active region. The first P-type active region is used to fabricate pull-down transistors, and the second P-type active region is used to fabricate pass transistors.

3. The manufacturing method of the SRAM device according to claim 2, characterized in that, Performing channel doping on the active regions includes the following steps: Perform N-type ion doping on at least one of the active regions to form the N-type active regions; Perform P-type ion doping on at least one of the active regions to form the P-type active regions.

4. The manufacturing method of the SRAM device according to claim 3, characterized in that: The doping ions of the N-type active regions include one of phosphorus ions and arsenic ions.

5. The manufacturing method of the SRAM device according to claim 3, characterized in that: The doping ions of the P-type active regions include boron ions.

6. The method for manufacturing an SRAM device according to claim 2, wherein Forming gate electrodes on the active regions includes the following steps: Form a gate oxide layer on the N-type active regions, the first P-type active region, and the second P-type active region; Form a first gate on the gate oxide layers of the N-type active regions and the first P-type active region, and form a second gate on the gate oxide layer of the second P-type active region.

7. The manufacturing method of the SRAM device according to claim 1, characterized in that, Forming the amorphous silicon masking layer covering the shallow trench isolation structure includes the following steps: Form an amorphous silicon layer on the oxide layer; Use in-situ steam generation oxidation to oxidize the amorphous silicon layer on the active regions to obtain a silicon oxide layer covering the active regions; Use wet etching to remove the silicon oxide layer to obtain the amorphous silicon masking layer.

8. The manufacturing method of the SRAM device according to claim 7, characterized in that: The thickness range of the gate oxide layer is 20nm to 30nm.

9. The method for manufacturing an SRAM device according to claim 7, characterized in that: The material of the first electrode includes polysilicon, and the material of the second electrode includes polysilicon.

10. The manufacturing method of the SRAM device according to claim 1, wherein: The method for removing the oxide layer on the active regions and the amorphous silicon masking layer includes wet etching.

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