Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device, a manufacturing method thereof and electronic equipment. The semiconductor device comprises at least one transistor and a bit line which are located on a substrate; the semiconductor column of the transistor extends along the direction vertical to the substrate, and the bit line is positioned between the semiconductor column of the transistor and the substrate and is electrically connected with one end of the semiconductor column of the transistor; the bit lines extend in a first direction, and the width of the bit lines does not exceed the width of the semiconductor columns in the direction perpendicular to the first direction. According to the semiconductor device, the contact performance of the bit line and the semiconductor column is improved, and the manufacturing method can reduce the process difficulty of the bit line.

Description

Technical Field

[0001] The embodiments of the present application relate to, but are not limited to, the field of semiconductor technology, and particularly to a semiconductor device, a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking day by day, and the types and quantities of devices included in a single chip are increasing accordingly, making it possible for small differences in the process production to affect the device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to fabricate as many device units as possible on a limited substrate. Since Moore's Law came out, various semiconductor structure designs and process optimizations have been proposed in the industry to meet the requirements for current products. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this document. This overview is not intended to limit the protection scope of the present disclosure.

[0005] The embodiments of the present application provide a semiconductor device, a manufacturing method thereof, and an electronic device. The semiconductor device can improve the contact performance between the bit line and the semiconductor pillar, and the manufacturing method can reduce the process difficulty of the bit line.

[0006] The present application provides a semiconductor device, which includes at least one transistor and a bit line located on a substrate; the semiconductor pillar of the transistor extends in a direction perpendicular to the substrate, the bit line is located between the semiconductor pillar of the transistor and the substrate and is electrically connected to one end of the semiconductor pillar of the transistor; the bit line extends in a first direction, and the width of the bit line does not exceed the width of the semiconductor pillar in a direction perpendicular to the first direction.

[0007] In some embodiments, the cross-sectional shapes of the bit line in different regions in the first direction and in a longitudinal section perpendicular to the first direction are the same.

[0008] In some embodiments, the bit line has a bottom surface close to the substrate and a top surface far from the substrate, and the bottom surface of the bit line is parallel to the substrate.

[0009] In some embodiments, the semiconductor pillar has a channel region and a first electrode region, and the first electrode region is electrically connected to the bit line;

[0010] The first electrode region contains a doping material, and the average bulk density of the doping material in the first electrode region is not less than 1e19 atoms / cm³.

[0011] In some embodiments, the average bulk density of the doping material in the first electrode region is from 1e19 atoms / cm³ to 1e20 atoms / cm³.

[0012] In some embodiments, the substrate is a silicon substrate, the semiconductor column is a silicon column, and the bit line is a metal-containing wire.

[0013] In some embodiments, a bit line hole is included, the bit line is located in the bit line hole, and the width of the bit line hole is the same as the width of the semiconductor column in a direction perpendicular to the first direction.

[0014] In some embodiments, the longitudinal cross-section of the bit line hole in a direction perpendicular to the first direction is rectangular.

[0015] The present application provides a method for manufacturing a semiconductor device, including:

[0016] Forming a sacrificial layer and a semiconductor layer on a substrate in sequence, wherein, under the same etching conditions, the etching selectivity ratio of the sacrificial layer to the semiconductor layer is different;

[0017] Etching the semiconductor layer and the sacrificial layer to form a plurality of semiconductor columns extending in a direction perpendicular to the substrate and spaced apart, and to form a plurality of sacrificial bars extending in a first direction and spaced apart in a second direction, and each of the sacrificial bars is connected to one end of a row of the semiconductor columns distributed along the first direction;

[0018] Removing the sacrificial bars to form bit line holes;

[0019] Forming a bit line in the bit line holes.

[0020] In some embodiments, the etching of the semiconductor layer and the sacrificial layer includes:

[0021] Etching the semiconductor layer and the sacrificial layer to form a plurality of first trenches extending in the first direction and spaced apart in the second direction and a plurality of second trenches extending in the second direction and spaced apart in the first direction in the semiconductor layer and the sacrificial layer, and the first trenches extend to the surface or inside of the substrate, and the second trenches extend to the surface or inside of the sacrificial layer; the first trenches and the second trenches divide the semiconductor layer into the plurality of semiconductor columns, and the first trenches divide the sacrificial layer into the plurality of sacrificial bars.

[0022] In some embodiments, etching the semiconductor layer and the sacrificial layer to form a plurality of first trenches extending along the first direction and spaced apart in the second direction and a plurality of second trenches extending along the second direction and spaced apart in the first direction within the semiconductor layer and the sacrificial layer includes:

[0023] Etching the semiconductor layer and the sacrificial layer to form the first trenches, the first trenches exposing the substrate, the first trenches spacing the semiconductor layer into a plurality of semiconductor walls extending along the first direction and spaced apart in the second direction, and spacing the sacrificial layer into the plurality of sacrificial strips; filling a first insulating layer in the first trenches; etching the semiconductor walls to form second trenches extending to the surface of the sacrificial strips, or etching the semiconductor walls and the sacrificial strips to form second trenches extending into the interior of the sacrificial strips, the second trenches exposing the sacrificial strips, the second trenches spacing the semiconductor walls into the plurality of semiconductor pillars;

[0024] Alternatively, etching the semiconductor layer to form second trenches extending to the surface of the sacrificial layer, or etching the semiconductor layer and the sacrificial layer to form second trenches extending into the interior of the sacrificial layer, the second trenches exposing the sacrificial layer, the second trenches spacing the semiconductor layer into a plurality of semiconductor walls extending along the second direction and spaced apart in the first direction; filling a first insulating layer in the second trenches; etching the semiconductor walls and the sacrificial layer to form the first trenches, the first trenches spacing the semiconductor walls into the plurality of semiconductor pillars and spacing the sacrificial layer into the plurality of sacrificial strips.

[0025] In some embodiments, forming the sacrificial layer and the semiconductor layer on the substrate in sequence includes:

[0026] Forming a sacrificial layer on one side of the substrate by an epitaxial method or a deposition method, the thickness of the sacrificial layer being not less than the thickness of the bit line to be formed;

[0027] Growing or depositing semiconductor material on the side of the sacrificial layer away from the substrate by an epitaxial method or a deposition method, and in-situ doping the first electrode region of the semiconductor material.

[0028] In some embodiments, further includes: after forming the semiconductor pillars and before removing the sacrificial strips,

[0029] Forming a first insulating layer on the exposed sidewalls of the semiconductor pillars.

[0030] In some embodiments, forming the bit line in the bit line hole includes:

[0031] Fill a conductive layer in the bit line hole and the second trench, and electrically connect the conductive layer in the bit line hole to one end of the semiconductor pillar close to the substrate;

[0032] Remove the conductive layer in the second trench, and retain the conductive layer in the bit line hole as the bit line.

[0033] In some embodiments, it further includes: after forming the bit line,

[0034] Form a second insulating layer on the exposed surface of the bit line;

[0035] The semiconductor pillar includes a first electrode region electrically connected to the bit line, a second electrode region away from the substrate, and a channel region between the first electrode region and the second electrode region. A gate insulating layer and a gate electrode surrounding the channel region are sequentially formed on the sidewall of the channel region.

[0036] The embodiment of the present application further provides an electronic device, which includes the semiconductor device provided by the embodiment of the present application or is fabricated by the above method.

[0037] Other features and advantages of the present application will be described in the following specification, and in part, will become more clear from the specification, or will be understood by implementing the present application. The objectives and advantages of the present application can be realized and obtained by the structures specifically pointed out in the specification and the drawings. Description of the Drawings

[0038] The drawings are used to provide an understanding of the technical solutions of the present application, and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solutions of the present application, and do not constitute a limitation to the technical solutions of the present application.

[0039] Figure 1A A three-dimensional structure diagram of the semiconductor device provided by the exemplary embodiment of the present application;

[0040] Figure 1B A top view structure diagram of the semiconductor device provided by the exemplary embodiment of the present application;

[0041] Figure 1C For Figure 1A A cross-sectional structure diagram of the local structure of the semiconductor device shown in the cross-section perpendicular to the substrate along the a-a' direction;

[0042] Figure 1D For Figure 1A A cross-sectional structure diagram of the local structure of the semiconductor device shown in the cross-section perpendicular to the substrate along the b-b' direction;

[0043] Figure 2Process flow chart of a manufacturing method of a semiconductor device provided by an exemplary embodiment of the present disclosure;

[0044] Figure 3A Three-dimensional structure diagram of a manufacturing method of a semiconductor device according to an exemplary embodiment of the present application after forming a sacrificial layer;

[0045] Figure 3B For Figure 3A Schematic cross-sectional structure diagram of the semiconductor structure shown in the cross-section perpendicular to the substrate along the a-a' direction;

[0046] Figure 4A Three-dimensional structure diagram of a manufacturing method of a semiconductor device according to an exemplary embodiment of the present application after forming a semiconductor pillar;

[0047] Figure 4B For Figure 4A Schematic cross-sectional structure diagram of the semiconductor structure shown in the cross-section perpendicular to the substrate along the a-a' direction;

[0048] Figure 4C For Figure 4A Schematic cross-sectional structure diagram of the semiconductor structure shown in the cross-section perpendicular to the substrate along the b-b' direction;

[0049] Figure 5A Three-dimensional structure diagram of a manufacturing method of a semiconductor device according to an exemplary embodiment of the present application after forming a bit line hole;

[0050] Figure 5B For Figure 5A Schematic cross-sectional structure diagram of the semiconductor structure shown in the cross-section perpendicular to the substrate along the a-a' direction;

[0051] Figure 5C For Figure 5A Schematic cross-sectional structure diagram of the semiconductor structure shown in the cross-section perpendicular to the substrate along the b-b' direction;

[0052] Figure 6A Three-dimensional structure diagram of a manufacturing method of a semiconductor device according to an exemplary embodiment of the present application after forming a bit line;

[0053] Figure 6B For Figure 6A Schematic cross-sectional structure diagram of the semiconductor structure shown in the cross-section perpendicular to the substrate along the a-a' direction;

[0054] Figure 6C For Figure 6A Schematic cross-sectional structure diagram of the semiconductor structure shown in the cross-section perpendicular to the substrate along the b-b' direction.

[0055] The meanings of the reference signs in the drawings are as follows:

[0056] 10 - Substrate; 11 - Sacrificial layer; 12 - Semiconductor layer; 13 - Sacrificial strip; 14 - First insulating layer; 15 - Second insulating layer; 20 - Transistor; 21 - Semiconductor pillar; 22 - Gate electrode; 23 - Gate insulating layer; 211 - First electrode region; 212 - Channel region; 213 - Second electrode region; 30 - Bit line; 31 - Bit line via; 40 - Word line; 51 - First trench; 52 - Second trench. Detailed implementation manners

[0057] To make the objectives, technical solutions and advantages of the present application more clearly understood, the embodiments of the present application will be described in detail below with reference to the drawings. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments may be arbitrarily combined with each other.

[0058] The implementation manners of the present application do not necessarily limit the sizes shown in the drawings. The shapes and sizes of the components in the drawings are preferred implementation schemes and may also be other shapes and sizes. In addition, the drawings schematically show ideal examples, and the implementation manners of the present application are not limited to the shapes or values shown in the drawings.

[0059] The size and proportional relationships between the various film layers or components in the drawings of the present application can be used as a reference in actual processes, which are implementation manners with better technical effects, but are not limited thereto. For example: the aspect ratio of the semiconductor layer, the thickness and spacing of the various film layers can be adjusted according to actual needs.

[0060] The ordinal numbers such as "first" and "second" in the present application are set to avoid confusion of the components and do not represent any order, quantity or importance.

[0061] In the present application, for convenience, terms indicating orientation or positional relationships such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationships of the components with reference to the drawings, which are only for facilitating the description of this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation to the present application. The positional relationships of the components are appropriately changed according to the directions describing the components. Therefore, it is not limited to the terms described in the disclosure and can be appropriately replaced according to the situation.

[0062] In this application, unless otherwise clearly defined and limited, the terms "installed", "connected", and "linked" shall be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, an indirect connection through an intermediate member, or a communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0063] In this application, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this application, the channel region refers to the region where current mainly flows.

[0064] In this application, it can be that the first electrode region is the drain electrode and the second electrode region is the source electrode, or it can be that the first electrode region is the source electrode and the second electrode region is the drain electrode. In cases such as using transistors with opposite polarities or changes in the current direction during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes swapped. Therefore, in this application, if not specifically stated, the "source electrode" and the "drain electrode" can be swapped with each other.

[0065] In this application, "electrically connected" or "connected" includes cases where components are connected together through an element with a certain electrical effect. For example, an electrical signal connection (coupled connection, such as coupled to), or a physical direct connection. There is no particular limitation on the "element with a certain electrical effect" as long as it can transfer electrical signals between the components to be connected. Examples of the "element with a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0066] In this application, "parallel" means approximately parallel or almost parallel. For example, the state where the angle formed by two straight lines is -10° or more and 10° or less, and thus also includes the state where the angle is -5° or more and 5° or less. In addition, "perpendicular" means approximately perpendicular. For example, the state where the angle formed by two straight lines is 80° or more and 100° or less, and thus also includes the state where the angle is 85° or more and 95° or less.

[0067] In this application, "film" and "layer" can be swapped with each other. For example, sometimes the "conductive layer" can be replaced with the "conductive film". Similarly, sometimes the "insulating film" can be replaced with the "insulating layer".

[0068] The substrate in the embodiments of the present application may be a support structure, for example, a silicon substrate, or a support structure with other film layers, functions, or circuits already distributed on the silicon substrate. The device involved in the inventive configuration of the embodiments of the present application is disposed on the main surface of the support structure.

[0069] In the present application, spaced-apart distribution can be understood as separated and independent (separated) distribution. It can be achieved by physical disconnection in the structure, or by electrical disconnection in electrical characteristics. For example, the semiconductor layer between the effective channels corresponding to two transistors is modified to achieve insulation to realize electrical spacing between the two channels.

[0070] With the progress of the semiconductor process technology, it is difficult for planar transistors to meet the need for high storage density, and vertical transistors have become a good choice. However, in vertical transistors, the bit line (Bit Line, BL) is located below the transistor, and there are problems such as large processing difficulty and large contact resistance with the transistor.

[0071] In the current manufacturing process of semiconductor devices with a VCT structure, usually a silicon pillar is first formed on a silicon substrate, and then an isotropic silicon etching method is used to etch the exposed silicon substrate between two rows of semiconductor pillars to form a bit line groove extending to the bottom of these two rows of semiconductor pillars. Then, a conductive material is deposited in the bit line groove to form a bit line. The currently common longitudinal cross-sectional shapes of the bit line grooves formed by this method are "sigma (∑)" shape, bowl shape, etc. The conductive materials in multiple bit line grooves are connected tip to tip to form a bit line. Since the contact surfaces of the conductive materials in each bit line groove are small, the formed bit line is prone to loose connection and thus open circuit.

[0072] The present application provides a semiconductor device. Figure 1A is a three-dimensional structure diagram of the semiconductor device provided by the exemplary embodiment of the present application; Figure 1B is a top view structural schematic diagram of the semiconductor device provided by the exemplary embodiment of the present application; Figure 1C is Figure 1A a cross-sectional structural schematic diagram of the local structure of the semiconductor device shown in the cross-section perpendicular to the substrate along the a-a' direction;

[0073] Figure 1D is Figure 1A a cross-sectional structural schematic diagram of the local structure of the semiconductor device shown in the cross-section perpendicular to the substrate along the b-b' direction.

[0074] As Figures 1A to 1D shown, the semiconductor device includes: at least one transistor 20 and a bit line 30 located on a substrate 10;

[0075] The semiconductor pillars of the transistor 20 extend in a direction perpendicular to the substrate 10;

[0076] The bit line 30 is located between the transistor 20 and the substrate 10 and is electrically connected to one end of the transistor 20; the bit line 30 extends in the first direction, and the width of the bit line does not exceed the width of the semiconductor pillar in the direction perpendicular to the first direction.

[0077] In the present application, the width of the bit line does not exceed the width of the semiconductor pillar in the direction perpendicular to the first direction, and the semiconductor pillar has good contact with the bit line.

[0078] Exemplarily, the cross-sectional shapes of different regions of the bit line 30 in the first direction are the same in the longitudinal cross-section perpendicular to the first direction.

[0079] In the embodiment of the present application, the longitudinal cross-sectional shapes of different regions of the bit line in the extending direction are the same, which can enable different regions of the bit line to have a large contact surface, form an effective connection, and avoid the situation of the bit line being open-circuited.

[0080] In an exemplary embodiment of the present application, the longitudinal cross-sectional shape of the bit line 30 in the direction perpendicular to the first direction may be rectangular.

[0081] In an exemplary embodiment of the present application, the bit line 30 has a bottom surface close to the substrate 10 and a top surface far from the substrate 10, and the bottom surface of the bit line 30 is parallel to the substrate 10.

[0082] In some embodiments, the bottom surface of the bit line hole formed by the isotropic silicon etching method is mostly arc-shaped, that is, there is a large difference in the height of the bit line in different regions, and the shape of the bit line is irregular, resulting in unstable performance of the bit line. However, the bottom surface of the bit line in the embodiment of the present application is parallel to the substrate, which can avoid or reduce the height difference of the bit line in different regions and obtain a bit line with stable performance.

[0083] In an exemplary embodiment of the present application, as Figure 1A , Figure 1C and Figure 1D shown, the transistor 20 may include a semiconductor pillar 21 extending in the direction perpendicular to the substrate 10, and the semiconductor pillar 21 has a first electrode region 211, and the first electrode region 211 is electrically connected to the bit line 30;

[0084] The first electrode region contains a doping material, and the average bulk density of the doping material in the first electrode region may not be lower than 1e19 atoms / cm³.

[0085] In the manufacturing process of semiconductor devices with the current VCT structure, ion implantation is often used to implant doping ions into the semiconductor pillar from the end far from the bit line. Since the path that the doping ions need to pass through to reach the end close to the bit line is relatively long, the ion doping concentration at the end of the semiconductor pillar close to the bit line is relatively low. For example, it is lower than 1e19 atoms per cubic centimeter, resulting in a relatively large contact resistance between the semiconductor pillar and the bit line.

[0086] In the semiconductor device according to an embodiment of the present application, the ion doping concentration at the end of the semiconductor pillar close to the bit line is relatively high. For example, the average bulk density of the doping material can be not less than 1e19 atoms per cubic centimeter. Therefore, the contact resistance between the semiconductor pillar and the bit line is relatively small.

[0087] In an exemplary embodiment of the present application, the average bulk density of the doping material in the first electrode region can be from 1e19 atoms per cubic centimeter to 1e20 atoms per cubic centimeter.

[0088] In an exemplary embodiment of the present application, as Figure 1C and Figure 1D shown, along the direction away from the substrate 10, the semiconductor pillar 21 may sequentially include a first electrode region 211, a channel region 212, and a second electrode region 213.

[0089] In an exemplary embodiment of the present application, as Figures 1A to 1D shown, the transistor 20 may further include a gate electrode 22. The gate electrode 22 surrounds the sidewall of the channel region of the semiconductor pillar 21, and there is a gate insulating layer 23 for insulation between the gate electrode 22 and the channel region.

[0090] Here, "surround" can be understood as partial surround or full surround. In some embodiments, the "surround" can be full surround, that is, the entire sidewall of the channel region is surrounded by the gate electrode, and the cross-section of the surrounded gate electrode is a closed ring. The cross-section is taken along a direction parallel to the substrate. In some embodiments, the "surround" can be partial surround, that is, a part of the sidewall of the channel region is surrounded by the gate electrode, and the cross-section of the surrounded gate electrode is not closed but presents a ring shape. For example, a ring with an opening or two independent gate electrodes. For example, the opposite side surfaces of the channel region are surrounded by the gate electrode, and at this time, the cross-section of the gate electrode is a ring with two openings.

[0091] In an exemplary embodiment of the present application, as Figure 1B shown, the semiconductor device may include a plurality of transistors 20. The plurality of transistors 20 may be arranged in an array on the substrate along the first direction and the second direction, and the second direction intersects the first direction.

[0092] Exemplarily, the first direction may be parallel to the substrate, the second direction may be parallel to the substrate, and the first direction and the second direction may be perpendicular to each other. For example, the first direction may be the a-a' direction as shown in Figure 1B and the second direction may be the b-b' direction as shown in Figure 1B .

[0093] In an exemplary embodiment of the present application, as shown in Figure 1A and Figure 1C , the bit line 30 may be connected to one end of a plurality of transistors 20 distributed along the first direction and close to the substrate 10.

[0094] In an exemplary embodiment of the present application, as shown in Figure 1A , the semiconductor device may further include a word line 40, and the word line 40 extends along the second direction. One word line 40 may be connected to the gate electrodes of a row of transistors 20 distributed along the second direction, or one word line 40 is formed by being connected together by the gate electrodes of a row of transistors 20 distributed along the second direction.

[0095] In an exemplary embodiment of the present application, as shown in Figure 1B , there is a first trench 51 between two adjacent rows of transistors 20 in the second direction, and there is a second trench 52 between two adjacent rows of transistors 20 in the first direction. The first trench 51 and the second trench 52 may be filled with an insulating layer to realize insulation of the plurality of transistors 20 in the first direction and the second direction.

[0096] In an exemplary embodiment of the present application, the depth of the first trench 51 is greater than the depth of the second trench 52. For example, the first trench 51 may extend to the surface or inside of the substrate 10, and the second trench 52 extends to the surface of the bit line 30.

[0097] In the present application, the semiconductor layer may be understood as a semiconductor material, and its shape and structure are not emphasized here, only its function is emphasized.

[0098] Exemplarily, the material of the substrate may be silicon or the like.

[0099] Exemplarily, the material of the semiconductor layer may be a material such as single-crystalline silicon or polycrystalline silicon with a band gap less than 1.65 eV, or it may also be a wide-band gap material, such as a metal oxide material with a band gap greater than 1.65 eV.

[0100] For example, the material of the metal oxide semiconductor layer or the channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide is not excluded from containing compounds of other elements, such as elements such as N and Si; nor is it excluded from containing other trace doping elements.

[0101] In some embodiments, the material of the metal oxide semiconductor layer may include any one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO, IWO), titanium oxide (TiO), zinc oxide nitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), etc. As long as the leakage current of the transistor can meet the requirements, it can be specifically adjusted according to the actual situation.

[0102] These materials have a wide bandgap and low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A to 10 -18 A, thereby improving the operating performance of the dynamic memory.

[0103] The materials of the above-mentioned metal oxide semiconductor layer or channel only emphasize the element type of the material, not the atomic ratio in the material and the film quality of the material.

[0104] Exemplarily, the material of the bit line may include any one or more of other metal materials with similar properties such as tungsten, molybdenum, cobalt, titanium, etc. The bit line may be a single-layer or multi-layer structure. For example, it may be a multi-layer structure formed by titanium (Ti), titanium nitride (TiN), and tungsten (W).

[0105] In the exemplary embodiments of the present application, the electrode material of the gate electrode may be any one or more of the following different types of materials:

[0106] For example, metals containing tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;

[0107] It can also be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO) and other metal oxide materials with relatively high conductivity; for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), etc.

[0108] Of course, it can also be polysilicon material; it can also be a semiconductor material doped with a conductive material, for example, silicon after conductive doping, germanium after conductive doping, silicon germanium after conductive doping, etc.; other materials that exhibit conductivity, etc.

[0109] In an exemplary embodiment of the present application, the material of the gate insulating layer may include one or more layers of Low-K and / or High-K dielectric materials, or include two or more regions with different dielectric constants K. The characteristics of the gate insulating layer of the present application will be exemplarily described below.

[0110] Low-K material, such as silicon oxide.

[0111] High-K material, such as a dielectric material with a dielectric constant K≥3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, it may include at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2) and other high-K materials.

[0112] In some embodiments, the substrate is a silicon substrate, the semiconductor pillar is a silicon pillar, and the bit line is a metal-containing wire.

[0113] In some embodiments, it includes a bit line hole, the bit line is located in the bit line hole, and the width of the bit line hole is the same as the width of the semiconductor pillar in the direction perpendicular to the first direction. The side walls of the bit line hole located below the semiconductor pillar include the semiconductor pillar and the substrate that are opposite to each other up and down, and the insulating layer that is opposite to each other left and right, such as silicon oxide.

[0114] In some embodiments, the longitudinal cross-section of the bit line hole in the direction perpendicular to the first direction is rectangular.

[0115] The embodiment of the present application also provides a manufacturing method of a semiconductor device.

[0116] Figure 2 It is a process flow chart of a manufacturing method of a semiconductor device provided for an exemplary embodiment of the present disclosure. As Figure 2 shown, the manufacturing method of the semiconductor device includes:

[0117] A sacrificial layer and a semiconductor layer are sequentially formed on a substrate. Among them, under the same etching conditions, the etching selectivity between the sacrificial layer and the semiconductor layer is different;

[0118] The semiconductor layer and the sacrificial layer are etched so that the semiconductor layer forms a plurality of semiconductor pillars extending in a direction perpendicular to the substrate and distributed at intervals, and the sacrificial layer forms a plurality of sacrificial strips extending in a first direction and distributed at intervals in a second direction, and each of the sacrificial strips is connected to one end of a row of the semiconductor pillars distributed in the first direction;

[0119] The sacrificial strips are removed to form bit line holes;

[0120] Bit lines are formed in the bit line holes.

[0121] In the manufacturing method of the embodiment of the present application, a sacrificial layer is first formed in the area where the bit lines are to be formed, and the sacrificial layer is made of a material with an etching selectivity different from that of the semiconductor layer. Then, the sacrificial layer is etched into a regular shape corresponding to the bit line pattern, and then the sacrificial layer is removed and the bit lines are formed, which can avoid the process of forming bit line holes by etching silicon with high processing difficulty and reduce the bit line processing difficulty of the VCT structure.

[0122] In an exemplary embodiment of the present application, the etching of the semiconductor layer and the sacrificial layer may include:

[0123] The semiconductor layer and the sacrificial layer are etched to form a plurality of first trenches extending in the first direction and distributed at intervals in the second direction and a plurality of second trenches extending in the second direction and distributed at intervals in the first direction in the semiconductor layer and the sacrificial layer, and the first trenches extend to the surface or inside of the substrate, and the second trenches extend to the surface or inside of the sacrificial layer; the first trenches and the second trenches divide the semiconductor layer into the plurality of semiconductor pillars, and the first trenches divide the sacrificial layer into the plurality of sacrificial strips.

[0124] In an exemplary embodiment of the present application, the etching of the semiconductor layer and the sacrificial layer to form a plurality of first trenches extending in the first direction and distributed at intervals in the second direction and a plurality of second trenches extending in the second direction and distributed at intervals in the first direction in the semiconductor layer and the sacrificial layer may include:

[0125] The semiconductor layer and the sacrificial layer are etched to form the first trenches, the first trenches expose the substrate, the first trenches divide the semiconductor layer into a plurality of semiconductor walls extending in the first direction and distributed at intervals in the second direction, and divide the sacrificial layer into the plurality of sacrificial strips;

[0126] Fill a first insulating layer in the first trench;

[0127] Etch the semiconductor wall to form a second trench extending to the surface of the sacrificial strip, or etch the semiconductor wall and the sacrificial strip to form a second trench extending into the sacrificial strip, the second trench exposing the sacrificial strip, and the second trench spacing the semiconductor wall into the plurality of semiconductor pillars.

[0128] In some embodiments, such as Figure 1A As shown, after the first trench exposes the substrate, continue to etch to etch a trench in the substrate, so that the bit lines are located on the islands between adjacent trenches on the substrate, which can reduce the parasitic capacitance between the bit lines.

[0129] In an exemplary embodiment of the present application, the etching of the semiconductor layer and the sacrificial layer to form a plurality of first trenches extending along the first direction and spaced apart in the second direction and a plurality of second trenches extending along the second direction and spaced apart in the first direction in the semiconductor layer and the sacrificial layer may include:

[0130] Etch the semiconductor layer to form a second trench extending to the surface of the sacrificial layer, or etch the semiconductor layer and the sacrificial layer to form a second trench extending into the sacrificial layer, the second trench exposing the sacrificial layer, and the second trench spacing the semiconductor layer into a plurality of semiconductor walls extending along the second direction and spaced apart in the first direction;

[0131] Fill a first insulating layer in the second trench;

[0132] Etch the semiconductor wall and the sacrificial layer to form the first trench, the first trench spacing the semiconductor wall into the plurality of semiconductor pillars and spacing the sacrificial layer into the plurality of sacrificial strips.

[0133] In an exemplary embodiment of the present application, the sequentially forming a sacrificial layer and a semiconductor layer on the substrate may include:

[0134] Form a sacrificial layer on one side of the substrate by an epitaxial method or a deposition method, the thickness of the sacrificial layer being not less than the thickness of the to-be-formed bit line;

[0135] Grow or deposit semiconductor material on the side of the sacrificial layer away from the substrate by an epitaxial method or a deposition method, and in-situ dope the semiconductor material to form a semiconductor layer containing a doped material.

[0136] In an exemplary embodiment of the present application, the manufacturing method may further include: after forming the semiconductor pillars and before removing the sacrificial strips,

[0137] A first insulating layer is formed on the exposed sidewall of the semiconductor pillar.

[0138] In an exemplary embodiment of the present application, forming the bit line in the bit line hole may include:

[0139] Filling a conductive layer in the bit line hole and the second trench, and electrically connecting the conductive layer in the bit line hole to one end of the semiconductor pillar close to the substrate;

[0140] Removing the conductive layer in the second trench, and retaining the conductive layer in the bit line hole as the bit line.

[0141] In an exemplary embodiment of the present application, the manufacturing method may further include: after forming the bit line,

[0142] Forming a second insulating layer on the exposed surface of the bit line;

[0143] The semiconductor pillar includes a first electrode region electrically connected to the bit line, a second electrode region far from the substrate, and a channel region located between the first electrode region and the second electrode region. A gate insulating layer and a gate electrode surrounding the channel region are sequentially formed on the sidewall of the channel region. The semiconductor pillar, the gate electrode, and the gate insulating layer constitute a transistor.

[0144] The technical solution of this embodiment will be further described below through the manufacturing process of a semiconductor device in an exemplary embodiment.

[0145] Figure 3A A three-dimensional structural diagram of a manufacturing method of a semiconductor device in an exemplary embodiment of the present application after forming a sacrificial layer; Figure 3B For Figure 3A A schematic cross-sectional structure diagram of the semiconductor structure shown in a cross-section perpendicular to the substrate along the a-a' direction; Figure 4A A three-dimensional structural diagram of a manufacturing method of a semiconductor device in an exemplary embodiment of the present application after forming a semiconductor pillar; Figure 4B For Figure 4A A schematic cross-sectional structure diagram of the semiconductor structure shown in a cross-section perpendicular to the substrate along the a-a' direction; Figure 4C For Figure 4A A schematic cross-sectional structure diagram of the semiconductor structure shown in a cross-section perpendicular to the substrate along the b-b' direction; Figure 5A A three-dimensional structural diagram of a manufacturing method of a semiconductor device in an exemplary embodiment of the present application after forming a bit line hole; Figure 5B For Figure 5A A schematic cross-sectional structure diagram of the semiconductor structure shown in a cross-section perpendicular to the substrate along the a-a' direction; Figure 5Cis Figure 5A A schematic cross-sectional structure diagram of the semiconductor structure shown in the cross-section perpendicular to the substrate taken along the b-b' direction; Figure 6A A three-dimensional structure diagram after forming bit lines in a manufacturing method of a semiconductor device according to an exemplary embodiment of the present application; Figure 6B is Figure 6A A schematic cross-sectional structure diagram of the semiconductor structure shown in the cross-section perpendicular to the substrate taken along the a-a' direction; Figure 6C is Figure 6A A schematic cross-sectional structure diagram of the semiconductor structure shown in the cross-section perpendicular to the substrate taken along the b-b' direction.

[0146] As Figures 3A to 6C shown, in an exemplary embodiment of the present disclosure, the manufacturing method of the semiconductor device may include:

[0147] S10: Sequentially form a sacrificial layer 11 and a semiconductor layer 12 on a substrate 10 to obtain a semiconductor structure as shown in Figure 3A and Figure 3B shown. Among them, under the same etching conditions, the etching selectivity between the sacrificial layer 11 and the semiconductor layer 12 is different.

[0148] The sacrificial layer 11 can select a material with a relatively large etching selectivity with respect to the semiconductor layer 12 and is easy to remove. For example, the material of the sacrificial layer 11 can be silicon germanium (SiGe), and the material of the semiconductor layer 12 can be single-crystalline silicon, IGZO, IAZO, ITO, ZnO, etc. The thickness of the sacrificial layer 11 is not less than the thickness of the bit line to be formed.

[0149] Exemplarily, the sacrificial layer 11 can be grown on one side of the substrate 10 by an epitaxial method, and then a semiconductor material can be grown on the side of the sacrificial layer 11 away from the substrate 10 by an epitaxial method, and in-situ doping is performed on the semiconductor material while growing it to form a semiconductor layer 12 containing a doped material; or, the sacrificial layer 11 can be deposited on one side of the substrate 10 by an atomic layer deposition (ALD) process, and then a semiconductor material can be deposited on the side of the sacrificial layer 11 away from the substrate 10 by an ALD process, and in-situ doping is performed on the semiconductor material while depositing it to form a semiconductor layer 12 containing a doped material.

[0150] S20: Etch the semiconductor layer 12 and the sacrificial layer 11 to form a plurality of semiconductor pillars 21 extending in a direction perpendicular to the substrate 10 and spaced apart, and to form a plurality of sacrificial strips 13 extending in a first direction and spaced apart in a second direction in the sacrificial layer 11, and each sacrificial strip 13 is connected to one end of a row of semiconductor pillars 21 distributed along the first direction, to obtain as shown in Figures 4A to 4CThe semiconductor structure shown.

[0151] Exemplarily, step S20 may include:

[0152] S21: Etch the semiconductor layer 12 and the sacrificial layer 11 to form a plurality of first trenches 51 extending along the first direction and spaced apart in the second direction within the semiconductor layer 12 and the sacrificial layer 11. The first trenches 51 penetrate through the semiconductor layer 12 and the sacrificial layer 11 and expose the substrate 10. The first trenches 51 may extend to the surface or inside of the substrate 10. The first trenches 51 divide the semiconductor layer 12 into a plurality of semiconductor walls extending along the first direction and spaced apart in the second direction, and divide the sacrificial layer 11 into a plurality of sacrificial strips 13 extending along the first direction;

[0153] S22: Fill the first trenches 51 with a first insulating layer 14. The first insulating layer 14 covers the sidewalls of the semiconductor walls. When etching the second trenches 52 subsequently, the first insulating layer 14 can act as an etching barrier layer to protect the sidewalls of the semiconductor walls covered by the first insulating layer 14 from being etched;

[0154] S23: Etch the semiconductor walls to form a plurality of second trenches 52 extending along the second direction and spaced apart in the first direction. The second trenches 52 expose the sacrificial strips 13. The second trenches 52 may extend to the surface of the sacrificial strips 13 or extend into the sacrificial strips 13. The second trenches 52 divide the semiconductor walls into a plurality of semiconductor columns 21 spaced apart in the first direction and the second direction and arranged in an array.

[0155] In the above exemplary embodiment, the first trenches 51 are etched first, and then the second trenches 52 are etched. In other embodiments, the second trenches 52 may also be etched first, and then the first trenches 51 are etched. In this case, step S20 may include:

[0156] S21: Etch the semiconductor layer 12 to form a plurality of second trenches 52 extending along the second direction and spaced apart in the first direction. The second trenches 52 expose the sacrificial layer 11. The second trenches 52 may extend to the surface of the sacrificial layer 11 or extend into the sacrificial layer 11. The second trenches 52 divide the semiconductor layer 12 into a plurality of semiconductor walls extending along the second direction and spaced apart in the first direction;

[0157] S22: Fill the second trenches 52 with a first insulating layer 14. The first insulating layer 14 covers the sidewalls of the semiconductor walls. When etching the first trenches 51 subsequently, the first insulating layer 14 can act as an etching barrier layer to protect the sidewalls of the semiconductor walls covered by the first insulating layer 14 from being etched;

[0158] S23: Etch the semiconductor wall and the sacrificial layer 11 to form a plurality of first trenches 51 extending along the first direction and spaced apart in the second direction. The first trenches 51 penetrate through the semiconductor wall and the sacrificial layer 11 and expose the substrate 10. The first trenches 51 may extend to the surface or inside of the substrate 10. The first trenches 51 divide the semiconductor wall into a plurality of semiconductor pillars 21 spaced apart along the first direction and the second direction and arranged in an array, and divide the sacrificial layer 11 into a plurality of sacrificial strips 13 extending along the first direction.

[0159] S30: Remove the sacrificial strips 13 to form bit line holes 31, obtaining the semiconductor structure as Figures 5A to 5C shown.

[0160] Exemplarily, step S30 may include:

[0161] S31: Deposit a first insulating layer 14 on the inner wall of the second trench 52. The first insulating layer 14 covers the exposed sidewalls of the semiconductor pillars 21. When the sacrificial strips 13 are etched and removed subsequently, the first insulating layer 14 deposited in this step and step S20 can act as an etch stop layer to protect the sidewalls of the semiconductor pillars 21 from being etched;

[0162] S32: Etch and remove the first insulating layer 14 on the bottom wall of the second trench 52 to expose the sacrificial strips 13;

[0163] S33: Selectively etch and remove the sacrificial strips 13 to form bit line holes 31.

[0164] As Figure 5B and Figure 5C shown, the formed bit line holes 31 may have a regular shape. The cross-sectional shape of different regions of the bit line holes 31 in the longitudinal section perpendicular to the first direction may be rectangles with the same size, and the bottom surface of the bit line holes 31 close to the substrate 10 is a plane and may be parallel to the substrate 10.

[0165] S40: Form bit lines 30 in the bit line holes 31, obtaining the semiconductor structure as Figures 6A to 6C shown.

[0166] Exemplarily, step S40 may include:

[0167] S41: Fill the bit line holes 31 and the second trenches 52 with a conductive layer, and make the conductive layer located in the bit line holes 31 electrically connected to the end of the semiconductor pillars 21 close to the substrate 10;

[0168] S42: Remove the conductive layer in the second trenches 52 and retain the conductive layer located in the bit line holes 31 as the bit lines 30;

[0169] S43: Deposit a second insulating layer 15 on the exposed surface of the bit line 30, and deposit a first insulating layer 14 on the surface of the second insulating layer 15. The first insulating layer 14 and the second insulating layer 15 can isolate the bit line 30 from the film layer located above the bit line 30.

[0170] The semiconductor pillar 21 includes a first electrode region 211 electrically connected to the bit line 30, a second electrode region 213 away from the substrate 10, and a channel region 212 located between the first electrode region 211 and the second electrode region 213. Exemplarily, the manufacturing method may further include:

[0171] S50: Sequentially form a gate insulating layer 23 and a gate electrode 22 surrounding the channel region 212 on the sidewall of the channel region 212. The semiconductor pillar 21, the gate electrode 22, and the gate insulating layer constitute a transistor 20, obtaining a semiconductor device as Figures 1A to 1D shown.

[0172] The embodiment of the present application also provides an electronic device, and the electronic device includes the semiconductor device provided in the above embodiment of the present application.

[0173] In the exemplary embodiment of the present application, the electronic device may be: a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply, etc. The storage device may include the memory in a computer, etc., which is not limited herein.

[0174] Although the disclosed embodiments of the present application are as above, the above content is only an embodiment adopted for the convenience of understanding the present application, and is not used to limit the present application. Any person skilled in the art within the scope of the present application can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed by the present application. However, the protection scope of the present application shall still be subject to the scope defined by the appended claims.

Claims

1. A semiconductor device, characterized in that, Comprising: At least one transistor and a bit line located on a substrate; a semiconductor pillar of the transistor extends in a direction perpendicular to the substrate, the bit line is located between the semiconductor pillar of the transistor and the substrate and is electrically connected to one end of the semiconductor pillar of the transistor; the bit line extends in a first direction, and a width of the bit line does not exceed a width of the semiconductor pillar in a direction perpendicular to the first direction.

2. The semiconductor device according to claim 1, characterized in that, Cross-sectional shapes of the bit line in different regions in the first direction and in a longitudinal section perpendicular to the first direction are the same.

3. The semiconductor device according to claim 1, characterized in that, The bit line has a bottom surface close to the substrate and a top surface away from the substrate, and the bottom surface of the bit line is parallel to the substrate.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The semiconductor pillar has a channel region and a first electrode region, and the first electrode region is electrically connected to the bit line; The first electrode region contains a doping material, and an average bulk density of the doping material in the first electrode region is not lower than 1e19 atoms / cm³.

5. The semiconductor device according to claim 4, wherein The average bulk density of the doping material in the first electrode region is from 1e19 atoms / cm³ to 1e20 atoms / cm³.

6. The semiconductor device according to claim 1, wherein, The substrate is a silicon substrate, the semiconductor pillar is a silicon pillar, and the bit line is a metal-containing wire.

7. The semiconductor device according to claim 1, wherein Including a bit line hole, the bit line is filled in the bit line hole, and a width of the bit line hole is the same as a width of the semiconductor pillar in a direction perpendicular to the first direction.

8. The semiconductor device according to claim 1, wherein A longitudinal section of the bit line hole perpendicular to the first direction is rectangular.

9. A method for manufacturing a semiconductor device, characterized in that, Comprising: A sacrificial layer and a semiconductor layer are sequentially formed on a substrate, wherein, under the same etching conditions, an etching selectivity between the sacrificial layer and the semiconductor layer is different; The semiconductor layer and the sacrificial layer are etched to form a plurality of semiconductor pillars extending in a direction perpendicular to the substrate and distributed at intervals, and to form a plurality of sacrificial strips extending in the first direction and distributed at intervals in a second direction, and each of the sacrificial strips is connected to one end of a row of the semiconductor pillars distributed along the first direction; The sacrificial strips are removed to form bit line holes; A bit line is formed in the bit line holes.

10. The manufacturing method according to claim 9, characterized in that, The etching of the semiconductor layer and the sacrificial layer includes: The semiconductor layer and the sacrificial layer are etched to form a plurality of first trenches extending in the first direction and distributed at intervals in the second direction and a plurality of second trenches extending in the second direction and distributed at intervals in the first direction in the semiconductor layer and the sacrificial layer, and the first trenches extend to the surface or inside of the substrate, and the second trenches extend to the surface or inside of the sacrificial layer; the first trenches and the second trenches divide the semiconductor layer into the plurality of semiconductor pillars, and the first trenches divide the sacrificial layer into the plurality of sacrificial strips.

11. The manufacturing method according to claim 10, characterized in that, The etching of the semiconductor layer and the sacrificial layer to form a plurality of first trenches extending in the first direction and distributed at intervals in the second direction and a plurality of second trenches extending in the second direction and distributed at intervals in the first direction in the semiconductor layer and the sacrificial layer includes: Etch the semiconductor layer and the sacrificial layer to form the first trench, the first trench exposing the substrate, the first trench spacing the semiconductor layer into a plurality of semiconductor walls extending in the first direction and spaced apart in the second direction, and spacing the sacrificial layer into the plurality of sacrificial strips; fill the first trench with a first insulating layer; etch the semiconductor walls to form a second trench extending to the surface of the sacrificial strip, or etch the semiconductor walls and the sacrificial strips to form a second trench extending into the interior of the sacrificial strip, the second trench exposing the sacrificial strip, the second trench spacing the semiconductor walls into the plurality of semiconductor pillars; Alternatively, etch the semiconductor layer to form a second trench extending to the surface of the sacrificial layer, or etch the semiconductor layer and the sacrificial layer to form a second trench extending into the interior of the sacrificial layer, the second trench exposing the sacrificial layer, the second trench spacing the semiconductor layer into a plurality of semiconductor walls extending in the second direction and spaced apart in the first direction; fill the second trench with a first insulating layer; etch the semiconductor walls and the sacrificial layer to form the first trench, the first trench spacing the semiconductor walls into the plurality of semiconductor pillars and spacing the sacrificial layer into the plurality of sacrificial strips.

12. The manufacturing method according to any one of claims 9 to 11, characterized in that, The forming of the sacrificial layer and the semiconductor layer on the substrate in sequence includes: Form a sacrificial layer on one side of the substrate by an epitaxial method or a deposition method, the thickness of the sacrificial layer being not less than the thickness of the bit line to be formed; Grow or deposit a semiconductor material on the side of the sacrificial layer away from the substrate by an epitaxial method or a deposition method, and perform in-situ doping on the first electrode region of the semiconductor material.

13. The manufacturing method according to any one of claims 9 to 11, characterized in that, Further included is: After forming the semiconductor pillars and before removing the sacrificial strips, Form a first insulating layer on the exposed sidewalls of the semiconductor pillars.

14. The manufacturing method according to claim 10 or 11, characterized in that, The forming of the bit line in the bit line hole includes: Fill the bit line hole and the second trench with a conductive layer, and electrically connect the conductive layer in the bit line hole to the end of the semiconductor pillar close to the substrate; Remove the conductive layer in the second trench, and retain the conductive layer in the bit line hole as the bit line.

15. The manufacturing method according to claim 9, characterized in that, Further included is: After forming the bit line, Form a second insulating layer on the exposed surface of the bit line; The semiconductor pillar includes a first electrode region electrically connected to the bit line, a second electrode region away from the substrate, and a channel region between the first electrode region and the second electrode region. A gate insulating layer and a gate electrode surrounding the channel region are formed in sequence on the sidewalls of the channel region.

16. An electronic device, characterized in that, Including the semiconductor device according to any one of claims 1 to 8.

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