Semiconductor structure and forming method thereof
By forming an isolation component in the dynamic random access memory and setting a discontinuous first word line and a continuous second word line, the work function adjustment structure is used to solve the leakage current problem between adjacent bit lines and improve the performance of the memory.
Patent Information
- Application Number
- CN202410149172.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-01-03
- Filing Date
- 2024-02-02
- Publication Date
- 2025-07-04
AI Technical Summary
In dynamic random access memory, as the component product concentration increases, the leakage current problem between adjacent bit lines still needs to be further improved.
By forming an isolation component in the substrate to define the active area, and burying the first word line and the second word line in the array area in the dummy word line area, the conductive structure of the first word line is discontinuous along the word line extension direction, and the conductive structure of the second word line is continuous along the word line extension direction, and the work function adjustment structure reduces leakage current.
The leakage circuit paths caused by different storage capacitors arranged in the channel extension direction of the wires in the dummy word line area are effectively avoided, and the performance of dynamic random access memory is improved.
Smart Images
Figure CN120264747A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor structure and a method for forming the same, and particularly to a dynamic random access memory structure and a method for forming the same. Background Art
[0002] Dynamic Random Access Memory (DRAM) is widely used in various consumer electronic products. In order to increase the integration density of components in the dynamic random access memory and improve its performance, efforts are still being made towards the miniaturization of component sizes. However, when the component integration density increases, many challenges arise. For example, the leakage current generated between adjacent bit lines still needs to be further improved. Summary of the Invention
[0003] An embodiment of the present invention provides a semiconductor structure, including a substrate, an isolation component, a first word line, and a second word line. The substrate has an array region and a dummy word line region adjacent to the array region. The isolation component is disposed in the substrate of the array region and the dummy word line region to define the active region of the substrate. The first word line is buried in the substrate within the dummy word line region and extends across the active region and the isolation component, wherein the first word line includes a plurality of first conductive structures. The second word line is buried in the substrate within the array region and extends across the active region and the isolation component, wherein the second word line includes a second conductive structure, and a first top surface of each first conductive structure is below a second top surface of the second conductive structure.
[0004] An embodiment of the present invention provides a method for forming a semiconductor structure, including providing a substrate, wherein the substrate has an array region and a dummy word line region adjacent to the array region; forming an isolation component in the substrate to define an active region; forming a first word line in the substrate within the dummy word line region, the first word line extending across the active region and the isolation component, wherein the first word line includes a plurality of first conductive structures; and forming a second word line in the substrate within the array region, the second word line extending across the active region and the isolation component, wherein the second word line includes a second conductive structure, and a first top surface of each first conductive structure is below a second top surface of the second conductive structure.
[0005] The semiconductor structure and the method for forming the same provided by the embodiments of the present invention can avoid forming a leakage path between adjacent bit lines due to the wires in the dummy word line region simultaneously connecting different storage capacitors arranged along the channel extension direction. Brief Description of the Drawings
[0006] Figure 1 A top view schematic diagram of a semiconductor structure according to some embodiments of the present invention.
[0007] Figure 2 For Figure 1Partial enlarged schematic diagram, showing the layout of a semiconductor structure according to some embodiments of the present invention.
[0008] Figure 3 According to some embodiments of the present invention, along Figure 2 Schematic cross-sectional view of the semiconductor structure along the A-A' tangent as shown.
[0009] Figure 4 、 Figure 5 、 Figure 6 According to some embodiments of the present invention, a schematic cross-sectional view of an intermediate stage of forming the semiconductor structure as shown. Figure 3 Schematic cross-sectional view of the semiconductor structure in an intermediate stage as shown.
[0010] Explanation of reference numerals in the drawings:
[0011] 200: Substrate
[0012] 201: Top surface
[0013] 202: First well region
[0014] 204: Second well region
[0015] 205, 205a, 205b: Doped regions
[0016] 206: Isolation component
[0017] 208: Active region
[0018] 210: Hard mask pattern
[0019] 212A: First trench
[0020] 212AB: Bottom surface
[0021] 212B: Second trench
[0022] 214: Gate dielectric layer
[0023] 214-2T: Upper surface
[0024] 216A, 216B, 225: Layers
[0025] 218A, 218B: Gate electrode layers
[0026] 220A: First conductive structure
[0027] 220AT, 220B-1T, 220B-2T: Top surfaces
[0028] 220B: Second conductive structure
[0029] 220B-1: First part
[0030] 220B-2: Second part
[0031] 222: Patterned mask
[0032] 226A, 226B: Work function adjustment structure
[0033] 230: Word line
[0034] 230A: First word line
[0035] 230B: Second word line
[0036] 242, 244: Capping layer
[0037] 246: Interlayer dielectric layer
[0038] 248a, 248b: Contact plug
[0039] 250: Bit line
[0040] 252: Barrier layer
[0041] 254: Conductive layer
[0042] 260: Storage capacitor
[0043] 262: First electrode
[0044] 264: Dielectric
[0045] 266: Second electrode
[0046] 268, 268A, 268B: Conductive wire
[0047] 270: Region
[0048] 272: Truncated region
[0049] 400: Array region
[0050] 402:Dummy word line region
[0051] 500: Semiconductor structure
[0052] D1, D2, D3: Directions
[0053] T1, T2: Thicknesses
[0054] θ: Acute angle Detailed implementation manners
[0055] Figure 1 FIG. is a top view schematic diagram of a semiconductor structure 500 according to some embodiments of the present invention. Figure 2 is Figure 1 an enlarged schematic diagram of the region 270 of Figure 2Layout of a semiconductor structure 500 according to some embodiments of the present invention. For ease of illustration, reference directions are indicated therein. Direction D1 is the channel extension direction, direction D2 is the gate extension direction (or word line extension direction), and direction D3 is the bit line extension direction. Direction D2 is substantially perpendicular to direction D3. Direction D1 intersects direction D2 at an acute angle θ.
[0056] As Figure 1 , Figure 2 shown, in some embodiments, the semiconductor structure 500 is part of a dynamic random access memory (DRAM). The semiconductor structure 500 includes a substrate 200, isolation components 206, active regions 208, word lines 230, contact plugs 248a, 248b, bit lines 250, and storage capacitors 260. For illustration, Figure 1 , Figure 2 only the above components are shown, and the remaining components can be seen in the Figures 3 - 6 cross-sectional schematic diagram of Figures 3 - 6 along the Figure 2 tangent line A - A' of
[0057] As Figure 1 , Figure 2 shown, the substrate 200 has an array region 400 and a dummy word line region 402 adjacent to the array region 400. The isolation components 206 are formed in the substrate 200 of the array region 400 and the dummy word line region 402, defining a plurality of active regions 208 in the substrate 200. The active regions 208 extend along direction D1 and are spaced apart along directions D1 and D2 respectively. Adjacent active regions 208 on the same straight line along direction D1 completely overlap each other and are separated from each other by the isolation components 206 of the truncation region 272. In direction D2, adjacent truncation regions 272 are misaligned or non - overlapping. Adjacent active regions 208 on the same straight line along direction D2 partially overlap each other and are separated from each other by the isolation components 206. In some embodiments, the size of the memory cells of the semiconductor structure 500 is 6F 2 (length is 3F, width is 2F, and F is the minimum feature size).
[0058] The word lines 230 are formed in the substrate and extend along direction D2. The word lines 230 are arranged in such a way that a pair of adjacent word lines 230 correspond to one active region 208 in direction D3. The bit lines 250 are formed above the substrate and extend along direction D3. The bit lines 250 are arranged corresponding to the active regions 208 in direction D2. The storage capacitors 260 are formed above the substrate and are located in the region between a pair of adjacent word lines 230 and a pair of adjacent bit lines 250.
[0059] The contact plug 248a is located at the intersection of the bit line 250 and the active region 208. When the bit line 250 crosses a pair of word lines 230 corresponding to the active region 208, the bit line 250 is electrically connected to the block of the active region 208 between the pair of word lines 230 through the contact plug 248a. The contact plug 248b is located between an adjacent pair of word lines 230 and an adjacent pair of bit lines 250, and partially overlaps with the corresponding active region 208. The storage capacitor 260 is electrically connected to the end portion of the corresponding active region 208 through the contact plug 248b.
[0060] Figure 3 According to some embodiments of the present invention, Figure 2 The schematic cross-sectional view of the semiconductor structure 500 taken along the AA' line is shown. Figure 3 The semiconductor structure 500 includes a substrate 200 , an isolation component 206 , a first word line 230A, a second word line 230B, a first well region 202 , and a second well region 204 .
[0061] The first well region 202 is located in the substrate 200 in the dummy word line region 402, and the second well region 204 is located in the substrate 200 in the array region 400. The first well region 202 and the second well region 204 have the same conductivity type and different doping concentrations. For example, the first well region 202 has a first doping concentration, the second well region 204 has a second doping concentration, and the first doping concentration is greater than the second doping concentration.
[0062] like Figure 2 , Figure 3 As shown, the isolation component 206 is disposed in the substrate 200 to define an active region 208 of the substrate 200. The bottom surface of the isolation component 206 is within the first well region 202 and the second well region 204. The isolation component 206 can be a shallow trench isolation, which is formed, for example, of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and / or a combination thereof. In some embodiments, the isolation component 206 is formed using a patterning process and a subsequent deposition process and a planarization process.
[0063] like Figure 3 As shown, the first word line 230A is buried in the first trench 212A of the substrate 200 in the dummy word line region 402 (eg, Figure 4 20A and extends across the active region 208 and the isolation component 206. In addition, the first word line 230A is disposed in the first well region 202. In some embodiments, the first word line 230A includes a gate dielectric layer 214, a plurality of first conductive structures 220A disposed on the gate dielectric layer 214, and a work function adjustment structure 226A disposed on the first conductive structure 220A. The first word line 230A also includes a liner 225 disposed between the first conductive structure 220A and the work function adjustment structure 226A.
[0064] The gate dielectric layer 214 conformally covers the first trench 212A (as Figure 4 shown). In some embodiments, the gate dielectric layer 214 is formed of silicon oxide, silicon nitride, silicon oxynitride, and / or a high-k dielectric material.
[0065] In some embodiments, the first conductive structure 220A of the first word line 230A is discontinuously disposed along the word line extending direction (direction D2). Specifically, the first conductive structure 220A of the first word line 230A is located in the first trench 212A of the isolation component 206 in the truncated region 272, and there is no first conductive structure 220A in the first trench 212A in the active region 208 (only the gate dielectric layer 214 and the work function adjustment structure 226A of the first word line 230A are present in the first trench 212A in the active region 208). Moreover, the first conductive structure 220A covers the gate dielectric layer 214 in the first trench 212A in the isolation component 206, but does not cover the gate dielectric layer 214 on the bottom surface 212AB of the first trench 212A in the active region 208. In some embodiments, the top surface 220AT of the first conductive structure 220A is aligned with the upper surface 214-2T of the gate dielectric layer 214 on the bottom surface 212AB of the first trench 212A in the active region 208.
[0066] In some embodiments, the first conductive structure 220A includes a liner layer 216A and a gate electrode layer 218A. The liner layer 216A conformally covers the first trench 212A in the substrate 200 (as Figure 4 shown), the gate electrode layer 218A is disposed on the liner layer 216A, and partially fills the first trench 212A. In some embodiments, the liner layer 216A includes tungsten nitride (WN) (work function of about 4.6), titanium nitride (TiN) (work function of about 4.7), or tantalum nitride (TaN) (work function of about 4.5), and the gate electrode layer 218A includes a metal such as tungsten (W) (work function of about 4.52). In some embodiments, the material and formation method of the liner layer 225 covering the first conductive structure 220A can be similar to those of the liner layer 216A.
[0067] The work function adjustment structure 226A contacts the liner 225 in the first trench 212A of the isolation component 206 in the cut-off region 272 and the upper surface 214-2T of the gate dielectric layer 214 on the bottom surface 212AB of the first trench 212A in the active region 208. The work function adjustment structure 226A is a conductive structure, which has a different material and structure from the first conductive structure 220A. In some embodiments, the work function of the work function adjustment structure 226A is less than the work function of the first conductive structure 220A and greater than the work function of the substrate 200 (for example, the work function of the substrate 200 made of silicon is about 3.9). The work function adjustment structure 226A is used to reduce the electric field in the overlapping region between it and the drain doping region of the final semiconductor structure, thereby reducing the gate-induced drain leakage current (GIDL), and can reduce the channel leakage current and junction leakage from the drain doping region to the underlying substrate 200. In some embodiments, the work function adjustment structure 226A can be a single-layer structure, which can include doped polysilicon, such as polysilicon doped with an N-type dopant (the work function is about 4.05). The liner 216A, the gate electrode layer 218A, and the work function adjustment structure 226A can be formed individually by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).
[0068] As Figure 3 shown, the second word line 230B is buried in the second trench 212B of the substrate 200 in the array region 400 (as Figure 4 shown) and extends across the active region 208 and the isolation component 206. Moreover, the second word line 230B is disposed in the second well region 204. In some embodiments, the second word line 230B includes a gate dielectric layer 214, a second conductive structure 220B disposed on the gate dielectric layer 214, and a work function adjustment structure 226B disposed on the second conductive structure 220B. The second word line 230B further includes a liner 225 disposed between the second conductive structure 220B and the work function adjustment structure 226B.
[0069] In some embodiments, the second conductive structure 220B of the second word line 230B is continuously disposed along the word line extension direction (direction D2). The top surface 220B-1T of the first portion 220B-1 of the second conductive structure 220B in the cut-off region 272 is flush with the top surface 220B-2T of the second portion 220B-2 of the second conductive structure 220B in the active region 208. In some embodiments, the top surface 220AT of the first conductive structure 220A is below the top surfaces 220B-1T and 220B-2T of the second conductive structure 220B. In some embodiments, the second conductive structure 220B can include a liner 216B and a gate electrode layer 218B. The liner 216B conformally covers the second trench 212B in the substrate 200 (as Figure 4As shown, the gate electrode layer 218B is disposed on the liner layer 216B and partially fills the second trench 212B. In some embodiments, the liner layers 216A and 216B have the same material and formation method and are formed simultaneously. Also, the gate electrode layers 218A and 218B have the same material.
[0070] The work function adjustment structure 226B contacts the liner layer 225. In some embodiments, the work function adjustment structures 226A and 226B have the same material and formation method and are formed simultaneously. Also, the thickness T1 of the work function adjustment structure 226A may be greater than the thickness T2 of the work function adjustment structure 226B.
[0071] As Figure 3 shown, the semiconductor structure 500 further includes a doped region 205. The doped region 205 includes a doped region (source doped region) 205a and a doped region (drain doped region) 205b, which are disposed in the active region 208 and adjacent to the first word line 230A and the second word line 230B. Also, the first portion 220B-1 of the first conductive structure 220A and the second conductive structure 220B in the isolation member 206 of the cutoff region 272 is below the doped region 205 and does not overlap with the doped region 205.
[0072] The semiconductor structure 500 further includes a capping layer 242 disposed on the first word line 230A and the second word line 230B and filling the upper portions of the first trench 212A and the second trench 212B (as Figure 4 shown). The capping layer 242 may be formed of a dielectric material, such as silicon nitride or silicon oxide. In some embodiments, the capping layer 242 is formed by a deposition process and a subsequent planarization process. In some embodiments, the deposition process includes a deposition process with high step coverage or high conformity, such as atomic layer deposition (ALD). In some embodiments, the planarization process includes chemical mechanical polishing (CMP) and / or etchback.
[0073] The semiconductor structure 500 further includes a capping layer 244 formed on the top surface 201 of the substrate 200 and covering the word line 230a. In some embodiments, the capping layer 244 is formed of an oxide, such as silicon oxide. In some embodiments, the capping layer 244 is formed using a deposition process (such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and / or a combination of the above).
[0074] The semiconductor structure 500 further includes an interlayer dielectric layer 246 disposed on the substrate 200. The interlayer dielectric layer 246 includes, for example, silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), other suitable low-k dielectric materials, or a combination of the above. In this embodiment, the interlayer dielectric layer 246 includes silicon nitride.
[0075] The contact plugs 248a and 248b of the semiconductor structure 500 are disposed on the substrate 200, pass through the interlayer dielectric layer 246 and the capping layer 244, and are electrically connected to the doped regions 205a and 205b respectively. In some embodiments, the contact plugs 248a and 248b are formed of a conductive material. In some embodiments, a deposition process and a subsequent removal process are used to form the contact plugs 248a and 248b in the openings (not shown) of the interlayer dielectric layer 246 and the capping layer 244.
[0076] As Figure 2 、 Figure 3 shown, the bit line 250 is formed above the substrate 200 and in the interlayer dielectric layer 246, and is disposed on the contact plug 248a and electrically connected to the doped region 205a through the contact plug 248a. In some embodiments, the bit line 250 includes a barrier layer 252 formed on the contact plug 248a, and a conductive layer 254 formed on the barrier layer 252. In some embodiments, the barrier layer 252 is formed of titanium (Ti), tantalum (Ta), titanium nitride (TiN), and / or tantalum nitride (TaN), and the conductive layer 254 is formed of tungsten (W), aluminum (Al), and / or copper (Cu). In some embodiments, a deposition process and a subsequent removal process are used to form the bit line 250.
[0077] The storage capacitor 260 of the semiconductor structure 500 is disposed above the substrate 200 and the contact plug 248b, and is electrically connected to the doped region 205b through the contact plug 248b. In some embodiments, the storage capacitor 260 includes a first electrode 262, a dielectric 264, and a second electrode 266 formed in sequence on the contact plug 248b. The first electrode 262 and the second electrode 266 may include a conductive material, and the dielectric 264 may include a high dielectric constant (k) dielectric material. In some embodiments, a deposition process and a subsequent removal process, such as, are used to form the storage capacitor 260.
[0078] As Figure 2 、 Figure 3 shown, the semiconductor structure 500 further includes a wire 268 on the storage capacitor 260. The wire 268 includes a wire 268A in the dummy word line region 402 and a wire 268B in the array region 400. In some embodiments, different storage capacitors 260 arranged in the dummy word line region 402 and along the direction D1 (channel extension direction) are connected to the same wire 268A. Also, different storage capacitors 260 arranged in the array region 400 and along the direction D1 (channel extension direction) are connected to different wires 268B.
[0079] The following describes a method for forming the semiconductor structure 500. Please refer to Figure 4, a substrate 200 is provided. Then, a multi-step ion implantation process is performed to implant a first dopant of a first conductivity type into the substrate 200 in the dummy word line region 402 and the adjacent array region 400 of the substrate 200, and a second dopant of the first conductivity type is implanted into the substrate 200 in the dummy word line region 402 to form a first well region 202 in the substrate 200 of the dummy word line region 402, and a second well region 204 is formed in the substrate 200 within the array region 400. Moreover, a dopant of a second conductivity type opposite to the first conductivity type is implanted into the substrate 200 to form a doped region 205 on the first well region 202 and the second well region 204.
[0080] After that, a patterning process is performed to form trenches (not shown) in the substrate 200 to define the formation positions of the isolation components 206. Then, a deposition process is carried out to deposit a dielectric material in the trenches. After that, a planarization process is performed to form the isolation components 206 in the substrate 200. The isolation components 206 extend downward from the top surface 201 of the substrate 200 to define the active regions 208 of the substrate 200, wherein the bottom surfaces of the isolation components 206 are within the first well region 202 and the second well region 204.
[0081] Next, a deposition process, a subsequent lithography process, and an etching process are performed to form a hard mask pattern 210 on the top surface 201 of the substrate 200, defining first trenches 212A and second trenches 212B for forming a first word line 230A and a second word line 230B. In some embodiments, the hard mask pattern 210 extends in the direction D2 and is spaced apart in the direction D3, exposing a portion of the substrate 200 and a portion of the isolation components 206.
[0082] Next, using the hard mask pattern 210 as an etching mask, an etching process (e.g., dry etching) is performed on the exposed substrate 200 and isolation components 206 to form a first trench 212A in the first well region 202 within the dummy word line region 402, and a second trench 212B in the second well region 204 within the array region 400. Since the etching rates of the etching process for the substrate 200 (e.g., silicon) and the isolation components 206 (e.g., silicon oxide) are different, the depths of the first trench 212A and the second trench 212B in the isolation components 206 are greater than the depths of the first trench 212A and the second trench 212B in the active region 208.
[0083] Next, a multi - layer deposition process is performed to conformally form a gate dielectric layer 214 in the first trench 212A and the second trench 212B respectively. Then, a liner layer (not shown in the figure) covering the gate dielectric layer 214 is conformally formed. After that, a gate electrode layer (not shown in the figure) is deposited in the first trench 212A and the second trench 212B respectively, covering the gate dielectric layer 214 and the liner layer and filling the first trench 212A and the second trench 212B. Next, an etch - back process (e.g., dry etching) is performed to remove a part of the liner layer and a part of the gate electrode layer on the substrate 200 and in the first trench 212A and the second trench 212B, so that the upper part of the trench 212 is exposed again, and a second conductive structure 220B is formed in the lower part of the second trench 212B, which includes a liner layer 216B and a gate electrode layer 218B. In some embodiments, the top surface 220B - 1T of the first part 220B - 1 of the second conductive structure 220B in the isolation component 206 is flush with the top surface 220B - 2T of the second part 220B - 2 of the second conductive structure 220B in the active region 208.
[0084] Next, as Figure 5 shown, a patterned mask 222 is covered over the second trench 212B within the array region 400, and the first trench 212A within the dummy word - line region 402 is exposed.
[0085] Next, as Figure 6 shown, an etch - back process is performed to remove a part of the liner layer 216B and a part of the gate electrode layer 218B in the first trench 212A to form a first conductive structure 220A. The above - mentioned etch - back process completely removes the liner layer 216B and the gate electrode layer 218B in the first trench 212A in the active region 208 until the gate dielectric layer 214 on the bottom surface 212AB of the first trench 212A in the active region 208 is exposed. After performing the above - mentioned etch - back process, a first conductive structure 220A is formed in the isolation component 206 of the truncated region 272 within the dummy word - line region 402, which includes a liner layer 216A and a gate electrode layer 218A. The top surface 220AT of the first conductive structure 220A is aligned with the upper surface 214 - 2T of the gate dielectric layer 214 on the bottom surface 212AB of the first trench 212A in the active region 208. After forming the first conductive structure 220A, the patterned mask 222 is removed.
[0086] Next, as Figure 3 shown, a liner material (the material is, for example, the same as the liner layer 216A) is deposited to conformally cover the first conductive structure 220A and the second conductive structure 220B. Then, another etch - back process is performed to remove a part of the conductive material in the first trench 212A and the second trench 212B, so that the upper parts of the first trench 212A and the second trench 212B and a part of the gate dielectric layer 214 are exposed to form a liner layer 225.
[0087] Next, as shown in Figure 3 , a conductive material (not shown in the figure) is deposited to cover the liner 225 and fill the first trench 212A and the second trench 212B. Then, another etch-back process is performed to remove a portion of the conductive material in the first trench 212A and the second trench 212B, exposing the upper portions of the first trench 212A and the second trench 212B and a portion of the gate dielectric layer 214 to form work function adjustment structures 226A and 226B. After the above processes, a first word line 230A is formed in the substrate 200 within the dummy word line region 402, and a second word line 230B is formed in the substrate 200 within the array region 400. The first word line 230A and the second word line 230B extend across the active region 208 and the isolation member 209. The top surface 220AT of the first conductive structure 220A of the first word line 230A is below the top surfaces 220B-1T and 220B-2T of the second conductive structure 220B.
[0088] Next, as shown in Figure 3 , a deposition process and a subsequent planarization process are performed to form a capping layer 242 on the first trench 212A and the second trench 212B and fill the upper portions of the first trench 212A and the second trench 212B. The top surface of the capping layer 242 is flush with the top surface 201 of the substrate 200.
[0089] Next, as shown in Figure 3 , a deposition process is performed to form a capping layer 244 and an interlayer dielectric layer 246 over the substrate 200. Thereafter, a patterning process, a deposition process, and a removal process are performed to form contact plugs 248a and 248b in the openings (not shown) of the capping layer 244 and the interlayer dielectric layer 246.
[0090] Next, as shown in Figure 3 , a deposition process and subsequent removal processes (including planarization processes (e.g., chemical mechanical polishing (CMP)), etch-back processes, or a combination of the above) are performed to form bit lines 250, storage capacitors 260, and conductive lines 268. After the above processes, a semiconductor structure 500 is formed. In addition, additional components, such as peripheral circuits or other suitable components, may be formed on the semiconductor structure 500 to fabricate a semiconductor memory device.
[0091] Embodiments of the present invention provide a semiconductor structure and a method for forming the same. In some embodiments, the dummy word line region of the semiconductor structure has a relatively high well doping concentration, and the first conductive structure in the dummy word line region is discontinuously arranged along the word line extending direction to increase the work function of the first word line, thereby increasing the threshold voltage (VT) of the first word line. During normal operation, the first word lines are all in the off state and are not easily turned on due to process variations or noise, so as to avoid forming a leakage path between adjacent bit lines due to the wires in the dummy word line region connecting different storage capacitors arranged along the channel extending direction, thereby affecting the performance of the dynamic random access memory in the array region.
[0092] Although the present invention has been disclosed above with the foregoing embodiments, it is not intended to limit the present invention. Those skilled in the art in the technical field to which the present invention pertains can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the claims.
Claims
1. A semiconductor structure, characterized in that, Comprising: A substrate having an array region and a dummy word line region adjacent to the array region; An isolation component disposed in the substrate of the array region and the dummy word line region for defining an active region of the substrate; A first word line buried in the substrate within the dummy word line region and extending across the active region and the isolation component, wherein the first word line includes a plurality of first conductive structures; And A second word line buried in the substrate within the array region and extending across the active region and the isolation component, wherein the second word line includes a second conductive structure, and a first top surface of each of the first conductive structures is below a second top surface of the second conductive structure.
2. The semiconductor structure according to claim 1, characterized in that, The plurality of first conductive structures are discontinuously arranged along the word line extending direction.
3. The semiconductor structure according to claim 1, wherein The first word line is formed in a first trench of the substrate within the dummy word line region, wherein the plurality of first conductive structures are disposed in the first trench in the isolation component, and the plurality of first conductive structures are not present in the first trench in the active region.
4. The semiconductor structure according to claim 3, wherein, The first word line further includes: A gate dielectric layer conformally covering the first trench, wherein the plurality of first conductive structures are disposed on the gate dielectric layer, and the gate dielectric layer on a bottom surface of the first trench in the active region is not covered by the plurality of first conductive structures; and A work function adjustment structure disposed on the first conductive structure, Wherein each of the first conductive structures includes: A liner conformally covering the gate dielectric layer; and A gate electrode layer disposed on the liner and partially filling the first trench, Wherein the first top surface of each of the first conductive structures aligns with an upper surface of the gate dielectric layer on the bottom surface of the first trench in the active region, and the work function adjustment structure contacts the upper surface of the gate dielectric layer on the bottom surface of the first trench in the active region.
5. The semiconductor structure according to claim 3, wherein Further comprising: A first well region in the substrate within the dummy word line region, wherein the first well region has a first doping concentration; and A second well region in the substrate within the array region, wherein the second well region has a second doping concentration, the first well region and the second well region have the same conduction type, the first doping concentration is greater than the second doping concentration, and the first word line is disposed in the first well region.
6. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate, wherein the substrate has an array region and a dummy word line region adjacent to the array region; Forming an isolation component in the substrate to define an active region; Forming a first word line in the substrate within the dummy word line region, the first word line extending across the active region and the isolation component, wherein the first word line includes a plurality of first conductive structures; and Forming a second word line in the substrate within the array region, the second word line extending across the active region and the isolation component, wherein the second word line includes a second conductive structure, and a first top surface of each of the first conductive structures is below a second top surface of the second conductive structure.
7. The method for forming a semiconductor structure as described in claim 6, wherein, Further comprising: Before forming the first word line and the second word line, implanting a first dopant in the substrate within the dummy word line region and the array region; A second dopant having the same conductivity type as the first dopant is implanted into the substrate in the dummy word line region to form a first well region in the substrate in the dummy word line region and a second well region in the substrate in the array region; A first trench is formed in the first well region in the dummy word line region, and a second trench is formed in the second well region in the array region; A gate dielectric layer and a first liner covering the gate dielectric layer are conformally formed in the first trench and the second trench, respectively; A gate electrode layer covering the first liner is formed in the first trench and the second trench, respectively, and the first trench and the second trench are filled; and A re-etching process is performed to remove a part of the first liner and a part of the gate electrode layer in the first trench and the second trench to form the second conductive structure.
8. The method for forming a semiconductor structure according to claim 7, wherein, Further comprising: After forming the second conductive structure, a patterned mask is covered on the second trench to expose the first trench; And Removing a part of the first liner and a part of the gate electrode layer in the first trench to form the plurality of first conductive structures, wherein removing a part of the first liner and a part of the gate electrode layer in the first trench includes completely removing the first liner and the gate electrode layer in the first trench in the active region until the gate dielectric layer on a bottom surface of the first trench in the active region is exposed.
9. The method for forming a semiconductor structure according to claim 7, wherein Forming the first word line and the second word line further comprises: A second liner is formed in the first trench and the second trench, respectively, and covers the first conductive structure and the second conductive structure; and A work function adjustment structure is formed in the first trench and the second trench, respectively, covers the second liner and fills the first trench and the second trench.
10. The method for forming a semiconductor structure according to claim 7, wherein, Further comprising: A capping layer is formed on the first word line and the second word line, and the first trench and the second trench are filled; A plurality of bit lines are formed on the substrate, and the plurality of bit lines are electrically connected to a plurality of drain doping regions of the active region; A plurality of storage capacitors are formed on the substrate, and the plurality of storage capacitors are electrically connected to a plurality of source doping regions of the active region; And A plurality of wires are formed on the plurality of storage capacitors, wherein the plurality of storage capacitors arranged along a channel extending direction in the dummy word line region are connected to the same one of the plurality of wires, and the plurality of storage capacitors arranged along the channel extending direction in the array region are connected to different ones of the plurality of wires.