Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The gate stack is located on the substrate, and the gate stack comprises a first gate layer and a second gate layer located on the first gate layer; the channel lamination layer penetrates through the gate lamination layer and is located on the substrate, and the channel lamination layer comprises a first channel layer and a second channel layer located on the first channel layer; the functional laminated layer covers the side wall of the channel laminated layer, the functional laminated layer comprises a first functional layer located between the first channel layer and the first gate layer, and a second functional layer located on the first functional layer and located between the second channel layer and the second gate layer, any one of the first functional layer and the second functional layer is a storage material layer, and the other one is a gate oxide layer. The reliability of the semiconductor structure can be improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] In the current semiconductor industry, integrated circuit products can be mainly divided into three major types: analog circuits, digital circuits, and digital / analog hybrid circuits. Among them, memory devices are an important type in digital circuits. In recent years, in memory devices, the development of flash memory has been particularly rapid. The main characteristics of flash memory are that it can retain the stored information for a long time without power supply; and it has advantages such as high integration, fast access speed, easy erasure and rewriting, etc., so it has been widely used in many fields such as microcomputers and automatic control. Summary of the Invention

[0003] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to improving the reliability of the semiconductor structure.

[0004] To solve the above problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate; a gate stack located on the substrate, the gate stack including a first gate layer and a second gate layer located on the first gate layer; a channel stack penetrating the gate stack and located on the substrate, the channel stack including a first channel layer and a second channel layer located on the first channel layer; a functional stack covering the sidewalls of the channel stack, the functional stack including a first functional layer located between the first channel layer and the first gate layer and a second functional layer located on the first functional layer and between the second channel layer and the second gate layer, wherein any one of the first functional layer and the second functional layer is a storage material layer and the other is a gate oxide layer.

[0005] Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate; forming a gate stack on the substrate, the gate stack including a first gate layer and a second gate layer located on the first gate layer; forming a through hole penetrating the gate stack; forming a channel stack and a functional stack covering the sidewalls of the channel stack in the through hole, the channel stack including a first channel layer and a second channel layer located on the first channel layer, the functional stack including a first functional layer located between the first channel layer and the first gate layer and a second functional layer located on the first functional layer and between the second channel layer and the second gate layer, wherein any one of the first functional layer and the second functional layer is a storage material layer and the other is a gate oxide layer.

[0006] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0007] In the semiconductor structure provided by the embodiment of the present invention, a gate stack is located on a substrate. The gate stack includes a first gate layer and a second gate layer located on the first gate layer. A channel stack penetrates the gate stack and is located on the substrate. The channel stack includes a first channel layer and a second channel layer located on the first channel layer. A functional stack covers the sidewalls of the channel stack. The functional stack includes a first functional layer located between the first channel layer and the first gate layer, and a second functional layer located on the first functional layer and between the second channel layer and the second gate layer. Wherein, either the first functional layer or the second functional layer is a storage material layer, and the other is a gate oxide layer. In the embodiment of the present invention, the first gate layer and the second gate layer are stacked longitudinally, the first channel layer and the second channel layer are stacked longitudinally. The gate stack corresponding to the storage material layer constitutes a storage gate, and the gate stack corresponding to the gate oxide layer constitutes a selection gate, forming a vertical structure memory, which is beneficial to reducing the area of the storage unit, and thus beneficial to increasing the storage density. Moreover, since the channel stack penetrates the gate stack, both the first gate layer and the second gate layer constitute a gate-all-around structure surrounding the channel, which is beneficial to improving the control ability of the gate over the channel, and can also realize a channel stack with a shorter channel length, which is beneficial to increasing the channel current density and improving the electrical performance. At the same time, it is also beneficial to increase the contact area between the channel and the gate, reduce the probability of gate and channel leakage, and thus improve the reliability of the semiconductor structure.

[0008] In the forming method provided by the embodiment of the present invention, a gate stack is formed on a substrate. The gate stack includes a first gate layer and a second gate layer located on the first gate layer. A through hole penetrating the gate stack is formed, and a channel stack and a functional stack covering the sidewalls of the channel stack are formed in the through hole. The channel stack includes a first channel layer and a second channel layer located on the first channel layer. The functional stack includes a first functional layer located between the first channel layer and the first gate layer, and a second functional layer located on the first functional layer and between the second channel layer and the second gate layer. Wherein, either the first functional layer or the second functional layer is a storage material layer, and the other is a gate oxide layer. In the embodiment of the present invention, the first gate layer and the second gate layer are stacked longitudinally, the first channel layer and the second channel layer are stacked longitudinally. The gate stack corresponding to the storage material layer constitutes a storage gate, and the gate stack corresponding to the gate oxide layer constitutes a selection gate, forming a vertical structure memory, which is beneficial to reducing the area of the storage unit, and thus beneficial to increasing the storage density. Moreover, since the channel stack penetrates the gate stack, both the first gate layer and the second gate layer constitute a gate-all-around structure surrounding the channel, which is beneficial to improving the control ability of the gate over the channel, and can also realize a channel stack with a shorter channel length, which is beneficial to increasing the channel current density and improving the electrical performance. At the same time, it is also beneficial to increase the contact area between the channel and the gate, reduce the probability of gate and channel leakage, and thus improve the reliability of the semiconductor structure. Description of the Drawings

[0009] Figures 1 to 3 is a schematic structural diagram corresponding to an embodiment of the semiconductor structure of the present invention;

[0010] Figures 4 to 29 is a schematic structural diagram corresponding to each step in an embodiment of the method for forming the semiconductor structure of the present invention. Detailed Description of the Invention

[0011] As known from the background art, in order to increase the device density of the current flash memory with a split gate structure, it is necessary to further reduce the device size, which will lead to the short channel effect. Moreover, the reduction of the thickness of the gate oxide layer will also cause charge leakage due to the tunneling effect, thereby reducing the device performance.

[0012] To solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate; a gate stack located on the substrate, the gate stack including a first gate layer and a second gate layer located on the first gate layer; a channel stack penetrating the gate stack and located on the substrate, the channel stack including a first channel layer and a second channel layer located on the first channel layer; a functional stack covering the sidewalls of the channel stack, the functional stack including a first functional layer located between the first channel layer and the first gate layer and a second functional layer located on the first functional layer and between the second channel layer and the second gate layer, wherein any one of the first functional layer and the second functional layer is a storage material layer and the other is a gate oxide layer.

[0013] In an embodiment of the present invention, the first gate layer and the second gate layer are longitudinally stacked, the first channel layer and the second channel layer are longitudinally stacked, the gate stack corresponding to the storage material layer constitutes a storage gate, and the gate stack corresponding to the gate oxide layer constitutes a select gate, forming a vertical structure memory, which is beneficial to reducing the storage unit area, thereby increasing the storage density. Moreover, since the channel stack penetrates the gate stack, both the first gate layer and the second gate layer constitute a surrounding gate structure surrounding the channel, which is beneficial to improving the gate's control ability over the channel, and can also realize a channel stack with a shorter channel length, which is beneficial to increasing the channel current density, improving the electrical performance, and at the same time is beneficial to increasing the contact area between the channel and the gate, reducing the probability of gate and channel leakage, thereby improving the reliability of the semiconductor structure.

[0014] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be made with reference to the accompanying drawings.

[0015] Figures 1 to 3 is a schematic structural diagram corresponding to an embodiment of the semiconductor structure of the present invention.

[0016] With reference to Figures 1 to 3 , Figure 1 is a top view, Figure 2 is Figure 1Cross-sectional view along the AA direction Figure 3 is Figure 1 Cross-sectional view along the BB direction. The semiconductor structure includes: a substrate 100; a gate stack 200 located on the substrate 100, the gate stack 200 including a first gate layer 210 and a second gate layer 220 located on the first gate layer 210; a channel stack 400 penetrating the gate stack 200 and located on the substrate 100, the channel stack 400 including a first channel layer 410 and a second channel layer 420 located on the first channel layer 410; a functional stack 300 covering the sidewalls of the channel stack 400, the functional stack 300 including a first functional layer 310 located between the first channel layer 410 and the first gate layer 210 and a second functional layer 320 located on the first functional layer 310 and between the second channel layer 420 and the second gate layer 220. Among them, any one of the first functional layer 310 and the second functional layer 320 is a storage material layer, and the other is a gate oxide layer.

[0017] The substrate 100 is used to provide a process operation platform for the formation process of the semiconductor structure.

[0018] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate can also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium. The substrate can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate can be a material suitable for process requirements or easy to integrate.

[0019] In this embodiment, the semiconductor structure constitutes a split gate Flash memory. The substrate 100 includes a storage array area and a peripheral device area (CMOS area). The drawings only show the structure of the storage array area.

[0020] The storage array area is used to form storage core devices, and the peripheral device area is used to form circuits for controlling and managing storage operations.

[0021] In this embodiment, the substrate 100 includes a storage cell area 100a extending along a first direction (such as Figure 1 shown by the X direction in Figure 1 and arranged in parallel along a second direction (such as

[0022] shown by the Y direction in).

[0023] The gate stack 200 is used to form the word line (WL) of the memory. Specifically, in the first gate layer 210 and the second gate layer 220, either one serves as the memory gate for storing charges to achieve data storage, and the other serves as the selected gate for controlling the current path of the memory cell and selecting the corresponding memory cell to participate in read and write operations. Among the first gate layer 210 and the second gate layer 220, the one covering the storage material layer is the memory gate, and the one covering the gate oxide layer is the selected gate.

[0024] In this embodiment, the gate stacks 200 of adjacent memory cell regions 100a are spaced apart in the second direction.

[0025] The gate stacks 200 of adjacent memory cell regions 100a are spaced apart in the second direction to enable independent storage operations between adjacent memory cell regions 100a.

[0026] In this embodiment, the material of the first gate layer 210 includes polysilicon, and the material of the second gate layer 220 includes polysilicon.

[0027] In this embodiment, the gate stack 200 further includes: a first isolation layer 230 located between the first gate layer 210 and the second gate layer 220, and a second isolation layer 240 located on the second gate layer 220.

[0028] The first isolation layer 230 is used to isolate the first gate layer 210 and the second gate layer 220, and the second isolation layer 240 is used to protect the second gate layer 220 and isolate the second gate layer 220 from other film layers.

[0029] In this embodiment, the material of the first isolation layer 230 includes silicon oxide, and the material of the second isolation layer 240 includes silicon oxide.

[0030] The channel stack 400 is used to form the bit line (BL) of the memory. Among them, the first channel layer 410 is used to provide a channel for the first gate layer 210, and the second channel layer 420 is used to provide a channel for the second gate layer 220.

[0031] In this embodiment, in the semiconductor manufacturing process, the first channel layer 410 and the second channel layer 420 are formed step by step. Therefore, in this embodiment, there is an interface between the first channel layer 410 and the second channel layer 420.

[0032] In other embodiments, in the semiconductor manufacturing process, an integrated channel stack can also be formed in one step. Therefore, in other embodiments, the first channel layer and the second channel layer can also be an integral structure.

[0033] In this embodiment, the top surface of the first channel layer 410 is higher than the top surface of the first gate layer 210 and lower than the bottom surface of the second gate layer 220, which is beneficial to ensuring that the first gate layer 210 completely surrounds the first channel layer 410. Moreover, the first functional layer 310 is located between the first channel layer 410 and the first gate layer 210. Thus, the top surface of the first channel layer 410 is higher than the top surface of the first gate layer 210 and lower than the bottom surface of the second gate layer 220, making the top surface of the first functional layer 310 higher than the top surface of the first gate layer 210 and lower than the bottom surface of the second gate layer 220, which is beneficial to ensuring that the first gate layer 210 realizes the function based on the first functional layer 310 and preventing the first gate layer 210 from being affected by the second functional layer 320 and thus affecting the memory performance.

[0034] In this embodiment, the top surface of the second channel layer 420 is higher than the top surface of the second gate layer 220, which is beneficial to ensuring that the second gate layer 220 completely surrounds the second channel layer 420. Moreover, the second functional layer 320 is located between the second channel layer 420 and the second gate layer 220. Thus, the top surface of the second channel layer 420 is higher than the top surface of the second gate layer 220, making the top surface of the second functional layer 320 higher than the top surface of the second gate layer 220, which is beneficial to ensuring that the second gate layer 220 realizes the function based on the second functional layer 320 and preventing the second gate layer 220 from being affected by the first functional layer 310 and thus affecting the memory performance.

[0035] In this embodiment, in the memory cell region 100a, multiple channel stacks 400 are arranged in the gate stack 200 along the first direction.

[0036] In the memory cell region 100a, multiple channel stacks 400 are arranged in the gate stack 200 along the first direction, making the arrangement of the channel stacks 400 relatively compact, which is beneficial to improving the density of the channel stacks 400, increasing the area utilization rate, and thus increasing the storage density.

[0037] In this embodiment, the material of the channel stack 400 is silicon.

[0038] Specifically, in this embodiment, the material of the first channel layer 410 is single-crystalline silicon, and the material of the second channel layer 420 is polycrystalline silicon. The first channel layer 410 is in contact with the substrate 100, so the first channel layer 410 can be obtained by epitaxial growth process, thus enabling the formation of single-crystalline silicon with better quality. The second channel layer 420 is located above the first channel layer 410 and is more easily obtained by deposition process with lower process cost, so the second channel layer 420 is more easily formed into polycrystalline silicon.

[0039] The functional stack 300 is used to provide corresponding functions for the gate stack 200. Specifically, the first functional layer 310 is used to provide corresponding functions for the first gate layer 210, and the second functional layer 320 is used to provide corresponding functions for the second gate layer 220. Among them, in the first functional layer 310 and the second functional layer 320, one of the layers serving as the storage material layer provides a data storage function, and the other layer serving as the gate oxide layer provides an isolation function.

[0040] In this embodiment, either the first functional layer 310 or the second functional layer 320 serves as the storage material layer, and the other serves as the gate oxide layer. That is, the first functional layer 310 can be the storage material layer and the second functional layer 320 can be the gate oxide layer. Correspondingly, the first gate layer 210 is the storage gate and the second gate layer 220 is the select gate. Or the first functional layer 310 can be the gate oxide layer and the second functional layer 320 can be the storage material layer. Correspondingly, the first gate layer 210 is the select gate and the second gate layer 220 is the storage gate.

[0041] As an example, in this embodiment, if the material of the first channel layer 410 is easily obtained as single-crystalline silicon and the material of the second channel layer 420 is easily obtained as polycrystalline silicon, then the first functional layer 310 is the storage material layer to form a storage unit with better quality, and the second functional layer 320 is the gate oxide layer to form a select unit with lower cost.

[0042] Reference Figure 2 , Figure 2 shows a partial enlarged view of the first functional layer 310 of the storage material layer at the dashed box. The first functional layer 310 of the storage material layer includes a charge tunneling layer 331, a charge blocking layer 333, and a charge trapping layer 332 located between the charge tunneling layer 331 and the charge blocking layer 333. Among them, the materials of the charge tunneling layer 331 and the charge blocking layer 333 are silicon oxide, and the material of the charge trapping layer 332 is silicon nitride, forming an Oxide-Nitride-Oxide (ONO) structure, thereby forming a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory.

[0043] In this embodiment, the material of the gate oxide layer includes silicon oxide.

[0044] In this embodiment, the semiconductor structure further includes: a source / drain doping layer 110 in the substrate 100 at the bottom of the channel stack 400.

[0045] The source / drain doping layer 110 is used to provide a source region or a drain region.

[0046] As an example, in this embodiment, the source-drain doping layer 110 is used to provide a source region, and the top of the channel stack 400 is used to electrically connect to the drain region.

[0047] In this embodiment, the semiconductor structure further includes: a dielectric layer 500 covering the gate stack 200, the channel stack 400, and the functional stack 300.

[0048] The dielectric layer 500 is used to provide a process operation platform for the interconnect process.

[0049] In this embodiment, the material of the dielectric layer 500 includes silicon oxide.

[0050] In this embodiment, the semiconductor structure further includes: a first source-drain plug 710 that penetrates the side of the channel stack 400, contacts the substrate 100, and is electrically connected to the substrate 100.

[0051] The first source-drain plug 710 is used to realize the electrical connection between the source region of the substrate 100 and the outside.

[0052] Correspondingly, in this embodiment, the first source-drain plug 710 also penetrates the dielectric layer 500 to expose the first source-drain plug 710 for subsequent interconnect preparation.

[0053] In this embodiment, the material of the first source-drain plug 710 includes tungsten.

[0054] In this embodiment, the semiconductor structure further includes: a second source-drain plug 720 located on the second channel layer 420 and electrically connected to the second channel layer 420.

[0055] The second source-drain plug 720 is used to realize the electrical connection between the channel stack 400 and the drain region.

[0056] Correspondingly, in this embodiment, the second source-drain plug 720 also penetrates the dielectric layer 500 to expose the second source-drain plug 720 for subsequent interconnect preparation.

[0057] In this embodiment, the material of the second source-drain plug 720 includes tungsten.

[0058] In this embodiment, the semiconductor structure further includes: a first gate plug 730 that penetrates the second gate layer 220, contacts the first gate layer 210, and is electrically connected to the first gate layer 210.

[0059] The first gate plug 730 is used to realize the electrical connection between the first gate layer 210 and the outside.

[0060] Correspondingly, in this embodiment, the first gate plug 730 also penetrates the first isolation layer 230, the second isolation layer 240, and the dielectric layer 500 to expose the first gate plug 730 for subsequent interconnect preparation.

[0061] In this embodiment, the material of the first gate plug 730 includes tungsten.

[0062] In this embodiment, the semiconductor structure further includes: a second gate plug 740, located on the second gate layer 220 and electrically connected to the second gate layer 220.

[0063] The second gate plug 740 is used to achieve the electrical connection between the second gate layer 220 and the outside.

[0064] Correspondingly, in this embodiment, the second gate plug 740 also penetrates through the second isolation layer 240 and the dielectric layer 500 to expose the second gate plug 740, preparing for subsequent interconnection.

[0065] In this embodiment, the material of the second gate plug 740 includes tungsten.

[0066] In this embodiment, in the storage unit region 100a, the first source / drain plug 710, the second source / drain plug 720, the first gate plug 730, and the second gate plug 740 are arranged along the first direction, and the first source / drain plug 710, the first gate plug 730, and the second gate plug 740 are arranged on the side of the channel stack 400 along the first direction, so that the arrangement of the first source / drain plug 710, the second source / drain plug 720, the first gate plug 730, and the second gate plug 740 is relatively compact, improving the device density.

[0067] In this embodiment, the semiconductor structure further includes: a spacer 510, extending along the first direction and arranged in parallel along the second direction at the junction of adjacent storage unit regions 100a, and the spacer 510 isolates the gate stack 200 in the second direction.

[0068] The spacer 510 is used to isolate adjacent storage unit regions 100a.

[0069] In this embodiment, the material of the spacer 510 includes silicon oxide.

[0070] Figures 4 to 29 It is a schematic structural diagram corresponding to each step in an embodiment of the method for forming the semiconductor structure of the present invention.

[0071] Refer to Figure 4 , and provide a substrate 100.

[0072] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate can also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium arsenide. The substrate can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate can be a material suitable for process requirements or easy to integrate.

[0073] In this embodiment, the semiconductor structure constitutes a split gate Flash memory. The substrate 100 includes a storage array area and a peripheral device area (CMOS area). The drawings only show the structure of the storage array area.

[0074] The storage array area is used to form storage core devices, and the peripheral device area is used to form circuits for controlling and managing storage operations.

[0075] In this embodiment, in the step of providing the substrate 100, the substrate 100 includes a storage cell area 100a that extends along a first direction (such as the X direction shown) and is arranged in parallel along a second direction (such as the Y direction shown). Figure 4 In the (such as the X direction shown), and is arranged in parallel along a second direction (such as the Y direction shown). Figure 4 The storage cell areas 100a share a gate stack, and adjacent storage cell areas 100a are isolated from each other.

[0076] The storage cell areas 100a share a gate stack, and adjacent storage cell areas 100a are isolated from each other.

[0077] Continuing to refer to Figure 4 , a gate stack 200 is formed on the substrate 100. The gate stack 200 includes a first gate layer 210 and a second gate layer 220 located on the first gate layer 210.

[0078] The gate stack 200 is used to form the word line (WL) of the memory. Specifically, in the first gate layer 210 and the second gate layer 220, any one serves as a memory gate for storing charges to achieve data storage, and the other serves as a selected gate for controlling the current path of the storage cell and selecting the corresponding storage cell to participate in read and write operations. Among the first gate layer 210 and the second gate layer 220, the one covering the storage material layer is the memory gate, and the one covering the gate oxide layer is the selected gate.

[0079] In this embodiment, in the step of forming the gate stack 200 on the substrate 100, the material of the first gate layer 210 includes polysilicon, and the material of the second gate layer 220 includes polysilicon.

[0080] In this embodiment, in the step of forming the gate stack 200 on the substrate 100, the gate stack 200 further includes a first isolation layer 230 located between the first gate layer 210 and the second gate layer 220, and a second isolation layer 240 located on the second gate layer 220.

[0081] The first isolation layer 230 is used to isolate the first gate layer 210 and the second gate layer 220, and the second isolation layer 240 is used to protect the second gate layer 220 and isolate the second gate layer 220 from other film layers.

[0082] In this embodiment, in the step of forming the gate stack 200 on the substrate 100, the material of the first isolation layer 230 includes silicon oxide, and the material of the second isolation layer 240 includes silicon oxide.

[0083] With reference to Figure 5 and Figure 6 , Figure 6 as Figure 5 a cross-sectional view along the AA direction, a via 250 is formed through the gate stack 200.

[0084] The via 250 is used to provide a spatial position for the subsequent formation of the channel stack.

[0085] In this embodiment, in the step of forming the via 250 through the gate stack 200, in the memory cell region 100a, a plurality of vias 250 are arranged in the gate stack 200 along a first direction.

[0086] The plurality of vias 250 are arranged in the gate stack 200 along the first direction, that is, the subsequent formed channel stack is arranged in the gate stack 200 along the first direction, so that the channel stack is arranged more closely, which is beneficial to improving the density of the channel stack, improving the area utilization rate, and thus increasing the storage density.

[0087] With reference to Figures 7 to 14 , a channel stack 400 and a functional stack 300 covering the sidewalls of the channel stack 400 are formed in the via 250. The channel stack 400 includes a first channel layer 410 and a second channel layer 420 located on the first channel layer 410. The functional stack 300 includes a first functional layer 310 located between the first channel layer 410 and the first gate layer 210, and a second functional layer 320 located on the first functional layer 310 and between the second channel layer 420 and the second gate layer 220. Among them, either the first functional layer 310 or the second functional layer 320 is a storage material layer, and the other is a gate oxide layer.

[0088] The channel stack 400 is used to form the bitline (BL) of the memory. Among them, the first channel layer 410 is used to provide a channel for the first gate layer 210, and the second channel layer 420 is used to provide a channel for the second gate layer 220.

[0089] In this embodiment, in the semiconductor manufacturing process, the first channel layer 410 and the second channel layer 420 are formed step by step. For this reason, in this embodiment, there is an interface between the first channel layer 410 and the second channel layer 420.

[0090] In other embodiments, in the semiconductor manufacturing process, an integrated channel stack may also be formed in one step. Therefore, in other embodiments, the first channel layer and the second channel layer may also be an integral structure.

[0091] In this embodiment, in the step of forming the channel stack 400 in the through hole 250 and the functional stack 300 covering the side walls of the channel stack 400, the top surface of the first channel layer 410 is higher than the top surface of the first gate layer 210 and lower than the bottom surface of the second gate layer 220, which is beneficial to ensuring that the first gate layer 210 completely surrounds the first channel layer 410. Moreover, the first functional layer 310 is located between the first channel layer 410 and the first gate layer 210. Thus, the top surface of the first channel layer 410 is higher than the top surface of the first gate layer 210 and lower than the bottom surface of the second gate layer 220, making the top surface of the first functional layer 310 higher than the top surface of the first gate layer 210 and lower than the bottom surface of the second gate layer 220, which is beneficial to ensuring that the first gate layer 210 realizes the function based on the first functional layer 310 and preventing the first gate layer 210 from being affected by the second functional layer 320 and thus affecting the memory performance.

[0092] In this embodiment, in the step of forming the channel stack 400 in the through hole 250 and the functional stack 300 covering the side walls of the channel stack 400, the top surface of the second channel layer 420 is higher than the top surface of the second gate layer 220, which is beneficial to ensuring that the second gate layer 220 completely surrounds the second channel layer 420. Moreover, the second functional layer 320 is located between the second channel layer 420 and the second gate layer 220. Thus, the top surface of the second channel layer 420 is higher than the top surface of the second gate layer 220, making the top surface of the second functional layer 320 higher than the top surface of the second gate layer 220, which is beneficial to ensuring that the second gate layer 220 realizes the function based on the second functional layer 320 and preventing the second gate layer 220 from being affected by the first functional layer 310 and thus affecting the memory performance.

[0093] Correspondingly, in this embodiment, in the step of forming the channel stack 400 in the through hole 250 and the functional stack 300 covering the side walls of the channel stack 400, in the memory cell region 100a, a plurality of channel stacks 400 are arranged in the gate stack 200 along the first direction.

[0094] In this embodiment, in the step of forming the channel stack 400 in the through hole 250 and the functional stack 300 covering the side walls of the channel stack 400, the material of the channel stack 400 is silicon.

[0095] Specifically, in this embodiment, the material of the first channel layer 410 is single crystal silicon, and the material of the second channel layer 420 is polycrystalline silicon. The first channel layer 410 is in contact with the substrate 100, so the first channel layer 410 can be obtained by epitaxial growth process, thus enabling the formation of single crystal silicon with better quality. The second channel layer 420 is located above the first channel layer 410 and is more easily obtained by deposition process, with lower process cost. Therefore, the second channel layer 420 is more easily formed into polycrystalline silicon.

[0096] The functional stack 300 is used to provide corresponding functions for the gate stack 200. Specifically, the first functional layer 310 is used to provide corresponding functions for the first gate layer 210, and the second functional layer 320 is used to provide corresponding functions for the second gate layer 220. Among them, in the first functional layer 310 and the second functional layer 320, one of the storage material layers provides a data storage function, and the other of the gate oxide layers provides an isolation function.

[0097] In this embodiment, either the first functional layer 310 or the second functional layer 320 is a storage material layer, and the other is a gate oxide layer. That is, the first functional layer 310 can be a storage material layer and the second functional layer 320 can be a gate oxide layer. Correspondingly, the first gate layer 210 is a storage gate and the second gate layer 220 is a select gate. Or the first functional layer 310 can be a gate oxide layer and the second functional layer 320 can be a storage material layer. Correspondingly, the first gate layer 210 is a select gate and the second gate layer 220 is a storage gate.

[0098] As an example, in this embodiment, the material of the first channel layer 410 is easy to obtain single-crystalline silicon, and the material of the second channel layer 420 is easy to obtain polycrystalline silicon. Then the first functional layer 310 is a storage material layer, forming a storage unit with better quality, and the second functional layer 320 is a gate oxide layer, forming a select unit with lower cost.

[0099] Reference Figure 14 , Figure 14 shows a partial enlarged view of the first functional layer 310 of the storage material layer at the dashed box. The first functional layer 310 of the storage material layer includes a charge tunneling layer 331, a charge blocking layer 333, and a charge trapping layer 332 located between the charge tunneling layer 331 and the charge blocking layer 333. Among them, the materials of the charge tunneling layer 331 and the charge blocking layer 333 are silicon oxide, and the material of the charge trapping layer 332 is silicon nitride, forming an Oxide-Nitride-Oxide (ONO) structure, thereby forming a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory.

[0100] In this embodiment, the material of the gate oxide layer includes silicon oxide.

[0101] Combined with reference Figures 7 to 11 , the steps of forming the channel stack 400 in the through hole 250 and the functional stack 300 covering the side walls of the channel stack 400 include: forming the first channel layer 410 in the through hole 250 and the first functional layer 310 covering the side walls of the first channel layer 410.

[0102] Specifically, referring to Figure 7, in the through hole 250, the steps of forming the first channel layer 410 and the first functional layer 310 covering the sidewalls of the first channel layer 410 include: forming a first functional material layer 330 covering the sidewalls of the through hole 250.

[0103] The first functional material layer 330 is used to form the first functional layer 310.

[0104] As an example, in this embodiment, the first functional material layer 330 is a storage material layer. Specifically, as Figure 7 shown in the partial enlarged view of the dashed box of the first functional material layer 330 in

[0105] In this embodiment, in the step of forming the first functional material layer 330 covering the sidewalls of the through hole 250, the first functional material layer 330 also covers the bottom surface of the through hole 250 and the top surface of the gate stack 200.

[0106] In this embodiment, the atomic layer deposition process is used to form the first functional material layer 330 covering the sidewalls of the through hole 250.

[0107] The first functional material layer 330 formed by the atomic layer deposition process has good thickness uniformity and good step coverage ability, so that the first functional material layer 330 can conformally cover the bottom and sidewalls of the through hole 250 and the top surface of the gate stack 200 well.

[0108] Refer to Figure 8 , before forming the first channel material layer in the remaining through hole 250 surrounded by the first functional material layer 330 subsequently, it further includes: removing the first functional material layer 330 on the bottom surface of the through hole 250 and the top surface of the gate stack 200 to expose the surface of the substrate 100.

[0109] Removing the first functional material layer 330 on the bottom surface of the through hole 250 and the top surface of the gate stack 200 to expose the surface of the substrate 100 is to prepare for the subsequent formation of the channel stack 400 and also for the formation of the source / drain doping layer.

[0110] Refer to Figure 9 , before forming the first channel material layer in the remaining through hole 250 surrounded by the first functional material layer 330 subsequently, it further includes: forming a source / drain doping layer 110 in the substrate 100 at the bottom of the through hole 250.

[0111] The source / drain doping layer 110 is used to provide a source region or a drain region.

[0112] As an example, in this embodiment, the source-drain doping layer 110 is used to provide a source region, and the top of the subsequent channel stack is used for electrical connection to the drain region.

[0113] Reference Figure 10 , a first channel material layer 430 is formed in the remaining vias 250 surrounded by the first functional material layer 330.

[0114] The first channel material layer 430 is used to form the first channel layer 410.

[0115] In this embodiment, the first channel material layer 430 is formed in the remaining vias 250 surrounded by the first functional material layer 330 by using an epitaxial growth process.

[0116] The epitaxial growth process can better control process parameters, has high process controllability, is easy to obtain a more accurate film thickness dimension, and the epitaxial growth process is easy to form a film layer with fewer impurities, so that the quality of the first channel material layer 430 is high, and the epitaxial growth process can form a single-crystal first channel material layer 430.

[0117] Reference Figure 11 , a part of the first functional material layer 330 and the first channel material layer 430 with a certain height is removed, and the remaining first functional material layer 330 and the first channel material layer 430 covering the sidewalls of the first gate layer 210 are respectively used as the first functional layer 310 and the first channel layer 410.

[0118] Correspondingly, in this embodiment, in the step of removing a part of the first functional material layer 330 and the first channel material layer 430 with a certain height, the top surface of the remaining first channel material layer 430 is higher than the top surface of the first gate layer 210 and lower than the bottom surface of the second gate layer 220, the top surface of the remaining first functional material layer 330 is higher than the top surface of the first gate layer 210 and lower than the bottom surface of the second gate layer 220, and the first channel material layer 430 and the first functional material layer 330 are flush, providing a better process platform for subsequent process manufacturing.

[0119] In this embodiment, a dry etching process is used to remove a part of the first functional material layer 330 and the first channel material layer 430 with a certain height.

[0120] The parameters of the dry etching process are easy to control, and it is easy to obtain the first functional layer 310 and the first channel layer 410 with relatively accurate dimensions by using the dry etching process.

[0121] Combined with reference Figures 12 to 14 , a second channel layer 420 and a second functional layer 320 covering the sidewalls of the second channel layer 420 are formed on the first channel layer 410.

[0122] Specifically, combined with reference Figure 12 and Figure 13, the steps of forming the second channel layer 420 on the first channel layer 410 and the second functional layer 320 covering the sidewalls of the second channel layer 420 include: forming the second functional layer 320 covering the sidewalls of the through holes 250 exposed on the first channel layer 410.

[0123] As an example, in this embodiment, the second functional layer 320 is a gate oxide layer.

[0124] Reference Figure 12 , the steps of forming the second functional layer 320 covering the sidewalls of the through holes 250 exposed on the first channel layer 410 include: forming a second functional material layer 340 covering the sidewalls of the through holes 250 exposed on the first channel layer 410, the top surfaces of the first channel layer 410 and the first functional layer 310, and the top surface of the gate stack 200.

[0125] The second functional material layer 340 is used to form the second functional layer 320.

[0126] In this embodiment, an atomic layer deposition process is used to form the second functional material layer 340 covering the sidewalls of the through holes 250 exposed on the first channel layer 410, the top surfaces of the first channel layer 410 and the first functional layer 310, and the top surface of the gate stack 200.

[0127] The second functional material layer 340 formed by the atomic layer deposition process has good thickness uniformity and good step coverage ability, so that the second functional material layer 340 can conformally cover the sidewalls of the through holes 250 exposed on the first channel layer 410, the top surfaces of the first channel layer 410 and the first functional layer 310, and the top surface of the gate stack 200 well.

[0128] Reference Figure 13 , removing the second functional material layer 340 on the top surfaces of the first channel layer 410 and the first functional layer 310 and the top surface of the gate stack 200, and retaining the second functional material layer 340 covering the sidewalls of the through holes 250 exposed on the first channel layer 410 as the second functional layer 320.

[0129] Removing the second functional material layer 340 on the top surfaces of the first channel layer 410 and the first functional layer 310 and the top surface of the gate stack 200 prepares for forming the second channel layer 420.

[0130] Reference Figure 14 , forming the second channel layer 420 filling the remaining through holes 250 surrounded by the second functional layer 320.

[0131] In this embodiment, a deposition process is used to form the second channel layer 420 filling the remaining through holes 250 surrounded by the second functional layer 320.

[0132] The process cost of the deposition process is simple, and the formed polysilicon second channel layer 420 also meets the process requirements.

[0133] In combination with reference Figure 15 and Figure 16 , Figure 16 being Figure 15 a cross-sectional view along the AA direction, after forming a channel stack 400 in the through hole 250 and a functional stack 300 covering the sidewalls of the channel stack 400, further comprising: a patterned gate stack 200, forming trenches 260 extending in a first direction and arranged in parallel in a second direction, the trenches 260 dividing the gate stack 200 in the second direction.

[0134] The trenches 260 are used to partition the gate stacks 200 of different memory cell regions 100a.

[0135] In this embodiment, before the patterned gate stack 200, further comprising: forming a dielectric layer 500 covering the gate stack 200, the channel stack 400, and the functional stack 300.

[0136] The dielectric layer 500 is used to provide a process operation platform for the interconnect process.

[0137] In this embodiment, in the step of forming the dielectric layer 500 covering the gate stack 200, the channel stack 400, and the functional stack 300, the material of the dielectric layer 500 includes silicon oxide.

[0138] Correspondingly, in this embodiment, in the step of patterning the gate stack 200, the trenches 260 also penetrate the dielectric layer 500.

[0139] In combination with reference Figure 17 and 18 , Figure 18 being Figure 17 a cross-sectional view along the AA direction, before subsequently forming a first source / drain plug, a second source / drain plug, a first gate plug, and a second gate plug, further comprising: filling the trenches 260 to form isolation walls 510.

[0140] The isolation walls 510 are used to isolate adjacent memory cell regions 100a.

[0141] In this embodiment, in the step of filling the trenches 260 to form the isolation walls 510, the material of the isolation walls 510 includes silicon oxide.

[0142] In combination with reference Figures 19 to 29, after forming the channel stack 400 in the through hole 250 and the functional stack 300 covering the sidewalls of the channel stack 400, it further includes: forming a first source-drain plug 710 that penetrates the side of the channel stack 400 to contact the substrate 100 and is electrically connected to the substrate 100; forming a second source-drain plug 720 on the second channel layer 420 and electrically connected to the second channel layer 420; forming a first gate plug 730 that penetrates the second gate layer 220 to contact the first gate layer 210 and is electrically connected to the first gate layer 210; forming a second gate plug 740 on the second gate layer 220 and electrically connected to the second gate layer 220.

[0143] The first source-drain plug 710 is used to realize the electrical connection between the source region of the substrate 100 and the outside.

[0144] Correspondingly, in this embodiment, the first source-drain plug 710 also penetrates the dielectric layer 500 to expose the first source-drain plug 710 for subsequent interconnection preparation.

[0145] In this embodiment, the material of the first source-drain plug 710 includes tungsten.

[0146] The second source-drain plug 720 is used to realize the electrical connection between the channel stack 400 and the drain region.

[0147] Correspondingly, in this embodiment, the second source-drain plug 720 also penetrates the dielectric layer 500 to expose the second source-drain plug 720 for subsequent interconnection preparation.

[0148] In this embodiment, the material of the second source-drain plug 720 includes tungsten.

[0149] The first gate plug 730 is used to realize the electrical connection between the first gate layer 210 and the outside.

[0150] Correspondingly, in this embodiment, the first gate plug 730 also penetrates the first isolation layer 230, the second isolation layer 240, and the dielectric layer 500 to expose the first gate plug 730 for subsequent interconnection preparation.

[0151] In this embodiment, the material of the first gate plug 730 includes tungsten.

[0152] The second gate plug 740 is used to realize the electrical connection between the second gate layer 220 and the outside.

[0153] Correspondingly, in this embodiment, the second gate plug 740 also penetrates the second isolation layer 240 and the dielectric layer 500 to expose the second gate plug 740 for subsequent interconnection preparation.

[0154] In this embodiment, the material of the second gate plug 740 includes tungsten.

[0155] In this embodiment, in the step of forming the first source-drain plug 710, the second source-drain plug 720, the first gate plug 730, and the second gate plug 740, in the memory cell region 100a, the first source-drain plug 710, the second source-drain plug 720, the first gate plug 730, and the second gate plug 740 are arranged along a first direction, and the first source-drain plug 710, the first gate plug 730, and the second gate plug 740 are arranged at the side of the channel stack 400 along the first direction, so that the arrangement of the first source-drain plug 710, the second source-drain plug 720, the first gate plug 730, and the second gate plug 740 is relatively compact, improving the device density.

[0156] Specifically, with reference to Figure 19 and Figure 20 , Figure 20 being Figure 19 a cross-sectional view along the AA direction, the step of forming the first source-drain plug 710, the second source-drain plug 720, the first gate plug 730, and the second gate plug 740 includes: forming a first opening 610 on the second channel layer 420 to expose the surface of the second channel layer 420.

[0157] The first opening 610 is used to provide a spatial position for forming the second source-drain plug 720.

[0158] Correspondingly, in this embodiment, the first opening 610 penetrates the dielectric layer 500.

[0159] With reference to Figure 21 and Figure 22 , Figure 22 being Figure 21 a cross-sectional view along the AA direction, a second opening 620 is formed on the second gate layer 220 to expose the surface of the second gate layer 220.

[0160] The second opening 620 is used to provide a spatial position for forming the second gate plug 740.

[0161] Correspondingly, in this embodiment, the second opening 620 penetrates the second isolation layer 240 and the dielectric layer 500.

[0162] With reference to Figure 23 and Figure 24 , Figure 24 being Figure 23 a cross-sectional view along the AA direction, a third opening 630 is formed to penetrate the second gate layer 220 and expose the surface of the first gate layer 210.

[0163] The third opening 630 is used to provide a spatial position for forming the first gate plug 730.

[0164] Correspondingly, in this embodiment, the third opening 630 also penetrates the first isolation layer 230, the second isolation layer 240, and the dielectric layer 500.

[0165] Combined reference Figure 25 and Figure 26 , Figure 26 is Figure 25 A cross-sectional view along the AA direction, forming a gate stack 200 that penetrates the side of the channel stack 400 and exposes the fourth opening 640 on the surface of the substrate 100.

[0166] The fourth opening 640 is used to provide a spatial position for forming the first source / drain plug 710.

[0167] Correspondingly, in this embodiment, the fourth opening 640 also penetrates the dielectric layer 500.

[0168] Combined reference Figures 27 to 29 , Figure 28 is Figure 27 A cross-sectional view along the AA direction, Figure 29 is Figure 27 A cross-sectional view along the BB direction, filling the first opening 610, the second opening 620, the third opening 630, and the fourth opening 640, respectively forming the second source / drain plug 720, the second gate plug 740, the first gate plug 730, and the first source / drain plug 710.

[0169] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate; A gate stack located on the substrate, the gate stack including a first gate layer and a second gate layer located on the first gate layer; A channel stack penetrating the gate stack and located on the substrate, the channel stack including a first channel layer and a second channel layer located on the first channel layer; A functional stack covering the sidewalls of the channel stack, the functional stack including a first functional layer between the first channel layer and the first gate layer and a second functional layer on the first functional layer and between the second channel layer and the second gate layer, wherein any one of the first functional layer and the second functional layer is a storage material layer and the other is a gate oxide layer.

2. The semiconductor structure according to claim 1, wherein, The first channel layer and the second channel layer are of an integral structure; Or, There is an interface between the first channel layer and the second channel layer.

3. The semiconductor structure according to claim 1, wherein The gate stack further includes: a first isolation layer between the first gate layer and the second gate layer and a second isolation layer on the second gate layer; The top surface of the first channel layer is higher than the top surface of the first gate layer and lower than the bottom surface of the second gate layer; The top surface of the second channel layer is higher than the top surface of the second gate layer.

4. The semiconductor structure according to claim 1, wherein The first functional layer is a storage material layer and the second functional layer is a gate oxide layer.

5. The semiconductor structure according to claim 1, wherein The semiconductor structure further includes: source-drain doping layers in the substrate at the bottom of the channel stack.

6. The semiconductor structure according to claim 1, wherein, The semiconductor structure further includes: a first source-drain plug penetrating the gate stack on the side of the channel stack and contacting the substrate and electrically connecting to the substrate; A second source-drain plug located on the second channel layer and electrically connecting to the second channel layer; A first gate plug penetrating the second gate layer and contacting the first gate layer and electrically connecting to the first gate layer; A second gate plug located on the second gate layer and electrically connecting to the second gate layer.

7. The semiconductor structure according to claim 6, wherein, The substrate includes storage cell regions extending in a first direction and arranged in parallel in a second direction; The gate stacks of adjacent storage cell regions are spaced apart in the second direction; In the storage cell regions, a plurality of the channel stacks are arranged in the first direction in the gate stack; In the storage cell regions, the first source-drain plug, the second source-drain plug, the first gate plug, and the second gate plug are arranged in the first direction, and the first source-drain plug, the first gate plug, and the second gate plug are arranged on the sides of the channel stack in the first direction.

8. The semiconductor structure according to claim 7, wherein The semiconductor structure further includes: isolation walls extending in the first direction and arranged in parallel in the second direction at the junctions of adjacent storage cell regions, the isolation walls isolating the gate stacks in the second direction.

9. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate; Forming a gate stack on the substrate, the gate stack including a first gate layer and a second gate layer located on the first gate layer; Forming a through hole penetrating the gate stack; A channel stack is formed in the through hole, and a functional stack covering the sidewalls of the channel stack. The channel stack includes a first channel layer and a second channel layer located on the first channel layer. The functional stack includes a first functional layer between the first channel layer and the first gate layer, and a second functional layer on the first functional layer and between the second channel layer and the second gate layer. Wherein, either the first functional layer or the second functional layer is a storage material layer, and the other is a gate oxide layer.

10. The method for forming a semiconductor structure as described in claim 9, wherein, In the step of forming a channel stack in the through hole and a functional stack covering the sidewalls of the channel stack, the first channel layer and the second channel layer are an integral structure; Or, There is an interface between the first channel layer and the second channel layer.

11. The method for forming a semiconductor structure as described in claim 9, wherein, In the step of forming a gate stack on the substrate, the gate stack further includes a first isolation layer between the first gate layer and the second gate layer, and a second isolation layer on the second gate layer; In the step of forming a channel stack in the through hole and a functional stack covering the sidewalls of the channel stack, the top surface of the first channel layer is higher than the top surface of the first gate layer and lower than the bottom surface of the second gate layer, and the top surface of the second channel layer is higher than the top surface of the second gate layer.

12. The method for forming a semiconductor structure according to claim 9, wherein, In the step of forming a channel stack in the through hole and a functional stack covering the sidewalls of the channel stack, the first functional layer is a storage material layer and the second functional layer is a gate oxide layer.

13. The method for forming a semiconductor structure according to claim 9, wherein, The step of forming a channel stack in the through hole and a functional stack covering the sidewalls of the channel stack includes: forming a first channel layer in the through hole and a first functional layer covering the sidewalls of the first channel layer; Forming a second channel layer on the first channel layer and a second functional layer covering the sidewalls of the second channel layer.

14. The method for forming a semiconductor structure according to claim 13, wherein, The step of forming a first channel layer in the through hole and a first functional layer covering the sidewalls of the first channel layer includes: forming a first functional material layer covering the sidewalls of the through hole; Forming a first channel material layer in the remaining through hole surrounded by the first functional material layer; Removing a part of the height of the first functional material layer and the first channel material layer, and retaining the remaining first functional material layer and first channel material layer covering the sidewalls of the first gate layer as the first functional layer and the first channel layer respectively.

15. The method for forming a semiconductor structure according to claim 14, wherein, In the step of forming a first functional material layer covering the sidewalls of the through hole, the first functional material layer also covers the bottom surface of the through hole and the top surface of the gate stack; Before forming a first channel material layer in the remaining through hole surrounded by the first functional material layer, it further includes: removing the first functional material layer on the bottom surface of the through hole and the top surface of the gate stack to expose the surface of the substrate.

16. The method for forming a semiconductor structure according to claim 14, wherein Using an epitaxial growth process to form a first channel material layer in the remaining through hole surrounded by the first functional material layer.

17. The method for forming a semiconductor structure according to claim 14, wherein, Before forming a first channel material layer in the remaining through hole surrounded by the first functional material layer, it further includes: forming a source / drain doping layer in the substrate at the bottom of the through hole.

18. The method for forming a semiconductor structure according to claim 13, wherein, The steps of forming a second channel layer on the first channel layer and a second functional layer covering the sidewalls of the second channel layer include: forming a second functional layer covering the sidewalls of the through holes exposed in the first channel layer; forming a second channel layer filling the remaining through holes surrounded by the second functional layer.

19. The method for forming a semiconductor structure according to claim 18, wherein, The step of forming a second functional layer covering the sidewalls of the through holes exposed in the first channel layer includes: forming a second functional material layer covering the sidewalls of the through holes exposed in the first channel layer, the top surface of the first channel layer and the first functional layer, and the top surface of the gate stack; removing the second functional material layer on the top surface of the first channel layer and the first functional layer, and the top surface of the gate stack, and retaining the second functional material layer covering the sidewalls of the through holes exposed in the first channel layer as the second functional layer.

20. The method for forming a semiconductor structure according to claim 18, wherein, A second channel layer filling the remaining through holes surrounded by the second functional layer is formed by a deposition process.

21. The method for forming a semiconductor structure according to claim 9, wherein After forming a channel stack in the through holes and a functional stack covering the sidewalls of the channel stack, it further includes: forming a first source / drain plug that penetrates the side portion of the channel stack, contacts the substrate, and is electrically connected to the substrate; forming a second source / drain plug on the second channel layer and electrically connected to the second channel layer; forming a first gate plug that penetrates the second gate layer, contacts the first gate layer, and is electrically connected to the first gate layer; forming a second gate plug on the second gate layer and electrically connected to the second gate layer.

22. The method for forming a semiconductor structure according to claim 21, wherein, In the step of providing the substrate, the substrate includes a storage unit region extending in a first direction and arranged in parallel in a second direction; In the step of forming through holes penetrating the gate stack, in the storage unit region, a plurality of the through holes are arranged in the gate stack in the first direction; After forming a channel stack in the through holes and a functional stack covering the sidewalls of the channel stack, it further includes: patterning the gate stack to form grooves extending in the first direction and arranged in parallel in the second direction, and the grooves divide the gate stack in the second direction; In the step of forming the first source / drain plug, the second source / drain plug, the first gate plug, and the second gate plug, in the storage unit region, the first source / drain plug, the second source / drain plug, the first gate plug, and the second gate plug are arranged in the first direction, and the first source / drain plug, the first gate plug, and the second gate plug are arranged on the side portion of the channel stack in the first direction.

23. The method for forming a semiconductor structure according to claim 22, wherein, The step of forming the first source / drain plug, the second source / drain plug, the first gate plug, and the second gate plug includes: forming a first opening on the second channel layer to expose the surface of the second channel layer; forming a second opening on the second gate layer to expose the surface of the second gate layer; forming a third opening that penetrates the second gate layer and exposes the surface of the first gate layer; forming a fourth opening that penetrates the side portion of the channel stack and the gate stack and exposes the surface of the substrate; filling the first opening, the second opening, the third opening, and the fourth opening to respectively form the second source / drain plug, the second gate plug, the first gate plug, and the first source / drain plug.

24. The method for forming a semiconductor structure according to claim 22, wherein Before forming the first source / drain plug, the second source / drain plug, the first gate plug, and the second gate plug, it further includes: filling the trench to form a spacer wall.

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