Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. A semiconductor device includes a ferroelectric memory cell, and the ferroelectric memory cell includes a select transistor and a memory transistor. The gate dielectric film of the select transistor includes a ferroelectric film, and the gate dielectric film of the memory transistor includes a ferroelectric film.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method of manufacturing the same. The present disclosure relates to a technique applicable to a semiconductor device including a ferroelectric memory and a method of manufacturing the same, for example. Background Art

[0002] In recent years, a ferroelectric memory cell having a ferroelectric film has been developed. In the ferroelectric memory cell, controlling the polarization direction of the ferroelectric film causes the state of the ferroelectric memory cell to change between a write state and an erase state. The ferroelectric memory cell can be driven at a lower voltage than a non-volatile memory cell including a charge storage film (such as a silicon nitride film).

[0003] The disclosed techniques are listed below.

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2019-201172

[0005] Patent Document 1 discloses a ferroelectric memory cell formed on a semiconductor substrate. The ferroelectric memory cell includes a ferroelectric film. The ferroelectric film has crystal grains serving as crystal nuclei. Summary of the Invention

[0006] A ferroelectric memory cell having a selection transistor and a memory transistor is known. The selection transistor selects a memory cell to be operated, and the memory transistor stores information. The selection transistor is formed beside the memory transistor. In the method of manufacturing the ferroelectric memory cell, first, a dielectric film is formed on a semiconductor substrate. Next, a ferroelectric film is formed on the semiconductor substrate. The ferroelectric film is provided beside the dielectric film. Next, a control gate electrode is formed on the dielectric film, and a memory gate electrode is formed on the ferroelectric film. Thereafter, the dielectric film and the ferroelectric film are processed using the control gate electrode and the memory gate electrode as masks to form a first gate dielectric film including the dielectric film and a second gate dielectric film including the ferroelectric film. Thereafter, through another manufacturing step, a selection transistor having the first gate dielectric film and the control gate electrode is formed, and a memory transistor having the second gate dielectric film and the memory gate electrode is formed.

[0007] As described above, before forming the control gate electrode and the memory gate electrode, the dielectric film and the ferroelectric film are processed. Different masks are used to process the dielectric film and the ferroelectric film. Therefore, misalignment of the masks may cause formation defects in the dielectric film, the ferroelectric film, the control gate electrode, and the memory gate electrode. To prevent these formation defects, it is conceivable to ensure a processing margin for the dielectric film, the ferroelectric film, the control gate electrode, and the memory gate electrode. That is, it is conceivable to increase the distance between the dielectric film, the ferroelectric film, the control gate electrode, and the memory gate electrode. However, in this case, the size of the ferroelectric memory cell increases, resulting in an increase in the size of the semiconductor chip.

[0008] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0009] In one embodiment of the present application, a semiconductor device includes a ferroelectric memory cell. The ferroelectric memory cell includes a control gate electrode, a memory gate electrode, a first gate dielectric film, a second gate dielectric film, a source region, and a drain region. The first gate dielectric film includes a ferroelectric film, and the second gate dielectric film includes a ferroelectric film.

[0010] In another embodiment of the present application, a method of manufacturing a semiconductor device includes forming a ferroelectric film on a semiconductor substrate, forming a control gate electrode and a memory gate electrode on the ferroelectric film, and processing the ferroelectric film to form a first gate dielectric film and a second gate dielectric film.

[0011] The technology of the present application provides miniaturization of semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a cross-sectional view showing a semiconductor device according to a first embodiment;

[0013] Figure 2 is a cross-sectional view showing manufacturing steps of a semiconductor device according to a first embodiment;

[0014] Figure 3 is showing Figure 2 cross-sectional views of manufacturing steps of a semiconductor device after;

[0015] Figure 4 is showing Figure 3 cross-sectional views of manufacturing steps of a semiconductor device after;

[0016] Figure 5 is showing Figure 4 cross-sectional views of manufacturing steps of a semiconductor device after;

[0017] Figure 6 is showing Figure 5 cross-sectional views of manufacturing steps of a semiconductor device after;

[0018] Figure 7 is showing Figure 6 cross-sectional views of manufacturing steps of a semiconductor device after;

[0019] Figure 8 is showing Figure 7 cross-sectional views of manufacturing steps of a semiconductor device after;

[0020] Figure 9 is a table showing an example of voltages applied to each part during the operation of the ferroelectric memory cell;

[0021] Figure 10 is a cross-sectional view showing the manufacturing steps of a semiconductor device according to a comparative example;

[0022] Figure 11 is a view showing Figure 10 a cross-sectional view of the manufacturing steps of the semiconductor device after;

[0023] Figure 12 is a view showing Figure 11 a cross-sectional view of the manufacturing steps of the semiconductor device after;

[0024] Figure 13 is a view showing Figure 12 a cross-sectional view of the manufacturing steps of the semiconductor device after;

[0025] Figure 14 is a view showing Figure 13 a cross-sectional view of the manufacturing steps of the semiconductor device after;

[0026] Figure 15 is a view showing Figure 14 a cross-sectional view of the manufacturing steps of the semiconductor device after;

[0027] Figure 16 is a view showing Figure 15 a cross-sectional view of the manufacturing steps of the semiconductor device after;

[0028] Figure 17 is a view showing Figure 16 a cross-sectional view of the manufacturing steps of the semiconductor device after;

[0029] Figure 18 is Figure 15 an enlarged cross-sectional view of a part of;

[0030] Figure 19 is a cross-sectional view showing a semiconductor device according to a first modified example of the first embodiment;

[0031] Figure 20 is a cross-sectional view showing the manufacturing steps of a semiconductor device according to a first modified example of the first embodiment;

[0032] Figure 21 is a view showing Figure 20 a cross-sectional view of the manufacturing steps of the semiconductor device after;

[0033] Figure 22 is a cross-sectional view showing a semiconductor device according to a second embodiment;

[0034] Figure 23 is a cross-sectional view showing the manufacturing steps of a semiconductor device according to a second embodiment;

[0035] Figure 24 is a cross-sectional view showing Figure 23 the manufacturing steps of a semiconductor device after; and

[0036] Figure 25 is a cross-sectional view showing Figure 24 the manufacturing steps of a semiconductor device after. DETAILED DESCRIPTION

[0037] In the following embodiments, when necessary for convenience, they will be described by dividing into multiple parts or embodiments, but unless otherwise specified, they are not independent of each other. A part or embodiment is related to part or all of the modification examples, details, supplementary descriptions, etc. of another part or embodiment. In the following embodiments, the number of elements, etc. (including the number of elements, numerical values, quantities, ranges, etc.) is not limited to a specific number, but can be less than or greater than a specific number, unless the number is specifically indicated and is clearly limited to a specific number in principle. In addition, in the following embodiments, needless to say, the constituent elements (including element steps, etc.) are not necessarily required, unless they are specifically specified and they are considered clearly necessary in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is assumed that the shapes, etc. are substantially approximate or similar to the shapes, etc., except in cases where they are specifically specified and cases where they are considered clearly obvious in principle. This also applies to the above numerical values and ranges.

[0038] Hereinafter, embodiments will be described in detail based on the drawings. In all the drawings for explaining the embodiments, components having the same function are denoted by the same reference numerals, and their repeated description is omitted. In the following embodiments, the description of the same or similar components will not be repeated unless particularly necessary. In the drawings used in the embodiments, hatching may be omitted to make the drawings easier to see.

[0039] First Embodiment

[0040] Structure of Semiconductor Device

[0041] As Figure 1As shown, the semiconductor device includes a semiconductor substrate SS, a well region WR, an element isolation structure EIS, a source region SR1, a drain region DR1, an impurity region IR, a gate dielectric film GDF1, a gate dielectric film GDF2, a metal film MF1, a metal film MF2, a gate electrode GE1, a gate electrode GE2, sidewall dielectric films SDF1 and SDF2, an interlayer dielectric film IDF, and a contact plug. The semiconductor device includes a ferroelectric memory cell, and the ferroelectric memory cell includes a select transistor and a memory transistor. The ferroelectric memory cell is formed on the semiconductor substrate SS and includes at least a source region SR1, a drain region DR1, a gate dielectric film GDF1, a gate dielectric film GDF2, a metal film MF1, a metal film MF2, a gate electrode GE1, and a gate electrode GE2. The select transistor includes at least a source region SR1, a drain region DR1, a gate dielectric film GDF1, a metal film MF1, and a gate electrode GE1. The memory transistor includes at least a source region SR1, a drain region DR1, a gate dielectric film GDF2, a metal film MF2, and a gate electrode GE2. Other semiconductor elements other than the ferroelectric memory cell may also be formed on the semiconductor substrate SS.

[0042] The semiconductor substrate SS is made of, for example, p-type single-crystalline silicon (Si) having a resistivity of about 1 to 10 Ωcm. The semiconductor substrate SS has an upper surface and a lower surface. The semiconductor substrate SS includes a well region WR and an element isolation structure EIS. The well region WR is formed in the semiconductor substrate SS. The conductivity type of the well region WR is, for example, p-type. The well region WR has a predetermined impurity concentration. The element isolation structure EIS is formed in the semiconductor substrate SS. The element isolation structure EIS is provided at the upper surface of the semiconductor substrate SS. Specifically, the element isolation structure EIS is formed in the well region WR to surround the upper portion of the well region WR. The element isolation structure EIS includes a trench and a dielectric film embedded in the trench. The element isolation structure EIS has a function of electrically isolating adjacent semiconductor devices from each other.

[0043] The source region SR1 is formed in the semiconductor substrate SS and the well region WR and is provided at the upper surface of the semiconductor substrate SS. The depth of the source region SR1 is less than the depth of the well region WR. The impurity concentration of the source region SR1 is greater than the impurity concentration of the well region WR. The conductivity type of the source region SR1 is, for example, n-type. The source region SR1 may have an LDD structure. The source region SR1 includes, for example, arsenic or phosphorus. The drain region DR1 is formed in the semiconductor substrate SS and the well region WR and is provided at the upper surface of the semiconductor substrate SS. The depth of the drain region DR1 is less than the depth of the well region WR. The impurity concentration of the drain region DR1 is greater than the impurity concentration of the well region WR. The drain region DR1 may have an LDD structure. The drain region DR1 is spaced apart from the source region SR1. In a plan view, the drain region DR1 and the source region SR1 are surrounded by the element isolation structure EIS. A silicide layer may be formed on the drain region DR1 and the source region SR1.

[0044] An impurity region IR is formed in a semiconductor substrate SS and a well region WR, and is provided at an upper surface of the semiconductor substrate SS. The depth of the impurity region IR is less than the depth of the well region WR. The conductivity type of the impurity region IR is, for example, n-type. The impurity concentration of the impurity region IR is greater than the impurity concentration of the well region WR. The impurity region IR is provided between a drain region DR1 and a source region SR1 in a cross-sectional view. The impurity region IR is provided so as not to be connected to a wiring or a plug, and is in an electrically floating state. The impurity region IR is formed to connect a channel of a selection transistor and a channel of a memory transistor.

[0045] A gate dielectric film GDF1 is formed on the semiconductor substrate SS, a metal film MF1 is formed on the gate dielectric film GDF1, and a gate electrode GE1 is formed on the metal film MF1. Specifically, the gate dielectric film GDF1 is formed on a portion of the semiconductor substrate SS that is located between the drain region DR1 and the impurity region IR in a cross-sectional view. The gate dielectric film GDF1 includes a dielectric film DF1 and a ferroelectric film FF1. The dielectric film DF1 is formed on the semiconductor substrate SS, and the ferroelectric film FF1 is formed on the dielectric film DF1 such that the dielectric film DF1 is provided between the semiconductor substrate SS and the ferroelectric film FF1. The dielectric film DF1 is formed of a paraelectric film and is formed of, for example, a silicon oxide film. In a direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the dielectric film DF1 is, for example, equal to or greater than 1 nm and equal to or less than 3 nm. The ferroelectric film FF1 provided between the dielectric film DF1 and the gate electrode GE1 is formed of, for example, a metal oxide film and is formed of a high dielectric constant film having a dielectric constant higher than that of a silicon nitride film. The ferroelectric film FF1 includes, for example, hafnium, oxygen, and zirconium. Instead of zirconium, the ferroelectric film FF1 may include at least one of silicon, germanium, yttrium, lanthanum, and ytterbium. In a direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the ferroelectric film FF1 is, for example, equal to or greater than 6 nm and equal to or less than 20 nm.

[0046] The metal film MF1 formed on the gate dielectric film GDF1 is provided between the ferroelectric film FF1 and the gate electrode GE1. The metal film MF1 is formed of, for example, a titanium nitride film, a tantalum nitride film, or a tungsten film. In a direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the metal film MF1 is, for example, equal to or greater than 2 nm and equal to or less than 20 nm. The metal film MF1 is used to efficiently crystallize the ferroelectric film FF1. Therefore, as long as the ferroelectric film FF1 can be efficiently crystallized without forming the metal film MF1, the metal film MF1 may not be formed. The metal film MF1 and the gate electrode GE1 serve as a control gate electrode of the selection transistor.

[0047] The gate electrode GE1 is formed on the gate dielectric film GDF1. Specifically, when the metal film MF1 is formed on the gate dielectric film GDF1, the gate electrode GE1 is formed on the metal film MF1. The gate electrode GE1 is formed of, for example, a polysilicon film into which an n-type impurity is introduced. The gate electrode GE1 may be formed of a titanium nitride film, an aluminum film, or a tungsten film. Further, the gate electrode GE1 may be formed of a stacked film including two or more conductive films.

[0048] The sidewall dielectric film SDF1 is formed on the side surfaces of the semiconductor substrate SS and the gate electrode GE1. The sidewall dielectric film SDF1 is formed of, for example, a stacked film including a silicon oxide film and a silicon nitride film.

[0049] The gate dielectric film GDF2 is formed on the semiconductor substrate SS, the metal film MF2 is formed on the gate dielectric film GDF2, and the gate electrode GE2 is formed on the metal film MF2. Specifically, the gate dielectric film GDF2 is formed on a portion of the semiconductor substrate SS that is located between the source region SR1 and the impurity region IR in the cross-sectional view. The gate dielectric film GDF2 includes a dielectric film DF2 and a ferroelectric film FF2. The dielectric film DF2 is formed on the semiconductor substrate SS, and the ferroelectric film FF2 is formed on the dielectric film DF2 such that the dielectric film DF2 is disposed between the semiconductor substrate SS and the ferroelectric film FF2. The dielectric film DF2 is formed of a paraelectric film and is formed of, for example, a silicon oxide film. In a direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the dielectric film DF2 is, for example, equal to or greater than 1 nm and equal to or less than 3 nm. The ferroelectric film FF2 disposed between the dielectric film DF2 and the gate electrode GE2 is formed of, for example, a metal oxide film and is formed of a high dielectric constant film having a dielectric constant higher than that of the silicon nitride film. The ferroelectric film FF2 includes, for example, hafnium, oxygen, and zirconium. Instead of zirconium, the ferroelectric film FF2 may include at least one of silicon, germanium, yttrium, lanthanum, and ytterbium. In a direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the ferroelectric film FF2 is, for example, equal to or greater than 6 nm and equal to or less than 20 nm. The thickness of the ferroelectric film FF2 is the same as the thickness of the ferroelectric film FF1.

[0050] The metal film MF2 formed on the gate dielectric film GDF2 is disposed between the ferroelectric film FF2 and the gate electrode GE2. The metal film MF2 is formed of, for example, a titanium nitride film, a tantalum nitride film, or a tungsten film. In a direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the metal film MF2 is, for example, equal to or greater than 2 nm and equal to or less than 20 nm. The metal film MF2 is used to efficiently crystallize the ferroelectric film FF2. Therefore, as long as the ferroelectric film FF2 can be efficiently crystallized without forming the metal film MF2, the metal film MF2 may not be formed. The metal film MF2 and the gate electrode GE2 serve as the memory gate electrode of the memory transistor.

[0051] A gate electrode GE2 is formed on a gate dielectric film GDF2. Specifically, when a metal film MF2 is formed on the gate dielectric film GDF2, the gate electrode GE2 is formed on the metal film MF2. The gate electrode GE2 is formed of, for example, a polysilicon film into which an n-type impurity is introduced. The gate electrode GE2 can be formed of a titanium nitride film, an aluminum film, or a tungsten film. In addition, the gate electrode GE2 can be formed of a stacked film including two or more conductive films.

[0052] A sidewall dielectric film SDF2 is formed on side surfaces of a semiconductor substrate SS and the gate electrode GE2. The sidewall dielectric film SDF2 is formed of, for example, a stacked film including a silicon oxide film and a silicon nitride film.

[0053] An interlayer dielectric film IDF is formed on the semiconductor substrate SS. Specifically, the interlayer dielectric film IDF is formed on the semiconductor substrate SS to cover ferroelectric memory cells. The interlayer dielectric film IDF is formed of, for example, a silicon oxide film. Contact plugs are formed in the interlayer dielectric film IDF. Each contact plug is formed of a barrier metal film and a conductive film. The barrier metal film is formed of a titanium film, a titanium nitride film, or a laminated film thereof, and the conductive film is formed of a tungsten film. The contact plugs include a contact plug CP1 and a contact plug CP2. The contact plug CP1 is connected to a drain region DR1, and the contact plug CP2 is connected to a source region SR1. Although not shown, the semiconductor device includes contact plugs provided on the gate electrode GE1 and contact plugs provided on the gate electrode GE2.

[0054] Although not shown, a multilayer wiring layer is provided on the interlayer dielectric film. The multilayer wiring layer includes wirings and interlayer dielectric films, and each wiring is connected to each contact plug.

[0055] Method for manufacturing a semiconductor device

[0056] As Figure 2 shown, a semiconductor substrate SS is prepared. Next, trenches are formed in the semiconductor substrate SS by a photolithography technique and an etching process. Next, a dielectric film is formed on the semiconductor substrate SS so as to be embedded in the trenches. Thereafter, the dielectric film formed outside the trenches is removed by using a CMP (chemical mechanical polishing) method to form an element isolation structure EIS. Next, a well region WR is formed in the semiconductor substrate SS by introducing impurities into the semiconductor substrate SS by using a photolithography technique and an ion implantation method.

[0057] Next, as Figure 3 shown, a heat treatment is performed on an upper surface of the semiconductor substrate SS to form a dielectric film DF3. The heat treatment for forming the dielectric film DF3 is performed in an oxygen-containing atmosphere. In a direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the dielectric film DF3 is, for example, equal to or greater than 1 nm and equal to or less than 3 nm.

[0058] Next, as shown in Figure 4 , an amorphous film AF1 is formed on the dielectric film DF3 by, for example, an ALD (atomic layer deposition) method. In a direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the amorphous film AF1 is, for example, equal to or greater than 6 nm and equal to or less than 20 nm. The amorphous film AF1 includes, for example, hafnium, oxygen, and zirconium. Instead of zirconium, the amorphous film AF1 may include at least one of silicon, germanium, yttrium, lanthanum, and ytterbium.

[0059] Next, as shown in Figure 5 , a metal film MF3 is formed on the amorphous film AF1 by, for example, a CVD method or a sputtering method. The metal film MF3 is formed of, for example, a titanium nitride film, a tantalum nitride film, or a tungsten film. In a direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the metal film MF3 is, for example, equal to or greater than 2 nm and equal to or less than 20 nm. The metal film MF3 is formed to apply stress to the amorphous film AF1.

[0060] Next, as shown in Figure 6 , the amorphous film AF1 is heat-treated to crystallize the amorphous film AF1, thereby forming a ferroelectric film FF3 on the semiconductor substrate SS. The heat treatment for crystallizing the amorphous film AF1 is performed in a state where the metal film MF3 is formed on the amorphous film AF1. The heat treatment for crystallizing the amorphous film AF1 is performed by, for example, an RTA (rapid thermal annealing) method or an annealing method using microwaves. The stress from the metal film MF3 controls the orientation of the crystals in the ferroelectric film FF3. When the amorphous film AF1 crystallizes into the ferroelectric film FF3, the metal film MF3 has a function of orienting the crystalline phase of the ferroelectric film FF3 into rectangular crystals.

[0061] Next, as shown in Figure 7 , a conductive film CF1 is formed on the metal film MF3 by, for example, a CVD method. The conductive film CF1 is formed of, for example, polysilicon into which an n-type impurity is introduced. When the metal film MF3 is not formed on the ferroelectric film FF3, the conductive film CF1 is formed on the ferroelectric film FF3.

[0062] Next, as shown in Figure 8 , a gate electrode GE1, a gate electrode GE2, a gate dielectric film GDF1, and a gate dielectric film GDF2 are formed. First, a mask film is formed on the conductive film CF1 by a known method. Next, the conductive film CF1 is processed by an anisotropic etching method using the mask film to form the gate electrode GE1 and the gate electrode GE2. Next, the metal film MF3, the ferroelectric film FF3, and the dielectric film DF3 are processed using the gate electrode GE1 and the gate electrode GE2 as masks to form a metal film MF1, a metal film MF2, a ferroelectric film FF1, a ferroelectric film FF2, a dielectric film DF1, and a dielectric film DF2.

[0063] Next, a drain region DR1, a source region SR1, an impurity region IR, sidewall dielectric films SDF1 and SDF2, an interlayer dielectric film IDF, and a contact plug are formed by known methods. Thus, a semiconductor device having the Figure 1 structure shown is formed.

[0064] Operation of the Semiconductor Device

[0065] Specifically, Figure 9 Examples of the voltages applied to each part during a write operation, an erase operation, and a read operation are shown. Figure 9 Each of the voltages shown is applied to a selected memory cell that is the target of the operation and is not applied to a non-selected memory cell that is not the target of the operation. Different voltages from those Figure 9 shown are applied to the non-selected memory cells. Figure 9 Examples of the voltage Vd applied to the drain region DR1 of the ferroelectric memory cell, the voltage Vcg applied to the gate electrode GE1, the voltage Vmg applied to the gate electrode GE2, the voltage Vs applied to the source region SR1, and the voltage Vb applied to the well region WR during each of the write operation, the erase operation, and the read operation are shown. Note that the Figure 9 applied voltages shown are examples.

[0066] In the first embodiment, a state in which the ferroelectric film FF2 is polarized upward and the threshold voltage of the memory transistor is relatively high is defined as the write state. Further, a state in which the ferroelectric film FF2 is polarized downward and the threshold voltage of the memory transistor is relatively low is defined as the erase state.

[0067] For example, in the write operation, Figure 9 the voltages shown in the "Write" row of are applied to each part of the selected memory cell to be written. As a result, the ferroelectric film FF2 is polarized upward, the threshold voltage of the memory transistor increases, and the ferroelectric film FF2 becomes the write state. Even if the voltages shown in the "Write" row of Figure 9 are no longer applied, the polarization in the ferroelectric film FF2 is maintained until an erase operation is performed on the selected memory cell.

[0068] For example, in the erase operation, Figure 9 the voltages shown in the "Erase" row of are applied to each part of the selected memory cell to be erased. As a result, the ferroelectric film FF2 is polarized downward, the threshold voltage of the memory transistor decreases, and the ferroelectric film FF2 becomes the erase state. Even if the voltages shown in the "Erase" row of Figure 9 are no longer applied, the polarization in the ferroelectric film FF2 is maintained until a write operation is performed on the selected memory cell.

[0069] For example, in the read operation, Figure 9The voltage shown in the "read" row is applied to each part of the selected memory cell to be read. The voltage Vmg applied to the gate electrode GE2 is set to a value between the threshold voltage of the memory transistor in the write state and the threshold voltage of the memory transistor in the erase state. Thus, the magnitude of the current flowing through the memory transistor in the write state is different from the magnitude of the current flowing through the memory transistor in the erase state. The state of the ferroelectric memory cell can be determined by detecting the magnitude of the current flowing through the ferroelectric memory cell during the read operation.

[0070] The selection transistor selects the memory transistor to be operated. If the threshold voltage of the selection transistor changes, the performance of the ferroelectric memory cell also changes. For example, the selection transistor may not select the memory transistor to be operated. Therefore, preferably, the threshold voltage of the selection transistor is unlikely to change. In the first embodiment, the selection transistor includes a ferroelectric film FF1, and the selection transistor can operate as a memory cell. In this case, a write operation or an erase operation is performed on the selection transistor, and the threshold voltage of the selection transistor can change. To suppress the change in the threshold voltage of the selection transistor, a write operation can be performed on the selection transistor after forming the selection transistor. For example, in the write operation, a voltage of 5V is applied to the gate electrode GE1, and a voltage of 0V is applied to each of the drain region DR1, the source region SR1, and the well region WR. Then, the selection transistor becomes an erase state, and the selection transistor has a relatively low threshold voltage. For example, the threshold voltage of the selection transistor is set to be lower than the positive voltage applied to the gate electrode GE1 during the operation of the selection transistor. Thus, it is possible to prevent the positive voltage applied to the gate electrode GE1 during the operation of the selection transistor from changing the threshold voltage of the selection transistor.

[0071] Main features and effects of the first embodiment

[0072] The main features and effects of the manufacturing method of the semiconductor device according to the first embodiment and the structure of the semiconductor device will be described by comparing with the manufacturing method of the semiconductor device according to the comparative example.

[0073] In the manufacturing method of the semiconductor device according to the comparative example, similar to the first embodiment, a semiconductor substrate SS is prepared, and referring again to Figure 2 , a well region WR and an element isolation structure EIS are formed in the semiconductor substrate SS. Next, in the comparative example, as Figure 10As shown, a dielectric film DFC and a protective film PFC are formed on a semiconductor substrate SS. First, for example, by performing a heat treatment on the semiconductor substrate SS, the dielectric film DFC is formed on the semiconductor substrate SS. Next, the protective film PFC is formed on the dielectric film DFC by, for example, CVD method. Thereafter, a mask film MKC1 is formed on the protective film PFC by CVD method or lithography technique. Thereafter, the protective film PFC is processed by an etching process to remove the protective film PFC exposed from the mask film MKC1. The processed protective film PFC covers at least a part of the upper surface of the semiconductor substrate SS where the gate dielectric film GDFC1 is to be formed, and exposes a part of the upper surface of the semiconductor substrate SS where the gate dielectric film GDFC2 is to be formed. Next, as Figure 11 shown, a mask film MKC2 is formed on the protective film PFC and the dielectric film DFC by CVD method or lithography technique. The mask film MKC2 is formed on the dielectric film DFC to cover the protective film PFC. Thereafter, the dielectric film DFC is processed by an etching process to remove the dielectric film DFC exposed from the mask film MKC2. Thus, the upper surface of the semiconductor substrate SS where the gate dielectric film GDFC2 is to be formed is exposed. Thereafter, although not shown, a dielectric film is formed beside the processed dielectric film DFC and on the upper surface of the semiconductor substrate SS.

[0074] Next, as Figure 12 shown, a ferroelectric film FFC1 and a metal film MFC1 are formed on the semiconductor substrate SS. First, an amorphous film is formed on the semiconductor substrate SS by, for example, ALD method. The amorphous film is formed to cover the dielectric film DFC and the protective film PFC. Next, the metal film MFC1 is formed on the amorphous film by, for example, CVD method or sputtering method. The metal film MFC1 is formed to cover the dielectric film DFC and the protective film PFC. Next, the ferroelectric film FFC1 is formed by performing a heat treatment on the amorphous film to crystallize the amorphous film.

[0075] Next, as Figure 13 shown, the metal film MFC1 and the ferroelectric film FFC1 are processed. First, a mask film MKC3 is formed on the metal film MFC1. Next, the metal film MFC1 and the ferroelectric film FFC1 are processed by an etching process to remove the metal film MFC1 and the ferroelectric film FFC1 exposed from the mask film MKC3. Thus, the side surfaces of the processed metal film MFC1 and the side surfaces of the processed ferroelectric film FFC1 are located on the dielectric film DFC, but not on the protective film PFC. That is, the side surfaces of the processed metal film MFC1 and the side surfaces of the processed ferroelectric film FFC1 are located on the dielectric film DFC exposed from the protective film PFC.

[0076] Next, as Figure 14As shown, the protective film PFC is removed by an etching method. Next, a conductive film CF3 is formed on the semiconductor substrate SS. Specifically, the conductive film CF3 is formed on the dielectric film DFC and the metal film MFC1. When the metal film MFC1 is not formed on the ferroelectric film FFC1, the conductive film CF3 is formed on the ferroelectric film FFC1.

[0077] Next, as Figure 15 shown, a mask film is formed on the conductive film CF3 by a known method. Next, the conductive film CF3 is processed using the mask film by an etching process. Thus, the gate electrode GEC1 and the gate electrode GEC2 are formed.

[0078] Next, as Figure 16 shown, the metal film MFC1 and the ferroelectric film FFC1 are processed using the gate electrode GEC2 as a mask to form a metal film MFC2 and a ferroelectric film FFC2 under the gate electrode GEC2.

[0079] Next, as Figure 17 shown, a drain region DR1, a source region SR1, an impurity region IR, sidewall dielectric films SDF1, SDF2, an interlayer dielectric film IDF, contact plugs CP1 and CP2 are formed by a known method. As described above, a semiconductor device according to the comparative example is manufactured.

[0080] Figure 18 The positions where the mask films MKC1, MKC2 and MKC3 are formed are shown. Specifically, in Figure 18 the dashed line A indicates the position of the end of the mask film MKC1 for processing the protective film PFC as Figure 10 shown. The dashed line B indicates the position of the end of the mask film MKC2 for processing the dielectric film DFC as Figure 11 shown. The dashed line C indicates the position of the end of the mask film MKC3 for processing the ferroelectric film FFC1 as Figure 13 shown.

[0081] In the comparative example, the gate dielectric film GDFC2 of the memory transistor includes the ferroelectric film FFC2, while the gate dielectric film GDFC1 of the selection transistor does not include the ferroelectric film. Therefore, referring again to Figures 10 to 13, the method of manufacturing a semiconductor device according to the comparative example includes steps of processing a protective film PFC, processing a dielectric film DFC, and processing a ferroelectric film FFC1. Therefore, in order to manufacture a semiconductor device according to the comparative example, at least mask films MKC1, MKC2, and MKC3 need to be formed. The mask films MKC1, MKC2, and MKC3 are formed by CVD method, photolithography technology, etching process, etc. Therefore, manufacturing variations affect the formation positions of the mask film MKC1, the mask film MKC2, and the mask film MKC3. Due to manufacturing variations, the formation positions of the structures formed on the semiconductor substrate SS vary in the plane.

[0082] For example, in the comparative example, the formation position of the mask film MKC1 can vary such that the distance between the mask film MKC1 and the mask film MKC3 decreases. Similarly, the formation position of the mask film MKC3 can vary such that the distance between the mask film MKC1 and the mask film MKC3 decreases. If the formation position of the mask film MKC1 varies such that the distance between the mask film MKC1 and the mask film MKC3 decreases, then Figure 18 the end portion of the shown mask film MKC1 and Figure 18 the end portion of the described mask film MKC3 can be interchanged with each other. In this case, for example, formation defects may occur in the ferroelectric film FFC1 processed using the mask film MKC3. Therefore, the formation position of one mask film affects the formation position of another mask film, and it is possible that the protective film PFC, the dielectric film DFC, and the ferroelectric film FFC2 cannot be formed at the desired positions. In order to form the protective film PFC, the dielectric film DFC, and the ferroelectric film FFC2 at the desired positions, it is necessary to ensure a sufficient distance between the formation position of one mask film and the formation position of another mask film. In addition, in order to prevent formation defects of the gate electrode GEC1, it is necessary to ensure a sufficient distance between the formation position of the end portion of the mask film MKC1 and the formation position of the gate electrode GEC1. In addition, in order to prevent formation defects of the gate electrode GEC2, it is necessary to ensure a sufficient distance between the formation position of the end portion of the mask film MKC2 and the formation position of the gate electrode GEC2.

[0083] As described above, when a sufficient distance is ensured between the mask films MKC1, MKC2, MKC3, the gate electrode GEC1, and the gate electrode GEC2, the distance between the gate electrode GEC1 and the gate electrode GEC2 increases. Increasing the distance between the gate electrode GEC1 and the gate electrode GEC2 results in an increase in the size of the ferroelectric memory cell. As a result, the size of the semiconductor chip on which the ferroelectric memory is mounted increases.

[0084] In the first embodiment, the gate dielectric film GDF1 includes the ferroelectric film FF1, and the gate dielectric film GDF2 includes the ferroelectric film FF2. Referring again toFigure 8 , in the first embodiment, the ferroelectric film FF3 is processed to form the ferroelectric film FF1 and the ferroelectric film FF2.

[0085] As Figure 8 shown, by using the gate electrode GE1 and the gate electrode GE2 as masks to process the metal film MF3, the ferroelectric film FF3, and the dielectric film DF3, the gate dielectric films GDF1 and GDF2 are formed. Therefore, the first embodiment does not require forming the mask film MKC1 for processing the protective film PFC, the mask film MKC2 for processing the dielectric film DFC, and the mask film MKC3 for processing the ferroelectric film FFC1 as required in the comparative example. Therefore, the first embodiment does not need to ensure sufficient distances between the positions for forming the mask film MKC1, the position for forming the mask film MKC2, and the position for forming the mask film MKC3. In the first embodiment, it is sufficient to ensure a sufficient distance between the formation positions of the gate electrode GE1 and the gate electrode GE2. The distance between the gate electrode GE1 and the gate electrode GE2 in the first embodiment can be smaller than the distance between the gate electrode GEC1 and the gate electrode GEC2 in the comparative example. Therefore, compared with the semiconductor device according to the comparative example, the semiconductor device according to the first embodiment can be miniaturized.

[0086] In the first embodiment, not only does the memory transistor include the ferroelectric film FF2, but the select transistor also includes the ferroelectric film FF1. The ferroelectric film FF1 is formed of a high dielectric constant film. Even if the physical thickness of the dielectric film DFC in the comparative example and the physical thickness of the gate dielectric film GDF1 in the first embodiment are the same as each other, the equivalent oxide thickness of the gate dielectric film GDF1 can be smaller than the equivalent oxide thickness of the dielectric film DFC. Therefore, compared with the semiconductor device in the comparative example, the performance of the semiconductor in the first embodiment can be improved while maintaining the reliability of the semiconductor device.

[0087] First Modified Example

[0088] Structure of the Semiconductor Device

[0089] The first modified example is a modification of the first embodiment. As Figure 19 shown, except for the thickness of the dielectric film DF1 and the thickness of the dielectric film DF2, the semiconductor device according to the first modified example has the same configuration as the semiconductor device according to the first embodiment. In the first modified example, the thickness of the dielectric film DF1 is greater than the thickness of the dielectric film DF2. In the direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the dielectric film DF1 is, for example, equal to or greater than 4 nm and equal to or less than 8 nm. In the direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the dielectric film DF2 is, for example, equal to or greater than 1 nm and equal to or less than 3 nm.

[0090] Method of manufacturing a semiconductor device

[0091] In the method of manufacturing a semiconductor device according to the first modification example, a semiconductor substrate SS is prepared, and a well region WR and an element isolation structure EIS are formed in the semiconductor substrate SS, as Figure 2 shown. Next, as Figure 20 shown, a dielectric film DFM1 is formed on the semiconductor substrate SS. The dielectric film DFM1 is formed by, for example, a thermal oxidation method or an ISSG oxidation method. Next, the dielectric film DFM1 is processed by a photolithography technique and an etching method to remove a part of the dielectric film DFM1. As a result, the dielectric film DFM1 on the part of the upper surface of the semiconductor substrate SS where the gate dielectric film GDF2 is to be formed is removed, while the dielectric film DFM1 on the part of the upper surface of the semiconductor substrate SS where the gate dielectric film GDF1 is to be formed is not removed. Next, a dielectric film DFM2 is formed on the part of the semiconductor substrate SS exposed from the dielectric film DFM1. The dielectric film DFM2 is formed by, for example, a thermal oxidation method or an ISSG oxidation method. The thickness of the dielectric film DFM1 is greater than the thickness of the dielectric film DFM2.

[0092] Then, as Figure 21 shown, an amorphous film AF3 is formed on the dielectric film DFM1 and the dielectric film DFM2. The formation method and configuration of the amorphous film AF3 in the first modification example are the same as the formation method and configuration of the amorphous film AF1 in the first embodiment. Next, a metal film MFM1 is formed on the amorphous film AF3. The formation method and configuration of the metal film MFM1 in the first modification example are the same as the formation method and configuration of the metal film MF3 in the first embodiment. Next, the amorphous film AF3 is crystallized to form a ferroelectric film FFM1. The crystallization method of the amorphous film AF3 in the first modification example is the same as the crystallization method of the amorphous film AF1 in the first embodiment. Next, a gate electrode GEM1 and a gate electrode GEM2 are formed on the metal film MFM1. The formation method of the gate electrode GEM1 and the formation method of the gate electrode GEM2 in the first modification example are the same as the formation method of the gate electrode GE1 and the formation method of the gate electrode GE2 in the first embodiment.

[0093] Next, the metal film MFM1 and the ferroelectric film FFM1 are processed using the gate electrode GEM1 and the gate electrode GEM2 as masks. Thus, the Figure 19 shown metal film MFM2, a gate dielectric film GDFM1 including a ferroelectric film FFM2 and a dielectric film DFM1, a metal film MFM3, and a gate dielectric film GDFM2 including a ferroelectric film FM3 and a dielectric film DFM2 are formed. Thereafter, a drain region DR1, a source region SR1, an impurity region IR, sidewall dielectric films SDF1, SDF2, an interlayer dielectric film IDF, and contact plugs are formed by known methods. Thus, aFigure 19 The semiconductor device shown

[0094] Main features and effects of the first modification example

[0095] When the thickness of the dielectric film DF1 is insufficient, the performance of the select transistor may deteriorate. When the select transistor operates, a positive voltage is applied to the gate electrode GE1 of the select transistor. If the thickness of the dielectric film DF1 is not enough, electrons flowing through the semiconductor substrate SS are injected through the dielectric film DF1 into the interface between the dielectric film DF1 and the ferroelectric film FF1. Since electrons exist at the interface between the dielectric film DF1 and the ferroelectric film FF1, the electric field strength applied to the ferroelectric film FF1 increases, causing the select transistor to operate as a memory cell. In this case, the operation of the select transistor as a memory cell represents a write operation being performed on the select transistor. As a result, the threshold voltage of the select transistor increases, and there is a possibility that no current flows through the select transistor. As a result, the ferroelectric memory cell may not operate properly.

[0096] In the first modification example, the thickness of the dielectric film DFM1 is greater than the thickness of the dielectric film DFM2. Therefore, when the select transistor operates, it is less likely that electrons flowing through the semiconductor substrate SS are injected through the dielectric film DFM1 into the interface between the dielectric film DFM1 and the ferroelectric film FFM2. Therefore, it is less likely that the select transistor operates as a memory cell, and the ferroelectric memory cell can operate properly. Also in the first modification example, as Figure 21 shown, the ferroelectric film FFM1 is processed to form the ferroelectric film FFM2 and the ferroelectric film FFM3. Therefore, the gate dielectric film GDFM1 including the ferroelectric film FFM2 is formed, and the gate dielectric film GDFM2 including the ferroelectric film FFM3 is formed. Therefore, similar to the first embodiment, the semiconductor device can be miniaturized.

[0097] Second embodiment

[0098] Structure of the semiconductor device

[0099] As Figure 22 shown, the semiconductor device of the second embodiment includes a ferroelectric memory cell and a MISFET (Metal Insulator Semiconductor Field Effect Transistor). The ferroelectric memory cell and the MISFET may not be arranged adjacent to each other. Other semiconductor elements, dummy patterns, etc. may be provided between the ferroelectric memory cell and the MISFET. The configuration of the ferroelectric memory cell according to the second embodiment is the same as the configuration according to the first embodiment. The MISFET includes at least a source region SR2, a drain region DR2, a gate dielectric film GDFS, a metal film MFS1, and a gate electrode GES.

[0100] The source region SR2 is formed in the semiconductor substrate SS and the well region WR, and is disposed at the upper surface of the semiconductor substrate SS. The depth of the source region SR2 is less than the depth of the well region WR. The impurity concentration of the source region SR2 is greater than the impurity concentration of the well region WR. The conductivity type of the source region SR2 is, for example, n-type. The source region SR2 may have an LDD structure. The source region SR2 includes, for example, arsenic or phosphorus. The drain region DR2 is formed in the semiconductor substrate SS and the well region WR, and is disposed at the upper surface of the semiconductor substrate SS. The depth of the drain region DR2 is less than the depth of the well region WR. The impurity concentration of the drain region DR2 is greater than the impurity concentration of the well region WR. The drain region DR2 may have an LDD structure. The drain region DR2 is spaced apart from the source region SR2. In a plan view, the drain region DR2 and the source region SR2 are surrounded by the element isolation structure EIS. A silicide layer may be formed on the drain region DR2 and the source region SR2.

[0101] The gate dielectric film GDFS is formed on the semiconductor substrate SS, the metal film MFS1 is formed on the gate dielectric film GDFS, and the gate electrode GES is formed on the metal film MFS1. Specifically, the gate dielectric film GDFS is formed on the portion of the semiconductor substrate SS that is located between the drain region DR2 and the source region SR2 in the cross-sectional view. The gate dielectric film GDFS includes the dielectric film DFS1 and the ferroelectric film FFS1. The dielectric film DFS1 is formed on the semiconductor substrate SS, and the ferroelectric film FFS1 is formed on the dielectric film DFS1 such that the dielectric film DFS1 is disposed between the semiconductor substrate SS and the ferroelectric film FFS1. The dielectric film DFS1 is formed of a paraelectric film and is formed of, for example, a silicon oxide film. In the direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the dielectric film DFS1 is, for example, equal to or greater than 1 nm and equal to or less than 3 nm. When a voltage is applied to the gate electrode GES, the dielectric film DFS1 has the function of preventing electrons from entering the ferroelectric film FFS1 from the semiconductor substrate SS. If electrons can be prevented from entering the ferroelectric film FFS1 without the dielectric film DF1, or if the influence of electrons entering the ferroelectric film FFS1 does not need to be considered, the dielectric film DFS1 may not be formed. The ferroelectric film FFS1 disposed between the dielectric film DFS1 and the gate electrode GES is formed of, for example, a metal oxide film and is formed of a high dielectric constant film having a dielectric constant higher than that of a silicon nitride film. The ferroelectric film FFS1 includes, for example, hafnium, oxygen, and zirconium. Instead of zirconium, the ferroelectric film FFS1 may include at least one of silicon, germanium, yttrium, lanthanum, and ytterbium. In the direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the ferroelectric film FFS1 is, for example, equal to or greater than 6 nm and equal to or less than 20 nm.

[0102] A metal film MFS1 formed on a gate dielectric film GDFS is disposed between the gate dielectric film GDFS and a gate electrode GES. The metal film MFS1 is formed of, for example, a titanium nitride film, a tantalum nitride film, or a tungsten film. In a direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the metal film MFS1 is, for example, equal to or greater than 2 nm and equal to or less than 20 nm. The metal film MFS1 is used to efficiently crystallize the ferroelectric film FFS1. Therefore, as long as the ferroelectric film FFS1 can be efficiently crystallized without forming the metal film MFS1, the metal film MFS1 may not be formed. The metal film MFS1 and the gate electrode GES serve as the gate electrode of the MISFET.

[0103] The gate electrode GES is formed on the gate dielectric film GDFS. Specifically, when the metal film MFS1 is formed on the gate dielectric film GDFS, the gate electrode GES is formed on the metal film MFS1. The gate electrode GES is formed of, for example, a polysilicon film into which an n-type impurity is introduced. The gate electrode GES may be formed of a titanium nitride film, an aluminum film, or a tungsten film. In addition, the gate electrode GES may be formed of a stacked film including two or more conductive films.

[0104] A sidewall dielectric film SDF3 is formed on side surfaces of the semiconductor substrate SS and the gate electrode GES. The sidewall dielectric film SDF3 is formed of, for example, a stacked film including a silicon oxide film and a silicon nitride film.

[0105] An interlayer dielectric film IDF is formed on the semiconductor substrate SS to cover the ferroelectric memory cell and the MISFET. In addition to the contact plugs CP1 and CP2, the contact plugs further include a contact plug CP3 and a contact plug CP4. The contact plug CP3 is disposed on the drain region DR2, and the contact plug CP4 is disposed on the source region SR2. Although not shown, the semiconductor device includes a contact plug disposed on the gate electrode GES.

[0106] Method of manufacturing a semiconductor device

[0107] As Figure 23As shown, a heat treatment is performed on the upper surface of the semiconductor substrate SS to form a dielectric film DFS2 on the semiconductor substrate SS. The dielectric film DFS2 is formed at a portion of the semiconductor substrate SS where a ferroelectric memory cell is to be formed and at a portion of the semiconductor substrate SS where a MISFET is to be formed. The heat treatment for forming the dielectric film DFS2 is performed in an oxygen-containing atmosphere. In a direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the dielectric film DFS2 is, for example, equal to or greater than 1 nm and equal to or less than 3 nm. Next, an amorphous film AF2 is formed on the dielectric film DFS2 by, for example, the ALD method. The amorphous film AF2 is formed at a portion of the semiconductor substrate SS where a ferroelectric memory cell is to be formed and at a portion of the semiconductor substrate SS where a MISFET is to be formed. In a direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the amorphous film AF2 is, for example, equal to or greater than 6 nm and equal to or less than 20 nm. The amorphous film AF2 includes, for example, hafnium, oxygen, and zirconium. Instead of zirconium, the amorphous film AF2 may include at least one of silicon, germanium, yttrium, lanthanum, and ytterbium.

[0108] Next, a metal film MFS2 is formed on the amorphous film AF2 by, for example, the CVD method or the sputtering method. The metal film MFS2 is formed at a portion of the semiconductor substrate SS where a ferroelectric memory cell is to be formed and at a portion of the semiconductor substrate SS where a MISFET is to be formed. The metal film MFS2 is formed of, for example, titanium nitride, tantalum nitride, or tungsten. In a direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the metal film MFS2 is, for example, equal to or greater than 2 nm and equal to or less than 20 nm. The metal film MFS2 is formed to apply stress to the amorphous film AF2. Next, a heat treatment is performed on the amorphous film AF2 to crystallize it, thereby forming a ferroelectric film FFS2. The method of crystallizing the amorphous film AF2 is the same as the method of crystallizing the amorphous film AF1 in the first embodiment.

[0109] Next, as Figure 24 shown, a conductive film CF2 is formed on the metal film MFS2 by, for example, the CVD method. The conductive film CF2 is formed of, for example, polysilicon into which an n-type impurity is introduced. When the metal film MFS2 is not formed on the ferroelectric film FFS2, the conductive film CF2 is formed on the ferroelectric film FFS2. Next, the conductive film CF2 is processed by an anisotropic etching treatment to form a gate electrode GE1, a gate electrode GE2, and a gate electrode GES.

[0110] Next, as Figure 25 shown, using the gate electrode GE1, the gate electrode GE2, and the gate electrode GES as masks, the metal film MFS2, the ferroelectric film FFS2, and the dielectric film DFS2 are processed by an anisotropic etching method. Accordingly, a metal film MF1, a metal film MF2, a metal film MFS1, a ferroelectric film FF1, a ferroelectric film FF2, a ferroelectric film FFS1, a dielectric film DF1, a dielectric film DF2, and a dielectric film DFS1 are formed.

[0111] Next, a drain region DR1, a drain region DR2, a source region SR1, a source region SR2, an impurity region IR, sidewall dielectric films SDF1, SDF2, SDF3, an interlayer dielectric film IDF, and contact plugs are formed by known methods. Accordingly, a semiconductor device having the Figure 22 structure shown is formed.

[0112] Main features and effects of the second embodiment

[0113] Various types of semiconductor elements are formed on a semiconductor substrate SS. For example, the semiconductor elements include a ferroelectric memory cell, a low breakdown voltage MISFET, and a high breakdown voltage MISFET. The ferroelectric memory cell, the low breakdown voltage MISFET, and the high breakdown voltage MISFET have different operating voltages and functions. Accordingly, the structures of the gate dielectric films of the ferroelectric memory cell, the low breakdown voltage MISFET, and the high breakdown voltage MISFET are different from each other. For example, the gate dielectric films of the low breakdown voltage MISFET and the high breakdown voltage MISFET are formed of silicon oxide. In a direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the gate dielectric film of the high breakdown voltage MISFET is greater than that of the gate dielectric film of the low breakdown voltage MISFET.

[0114] Referring again to Figure 17 , in the ferroelectric memory cell according to the comparative example, the structure of the gate dielectric film GDFC1 of the select transistor is different from the structure of the gate dielectric film GDFC2 of the memory transistor. Accordingly, referring again to Figures 10 to 13 , it is necessary to process the dielectric film DFC, the ferroelectric film FFC1, and the metal film MFC1 such that the dielectric film DFC, the ferroelectric film FFC1, and the metal film MFC1 are formed at desired positions. Accordingly, in the comparative example, the number of manufacturing steps increases. Similarly, the structure of the gate dielectric film of the MISFET is different from the structure of the gate dielectric film GDFC1 of the select transistor and the structure of the gate dielectric film GDFC2 of the memory transistor. Accordingly, a step of processing the gate dielectric film of the MISFET is performed such that the gate dielectric film of the MISFET is formed at a desired position. Accordingly, the number of manufacturing steps increases.

[0115] In the second embodiment, as Figure 22 shown, the gate dielectric film GDF1 includes a ferroelectric film FF1, the gate dielectric film GDF2 includes a ferroelectric film FF2, and the gate dielectric film GDFS includes a ferroelectric film FFS1. Then, as Figure 25 shown, the ferroelectric films FF1, FF2, and FFS1 are formed by processing the ferroelectric film FFS2.

[0116] As Figure 25As shown, the gate electrode GE1, gate electrode GE2, and gate electrode GES are used as masks to process the metal film MFS2, ferroelectric film FFS2, and dielectric film DFS2 to form the gate dielectric film GDF1, gate dielectric film GDF2, and gate dielectric film GDFS. In the second embodiment, it is not necessary to form the mask films MKC1, MKC2, and MKC3, nor is it necessary to form a mask film for processing the gate dielectric film GDFS. In the second embodiment, since the step of processing the gate dielectric film GDFS is not required, the number of manufacturing steps can be reduced, and the manufacturing steps can be simplified. Compared with the semiconductor device according to the comparative example, the semiconductor device according to the second embodiment can be miniaturized similarly to the first embodiment.

[0117] The technique described in the first modification example of the first embodiment is applicable to the method described in the second embodiment. That is, in the Figure 22 structure shown, the thickness of the dielectric film DF1 can be greater than the thickness of the dielectric film DF2. To optimize the performance of the MISFET, the thickness of the dielectric film DFS1 can be different from the thicknesses of the dielectric film DF1 and the dielectric film DF2.

[0118] Although the invention made by the inventors of the present application has been specifically described based on the embodiments, the present disclosure is not limited to the above embodiments and can be variously modified without departing from its gist.

Claims

1. A semiconductor device, comprising: A semiconductor substrate; And A ferroelectric memory cell formed on the semiconductor substrate, Wherein the ferroelectric memory cell comprises: A first gate dielectric film formed on the semiconductor substrate; A first gate electrode formed on the first gate dielectric film; A second gate dielectric film formed on the semiconductor substrate; A second gate electrode formed on the second gate dielectric film; A source region formed in the semiconductor substrate; and A drain region formed in the semiconductor substrate, Wherein the first gate dielectric film includes a first ferroelectric film, and Wherein the second gate dielectric film includes a second ferroelectric film.

2. The semiconductor device according to claim 1, Wherein the semiconductor substrate has an upper surface, Wherein the first gate dielectric film includes a first dielectric film disposed between the semiconductor substrate and the first ferroelectric film, and Wherein the second gate dielectric film includes a second dielectric film disposed between the semiconductor substrate and the second ferroelectric film.

3. The semiconductor device according to claim 2, Wherein, in a direction perpendicular to the upper surface of the semiconductor substrate, the thickness of the first dielectric film is greater than the thickness of the second dielectric film.

4. The semiconductor device according to claim 1, Wherein the semiconductor substrate has an upper surface, and Wherein, in a direction perpendicular to the upper surface of the semiconductor substrate, the thickness of the first ferroelectric film is equal to the thickness of the second ferroelectric film.

5. The semiconductor device according to claim 2, Wherein the first dielectric film is formed of a silicon oxide film, and Wherein the second dielectric film is formed of a silicon oxide film.

6. The semiconductor device according to claim 1, Wherein the first ferroelectric film includes hafnium and oxygen, and Wherein the second ferroelectric film includes hafnium and oxygen.

7. The semiconductor device according to claim 1, comprising: An impurity region formed in the semiconductor substrate, Wherein the impurity region is disposed between the source region and the drain region.

8. The semiconductor device according to claim 7, Wherein the first gate dielectric film is formed on a portion of the semiconductor substrate located between the drain region and the impurity region, and Wherein the second gate dielectric film is formed on a portion of the semiconductor substrate located between the source region and the impurity region.

9. The semiconductor device according to claim 1, Wherein the ferroelectric memory cell comprises: A first metal film disposed between the first ferroelectric film and the first gate electrode; And A second metal film disposed between the second ferroelectric film and the second gate electrode.

10. The semiconductor device according to claim 1, comprising: An interlayer dielectric film formed on the semiconductor substrate to cover the ferroelectric memory cell; A first contact plug formed in the interlayer dielectric film and connected to the drain region; And A second contact plug formed in the interlayer dielectric film and connected to the source region.

11. A method of manufacturing a semiconductor device, the method comprising: (a) Preparing a semiconductor substrate; (b) Form a third ferroelectric film on the semiconductor substrate; (c) Form a conductive film on the third ferroelectric film; (d) Process the conductive film to form a first gate electrode and a second gate electrode; (e) After (d), process the third ferroelectric film to form a first ferroelectric film between the first gate electrode and the semiconductor substrate and a second ferroelectric film between the second gate electrode and the semiconductor substrate; And (f) Form a source region and a drain region in the semiconductor substrate, wherein the first gate electrode, the second gate electrode, the first ferroelectric film, the second ferroelectric film, the source region and the drain region constitute a ferroelectric memory cell.

12. The method according to claim 11, comprising: (g1) Before (b), form a third dielectric film on the semiconductor substrate, wherein in (b), the third ferroelectric film is formed on the third dielectric film, and wherein in (e), the third dielectric film is processed to form a first dielectric film between the semiconductor substrate and the first ferroelectric film and a second dielectric film between the semiconductor substrate and the second ferroelectric film.

13. The method according to claim 11, comprising: (g1) Before (b), form a third dielectric film on the semiconductor substrate; (g2) After (g1) and before (b), remove a part of the third dielectric film; and (g3) After (g2) and before (b), form a fourth dielectric film on the semiconductor substrate, wherein in (b), the third ferroelectric film is formed on the third dielectric film and the fourth dielectric film, wherein in (e), the third dielectric film and the fourth dielectric film are processed to form the first dielectric film between the semiconductor substrate and the first ferroelectric film and the second dielectric film between the semiconductor substrate and the second ferroelectric film, and wherein in a direction perpendicular to the upper surface of the semiconductor substrate, the thickness of the first dielectric film is greater than the thickness of the second dielectric film.

14. The method according to claim 12, wherein the first dielectric film is formed of a silicon oxide film, and wherein the second dielectric film is formed of a silicon oxide film.

15. The method according to claim 11, wherein the first ferroelectric film includes hafnium and oxygen, and wherein the second ferroelectric film includes hafnium and oxygen.

16. The method according to claim 11, wherein in (f), an impurity region is formed in the semiconductor substrate, wherein the impurity region is disposed between the source region and the drain region.

17. The method according to claim 16, wherein the first ferroelectric film is formed on a portion of the semiconductor substrate located between the drain region and the impurity region, and wherein the second ferroelectric film is formed on a portion of the semiconductor substrate located between the source region and the impurity region.

18. The method according to claim 11, comprising: (h) After the step (b) and before the step (c), a third metal film is formed on the third ferroelectric film, wherein in the step (e), the third metal film is processed to form a first metal film between the first gate electrode and the first ferroelectric film, and a second metal film between the second gate electrode and the second ferroelectric film.

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