Semiconductor memory device and method for forming the same

Abstract

The present application provides a semiconductor memory device and a method for forming the same, relating to the field of semiconductor technology, and is intended to address the problem in existing semiconductor memory devices where both magnetic resistance and area utilization cannot be simultaneously improved. The semiconductor memory device comprises a spin-orbit moment layer, and a first magnetic tunnel junction, a second magnetic tunnel junction, and a spacer layer disposed on the spin-orbit moment layer. The second magnetic tunnel junction is disposed in a through-opening of the first magnetic tunnel junction, and the spacer layer fills the gap between the first and second magnetic tunnel junctions. The first magnetic tunnel junction surrounds the outside of the second magnetic tunnel junction, significantly improving the second magnetic tunnel junction's magnetic interference resistance. Furthermore, the sidewalls of the first magnetic tunnel junction away from the spacer layer form a circular or convex polygonal shape, and the geometric centers of the first magnetic tunnel junction and the spacer layer do not coincide, enabling the first magnetic tunnel junction to be used for field-free flipping and multi-state storage, thereby simultaneously improving the area utilization of the semiconductor memory device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor memory device and a method for forming the same. Background Art

[0002] Magnetic memory, a type of semiconductor memory, is considered a leading candidate for next-generation memory technology. The core storage unit of magnetic memory is a sandwich structure consisting of a ferromagnetic layer, an oxide barrier layer, and a ferromagnetic layer. One ferromagnetic layer, known as the pinned layer, maintains a constant magnetization direction; the other, known as the free layer, can be magnetized by external stimuli. When the free layer's magnetization direction is parallel or antiparallel to that of the pinned layer, the magnetic tunnel junction is in a low-resistance or high-resistance state, respectively. These two resistance states represent binary data "0" and "1," respectively.

[0003] The development of magnetic memory has undergone three generations of evolution, driven by different data writing mechanisms. Among them, spin-orbit moment magnetic memory, with its advantages of non-volatility, high-speed, low-power data writing, and high device durability, is a key technology that is expected to break through the power consumption bottleneck of integrated circuits in the post-Moore era. Its basic storage cell structure involves adding a spin-orbit moment layer adjacent to a free layer. Current flowing through the spin-orbit moment layer generates a spin-polarized current that flips the magnetization direction of the free layer, enabling data writing.

[0004] Since the information in the spin-orbit moment magnetic memory is stored as a magnetic signal, it is necessary to improve the magnetic interference resistance of the magnetic memory to avoid interference caused by magnetic signals from other components or magnetic signals in the environment. However, in order to enhance the anti-magnetic ability of the device, the existing technology generally considers wrapping a single chip with a high magnetic permeability material for magnetic shielding during packaging. This does not solve the mutual interference between multiple storage units within the chip, and also leads to an increase in chip area, making it difficult to increase the integration density. Although wrapping antiferromagnetic and ferromagnetic materials around the magnetic tunnel junction can improve the anti-magnetic ability, the wrapping material has no other function except magnetic shielding, which simply increases the device area. Summary of the Invention

[0005] To solve the above problems, embodiments of the present application provide a semiconductor memory device and a method for forming the same, which can improve the anti-magnetic interference capability of the semiconductor memory device while also improving its area utilization.

[0006] According to some embodiments, the embodiments of the present application provide a semiconductor memory device, comprising a spin-orbit moment layer and a first magnetic tunnel junction, a second magnetic tunnel junction and an interval layer arranged on the spin-orbit moment layer; the first magnetic tunnel junction is provided with a through opening, the second magnetic tunnel junction is provided in the through opening, and the interval layer fills the gap between the first magnetic tunnel junction and the second magnetic tunnel junction; wherein, the figure formed by the side wall of the first magnetic tunnel junction away from the interval layer is a circle or a convex polygon, and the geometric center of the first magnetic tunnel junction does not coincide with the geometric center of the interval layer.

[0007] In some possible implementations, the first magnetic tunnel junction has a first flip current, the second magnetic tunnel junction has a second flip current, and the first flip current and the second flip current are different in magnitude; wherein, the first flip current and the second flip current are made different in magnitude by adjusting the sidewall width of the spacer layer.

[0008] In some possible implementations, a first conductive terminal and a second conductive terminal are respectively arranged above the first magnetic tunnel junction and the second magnetic tunnel junction, so that the first magnetic tunnel junction and the second magnetic tunnel junction are connected in series; based on the different magnitudes of the first flip current and the second flip current, the magnitude and / or direction of the write current passed into the spin-orbit moment layer are changed so that the semiconductor memory device has a variety of resistance values.

[0009] In some possible implementations, the first magnetic tunnel junction and the second magnetic tunnel junction are provided with a common third conductive terminal so that the first magnetic tunnel junction and the second magnetic tunnel junction are connected in parallel; based on the different magnitudes of the first flip current and the second flip current, the magnitude and / or direction of the write current passed into the spin-orbit moment layer is changed so that the semiconductor memory device has a variety of resistance values.

[0010] In some possible implementations, the spacer layer is formed of an insulating material, or the first magnetic tunnel junction and the second magnetic tunnel junction are in direct contact, and the material in the transition region is rendered magnetically ineffective and insulated by ion implantation in the directly contacted transition region to form a spacer layer.

[0011] The semiconductor memory device provided by the embodiments of the present application has at least the following advantages:

[0012] The semiconductor memory device in an embodiment of the present application includes a spin-orbit moment layer, and a first magnetic tunnel junction, a second magnetic tunnel junction, and a spacer layer disposed on the spin-orbit moment layer. By forming the second magnetic tunnel junction in the through-opening of the first magnetic tunnel junction and the spacer layer filling the gap between the first and second magnetic tunnel junctions, the magnetic interference resistance of the second magnetic tunnel junction is greatly improved. Furthermore, the sidewalls of the first magnetic tunnel junction away from the spacer layer form a circular or convex polygonal shape, resulting in a circular magnetic moment distribution of the first magnetic tunnel junction and enhanced magnetic interference resistance. Furthermore, the geometric centers of the first magnetic tunnel junction and the spacer layer do not coincide, thereby breaking the magnetic symmetry between the first and second magnetic tunnel junctions, enabling field-free switching of the first magnetic tunnel junction and field-free switching of the out-of-plane magnetized second magnetic tunnel junction. Furthermore, the reading methods of the first and second magnetic tunnel junctions can be designed, so that the semiconductor memory device has multiple resistance states and realizes a multi-state storage function, thereby improving the magnetic interference resistance of the semiconductor memory device while increasing its area utilization.

[0013] According to some embodiments, the embodiments of the present application also provide a semiconductor memory device, including a spin-orbit moment layer and a first magnetic tunnel junction, at least one second magnetic tunnel junction and an interval layer arranged on the spin-orbit moment layer; the first magnetic tunnel junction is provided with a through opening, the second magnetic tunnel junction is provided in the through opening, and the interval layer fills the gap between the first magnetic tunnel junction and the second magnetic tunnel junction; wherein the geometric center of the first magnetic tunnel junction coincides with that of the interval layer; by adjusting the sidewall width of the interval layer, the resistance of the first magnetic tunnel junction is made between the maximum resistance and the minimum resistance of the second magnetic tunnel junction, and can be used as a self-reference device.

[0014] In some possible implementations, the first magnetic tunnel junction has a first resistance value, and the second magnetic tunnel junction has a second resistance value. By simultaneously reading the first resistance value and the second resistance value and comparing them, read data of the semiconductor memory device is defined based on the comparison result.

[0015] The semiconductor memory device provided by the embodiments of the present application has at least the following advantages:

[0016] The semiconductor memory device in the embodiment of the present application includes a spin-orbit moment layer and a first magnetic tunnel junction, a second magnetic tunnel junction and a spacer layer arranged on the spin-orbit moment layer. By forming the second magnetic tunnel junction in the through-opening of the first magnetic tunnel junction and the spacer layer filling the gap between the first magnetic tunnel junction and the second magnetic tunnel junction, the anti-magnetic interference capability of the second magnetic tunnel junction is greatly improved; wherein, the geometric center of the first magnetic tunnel junction coincides with the geometric center of the spacer layer, avoiding the flipping of the first magnetic tunnel junction to generate a fixed resistance value, and by adjusting the sidewall width of the spacer layer, the resistance value of the first magnetic tunnel junction is made between the maximum resistance value and the minimum resistance value of the second magnetic tunnel junction, which can be used to realize the self-reference function of the device, improving the anti-magnetic interference capability of the semiconductor memory device while improving its area utilization.

[0017] According to some embodiments, the present application also provides a method for forming a semiconductor memory device, comprising the following steps: forming an initial magnetic tunnel junction on a spin-orbit moment layer; forming an interval layer inside the initial magnetic tunnel junction, wherein the portion of the initial magnetic tunnel junction located outside the interval layer forms a first magnetic tunnel junction, and the portion of the initial magnetic tunnel junction located inside the interval layer forms a second magnetic tunnel junction; wherein the interval layer is annular and passes through the initial magnetic tunnel junction; the shape of the initial magnetic tunnel junction is circular or a convex polygon, and the geometric center of the initial magnetic tunnel junction does not coincide with that of the interval layer.

[0018] In some possible implementations, the first magnetic tunnel junction formed has a first flip current, the second magnetic tunnel junction formed has a second flip current, and the first flip current and the second flip current are different in magnitude; wherein, the first flip current and the second flip current are different in magnitude by adjusting the sidewall width of the spacer layer.

[0019] According to some embodiments, the present application also provides another method for forming a semiconductor memory device, comprising the following steps: forming an interval layer on a spin-orbit moment layer; depositing a magnetic tunnel junction film layer to cover at least the outer wall of the interval layer and the area enclosed by the inner wall of the interval layer; etching the magnetic tunnel junction film layer to form a first magnetic tunnel junction, and forming a second magnetic tunnel junction in the magnetic tunnel junction film layer in the area enclosed by the inner wall of the interval layer; wherein the interval layer is annular; the figure enclosed by the side walls of the first magnetic tunnel junction away from the interval layer is a circle or a convex polygon, and the geometric centers of the first magnetic tunnel junction and the interval layer do not coincide.

[0020] In some possible implementations, the first magnetic tunnel junction formed has a first flip current, the second magnetic tunnel junction formed has a second flip current, and the first flip current and the second flip current are different in magnitude; wherein, the first flip current and the second flip current are different in magnitude by adjusting the sidewall width of the spacer layer.

[0021] The method for forming a semiconductor memory device in the embodiment of the present application has at least the following advantages:

[0022] In the method for forming a semiconductor memory device in an embodiment of the present application, a spin-orbit moment layer is formed, and a first magnetic tunnel junction, a second magnetic tunnel junction, and a spacer layer are formed on the spin-orbit moment layer. The second magnetic tunnel junction is formed in a through-opening of the first magnetic tunnel junction, and the spacer layer fills the gap between the first and second magnetic tunnel junctions, thereby greatly improving the anti-magnetic interference capability of the second magnetic tunnel junction. Furthermore, the sidewalls of the first magnetic tunnel junction away from the spacer layer form a circular or convex polygonal shape, so that the magnetic moment of the first magnetic tunnel junction is annularly distributed, thereby enhancing the anti-magnetic capability. Furthermore, the geometric centers of the first magnetic tunnel junction and the spacer layer do not coincide, thereby breaking the magnetic symmetry of the first and second magnetic tunnel junctions, enabling field-free switching of the first magnetic tunnel junction and field-free switching of the out-of-plane magnetized second magnetic tunnel junction. Furthermore, the reading methods of the first and second magnetic tunnel junctions can be designed, so that the semiconductor memory device has multiple resistance states and realizes the function of multi-state storage, thereby improving the anti-magnetic interference capability of the semiconductor memory device while improving its area utilization. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a top view of a first semiconductor memory device in an embodiment of the present application.

[0024] Figure 2 FIG. 1 is a schematic cross-sectional view of a first semiconductor memory device according to an embodiment of the present application.

[0025] Figure 3 FIG. 1 is a schematic cross-sectional view of a second semiconductor memory device in an embodiment of the present application.

[0026] Figure 4 FIG. 1 is a top view of a third semiconductor memory device according to an embodiment of the present application.

[0027] Figure 5 This is a flow chart of a method for forming a first semiconductor memory device in an embodiment of the present application.

[0028] Figure 6 This is a top view of forming an initial magnetic tunnel junction on a spin-track moment layer in a method for forming a first semiconductor memory device in an embodiment of the present application.

[0029] Figure 7 Schematic cross-sectional view of forming an initial magnetic tunnel junction on a spin-track moment layer in a method for forming a first semiconductor memory device in an embodiment of the present application.

[0030] Figure 8 This is a flow chart of a method for forming a second semiconductor memory device in an embodiment of the present application.

[0031] Figure 9FIG1 is a top view of forming a spacer layer on a spin-track moment layer in a second method for forming a semiconductor memory device in an embodiment of the present application.

[0032] Figure 10 1 is a cross-sectional schematic diagram of forming a spacer layer on a spin-track moment layer in a method for forming a second semiconductor memory device in an embodiment of the present application.

[0033] Description of reference numerals:

[0034] 10 - spin-orbit moment layer; 20 - first magnetic tunnel junction; 30 - second magnetic tunnel junction; 40 - spacer layer; 50 - first conductive terminal; 60 - second conductive terminal; 70 - third conductive terminal; 80 - initial magnetic tunnel junction. DETAILED DESCRIPTION

[0035] Spin-orbit moment magnetic memory is a key technology that is expected to break through the power consumption bottleneck of integrated circuits in the post-Moore era due to its advantages such as non-volatility, high-speed and low-power data writing, and high device durability. Its basic storage unit structure is to add a spin-orbit moment layer adjacent to the free layer in the magnetic tunnel junction, and use the spin-polarized current generated by the current flowing through the spin-orbit moment layer to flip the magnetization direction of the free layer, thereby realizing data writing.

[0036] Since the information in the spin-orbit moment magnetic memory is stored as a magnetic signal, it is necessary to improve the magnetic interference resistance of the magnetic memory to avoid interference caused by magnetic signals from other components or magnetic signals in the environment. However, in order to enhance the anti-magnetic ability of the device, the existing technology generally considers wrapping a single chip with a high magnetic permeability material for magnetic shielding during packaging. This does not solve the mutual interference between multiple storage units within the chip, and also leads to an increase in chip area, making it difficult to increase the integration density. Although wrapping antiferromagnetic and ferromagnetic materials around the magnetic tunnel junction can improve the anti-magnetic ability, the wrapping material has no other function except magnetic shielding, which simply increases the device area.

[0037] The semiconductor memory device in an embodiment of the present application includes a spin-orbit moment layer, and a first magnetic tunnel junction, a second magnetic tunnel junction, and a spacer layer disposed on the spin-orbit moment layer. By forming the second magnetic tunnel junction in the through-opening of the first magnetic tunnel junction and the spacer layer filling the gap between the first and second magnetic tunnel junctions, the magnetic interference resistance of the second magnetic tunnel junction is greatly improved. Furthermore, the sidewalls of the first magnetic tunnel junction away from the spacer layer form a circular or convex polygonal shape, resulting in a circular magnetic moment distribution of the first magnetic tunnel junction and enhanced magnetic interference resistance. Furthermore, the geometric centers of the first magnetic tunnel junction and the spacer layer do not coincide, thereby breaking the magnetic symmetry between the first and second magnetic tunnel junctions, enabling field-free switching of the first magnetic tunnel junction and field-free switching of the out-of-plane magnetized second magnetic tunnel junction. Furthermore, the reading methods of the first and second magnetic tunnel junctions can be designed, so that the semiconductor memory device has multiple resistance states and realizes a multi-state storage function, thereby improving the magnetic interference resistance of the semiconductor memory device while increasing its area utilization.

[0038] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the embodiments described in this application are only some embodiments of the present application, not all embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0039] An embodiment of the present application provides a semiconductor memory device, comprising a spin-orbit moment layer and a first magnetic tunnel junction, a second magnetic tunnel junction and a spacer layer arranged on the spin-orbit moment layer; the first magnetic tunnel junction is provided with a through-opening, the second magnetic tunnel junction is provided in the through-opening, and the spacer layer fills the gap between the first magnetic tunnel junction and the second magnetic tunnel junction; wherein the figure formed by the side walls of the first magnetic tunnel junction away from the spacer layer is a circle or a convex polygon, and the geometric centers of the first magnetic tunnel junction and the spacer layer do not coincide.

[0040] refer to Figure 1 and Figure 2 , which are a top view and a schematic cross-sectional view of a first semiconductor memory device provided in an embodiment of the present application, the semiconductor memory device includes a spin-orbit moment layer 10 and a first magnetic tunnel junction 20, a second magnetic tunnel junction 30 and a spacer layer 40 arranged on the spin-orbit moment layer 10; the first magnetic tunnel junction 20 is provided with a through-opening, the second magnetic tunnel junction 30 is arranged in the through-opening, and the spacer layer 40 fills the gap between the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30; wherein, the figure formed by the sidewalls of the first magnetic tunnel junction 20 away from the spacer layer 40 is a circle or a convex polygon, and the geometric centers of the first magnetic tunnel junction 20 and the spacer layer 40 do not coincide.

[0041] The spin-orbit moment layer 10 is made of a material that can produce a spin-orbit moment effect, including heavy metal materials such as platinum, palladium, hafnium, gold, tantalum, tungsten, iridium, and their alloys; or topological insulators, including bismuth selenide (Bi x Se 1-x ), bismuth antimonide (Bi x Sb 1-x ), bismuth telluride-based materials (Bi, Sb) 2Te3, etc., 0<x<1; it can also be a two-dimensional material, such as molybdenum disulfide (MoS2), tungsten ditelluride (WTe2), etc.; the spin-orbit moment layer 10 can be a single-layer film or a multi-layer composite film, including a combination of two or more of the above materials.

[0042] A substrate (not shown in the figure) can also be provided under the spin-orbit moment layer 10 to support the device. The material of the substrate can be a semiconductor material, such as silicon, silicon carbide, gallium nitride, aluminum nitride, etc., or an insulating material, such as germanium; it can also be a logic substrate containing logic circuits inside; the spin-orbit moment layer 10 can completely cover the substrate or partially cover the substrate; conductive through holes can also be provided in the substrate to pass a write current into the spin-orbit moment layer 10, thereby generating a spin-orbit moment effect in the spin-orbit moment layer 10, causing the free layer magnetic moment in the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 to flip.

[0043] The first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 are both multi-layer composite structures (not shown in the figure), which include, from bottom to top: a free layer, a barrier layer and a reference layer. The free layer is adjacent to the spin-orbit moment layer 10. The materials of the free layer and the reference layer can be ferromagnetic materials, such as cobalt, iron, boron, nickel, ruthenium, iridium, platinum and other materials and their alloys, or ferrimagnetic materials; the free layer and the reference layer can be single-layer or multi-layer composite film layers; the material of the barrier layer is an insulating material, such as magnesium oxide, aluminum oxide, silicon oxide, etc.; a pinning layer can also be provided in the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30, located on the side of the reference layer away from the barrier layer to fix the magnetization direction of the reference layer. A functional layer, such as metal Hf or non-metal MgO, can be inserted between the spin-orbit moment layer 10 and the free layer to regulate the magnetic anisotropy of the free layer or the interface Rashba effect, thereby reducing the write power consumption of the free layer. In addition, a covering layer can be set above the reference layer to achieve electrical connection with the outside. The covering layer is generally a metal material, including conductive metals such as Ta, Ru, and Pt.

[0044] A through opening is provided in the first magnetic tunnel junction 20, and the through opening extends vertically through all film layers of the first magnetic tunnel junction 20. The second magnetic tunnel junction 30 is provided in the through opening, and the spacer layer 40 fills the gap between the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 to protect the second magnetic tunnel junction 30 and improve the magnetic resistance of the semiconductor memory device.

[0045] The shape formed by the sidewalls of the first magnetic tunnel junction 20 away from the spacer layer 40 is a circle or a convex polygon, where all interior angles of the convex polygon are less than 180 degrees, such as an equilateral triangle, a rectangle, a regular pentagon, etc., so that the magnetic moment of the first magnetic tunnel junction 20 is annularly distributed. Due to the closed magnetic circuit and low demagnetization factor of the annular magnet, it is more difficult for magnetization reversal to occur, thereby enhancing the anti-magnetic ability of the first magnetic tunnel junction 20. In addition, the geometric centers of the first magnetic tunnel junction 20 and the spacer layer 40 do not coincide, so that the magnetic symmetry of the first magnetic tunnel junction 20 is broken. When a write current is applied to the spin-orbit moment layer 10, the side of the first magnetic tunnel junction 20 away from the spacer layer 40 is flipped first, causing the first magnetic tunnel junction 20 to undergo deterministic flipping. The flipping process does not require external field assistance, thus achieving field-free flipping of the first magnetic tunnel junction 20. In addition, the greater the degree to which the geometric center of the first magnetic tunnel junction 20 deviates from the geometric center of the spacer layer 40, the smaller the flipping current of the first magnetic tunnel junction 20, and the easier it is to flip.

[0046] The shape of the second magnetic tunnel junction 30 can be circular, elliptical, rectangular, etc., and the direction of its magnetic moment can be in-plane magnetization or out-of-plane magnetization. Figure 1 The elliptical shape of the second magnetic tunnel junction 30 shown in the top view is merely an example and is not intended to limit its shape. When the second magnetic tunnel junction 30 is an out-of-plane magnetized device, the geometric centers of the first magnetic tunnel junction 20 and the spacer layer 40 do not coincide, breaking the magnetic symmetry of the second magnetic tunnel junction 30 and thereby achieving field-free flipping of the second magnetic tunnel junction 30.

[0047] The spacer layer 40 fills the gap between the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30, and is made of an insulating material, such as silicon oxide, silicon nitride, etc. Alternatively, when forming the semiconductor memory device, the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 are made in direct contact, and the material in the transition region is magnetically inactivated and insulated by ion implantation in the directly contacted transition region to form the spacer layer 40. Those skilled in the art can select an appropriate formation method according to actual needs during the actual formation process, and no limitation is imposed on the formation method of the spacer layer 40 herein.

[0048] The spacer layer 40 is annular, such as a circular ring or a square ring. The shapes of the inner and outer side walls of the annular spacer layer 40 may be different, and its specific shape depends on the shapes of the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30. Preferably, the area of the second magnetic tunnel junction 30 and the spacer layer 40 does not exceed half of the total area of the first magnetic tunnel junction 20, the second magnetic tunnel junction 30, and the spacer layer 40, to ensure that the magnetic moment of the outer first magnetic tunnel junction 20 is annularly distributed and has a good field-free switching effect.

[0049] Continue to refer Figure 1 and Figure 2 The first magnetic tunnel junction 20 has a first switching current, denoted as I1, and the second magnetic tunnel junction 30 has a second switching current, denoted as I2. When the overall area of the first magnetic tunnel junction 20, the second magnetic tunnel junction 30 and the spacer layer 40 remains unchanged, the area of the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 can be adjusted by adjusting the sidewall width w of the spacer layer 40, so that the first switching current I1 and the second switching current I2 are different in size.

[0050] In the semiconductor memory device of this embodiment, the reading method of the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 used for magnetic shielding can also be designed to improve the area utilization. Figure 2 As shown, a first conductive terminal 50 and a second conductive terminal 60 may be respectively provided above the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 to respectively implement data reading of the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30. The function of the first conductive terminal 50 and the second conductive terminal 60 is to conduct electricity to form a reading path, and the shape thereof may be a rectangle, a trapezoid, a triangle, or the like. Figure 2 The figure is only an example of the location of the first conductive terminal 50 and the second conductive terminal 60, and is not a limitation on their shapes. Based on the different sizes of the first flip current I1 and the second flip current I2, by changing the size and / or direction of the write current I passed into the spin-orbit moment layer 10, the semiconductor memory device has a variety of resistance values and can realize polymorphic storage.

[0051] Specifically, by adjusting the sidewall width w of the spacer layer 40, the first switching current I1 is made greater than the second switching current I2. By changing the magnitude or direction of the write current I supplied to the spin-track moment layer 10, the semiconductor memory device has at least three resistance values. By adjusting both the magnitude and direction of the write current I, the semiconductor memory device has at least four resistance values. The specific process of achieving multiple resistance values in the semiconductor memory device is as follows:

[0052] In the initial state, the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 are both in low resistance state, with resistance values of R P1 and R P2When a write current I is applied to the spin-orbit moment layer 10 along the first direction, so that I1<I<I2, the free layer of the first magnetic tunnel junction 20 does not flip, and the resistance is R P1 The free layer of the second magnetic tunnel junction 30 flips and becomes a high resistance state with a resistance of R AP2 Continue to increase the write current I in the first direction, so that I>I2, the free layer of the first magnetic tunnel junction 20 is flipped, and the resistance is R AP1 , the resistance of the second magnetic tunnel junction 30 is still R AP2 When a second write current I in the opposite direction is applied to the spin-track moment layer 10 反向 When I1<I 反向 <I2, the free layer of the first magnetic tunnel junction 20 does not flip, and the resistance remains R AP1 The free layer of the second magnetic tunnel junction 30 flips and becomes a low resistance state with a resistance of R P2 ; Continue to increase the write current I along the second direction 反向 , making I 反向 >I2, the free layer of the first magnetic tunnel junction 20 is reversed, and the resistance is R P1 , the resistance of the second magnetic tunnel junction 30 is still R P2 .

[0053] Similarly, by adjusting the sidewall width w of the spacer layer 40, the first flip current I1 is made smaller than the second flip current I2. Based on the different sizes of the first flip current I1 and the second flip current I2, by changing the size and / or direction of the write current I passed into the spin-orbit moment layer 10, the semiconductor memory device can also have a variety of resistance values. The writing principle and specific process can be referred to the above description and will not be repeated here.

[0054] In addition, the first conductive terminal 50 and the second conductive terminal 60 above the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 can be connected in series. Based on the different sizes of the first flip current I1 and the second flip current I2, by changing the size and / or direction of the write current I passed into the spin-track moment layer 10, the semiconductor memory device has multiple resistance values, and the total resistance of the semiconductor memory device is the series resistance of the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30.

[0055] Specifically, by adjusting the sidewall width w of the spacer layer 40, the first switching current I1 is made greater than the second switching current I2, and the read current flows between the first conductive terminal 50 and the second conductive terminal 60, forming a series read circuit. In the initial state, the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 are both in a low resistance state, with resistance values of R P1 and R P2 , the total resistance of the semiconductor memory device R = R P1 +R P2When a write current I is applied to the spin-orbit moment layer 10 along the first direction, so that I1<I<I2, the free layer of the first magnetic tunnel junction 20 does not flip, and the resistance is R P1 The free layer of the second magnetic tunnel junction 30 flips and becomes a high resistance state with a resistance of R AP2 , the total resistance of the semiconductor memory device R = R P1 + R AP2 Continue to increase the write current I in the first direction, so that I>I2, the free layer of the first magnetic tunnel junction 20 is flipped, and the resistance is R AP1 , the resistance of the second magnetic tunnel junction 30 is still R AP2 , the total resistance of the semiconductor memory device R = R AP1 + R AP2 When a second write current I in the opposite direction is applied to the spin-track moment layer 10 反向 When I1<I 反向 <I2, the free layer of the first magnetic tunnel junction 20 does not flip, and the resistance remains R AP1 The free layer of the second magnetic tunnel junction 30 flips and becomes a low resistance state with a resistance of R P2 , the total resistance of the semiconductor memory device R = R AP1 + R P2 ; Continue to increase the write current I along the second direction 反向 , making I 反向 >I2, the free layer of the first magnetic tunnel junction 20 is reversed, and the resistance is R P1 , the resistance of the second magnetic tunnel junction 30 is still R P2 , at this time the semiconductor memory device returns to its initial state, the total resistance R = R P1 +R P2 .

[0056] In addition, a common third conductive terminal 70 may be provided above the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 so that the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 are connected in parallel. The cross-sectional view of the second semiconductor memory device finally formed is shown in FIG. Figure 3 As shown, the function of the third conductive terminal 70 is to conduct electricity to form a reading path, and its shape can be a rectangle, trapezoid, triangle, etc. Figure 3 The figure is only an example of the setting position of the third conductive terminal 70 and is not a limitation on its shape; based on the different sizes of the first flip current I1 and the second flip current I2, the size and / or direction of the write current I passed into the spin-track moment layer 10 are changed, and the semiconductor memory device can have a variety of resistance values, wherein the total resistance R of the semiconductor memory device is the parallel resistance of the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30.

[0057] Specifically, by adjusting the sidewall width w of the spacer layer 40, the first switching current I1 is made greater than the second switching current I2, and the reading current flows between one end of the spin-track moment layer 10 and the third conductive terminal 70 to form a reading path, reading the parallel resistance of the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30. In the initial state, the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 are both in a low resistance state, with resistance values of R P1 and R P2 , the total resistance of the semiconductor memory device When a write current I is applied to the spin-orbit moment layer 10 along the first direction, so that I1<I<I2, the free layer of the first magnetic tunnel junction 20 does not flip, and the resistance is R P1 The free layer of the second magnetic tunnel junction 30 flips and becomes a high resistance state with a resistance of R AP2 , the total resistance of the semiconductor memory device Continue to increase the write current I in the first direction, so that I>I2, the free layer of the first magnetic tunnel junction 20 is flipped, and the resistance is R AP1 , the resistance of the second magnetic tunnel junction 30 is still R AP2 , the total resistance of the semiconductor memory device When a second write current I in the opposite direction is applied to the spin-track moment layer 10 反向 When I1<I 反向 <I2, the free layer of the first magnetic tunnel junction 20 does not flip, and the resistance remains R AP1 The free layer of the second magnetic tunnel junction 30 flips and becomes a low resistance state with a resistance of R P2 , the total resistance of the semiconductor memory device ; Continue to increase the write current I along the second direction 反向 , making I 反向 >I2, the free layer of the first magnetic tunnel junction 20 is reversed, and the resistance is R P1 , the resistance of the second magnetic tunnel junction 30 is still R P2 , at this time the semiconductor memory device returns to its initial state, the total resistance .

[0058] The first and second semiconductor memory devices provided in the embodiments of the present application include a spin-orbit moment layer 10 and a first magnetic tunnel junction 20, a second magnetic tunnel junction 30, and a spacer layer 40 disposed on the spin-orbit moment layer 10. The second magnetic tunnel junction 30 is formed in a through-opening of the first magnetic tunnel junction 20, and the spacer layer 40 fills the gap between the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30, thereby greatly improving the anti-magnetic interference capability of the second magnetic tunnel junction 30. In addition, the sidewalls of the first magnetic tunnel junction 20 away from the spacer layer 40 are arranged to form a circular or convex polygonal shape, so that the magnetic moment of the first magnetic tunnel junction 20 is annularly distributed. Due to the closed magnetic circuit and low demagnetization factor of the annular magnet, it is more difficult for magnetization reversal to occur, and the anti-magnetic ability of the first magnetic tunnel junction 20 is enhanced; and the geometric centers of the first magnetic tunnel junction 20 and the spacer layer 40 do not coincide, so that the magnetic symmetry of the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 is broken, which can achieve field-free reversal of the first magnetic tunnel junction 20 and field-free reversal of the out-of-plane magnetized second magnetic tunnel junction 30; in addition, the reading method of the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 can be designed so that the semiconductor memory device has multiple resistance states and realizes the function of multi-state storage, thereby improving the anti-magnetic interference ability of the semiconductor memory device while improving its area utilization.

[0059] An embodiment of the present application also provides a third semiconductor memory device, including a spin-orbit moment layer and a first magnetic tunnel junction, at least one second magnetic tunnel junction and a spacer layer arranged on the spin-orbit moment layer; the first magnetic tunnel junction is provided with a through-opening, the second magnetic tunnel junction is provided in the through-opening, and the spacer layer fills the gap between the first magnetic tunnel junction and the second magnetic tunnel junction; wherein the geometric center of the first magnetic tunnel junction coincides with that of the spacer layer; by adjusting the sidewall width of the spacer layer, the resistance of the first magnetic tunnel junction is made between the maximum resistance and the minimum resistance of the second magnetic tunnel junction, and the first magnetic tunnel junction can be used as a self-reference device.

[0060] refer to Figure 4 The top view shown is different from the first semiconductor memory device of the embodiment of the present application. In the third semiconductor memory device provided by the embodiment of the present application, the through opening of the first magnetic tunnel junction 20 includes at least one second magnetic tunnel junction 30, and the geometric center of the first magnetic tunnel junction 20 coincides with the geometric center of the spacer layer 40; by adjusting the sidewall width of the spacer layer 40, the resistance of the first magnetic tunnel junction 20 is between the maximum resistance and the minimum resistance of the second magnetic tunnel junction 30, and can be used as a self-reference device.

[0061] Among them, since the first magnetic tunnel junction 20 is used as a reference device, there is no need to flip the direction of the free layer magnetic moment of the first magnetic tunnel junction 20. By setting the geometric center of the first magnetic tunnel junction 20 to coincide with the geometric center of the spacer layer 40, the magnetic moment of the first magnetic tunnel junction 20 will not be offset and its free layer will not be flipped, and its resistance will not change with changes in the external field and the write current; the shape of the first magnetic tunnel junction 20 can be unrestricted, such as circular, elliptical, square, etc., preferably circular, so that the first magnetic tunnel junction 20 can generate a ring-shaped uniform magnetic moment, and the resistance value has better stability.

[0062] By adjusting the sidewall width of the spacer layer 40 , the resistance of the first magnetic tunnel junction 20 can be adjusted so that its resistance is between the maximum resistance and the minimum resistance of the second magnetic tunnel junction 30 , thereby achieving self-referencing of the semiconductor memory device.

[0063] Specifically, the resistance value of the first magnetic tunnel junction 20 is recorded as a first resistance value, and the magnitude of the first resistance value is between the maximum resistance value and the minimum resistance value of the second magnetic tunnel junction 30, and the second magnetic tunnel junction 30 has a second resistance value; when reading, the first resistance value and the second resistance value are read simultaneously and compared, and the read data of the semiconductor memory device is defined based on the comparison result: if the first resistance value is greater than the second resistance value, the second magnetic tunnel junction 30 is in a low resistance state, and the semiconductor memory device reads it as data "1"; if the first resistance value is less than the second resistance value, the second magnetic tunnel junction 30 is in a high resistance state, and the semiconductor memory device reads it as data "0"; alternatively, if the first resistance value is greater than the second resistance value, the second magnetic tunnel junction 30 is in a low resistance state, and the semiconductor memory device reads it as data "0"; if the first resistance value is less than the second resistance value, the second magnetic tunnel junction 30 is in a high resistance state, and the semiconductor memory device reads it as data "1". The read data of the semiconductor memory device can also be defined based on the comparison result according to actual usage requirements.

[0064] The number of second magnetic tunnel junctions 30 can be one or more, and multiple second magnetic tunnel junctions 30 can be arranged in an array or in an arrangement designed according to actual needs; conductive terminals (not shown in the figure) are respectively provided above the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 to electrically connect to the external circuit to realize data reading. When there are multiple second magnetic tunnel junctions 30, each second magnetic tunnel junction 30 can be compared with the same first magnetic tunnel junction 20 for resistance value. Compared with the existing self-reference device in which each storage unit needs to be provided with a corresponding reference device, it not only saves the unit area, but also reduces the number of openings of the top electrode, which simplifies the formation process and is also conducive to device integration.

[0065] The third semiconductor memory device provided by the embodiment of the present application greatly improves the anti-magnetic interference capability of the second magnetic tunnel junction 30 by forming the second magnetic tunnel junction 30 in the through-opening of the first magnetic tunnel junction 20, and the spacer layer 40 fills the gap between the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30. The geometric centers of the first magnetic tunnel junction 20 and the spacer layer 40 coincide with each other, thereby preventing the first magnetic tunnel junction 20 from flipping to produce a fixed resistance value. By adjusting the sidewall width of the spacer layer 40, the resistance value of the first magnetic tunnel junction 20 is adjusted to be between the maximum resistance value and the minimum resistance value of the second magnetic tunnel junction 30, which can be used to realize a self-reference function, thereby improving the anti-magnetic interference capability of the semiconductor memory device and improving its area utilization. In addition, multiple second magnetic tunnel junctions 30 can be compared with the same first magnetic tunnel junction 20 for resistance, which not only saves unit area but also reduces the number of openings of the top electrode, simplifies the formation process and facilitates device integration.

[0066] On the other hand, the embodiment of the present application further provides a method for forming a semiconductor memory device. The flow chart of the first method for forming a semiconductor memory device is shown in FIG. Figure 5 , including the following steps:

[0067] Step S10: forming an initial magnetic tunnel junction on the spin-orbit moment layer;

[0068] Step S20: forming a spacer layer inside the initial magnetic tunnel junction, wherein the portion of the initial magnetic tunnel junction located outside the spacer layer forms a first magnetic tunnel junction, and the portion of the initial magnetic tunnel junction located inside the spacer layer forms a second magnetic tunnel junction; wherein the spacer layer is annular and passes through the initial magnetic tunnel junction; the shape of the initial magnetic tunnel junction is circular or a convex polygon, and the geometric centers of the initial magnetic tunnel junction and the spacer layer do not coincide.

[0069] For step S10, see Figure 6 and Figure 7 The specific steps are: depositing a magnetic tunnel junction film layer (not shown in the figure) above the spin-orbit moment layer 10, etching the magnetic tunnel junction film layer to form an initial magnetic tunnel junction 80, and the shape of the formed initial magnetic tunnel junction 80 is circular or convex polygonal.

[0070] The spin-orbit moment layer 10 is made of a material that can produce a spin-orbit moment effect, including heavy metal materials such as platinum, palladium, hafnium, gold, tantalum, tungsten, iridium, and their alloys; or topological insulators, including bismuth selenide (Bi x Se 1-x ), bismuth antimonide (Bi x Sb 1-x), bismuth telluride-based materials (Bi, Sb) 2Te3, etc., 0<x<1; it can also be a two-dimensional material, such as molybdenum disulfide (MoS2), tungsten ditelluride (WTe2), etc.; the spin-orbit moment layer 10 can be a single-layer film or a multi-layer composite film, including a combination of two or more of the above materials.

[0071] The initial magnetic tunnel junction 80 is a multi-layer composite structure (not shown), comprising, from bottom to top, a free layer, a barrier layer, and a reference layer. The free layer is adjacent to the spin-orbit moment layer 10. Both the free and reference layers can be made of ferromagnetic materials, such as cobalt, iron, boron, nickel, ruthenium, iridium, platinum, and their alloys, or ferrimagnetic materials. The free and reference layers can be single or multi-layer composite films. The barrier layer is made of insulating materials, such as magnesium oxide, aluminum oxide, or silicon oxide. A pinning layer can also be included in the initial magnetic tunnel junction 80. This layer is located on the side of the reference layer away from the barrier layer to pin the magnetization of the reference layer. Other functional layers, such as metallic Hf or non-metallic MgO, can be inserted between the spin-orbit moment layer 10 and the free layer to modulate the magnetic anisotropy of the free layer or the interfacial Rashba effect, thereby reducing write power consumption in the free layer. Furthermore, a capping layer can be placed above the reference layer to provide external electrical connection. The capping layer is typically made of a conductive metal, such as Ta, Ru, or Pt.

[0072] Regarding step S20, the top view and cross-sectional view of the finally formed semiconductor memory device can be referred to respectively. Figure 1 and Figure 2 As shown, by forming a spacer layer 40 inside the initial magnetic tunnel junction 80, the part of the initial magnetic tunnel junction 80 located outside the spacer layer 40 forms the first magnetic tunnel junction 20, and the part of the initial magnetic tunnel junction 80 located inside the spacer layer 40 forms the second magnetic tunnel junction 30; wherein, the spacer layer 40 is annular and passes through the initial magnetic tunnel junction 80; the geometric centers of the initial magnetic tunnel junction 80 and the spacer layer 40 do not coincide.

[0073] The method for forming the spacer layer 40 inside the initial magnetic tunnel junction 80 can be etching. First, a gap where the spacer layer 40 is located is formed inside the initial magnetic tunnel junction 80 through an etching process. The gap is annular and runs through the initial magnetic tunnel junction 80. Then, an insulating material, such as silicon oxide, silicon nitride, etc., is filled in the gap to form the spacer layer 40. Alternatively, a target area where the spacer layer 40 is located is preset inside the initial magnetic tunnel junction 80, and ion implantation is performed on the target area to render the material in the target area magnetically ineffective and insulated to form the spacer layer 40. Those skilled in the art can reasonably select the formation method according to actual needs during the actual manufacturing process. No limitation is imposed on the formation method of the spacer layer 40 herein. The spacer layer 40 fills the gap between the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 to protect the second magnetic tunnel junction 30 and improve the anti-magnetic capability of the semiconductor memory device.

[0074] The spacer layer 40 is formed in an annular shape, such as a circular ring or a square ring. The shapes of the inner and outer side walls of the annular spacer layer 40 may be different, and its specific shape depends on the shapes of the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30. Preferably, the area of the second magnetic tunnel junction 30 and the spacer layer 40 does not exceed half of the total area of the first magnetic tunnel junction 20, the second magnetic tunnel junction 30, and the spacer layer 40, so as to ensure that the magnetic moment of the first magnetic tunnel junction 20 is annularly distributed and has a good field-free switching effect.

[0075] Continue to refer Figure 1 and Figure 2 Since the initial magnetic tunnel junction 80 is a circle or a convex polygon, the sidewall of the first magnetic tunnel junction 20 away from the spacer layer 40 forms a circle or a convex polygon. A convex polygon is a polygon with all internal angles less than 180 degrees, such as an equilateral triangle, a rectangle, a regular pentagon, etc., so that the magnetic moment of the first magnetic tunnel junction 20 is annular. Due to the closed magnetic circuit and low demagnetization factor of the annular magnet, it is more difficult for magnetization reversal to occur, and the anti-magnetic ability of the first magnetic tunnel junction 20 is enhanced. In addition, the first magnetic tunnel junction 20 and the spacer layer 40 are connected. The geometric centers of the spacer layer 40 do not overlap, so that the magnetic symmetry of the first magnetic tunnel junction 20 is broken. When a write current is applied to the spin-orbit moment layer 10, the side of the first magnetic tunnel junction 20 away from the spacer layer 40 is flipped first, causing the first magnetic tunnel junction 20 to undergo a deterministic flip. The flipping process does not require external field assistance, thereby realizing a field-free flip of the first magnetic tunnel junction 20. Moreover, the greater the degree to which the geometric center of the first magnetic tunnel junction 20 deviates from the geometric center of the spacer layer 40, the smaller the flipping current of the first magnetic tunnel junction 20, and the easier it is to be flipped.

[0076] The shape of the second magnetic tunnel junction 30 can be circular, elliptical, rectangular, etc., and the direction of its magnetic moment can be in-plane magnetization or out-of-plane magnetization. Figure 1The elliptical shape of the second magnetic tunnel junction 30 shown in the top view is merely an example and is not intended to limit its shape. When the second magnetic tunnel junction 30 is an out-of-plane magnetized device, the geometric centers of the first magnetic tunnel junction 20 and the spacer layer 40 do not coincide, breaking the magnetic symmetry of the second magnetic tunnel junction 30 and thereby achieving field-free flipping of the second magnetic tunnel junction 30.

[0077] A substrate (not shown in the figure) can also be provided under the spin-orbit moment layer 10 to support the device. The material of the substrate can be a semiconductor material, such as silicon, silicon carbide, gallium nitride, aluminum nitride, etc., or an insulating material, such as germanium; it can also be a logic substrate containing logic circuits inside; the spin-orbit moment layer 10 can completely cover the substrate or partially cover the substrate; conductive through holes can also be provided in the substrate to pass a write current into the spin-orbit moment layer 10, thereby generating a spin-orbit moment effect in the spin-orbit moment layer 10, causing the free layer magnetic moment in the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 to flip.

[0078] Continue to refer Figure 1 and Figure 2 The first magnetic tunnel junction 20 has a first switching current, denoted as I1, and the second magnetic tunnel junction 30 has a second switching current, denoted as I2. When the overall area of the first magnetic tunnel junction 20, the second magnetic tunnel junction 30 and the spacer layer 40 remains unchanged, the area of the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 can be changed by adjusting the sidewall width w of the spacer layer 40, so that the first switching current I1 and the second switching current I2 are different in size.

[0079] In the method for forming the semiconductor memory device of this embodiment, a reading method for the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 for magnetic shielding can be designed to improve the anti-magnetic interference capability of the semiconductor memory device while improving its area utilization. Figure 2 As shown, a first conductive terminal 50 and a second conductive terminal 60 can be formed above the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30, respectively, to respectively realize data reading of the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30. The function of the first conductive terminal 50 and the second conductive terminal 60 is to conduct electricity to form a reading path, and the shape thereof can be a variety of shapes such as a rectangle, a trapezoid, and a triangle. Figure 2 The figure is only an example of the location of the first conductive terminal 50 and the second conductive terminal 60, and is not a limitation on their shapes. Based on the different sizes of the first flip current I1 and the second flip current I2, by changing the size and / or direction of the write current I passed into the spin-orbit moment layer 10, the semiconductor memory device has a variety of resistance values and can realize polymorphic storage.

[0080] Specifically, by adjusting the sidewall width w of the spacer layer 40, the first switching current I1 is made greater than the second switching current I2. By changing the magnitude or direction of the write current I supplied to the spin-track moment layer 10, the semiconductor memory device has at least three resistance values. By adjusting both the magnitude and direction of the write current I, the semiconductor memory device has at least four resistance values. The specific process of achieving multiple resistance values in the semiconductor memory device is as follows:

[0081] In the initial state, the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 are both in low resistance state, with resistance values of R P1 and R P2 When a write current I is applied to the spin-orbit moment layer 10 along the first direction, so that I1<I<I2, the free layer of the first magnetic tunnel junction 20 does not flip, and the resistance is R P1 The free layer of the second magnetic tunnel junction 30 flips and becomes a high resistance state with a resistance of R AP2 Continue to increase the write current I in the first direction, so that I>I2, the free layer of the first magnetic tunnel junction 20 is flipped, and the resistance is R AP1 , the resistance of the second magnetic tunnel junction 30 is still R AP2 When a second write current I in the opposite direction is applied to the spin-track moment layer 10 反向 When I1<I 反向 <I2, the free layer of the first magnetic tunnel junction 20 does not flip, and the resistance remains R AP1 The free layer of the second magnetic tunnel junction 30 flips and becomes a low resistance state with a resistance of R P2 ; Continue to increase the write current I along the second direction 反向 , making I 反向 >I2, the free layer of the first magnetic tunnel junction 20 is reversed, and the resistance is R P1 , the resistance of the second magnetic tunnel junction 30 is still R P2 .

[0082] Similarly, by adjusting the sidewall width w of the spacer layer 40, the first flip current I1 is made smaller than the second flip current I2. Based on the different sizes of the first flip current I1 and the second flip current I2, by changing the size and / or direction of the write current I passed into the spin-orbit moment layer 10, the semiconductor memory device can also have a variety of resistance values. The writing principle and specific process can be referred to the above description and will not be repeated here.

[0083] In addition, the first conductive terminal 50 and the second conductive terminal 60 above the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 can be connected in series. Based on the different sizes of the first flip current I1 and the second flip current I2, by changing the size and / or direction of the write current I passed into the spin-track moment layer 10, the semiconductor memory device has multiple resistance values, and the total resistance of the semiconductor memory device is the series resistance of the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30.

[0084] Specifically, by adjusting the sidewall width w of the spacer layer 40, the first switching current I1 is made greater than the second switching current I2, and the read current flows between the first conductive terminal 50 and the second conductive terminal 60, forming a series read circuit. In the initial state, the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 are both in a low resistance state, with resistance values of R P1 and R P2 , the total resistance of the semiconductor memory device R = R P1 +R P2 When a write current I is applied to the spin-orbit moment layer 10 along the first direction, so that I1<I<I2, the free layer of the first magnetic tunnel junction 20 does not flip, and the resistance is R P1 The free layer of the second magnetic tunnel junction 30 flips and becomes a high resistance state with a resistance of R AP2 , the total resistance of the semiconductor memory device R = R P1 + R AP2 Continue to increase the write current I in the first direction, so that I>I2, the free layer of the first magnetic tunnel junction 20 is flipped, and the resistance is R AP1 , the resistance of the second magnetic tunnel junction 30 is still R AP2 , the total resistance of the semiconductor memory device R = R AP1 + R AP2 When a second write current I in the opposite direction is applied to the spin-track moment layer 10 反向 When I1<I 反向 <I2, the free layer of the first magnetic tunnel junction 20 does not flip, and the resistance remains R AP1 The free layer of the second magnetic tunnel junction 30 flips and becomes a low resistance state with a resistance of R P2 , the total resistance of the semiconductor memory device R = R AP1 + R P2 ; Continue to increase the write current I along the second direction 反向 , making I 反向 >I2, the free layer of the first magnetic tunnel junction 20 is reversed, and the resistance is R P1 , the resistance of the second magnetic tunnel junction 30 is still R P2 , at this time the semiconductor memory device returns to its initial state, the total resistance R = R P1 +R P2 .

[0085] In addition, a common third conductive terminal can be provided above the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 so that the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 are connected in parallel. The cross-sectional view of the second semiconductor memory device finally formed is shown in FIG. Figure 3 As shown, the function of the third conductive terminal 70 is to conduct electricity to form a reading path, and its shape can be a rectangle, trapezoid, triangle, etc. Figure 3 The figure is only an example of the setting position of the third conductive terminal 70 and is not a limitation on its shape; based on the different sizes of the first flip current I1 and the second flip current I2, the size and / or direction of the write current I passed into the spin-track moment layer 10 are changed, and the semiconductor memory device can have a variety of resistance values, wherein the total resistance R of the semiconductor memory device is the parallel resistance of the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30.

[0086] Specifically, by adjusting the sidewall width w of the spacer layer 40, the first switching current I1 is made greater than the second switching current I2, and the reading current flows between one end of the spin-track moment layer 10 and the third conductive terminal 70 to form a reading path, reading the parallel resistance of the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30. In the initial state, the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 are both in a low resistance state, with resistance values of R P1 and R P2 , the total resistance of the semiconductor memory device When a write current I is applied to the spin-orbit moment layer 10 along the first direction, so that I1<I<I2, the free layer of the first magnetic tunnel junction 20 does not flip, and the resistance is R P1 The free layer of the second magnetic tunnel junction 30 flips and becomes a high resistance state with a resistance of R AP2 , the total resistance of the semiconductor memory device Continue to increase the write current I in the first direction, so that I>I2, the free layer of the first magnetic tunnel junction 20 is flipped, and the resistance is R AP1 , the resistance of the second magnetic tunnel junction 30 is still R AP2 , the total resistance of the semiconductor memory device When a second write current I in the opposite direction is applied to the spin-track moment layer 10 反向 When I1<I 反向 <I2, the free layer of the first magnetic tunnel junction 20 does not flip, and the resistance remains R AP1 The free layer of the second magnetic tunnel junction 30 flips and becomes a low resistance state with a resistance of R P2 , the total resistance of the semiconductor memory device ; Continue to increase the write current I along the second direction 反向 , making I 反向>I2, the free layer of the first magnetic tunnel junction 20 is reversed, and the resistance is R P1 , the resistance of the second magnetic tunnel junction 30 is still R P2 , at this time the semiconductor memory device returns to its initial state, the total resistance .

[0087] In order to form the device described in the first method for forming a semiconductor memory device, the present invention also provides another method for forming a semiconductor memory device. The flow chart of the second method for forming a semiconductor memory device is shown in FIG. Figure 8 , including the following steps:

[0088] Step S10: forming a spacer layer on the spin-orbit moment layer, wherein the spacer layer is ring-shaped;

[0089] Step S20: depositing a magnetic tunnel junction film layer to at least cover the outer wall of the spacer layer and the area enclosed by the inner wall of the spacer layer;

[0090] Step S30: Etching the magnetic tunnel junction film layer to form a first magnetic tunnel junction, and the magnetic tunnel junction film layer in the area enclosed by the inner side wall of the spacer layer forms a second magnetic tunnel junction; wherein, the figure enclosed by the side wall of the first magnetic tunnel junction away from the spacer layer is a circle or a convex polygon, and the geometric center of the first magnetic tunnel junction does not coincide with the geometric center of the spacer layer.

[0091] In step S10, a ring-shaped spacer layer is formed on the spin-orbit moment layer. The forming method adopted can be to first form an overall insulating material and then etch the insulating material to form the spacer layer. Alternatively, a photoresist is first used to cover the area where the spacer layer is not required. After depositing the insulating material, the photoresist and the insulating material on the photoresist are removed to form the spacer layer. The top view and the cross-sectional view of the semiconductor memory device formed in this step can be referred to respectively. Figure 9 and Figure 10 .

[0092] The magnetic tunnel junction film layer deposited in step S20 is the same as the magnetic tunnel junction film layer deposited when forming the initial magnetic tunnel junction in the first method for forming a semiconductor memory device, and will not be repeated here; the deposited magnetic tunnel junction film layer at least covers the outer wall of the spacer layer and the area enclosed by the inner wall of the spacer layer, so as to form the first magnetic tunnel junction and the second magnetic tunnel junction in the subsequent manufacturing process.

[0093] The semiconductor memory device finally formed by the formation method of this embodiment can be referred to Figure 1 The top view and Figure 2In the device cross-sectional view shown, the sidewalls of the first magnetic tunnel junction 20 away from the spacer layer 40 form a circular or convex polygon, so that the magnetic moment of the first magnetic tunnel junction 20 is annularly distributed. Due to the closed magnetic circuit and low demagnetization factor of the annular magnet, it is more difficult for magnetization reversal to occur, and the anti-magnetic ability of the first magnetic tunnel junction 20 is enhanced. In addition, the geometric centers of the first magnetic tunnel junction 20 and the spacer layer 40 do not coincide, so that the magnetic symmetry of the first magnetic tunnel junction 20 is broken. When a write current is applied to the spin-orbit moment layer 10, the side of the first magnetic tunnel junction 20 away from the spacer layer 40 is flipped first, causing the first magnetic tunnel junction 20 to undergo deterministic flipping. The flipping process does not require external field assistance, achieving field-free flipping of the first magnetic tunnel junction 20. In addition, the greater the degree to which the geometric center of the first magnetic tunnel junction 20 deviates from the geometric center of the spacer layer 40, the smaller the flipping current of the first magnetic tunnel junction 20, and the easier it is to be flipped.

[0094] The shape of the second magnetic tunnel junction 30 can be circular, elliptical, rectangular, etc., and the direction of its magnetic moment can be in-plane magnetization or out-of-plane magnetization. When the second magnetic tunnel junction 30 is an out-of-plane magnetized device, the geometric centers of the first magnetic tunnel junction 20 and the spacer layer 40 do not coincide, which can break the magnetic symmetry of the second magnetic tunnel junction 30, thereby realizing field-free flipping of the second magnetic tunnel junction 30.

[0095] The semiconductor memory device formed by the formation method of this embodiment can also realize polymorphic storage of the semiconductor memory device by designing the reading method of the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30, such as reading the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 separately, reading the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 in series, reading the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 in parallel, etc., thereby improving the anti-magnetic interference capability of the semiconductor memory device and improving its area utilization. The specific implementation method and related mechanism have been explained in detail when describing the formation method of the first semiconductor memory device, and will not be repeated here.

[0096] The first and second methods for forming semiconductor memory devices of the present invention are as follows: by filling the gap between the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 with the spacer layer 40, the anti-magnetic interference capability of the second magnetic tunnel junction 30 is greatly improved; and by setting the sidewall of the first magnetic tunnel junction 20 away from the spacer layer 40 to form a circular or convex polygon, the magnetic moment of the first magnetic tunnel junction 20 is annularly distributed. The annular magnet is more difficult to undergo magnetization reversal due to its closed magnetic circuit and low demagnetization factor, and the anti-magnetic interference capability of the first magnetic tunnel junction 20 is greatly improved. The capability is enhanced; and the geometric centers of the first magnetic tunnel junction 20 and the spacer layer 40 do not coincide, so that the magnetic symmetry of the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 is broken, and the field-free flipping of the first magnetic tunnel junction 20 and the field-free flipping of the out-of-plane magnetized second magnetic tunnel junction 30 can be realized; moreover, the reading method of the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 can be designed, so that the semiconductor memory device has multiple resistance states, realizes the function of multi-state storage, and improves its area utilization while improving the anti-magnetic interference capability of the semiconductor memory device.

[0097] An embodiment of the present application also provides a third method for forming a semiconductor memory device, which differs from the first method for forming a semiconductor memory device in that: after forming an initial magnetic tunnel junction, an interval layer is formed inside the initial magnetic tunnel junction, the interval layer penetrates the initial magnetic tunnel junction and causes the portion of the initial magnetic tunnel junction located outside the interval layer to form a first magnetic tunnel junction, and the portion of the initial magnetic tunnel junction located inside the interval layer to form at least one second magnetic tunnel junction; wherein the geometric center of the initial magnetic tunnel junction coincides with that of the interval layer; by adjusting the sidewall width of the interval layer, the resistance of the first magnetic tunnel junction is made between the maximum resistance and the minimum resistance of the second magnetic tunnel junction, and can be used as a self-reference device.

[0098] The semiconductor memory device finally formed by the formation method of this embodiment can be referred to Figure 4 As shown in the top view, the spacer layer 40 runs through the first magnetic tunnel junction 20, that is, the spacer layer 40 extends vertically through all film layers of the first magnetic tunnel junction 20, at least one second magnetic tunnel junction 30 is arranged in the through opening formed by the spacer layer 40, and the spacer layer 40 fills the gap between the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 to protect the second magnetic tunnel junction 30 and improve the magnetic resistance of the semiconductor memory device.

[0099] Since the first magnetic tunnel junction 20 is used as a reference device, there is no need to flip the direction of the free layer magnetic moment of the first magnetic tunnel junction 20. By setting the geometric center of the first magnetic tunnel junction 20 to coincide with the geometric center of the spacer layer 40, the magnetic moment of the first magnetic tunnel junction 20 will not be offset and its free layer will not be flipped, and its resistance will not change with changes in the external field and the write current; the shape of the first magnetic tunnel junction 20 can be not restricted, such as circular, elliptical, square, etc., preferably circular, so that the first magnetic tunnel junction 20 produces a ring-shaped uniform magnetic moment, and its resistance has better stability.

[0100] By adjusting the sidewall width of the spacer layer 40 , the resistance of the first magnetic tunnel junction 20 can be adjusted so that its resistance is between the maximum resistance and the minimum resistance of the second magnetic tunnel junction 30 , thereby achieving self-referencing of the semiconductor memory device.

[0101] Specifically, the resistance value of the first magnetic tunnel junction 20 is recorded as a first resistance value, and the magnitude of the first resistance value is between the maximum resistance value and the minimum resistance value of the second magnetic tunnel junction 30, and the second magnetic tunnel junction 30 has a second resistance value; when reading, the first resistance value and the second resistance value are read simultaneously and compared, and the read data of the semiconductor memory device is defined based on the comparison result: if the first resistance value is greater than the second resistance value, the second magnetic tunnel junction 30 is in a low resistance state, and the semiconductor memory device reads it as data "1"; if the first resistance value is less than the second resistance value, the second magnetic tunnel junction 30 is in a high resistance state, and the semiconductor memory device reads it as data "0"; alternatively, if the first resistance value is greater than the second resistance value, the second magnetic tunnel junction 30 is in a low resistance state, and the semiconductor memory device reads it as data "0"; if the first resistance value is less than the second resistance value, the second magnetic tunnel junction 30 is in a high resistance state, and the semiconductor memory device reads it as data "1". The read data of the semiconductor memory device can also be defined based on the comparison result according to actual usage requirements.

[0102] The number of second magnetic tunnel junctions 30 can be one or more, and multiple second magnetic tunnel junctions 30 can be arranged in an array or in an arrangement designed according to actual needs; conductive terminals (not shown in the figure) are respectively provided above the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 to electrically connect to the external circuit to realize data reading. When there are multiple second magnetic tunnel junctions 30, each second magnetic tunnel junction 30 can be compared with the same first magnetic tunnel junction 20 for resistance value. Compared with the existing self-reference device in which each storage unit needs to be provided with a corresponding reference device, it not only saves the unit area, but also reduces the number of openings of the top electrode, which simplifies the formation process and is also conducive to device integration.

[0103] The present application embodiment also provides another method of forming Figure 4The method for forming the semiconductor memory device shown differs from the method for forming the second semiconductor memory device in that: when forming the spacer layer 40 on the spin-orbit moment layer 10, at least one through-opening exists inside the spacer layer 40; a magnetic tunnel junction film layer (not shown in the figure) is deposited to cover at least the outer wall of the spacer layer 40 and all through-openings on the inner wall of the spacer layer 40; the magnetic tunnel junction film layer is etched to form a first magnetic tunnel junction 20, and the magnetic tunnel junction film layer in the through-opening on the inner wall of the spacer layer 40 forms a second magnetic tunnel junction 30; wherein the geometric centers of the first magnetic tunnel junction 20 and the spacer layer 40 coincide; and by adjusting the sidewall width of the spacer layer 40, the resistance of the first magnetic tunnel junction 20 is adjusted to be between the maximum resistance and the minimum resistance of the second magnetic tunnel junction 30, so that it can be used as a self-reference device.

[0104] The semiconductor memory device formed using the formation method of this embodiment can also be used as a self-reference device, which improves the area utilization of the semiconductor memory device while improving its anti-magnetic interference capability. Its specific implementation method and related mechanism have been explained in detail when describing the third method for forming a semiconductor memory device, and will not be repeated here.

[0105] The third and fourth methods for forming semiconductor memory devices provided in the embodiments of the present application greatly improve the anti-magnetic interference capability of the second magnetic tunnel junction 30 by filling the gap between the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 with a spacer layer 40. The geometric centers of the first magnetic tunnel junction 20 and the spacer layer 40 coincide with each other, thereby preventing the first magnetic tunnel junction 20 from flipping to produce a fixed resistance value. The sidewall width of the spacer layer 40 is adjusted so that the resistance value of the first magnetic tunnel junction 20 is between the maximum resistance value and the minimum resistance value of the second magnetic tunnel junction 30. This can be used to realize a self-reference function, thereby improving the anti-magnetic interference capability of the semiconductor memory device while increasing its area utilization. In addition, the resistance value of multiple second magnetic tunnel junctions 30 can be compared with that of the same first magnetic tunnel junction 20, which not only saves unit area but also reduces the number of openings in the top electrode, simplifies the formation process and facilitates device integration.

[0106] In this specification, each embodiment or implementation method is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referenced to each other. The descriptions with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0107] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor memory device, characterized in that: The invention comprises a spin-orbit moment layer, and a first magnetic tunnel junction, a second magnetic tunnel junction and a spacer layer arranged on the spin-orbit moment layer; The first magnetic tunnel junction is provided with a penetrating opening, the second magnetic tunnel junction is provided in the penetrating opening, and the spacer layer fills a gap between the first magnetic tunnel junction and the second magnetic tunnel junction; The figure formed by the sidewalls of the first magnetic tunnel junction away from the spacer layer is a circle or a convex polygon, and the geometric centers of the first magnetic tunnel junction and the spacer layer do not coincide with each other.

2. The semiconductor memory device according to claim 1, wherein The first magnetic tunnel junction has a first switching current, the second magnetic tunnel junction has a second switching current, and the first switching current and the second switching current are different in magnitude; The first switching current and the second switching current are made different in magnitude by adjusting the sidewall width of the spacer layer.

3. The semiconductor memory device according to claim 2, wherein: A first conductive terminal and a second conductive terminal are respectively provided above the first magnetic tunnel junction and the second magnetic tunnel junction, so that the first magnetic tunnel junction and the second magnetic tunnel junction are connected in series; Based on the difference between the first switching current and the second switching current, the semiconductor memory device is made to have a variety of resistance values by changing the magnitude and / or direction of the write current supplied to the spin-track moment layer.

4. The semiconductor memory device according to claim 2, wherein The first magnetic tunnel junction and the second magnetic tunnel junction are provided with a common third conductive terminal, so that the first magnetic tunnel junction and the second magnetic tunnel junction are connected in parallel; Based on the difference between the first switching current and the second switching current, the magnitude and / or direction of the write current supplied to the spin-track moment layer is changed, so that the semiconductor memory device has a variety of resistance values.

5. The semiconductor memory device according to any one of claims 1 to 4, wherein: The spacer layer is formed of an insulating material, or the first magnetic tunnel junction and the second magnetic tunnel junction are in direct contact, and the material in the transition region is rendered magnetically ineffective and insulated by ion implantation in the directly contacting transition region to form the spacer layer.

6. A semiconductor memory device, characterized in that: The invention comprises a spin-orbit moment layer, a first magnetic tunnel junction, at least one second magnetic tunnel junction and a spacer layer arranged on the spin-orbit moment layer; The first magnetic tunnel junction is provided with a penetrating opening, the second magnetic tunnel junction is provided in the penetrating opening, and the spacer layer fills a gap between the first magnetic tunnel junction and the second magnetic tunnel junction; Wherein, the geometric center of the first magnetic tunnel junction coincides with the geometric center of the spacer layer; By adjusting the sidewall width of the spacer layer, the resistance of the first magnetic tunnel junction is made between the maximum resistance and the minimum resistance of the second magnetic tunnel junction, so that the first magnetic tunnel junction can be used as a self-reference device.

7. The semiconductor memory device according to claim 6, wherein: The first magnetic tunnel junction has a first resistance value, and the second magnetic tunnel junction has a second resistance value. The first resistance value and the second resistance value are read simultaneously and compared, and read data of the semiconductor memory device is defined based on the comparison result.

8. A method for forming a semiconductor memory device, characterized in that: The steps include: forming an initial magnetic tunnel junction on the spin-orbit moment layer; forming a spacer layer inside the initial magnetic tunnel junction, wherein a portion of the initial magnetic tunnel junction located outside the spacer layer forms a first magnetic tunnel junction, and a portion of the initial magnetic tunnel junction located inside the spacer layer forms a second magnetic tunnel junction; Wherein, the spacer layer is annular and passes through the initial magnetic tunnel junction; The shape of the initial magnetic tunnel junction is a circle or a convex polygon, and the geometric center of the initial magnetic tunnel junction does not coincide with the geometric center of the spacer layer.

9. A method for forming a semiconductor memory device, characterized in that: The steps include: forming a spacer layer on the spin-orbit moment layer; Depositing a magnetic tunnel junction film layer to at least cover the outer wall of the spacer layer and the area enclosed by the inner wall of the spacer layer; Etching the magnetic tunnel junction film layer to form a first magnetic tunnel junction, and the magnetic tunnel junction film layer in the area surrounded by the inner sidewall of the spacer layer forms a second magnetic tunnel junction; Wherein, the spacer layer is annular; A shape formed by side walls of the first magnetic tunnel junction away from the spacer layer is a circle or a convex polygon, and the geometric centers of the first magnetic tunnel junction and the spacer layer do not coincide with each other.

10. The forming method according to claim 8 or 9, characterized in that: The first magnetic tunnel junction formed has a first switching current, the second magnetic tunnel junction formed has a second switching current, and the first switching current and the second switching current are different in magnitude; The first switching current and the second switching current are made different in magnitude by adjusting the sidewall width of the spacer layer.

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