Preparation method of gate-all-around device and gate-all-around device

Abstract

The invention discloses a gate-all-around device preparation method and a gate-all-around device, and the gate-all-around device comprises a substrate which is provided with a P-type transistor region and an N-type transistor region; the P-type transistor region is provided with a first nanosheet channel, and the N-type transistor region is provided with a second nanosheet channel; the preparation method comprises the following steps: forming a first sacrificial stress layer on the surface of a first nanosheet channel, and / or forming a second sacrificial stress layer on the surface of a second nanosheet channel; the intrinsic lattice constant of the first sacrificial stress layer is smaller than that of the first nanosheet channel, and the intrinsic lattice constant of the second sacrificial stress layer is larger than that of the second nanosheet channel; carrying out annealing treatment on the ring gate device; and removing the first sacrificial stress layer, and / or removing the second sacrificial stress layer. According to the invention, the hole current of the P-type transistor region is effectively improved, and / or the electron current of the N-type transistor region is effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular, to a method for manufacturing a gate-all-around device and a gate-all-around device. Background Art

[0002] With the development of semiconductor technology, transistor devices have evolved from planar transistors to fin field-effect transistors (FinFETs), and then to gate-all-around field-effect transistors (GAAFETs).

[0003] A GAA transistor device is provided with an N-type transistor region and a P-type transistor region. For GAA transistor devices, improving the electron mobility of the N-type transistor region and the hole mobility of the P-type transistor region are technical problems that the industry urgently needs to solve. Summary of the Invention

[0004] The present invention provides a method for manufacturing a gate-all-around device and a gate-all-around device to improve the electron mobility of the N-type transistor region and the hole mobility of the P-type transistor region.

[0005] In a first aspect, the present invention provides a method for manufacturing a gate-all-around device, wherein the gate-all-around device includes: a substrate, the substrate is provided with a P-type transistor region and an N-type transistor region, and the N-type transistor region and the P-type transistor region are insulated from each other and located on one side of the substrate; the P-type transistor region is provided with a first nanosheet channel, and the N-type transistor region is provided with a second nanosheet channel;

[0006] The manufacturing method includes:

[0007] Forming a first sacrificial stress layer on the surface of the first nanosheet channel, and / or forming a second sacrificial stress layer on the surface of the second nanosheet channel; the intrinsic lattice constant of the first sacrificial stress layer is smaller than the intrinsic lattice constant of the first nanosheet channel, and the intrinsic lattice constant of the second sacrificial stress layer is larger than the intrinsic lattice constant of the second nanosheet channel;

[0008] Performing an annealing treatment on the gate-all-around device;

[0009] Removing the first sacrificial stress layer, and / or removing the second sacrificial stress layer.

[0010] Optionally, the first nanosheet channel includes a silicon-germanium nanosheet channel; forming a first sacrificial stress layer on the surface of the first nanosheet channel includes:

[0011] Forming a silicon sacrificial stress layer on the surface of the first nanosheet channel.

[0012] Optionally, the first nanosheet channel includes a silicon nanosheet channel; forming a first sacrificial stress layer on the surface of the first nanosheet channel includes:

[0013] A silicon carbide sacrificial stress layer is formed on the surface of the first nanosheet channel.

[0014] Optionally, the second nanosheet channel includes a silicon nanosheet channel; forming a second sacrificial stress layer on the surface of the second nanosheet channel, including:

[0015] Form a first silicon-germanium sacrificial stress layer on the surface of the second nanosheet channel.

[0016] Optionally, the second nanosheet channel includes a silicon-germanium nanosheet channel; forming a second sacrificial stress layer on the surface of the second nanosheet channel, including:

[0017] Form a second silicon-germanium sacrificial stress layer on the surface of the second nanosheet channel, and the content of germanium element in the second silicon-germanium sacrificial stress layer is greater than that in the silicon-germanium nanosheet channel.

[0018] Optionally, the first silicon-germanium sacrificial stress layer includes a first sub-silicon-germanium sacrificial stress layer and a second sub-silicon-germanium sacrificial stress layer; forming a first silicon-germanium sacrificial stress layer on the surface of the second nanosheet channel, including:

[0019] Form a first sub-silicon-germanium sacrificial stress layer on the surface of the second nanosheet channel;

[0020] Form a second sub-silicon-germanium sacrificial stress layer on the side of the first sub-silicon-germanium sacrificial stress layer away from the second nanosheet channel; the content of germanium element in the second sub-silicon-germanium sacrificial stress layer is greater than that in the first sub-silicon-germanium sacrificial stress layer.

[0021] Optionally, forming a first sacrificial stress layer on the surface of the first nanosheet channel, and / or forming a second sacrificial stress layer on the surface of the second nanosheet channel, including:

[0022] Provide a substrate, sequentially form an alternately stacked first channel layer and a second channel layer on one side of the substrate, etch the first channel layer and the second channel layer to form a plurality of fins distributed periodically, etch part of the substrate to form isolation trenches, and form a shallow trench isolation region in the isolation trenches; define one of the adjacent fins as a P-type transistor region and the other as an N-type transistor region;

[0023] Form a dummy gate layer on the surfaces of the fins and the shallow trench isolation region, and form a first sidewall isolation layer on both sides of the dummy gate layer;

[0024] Etch the fins to form electrode regions on both sides of the first sidewall isolation layer, and the vertical projection of the fins on the substrate coincides with the vertical projections of the dummy gate layer and the first sidewall isolation layer on the substrate;

[0025] Etch the edge of the first channel layer or the second channel layer from the electrode region corresponding to the P-type transistor region towards the center, so as to form a first groove at both ends of the first channel layer or the second channel layer in the P-type transistor region; etch the edge of the first channel layer or the second channel layer from the electrode region corresponding to the N-type transistor region towards the center, so as to form a second groove at both ends of the first channel layer or the second channel layer in the N-type transistor region;

[0026] Form a second sidewall isolation layer in the first groove and the second groove;

[0027] Form a second source electrode and a second drain electrode in the electrode region corresponding to the N-type transistor region, and form a first source electrode and a first drain electrode in the electrode region corresponding to the P-type transistor region;

[0028] Form an insulating region between the electrode region corresponding to the N-type transistor region and the electrode region corresponding to the P-type transistor region;

[0029] Remove the dummy gate layer;

[0030] Remove the etched first channel layer in the P-type transistor region, and release the second channel layer in the P-type transistor region to form a first nanosheet channel, or remove the etched second channel layer in the P-type transistor region, and release the first channel layer in the P-type transistor region to form a first nanosheet channel; remove the etched first channel layer in the N-type transistor region, and release the second channel layer in the N-type transistor region to form a second nanosheet channel, or remove the etched second channel layer in the N-type transistor region, and release the first channel layer in the N-type transistor region to form a second nanosheet channel.

[0031] Optionally, after removing the first sacrificial stress layer and / or removing the second sacrificial stress layer, further include:

[0032] Form a first gate surrounding the first nanosheet channel;

[0033] Form a second gate surrounding the second nanosheet channel.

[0034] Optionally, removing the second sacrificial stress layer includes:

[0035] Etch the second sacrificial stress layer using a combined gas of a halogen-based oxidizing gas and a halogen-based acidic gas.

[0036] In a second aspect, the present invention provides a gate-all-around device, wherein the gate-all-around device is prepared by using the preparation method of the gate-all-around device provided in the first aspect above.

[0037] In the technical solution of the embodiment of the present invention, a first sacrificial stress layer is formed on the surface of the first nanosheet channel, and / or a second sacrificial stress layer is formed on the surface of the second nanosheet channel; the intrinsic lattice constant of the first sacrificial stress layer is smaller than the intrinsic lattice constant of the first nanosheet channel, and the intrinsic lattice constant of the second sacrificial stress layer is larger than the intrinsic lattice constant of the second nanosheet channel. After high-temperature annealing treatment, the first sacrificial stress layer is removed, and / or the second sacrificial stress layer is removed. The technical solution of the embodiment of the present invention changes the first nanosheet channel into a nanosheet channel with compressive stress in the first direction, and / or changes the second nanosheet channel into a nanosheet channel with tensile stress in the first direction, thereby effectively improving the hole mobility in the P-type transistor region, and / or effectively improving the electron mobility in the N-type transistor region, and further effectively increasing the hole current in the P-type transistor region, and / or effectively increasing the electron current in the N-type transistor region. The technical solution of the embodiment of the present invention can only process the P-type transistor region to improve the hole mobility in the P-type transistor region, thereby effectively solving the problem that the performance of the P-type transistor region in the gate-all-around device is seriously low. It is expected that the performance of the P-type transistor region can be improved by 50%. The performance ratio of the N-type transistor region to the P-type transistor region reaches the level of 1:1 - 2:1, improving the imbalance between electron mobility and hole mobility, and enhancing the comprehensive competitiveness of the gate-all-around device. At the same time, the performance of the logic digital unit and the static random access memory unit of the gate-all-around device can be effectively improved, and the process window of the lithography process can be indirectly improved. The technical solution of the embodiment of the present invention improves the performance of the P-type transistor region and / or the N-type transistor region, and finally forms a gate-all-around device with a geometric structure completely the same as that of the traditional gate-all-around device, without introducing new film layers, making the process flow fully compatible with the current process, and the product is easy to implement. Moreover, the photomasks required for the P-type transistor region and the N-type transistor region can be shared without introducing additional photomasks, saving costs.

[0038] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0040] Figure 1 is a flowchart of a method for manufacturing a gate-all-around device provided by an embodiment of the present invention;

[0041] Figures 2 - 3It is a schematic structural diagram corresponding to each step in a method for manufacturing a gate-all-around device provided by an embodiment of the present invention;

[0042] Figure 4 It is a flowchart of another method for manufacturing a gate-all-around device provided by an embodiment of the present invention;

[0043] Figure 5 It is a flowchart of yet another method for manufacturing a gate-all-around device provided by an embodiment of the present invention;

[0044] Figure 6 It is a flowchart of yet another method for manufacturing a gate-all-around device provided by an embodiment of the present invention;

[0045] Figure 7 It is a flowchart of yet another method for manufacturing a gate-all-around device provided by an embodiment of the present invention;

[0046] Figure 8 It is a flowchart of yet another method for manufacturing a gate-all-around device provided by an embodiment of the present invention;

[0047] Figure 9 It is a schematic structural diagram corresponding to some steps in yet another method for manufacturing a gate-all-around device provided by an embodiment of the present invention;

[0048] Figure 10 It is a flowchart of yet another method for manufacturing a gate-all-around device provided by an embodiment of the present invention;

[0049] Figures 11 - 18 It is a schematic structural diagram corresponding to some steps in yet another method for manufacturing a gate-all-around device provided by an embodiment of the present invention;

[0050] Figure 19 It is a flowchart of yet another method for manufacturing a gate-all-around device provided by an embodiment of the present invention;

[0051] Figure 20 It is a schematic structural diagram corresponding to some steps in yet another method for manufacturing a gate-all-around device provided by an embodiment of the present invention;

[0052] Figure 21 It is a flowchart of yet another method for manufacturing a gate-all-around device provided by an embodiment of the present invention. Detailed implementation manners

[0053] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0054] It should be noted that the terms "first", "second", etc. in the description, claims and the above-mentioned drawings of the present invention are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0055] Figure 1 is a flowchart of a method for manufacturing a gate-all-around device provided by an embodiment of the present invention. Figures 2 - 3 is a schematic structural diagram corresponding to each step in a method for manufacturing a gate-all-around device provided by an embodiment of the present invention. As Figures 2 - 3 shown, the gate-all-around device includes: a substrate 10, the substrate 10 is provided with a P-type transistor region 1 and an N-type transistor region 2, and the N-type transistor region 2 and the P-type transistor region 1 are insulated from each other and located on one side of the substrate 10. The P-type transistor region 1 is provided with a first nanosheet channel 11, and the N-type transistor region 2 is provided with a second nanosheet channel 21. As Figure 1 shown, the manufacturing method includes:

[0056] S100: forming a first sacrificial stress layer on the surface of the first nanosheet channel, and / or forming a second sacrificial stress layer on the surface of the second nanosheet channel; the intrinsic lattice constant of the first sacrificial stress layer is smaller than the intrinsic lattice constant of the first nanosheet channel, and the intrinsic lattice constant of the second sacrificial stress layer is larger than the intrinsic lattice constant of the second nanosheet channel.

[0057] Specifically, as Figure 2 shown, the gate-all-around transistor device may include a P-type transistor region 1 and an N-type transistor region 2. An insulating region 3 may be provided between the P-type transistor region 1 and the N-type transistor region 2, and the insulating region 3 may also be provided on both sides of the P-type transistor region 1 and both sides of the N-type transistor region 2. The P-type transistor region 1 may include a first source 13, a first drain 14 and a first nanosheet channel 11. The first source 13 and the first drain 14 are respectively located on both sides of the first nanosheet channel 11, and both the first source 13 and the first drain 14 are in contact with the first nanosheet channel 11. The N-type transistor region 2 may include a second source 23, a second drain 24 and a second nanosheet channel 21. The second source 23 and the second drain 24 are respectively located on both sides of the second nanosheet channel 21, and both the second source 23 and the second drain 24 are in contact with the second nanosheet channel 21.

[0058] To improve the hole mobility of the P-type transistor region 1, compressive stress in the first direction X can be provided to the first nanosheet channel 11; to improve the electron mobility of the N-type transistor region 2, tensile stress in the first direction X can be provided to the second nanosheet channel 21. Embodiments of the present invention include three technical solutions, which can separately improve the hole mobility of the P-type transistor region 1, or separately improve the electron mobility of the N-type transistor region 2, or simultaneously improve the hole mobility of the P-type transistor region 1 and the electron mobility of the N-type transistor region 2.

[0059] For the P-type transistor region 1, a first sacrificial stress layer 12 is formed around the first nanosheet channel 11, and the intrinsic lattice constant of the first sacrificial stress layer 12 is smaller than the intrinsic lattice constant of the first nanosheet channel 11. And / or, for the N-type transistor region 2, a second sacrificial stress layer 22 is formed around the second nanosheet channel 21, and the intrinsic lattice constant of the second sacrificial stress layer 22 is larger than the intrinsic lattice constant of the second nanosheet channel 21. Exemplarily, the first nanosheet channel 11 can be a silicon nanosheet channel, and then the first sacrificial stress layer 12 formed around the first nanosheet channel 11 can be a silicon carbide sacrificial stress layer. And / or, the second nanosheet channel 21 can be a silicon nanosheet channel, and then the second sacrificial stress layer 22 formed around the second nanosheet channel 21 can be a silicon germanium sacrificial stress layer.

[0060] S110: Anneal the gate-all-around device.

[0061] Specifically, as Figure 2 shown, perform high-temperature annealing on the entire gate-all-around device. Exemplarily, the annealing temperature can be 750 - 850 degrees Celsius.

[0062] S120: Remove the first sacrificial stress layer, and / or remove the second sacrificial stress layer.

[0063] Specifically, as Figure 3 shown, after the high-temperature annealing treatment, remove the first sacrificial stress layer around the first nanosheet channel 11, and / or remove the second sacrificial stress layer around the second nanosheet channel 21.

[0064] For the P-type transistor region 1, after removing the first sacrificial stress layer, compressive stress will transfer to the first nanosheet channel 11, and the first nanosheet channel 11 becomes a nanosheet channel with compressive stress in the first direction X. This compressive stress can effectively increase the hole mobility of the first nanosheet channel 11 in the P-type transistor region 1, thereby effectively improving the hole current of the P-type transistor region 1.

[0065] For the N-type transistor region 2, after removing the second sacrificial stress layer, tensile stress will transfer to the second nanosheet channel 21. The second nanosheet channel 21 becomes a nanosheet channel with tensile stress in the first direction X. This tensile stress can effectively increase the electron mobility of the second nanosheet channel 21 in the N-type transistor region 2, thereby effectively increasing the electron current of the N-type transistor region 2.

[0066] After the current transition from FinFET to gate-all-around transistor, a nanosheet channel with slightly tensile stress will ultimately be formed, that is, both the first nanosheet channel 11 and the second nanosheet channel 21 have weak tensile stress in the first direction X. This tensile stress is very unfavorable to the P-type transistor region 1.

[0067] At the same time, the crystal orientation of the lower surface of the first nanosheet channel 11 close to the substrate 10 and the upper surface far from the substrate 10 is 100, while the crystal orientation of the surrounding sidewalls is 110. The crystal orientation of the lower surface of the second nanosheet channel 21 close to the substrate 10 and the upper surface far from the substrate 10 is 100, while the crystal orientation of the surrounding sidewalls is 110. The upper and lower surfaces of the nanosheet channel dominate carrier transport. The above crystal orientation settings will cause an increase in the electron mobility of the N-type transistor region 2 of the gate-all-around transistor device, while a decrease in the hole mobility of the P-type transistor region 1, resulting in serious current mismatch in the gate-all-around transistor device. The wider the width of the nanosheet channel, the more serious the current matching. The ratio of the electron current of the N-type transistor region 2 to the hole current of the P-type transistor region 1 can reach 2.6:1, resulting in poor performance of the gate-all-around device.

[0068] In the prior art, the current mismatch problem of the gate-all-around transistor device is reduced by increasing the width of the first nanosheet channel 11 and appropriately reducing the width of the second nanosheet channel 21. However, in a standard digital cell, the width of the nanosheet channel is reduced to 20 - 50 nm. Achieving the first nanosheet channel 11 and the second nanosheet channel 21 with a large width difference at this level will further increase the lithography difficulty, reduce the lithography process window, and waste the digital cell area.

[0069] The technical solution of the embodiment of the present invention can separately increase the hole mobility of the P-type transistor region 1. At this time, it is necessary to first deposit a combined material barrier layer of silicon oxide and silicon nitride on the entire surface of the gate-all-around device by atomic layer deposition (ALD). The thickness of the combined material barrier layer of silicon oxide and silicon nitride can be 5 - 15 nm. Then, the combined material barrier layer of silicon oxide and silicon nitride on the surface of the P-type transistor region 1 is removed through processes such as lithography. The other regions except the P-type transistor region 1 are protected by depositing the combined material barrier layer of silicon oxide and silicon nitride.

[0070] A first sacrificial stress layer 12 is formed around the first nanosheet channel 11, and the intrinsic lattice constant of the first sacrificial stress layer 12 is smaller than that of the first nanosheet channel 11. The P-type transistor region 1 is subjected to a high-temperature annealing treatment. After the high-temperature annealing treatment, the first sacrificial stress layer around the first nanosheet channel 11 is removed. For the P-type transistor region 1, after the first sacrificial stress layer is removed, compressive stress will be transferred to the first nanosheet channel 11, and the first nanosheet channel 11 becomes a nanosheet channel with compressive stress in the first direction X. This compressive stress can effectively increase the hole mobility of the first nanosheet channel 11 in the P-type transistor region 1, thereby effectively increasing the hole current of the P-type transistor region 1.

[0071] In the technical solution of the embodiment of the present invention, a first sacrificial stress layer is formed on the surface of the first nanosheet channel, and / or a second sacrificial stress layer is formed on the surface of the second nanosheet channel; the intrinsic lattice constant of the first sacrificial stress layer is smaller than that of the first nanosheet channel, and the intrinsic lattice constant of the second sacrificial stress layer is larger than that of the second nanosheet channel. After a high-temperature annealing treatment, the first sacrificial stress layer is removed, and / or the second sacrificial stress layer is removed. The technical solution of the embodiment of the present invention changes the first nanosheet channel into a nanosheet channel with compressive stress in the first direction, and / or changes the second nanosheet channel into a nanosheet channel with tensile stress in the first direction, thereby effectively increasing the hole mobility of the P-type transistor region, and / or effectively increasing the electron mobility of the N-type transistor region, and further effectively increasing the hole current of the P-type transistor region, and / or effectively increasing the electron current of the N-type transistor region. The technical solution of the embodiment of the present invention can only process the P-type transistor region to improve the hole mobility of the P-type transistor region, thereby effectively solving the problem that the performance of the P-type transistor region of the gate-all-around device is seriously low. It is expected to improve the performance of the P-type transistor region by 50%. The performance ratio of the N-type transistor region to the P-type transistor region reaches the level of 1:1 - 2:1, improving the imbalance between electron mobility and hole mobility, and enhancing the comprehensive competitiveness of the gate-all-around device. At the same time, the performance of the logic digital unit and the static random access memory unit of the gate-all-around device can be effectively improved, and the process window of the lithography process can be indirectly improved. The technical solution of the embodiment of the present invention improves the performance of the P-type transistor region and / or the N-type transistor region, and finally forms a gate-all-around device with a geometric structure completely the same as that of the traditional gate-all-around device, without introducing new film layers, making the process flow fully compatible with the current process, and the product is easy to implement. Moreover, the photomasks required for the P-type transistor region and the N-type transistor region can be shared, without introducing additional photomasks, saving costs.

[0072] Optionally, on the basis of the above embodiments, Figure 4 is a flowchart of another method for manufacturing a gate-all-around device provided by an embodiment of the present invention. As Figure 4 shown, the manufacturing method includes:

[0073] S200: The first nanosheet channel includes a silicon-germanium nanosheet channel, a silicon sacrificial stress layer is formed on the surface of the first nanosheet channel, and / or a second sacrificial stress layer is formed on the surface of the second nanosheet channel; the intrinsic lattice constant of the second sacrificial stress layer is greater than the intrinsic lattice constant of the second nanosheet channel.

[0074] Specifically, as Figure 2 shown, when the first nanosheet channel 11 is a silicon-germanium nanosheet channel, a silicon sacrificial stress layer can be epitaxially formed around the first nanosheet channel 11, and the intrinsic lattice constant of the silicon sacrificial stress layer is smaller than the intrinsic lattice constant of the silicon-germanium nanosheet channel.

[0075] S210: Anneal the gate-all-around device.

[0076] S220: Remove the silicon sacrificial stress layer, and / or remove the second sacrificial stress layer.

[0077] Specifically, as Figure 3 shown, after high-temperature annealing treatment, etch and remove the silicon sacrificial stress layer around the first nanosheet channel 11. At this time, compressive stress will be transferred to the first nanosheet channel 11, and the first nanosheet channel 11 becomes a nanosheet channel with compressive stress in the first direction X. This compressive stress can effectively increase the hole mobility of the first nanosheet channel 11 in the P-type transistor region 1, thereby effectively improving the hole current of the P-type transistor region 1.

[0078] Optionally, based on the above embodiments, Figure 5 is a flowchart of another method for manufacturing a gate-all-around device provided by an embodiment of the present invention. As Figure 5 shown, the manufacturing method includes:

[0079] S300: The first nanosheet channel includes a silicon nanosheet channel, a silicon carbide sacrificial stress layer is formed on the surface of the first nanosheet channel, and / or a second sacrificial stress layer is formed on the surface of the second nanosheet channel; the intrinsic lattice constant of the second sacrificial stress layer is greater than the intrinsic lattice constant of the second nanosheet channel.

[0080] Specifically, as Figure 2 shown, when the first nanosheet channel 11 is a silicon nanosheet channel, a silicon carbide sacrificial stress layer can be epitaxially formed around the first nanosheet channel 11, and the intrinsic lattice constant of the silicon carbide sacrificial stress layer is smaller than the intrinsic lattice constant of the silicon nanosheet channel.

[0081] S310: Anneal the gate-all-around device at high temperature.

[0082] S320: Remove the silicon carbide sacrificial stress layer, and / or remove the second sacrificial stress layer.

[0083] Specifically, as Figure 3 shown, after high-temperature annealing treatment, the silicon carbide sacrificial stress layer around the first nanosheet channel 11 is etched away. At this time, compressive stress will transfer to the first nanosheet channel 11, and the first nanosheet channel 11 becomes a nanosheet channel with compressive stress in the first direction X. This compressive stress can effectively increase the hole mobility of the first nanosheet channel 11 in the P-type transistor region 1, thereby effectively increasing the hole current of the P-type transistor region 1.

[0084] Optionally, based on the above embodiments, Figure 6 is a flowchart of another method for manufacturing a gate-all-around device provided by an embodiment of the present invention. As Figure 6 shown, the manufacturing method includes:

[0085] S400: Form a first sacrificial stress layer on the surface of the first nanosheet channel, and / or form a first silicon-germanium sacrificial stress layer on the surface of the second nanosheet channel; the second nanosheet channel includes a silicon nanosheet channel, and the intrinsic lattice constant of the first sacrificial stress layer is smaller than the intrinsic lattice constant of the first nanosheet channel.

[0086] Specifically, as Figure 2 shown, when the second nanosheet channel 21 is a silicon nanosheet channel, a silicon-germanium sacrificial stress layer can be epitaxially formed around the second nanosheet channel 21, and the concentration of germanium elements in the silicon-germanium sacrificial stress layer can be 20%-80%. The intrinsic lattice constant of the silicon-germanium sacrificial stress layer is larger than the intrinsic lattice constant of the silicon nanosheet channel.

[0087] S410: Perform high-temperature annealing treatment on the gate-all-around device.

[0088] Specifically, when performing high-temperature annealing treatment on the gate-all-around device, the annealing temperature can be 750-850 degrees Celsius. The annealing temperature should ensure that germanium elements in the silicon-germanium sacrificial stress layer do not significantly diffuse into the silicon nanosheet channel, and at the same time, can transfer compressive stress to the silicon nanosheet channel.

[0089] S420: Remove the first sacrificial stress layer, and / or remove the first silicon-germanium sacrificial stress layer.

[0090] Specifically, as Figure 3 shown, after high-temperature annealing treatment, the first silicon-germanium sacrificial stress layer around the second nanosheet channel 21 is etched away. At this time, tensile stress will transfer to the second nanosheet channel 21, and the second nanosheet channel 21 becomes a nanosheet channel with tensile stress in the first direction X. This tensile stress can effectively increase the electron mobility of the second nanosheet channel 21 in the N-type transistor region 2, thereby effectively increasing the electron current of the N-type transistor region 2.

[0091] Optionally, based on the above embodiments,Figure 7 It is a flowchart of another preparation method of a gate-all-around device provided by an embodiment of the present invention. As Figure 7 shown, the preparation method includes:

[0092] S500: Form a first sacrificial stress layer on the surface of the first nanosheet channel, and / or form a second silicon-germanium sacrificial stress layer on the surface of the second nanosheet channel; the second nanosheet channel includes a silicon-germanium nanosheet channel, and the content of germanium element in the second silicon-germanium sacrificial stress layer is greater than that in the silicon-germanium nanosheet channel. The intrinsic lattice constant of the first sacrificial stress layer is smaller than the intrinsic lattice constant of the first nanosheet channel.

[0093] Specifically, as Figure 2 shown, when the second nanosheet channel 21 is a silicon-germanium nanosheet channel, a silicon-germanium sacrificial stress layer can be epitaxially formed around the second nanosheet channel 21. The content of germanium element in this silicon-germanium sacrificial stress layer is greater than that in the silicon-germanium nanosheet channel, ensuring that the intrinsic lattice constant of the silicon-germanium sacrificial stress layer is greater than the intrinsic lattice constant of the silicon-germanium nanosheet channel.

[0094] S510: Perform a high-temperature annealing treatment on the gate-all-around device.

[0095] S520: Remove the first sacrificial stress layer, and / or remove the first silicon-germanium sacrificial stress layer.

[0096] Specifically, as Figure 3 shown, after the high-temperature annealing treatment, etch and remove the second silicon-germanium sacrificial stress layer around the second nanosheet channel 21. At this time, tensile stress will be transferred to the second nanosheet channel 21, and the second nanosheet channel 21 becomes a nanosheet channel with tensile stress in the first direction X. This tensile stress can effectively increase the electron mobility of the second nanosheet channel 21 in the N-type transistor region 2, thereby effectively increasing the electron current of the N-type transistor region 2.

[0097] Optionally, on the basis of the above embodiments, Figure 8 It is a flowchart of another preparation method of a gate-all-around device provided by an embodiment of the present invention. Figure 9 It is a schematic structural diagram corresponding to some steps in another preparation method of a gate-all-around device provided by an embodiment of the present invention. As Figure 8 shown, the preparation method includes:

[0098] S600: Form a first sacrificial stress layer on the surface of the first nanosheet channel, and / or form a first sub-silicon-germanium sacrificial stress layer on the surface of the second nanosheet channel; the second nanosheet channel includes a silicon nanosheet channel, and the intrinsic lattice constant of the first sacrificial stress layer is smaller than the intrinsic lattice constant of the first nanosheet channel.

[0099] Specifically, as Figure 9As shown, the second sacrificial stress layer 22 may include a first sub-sacrificial stress layer 221 and a second sub-sacrificial stress layer 222. The first sub-sacrificial stress layer 221 is epitaxially formed around the second nanosheet channel 21, and the second sub-sacrificial stress layer 222 is epitaxially formed around the first sub-sacrificial stress layer 221.

[0100] Exemplarily, when the second nanosheet channel 21 is a silicon nanosheet channel, a first silicon-germanium sacrificial stress layer may be epitaxially formed around the second nanosheet channel 21. The first silicon-germanium sacrificial stress layer may include a first sub-silicon-germanium sacrificial stress layer and a second sub-silicon-germanium sacrificial stress layer. That is, the first sub-sacrificial stress layer 221 is the first sub-silicon-germanium sacrificial stress layer, and the second sub-sacrificial stress layer 222 is the second sub-silicon-germanium sacrificial stress layer. First, the first sub-silicon-germanium sacrificial stress layer is epitaxially formed around the second nanosheet channel 21. The intrinsic lattice constant of the first sub-silicon-germanium sacrificial stress layer is greater than that of the silicon nanosheet channel.

[0101] S610: Form a second sub-silicon-germanium sacrificial stress layer on the side of the first sub-silicon-germanium sacrificial stress layer away from the second nanosheet channel; the content of germanium element in the second sub-silicon-germanium sacrificial stress layer is greater than that in the first sub-silicon-germanium sacrificial stress layer.

[0102] Specifically, as Figure 9 shown, the second sub-silicon-germanium sacrificial stress layer is epitaxially formed around the first sub-silicon-germanium sacrificial stress layer, and the content of germanium element in the second sub-silicon-germanium sacrificial stress layer is greater than that in the first sub-silicon-germanium sacrificial stress layer. That is, when the first nanosheet channel 21 is a silicon nanosheet channel, a silicon-germanium sacrificial stress layer with a lower germanium element concentration is first formed on the side close to the first nanosheet channel 21, and then a silicon-germanium sacrificial stress layer with a higher germanium element concentration is epitaxially formed around the silicon-germanium sacrificial stress layer with a lower concentration. That is, a silicon-germanium sacrificial stress layer with a germanium element concentration gradient stack is epitaxially formed around the silicon nanosheet channel, avoiding defects caused by lattice mismatch and enabling effective stress transfer in subsequent processes. In some embodiments of the present invention, the second sacrificial stress layer 22 may include more than two sub-sacrificial stress layers. Exemplarily, when the second nanosheet channel 21 is a silicon nanosheet channel, a first silicon-germanium sacrificial stress layer may be epitaxially formed around the second nanosheet channel 21. The first silicon-germanium sacrificial stress layer may include multiple sub-silicon-germanium sacrificial stress layers, and the germanium element concentration increases sequentially in the direction away from the second nanosheet channel 21.

[0103] S620: Perform a high-temperature annealing treatment on the gate-all-around device.

[0104] S630: Remove the first sacrificial stress layer, and / or remove the first sub-silicon-germanium sacrificial stress layer and the second sub-silicon-germanium sacrificial stress layer.

[0105] Specifically, as Figure 3As shown, after high-temperature annealing treatment, the first sub-silicon germanium sacrificial stress layer and the second sub-silicon germanium sacrificial stress layer around the second nanosheet channel 21 are etched away. At this time, tensile stress will be transferred to the second nanosheet channel 21, and the second nanosheet channel 21 becomes a nanosheet channel with tensile stress in the first direction X. This tensile stress can effectively increase the electron mobility of the second nanosheet channel 21 in the N-type transistor region 2, thereby effectively improving the electron current of the N-type transistor region 2.

[0106] Optionally, based on the above embodiments, Figure 10 is a flowchart of another method for manufacturing a gate-all-around device provided by an embodiment of the present invention, Figures 11 - 18 is a schematic structural diagram corresponding to some steps in another method for manufacturing a gate-all-around device provided by an embodiment of the present invention. As Figure 10 shown, the manufacturing method includes:

[0107] S700: Provide a substrate, sequentially form an alternately stacked first channel layer and a second channel layer on one side of the substrate, etch the first channel layer and the second channel layer to form a plurality of fins distributed periodically, etch a part of the substrate to form isolation trenches, and form a shallow trench isolation region in the isolation trenches; define one of the adjacent fins as a P-type transistor region and the other as an N-type transistor region.

[0108] Specifically, as Figure 11 shown, first provide a substrate 10, and sequentially and alternately stack a first channel layer 20 and a second channel layer 30 on the substrate 10. Exemplarily, the first channel layer 20 can be a silicon germanium channel layer, and the second channel layer 30 can be a silicon channel layer; alternatively, the first channel layer 20 can be a silicon channel layer, and the second channel layer 30 can be a silicon germanium channel layer.

[0109] As Figure 12 shown, etch the first channel layer 20 and the second channel layer 30 to form a plurality of fins distributed periodically, Figure 12 exemplarily showing the formation of four fins in [FIGURE REFERENCE]. The first fin 31 can be the P-type transistor region 1, and the second fin 32 can be the N-type transistor region 2. Etch a part of the substrate 10 to form isolation trenches 40. As Figure 13 shown, form a shallow trench isolation region 33 in the isolation trenches.

[0110] S710: Form a dummy gate layer on the surfaces of the fins and the shallow trench isolation region, and form first sidewall isolation layers on both sides of the dummy gate layer.

[0111] Specifically, as Figure 14 shown, form a dummy gate layer 34 on the surface of each fin and the shallow trench isolation region 33, and form first sidewall isolation layers 35 on both sides of the dummy gate layer 34.

[0112] S720: Etch the fin to form electrode regions on both sides of the first sidewall isolation layer. The vertical projection of the fin on the substrate coincides with the vertical projections of the dummy gate layer and the first sidewall isolation layer on the substrate.

[0113] Specifically, as Figure 15 shown, etching the fin can make the vertical projection of the fin on the substrate 10 coincide with the vertical projections of the dummy gate layer 34 and the first sidewall isolation layer 35 on the substrate 10. By etching the fin to form electrode regions in the P-type transistor region 1 and the N-type transistor region 2, it is used to form the first source and the first drain of the P-type transistor region 1 in the electrode region later, and to form the second source and the second drain of the N-type transistor region 2 in the electrode region.

[0114] S730: Etch the edge of the first channel layer or the second channel layer from the electrode region corresponding to the P-type transistor region towards the center direction, so that first grooves are formed at both ends of the first channel layer or the second channel layer in the P-type transistor region; etch the edge of the first channel layer or the second channel layer from the electrode region corresponding to the N-type transistor region towards the center direction, so that second grooves are formed at both ends of the first channel layer or the second channel layer in the N-type transistor region.

[0115] Specifically, as Figure 16 shown, etch the edge of the first channel layer 20 or the second channel layer 30 from the electrode region corresponding to the P-type transistor region 1 towards the center direction, so that first grooves 50 are formed at both ends of the first channel layer 20 or the second channel layer 30 in the P-type transistor region 1. Figure 16 Exemplarily, it shows etching the first channel layer 20 from the electrode region corresponding to the P-type transistor region 1 towards the center direction to form the first groove 50. Etch the edge of the first channel layer 20 or the second channel layer 30 from the electrode region corresponding to the N-type transistor region 2 towards the center direction, so that second grooves 60 are formed at both ends of the first channel layer 20 or the second channel layer 30 in the N-type transistor region 1. Figure 16 Exemplarily, it shows etching the first channel layer 20 from the electrode region corresponding to the N-type transistor region 2 towards the center direction to form the second groove 60.

[0116] S740: Form a second sidewall isolation layer in the first groove and the second groove.

[0117] Specifically, as Figure 17 shown, form a second sidewall isolation layer 36 in the first groove and the second groove.

[0118] S750: Form a second source and a second drain in the electrode region corresponding to the N-type transistor region, and form a first source and a first drain in the electrode region corresponding to the P-type transistor region.

[0119] Specifically, as Figure 18As shown, a second source electrode 23 and a second drain electrode (not shown in the figure) are formed in the electrode region corresponding to the N-type transistor region 2, and a first source electrode 13 and a first drain electrode 14 are formed in the electrode region corresponding to the P-type transistor region 1.

[0120] S760: An insulating region is formed between the electrode region corresponding to the N-type transistor region and the electrode region corresponding to the P-type transistor region.

[0121] Specifically, as Figure 18 shown, an insulating region (not shown in the figure) is formed between the electrode region corresponding to the N-type transistor region 2 and the electrode region corresponding to the P-type transistor region 1.

[0122] S770: Remove the dummy gate layer.

[0123] Specifically, as Figure 18 shown, remove the dummy gate layer.

[0124] S780: Remove the first etched channel layer in the P-type transistor region to release the second channel layer in the P-type transistor region to form a first nanosheet channel, or remove the second etched channel layer in the P-type transistor region to release the first channel layer in the P-type transistor region to form a first nanosheet channel; remove the first etched channel layer in the N-type transistor region to release the second channel layer in the N-type transistor region to form a second nanosheet channel, or remove the second etched channel layer in the N-type transistor region to release the first channel layer in the N-type transistor region to form a second nanosheet channel.

[0125] Specifically, as Figure 18 shown, remove the first etched channel layer 20 in the P-type transistor region 1 to release the second channel layer 30 in the P-type transistor region 1 to form a first nanosheet channel, or remove the second etched channel layer 30 in the P-type transistor region 1 to release the first channel layer 20 in the P-type transistor region 1 to form a first nanosheet channel. Remove the first etched channel layer 20 in the N-type transistor region 2 to release the second channel layer 30 in the N-type transistor region 2 to form a second nanosheet channel, or remove the second etched channel layer 30 in the N-type transistor region 2 to release the first channel layer 20 in the N-type transistor region 2 to form a second nanosheet channel.

[0126] Figure 18 Exemplarily shows the removal of the first channel layer 20 in the P-type transistor region 1, and the unremoved second channel layer 30 serves as the first nanosheet channel 11. Figure 18 Also exemplarily shows the removal of the first channel layer 20 in the N-type transistor region 2, and the unremoved second channel layer 30 serves as the second nanosheet channel.

[0127] S790: Form a first sacrificial stress layer on the surface of the first nanosheet channel, and / or form a second sacrificial stress layer on the surface of the second nanosheet channel; the intrinsic lattice constant of the first sacrificial stress layer is smaller than that of the first nanosheet channel, and the intrinsic lattice constant of the second sacrificial stress layer is larger than that of the second nanosheet channel.

[0128] S791: Perform a high-temperature annealing treatment on the gate-all-around device.

[0129] S792: Remove the first sacrificial stress layer, and / or remove the second sacrificial stress layer.

[0130] Optionally, based on the above embodiments, Figure 19 is a flowchart of yet another method for manufacturing a gate-all-around device provided by an embodiment of the present invention. Figure 20 is a structural diagram corresponding to some steps in yet another method for manufacturing a gate-all-around device provided by an embodiment of the present invention. As Figure 19 shown, the manufacturing method includes:

[0131] S800: Provide a substrate, sequentially form an alternating stack of a first channel layer and a second channel layer on one side of the substrate, etch the first channel layer and the second channel layer to form a plurality of fins distributed periodically, etch a part of the substrate to form isolation trenches, and form a shallow trench isolation region in the isolation trenches; define one of the adjacent fins as a P-type transistor region and the other as an N-type transistor region.

[0132] S810: Form a dummy gate layer on the surfaces of the fins and the shallow trench isolation region, and form first sidewall isolation layers on both sides of the dummy gate layer.

[0133] S820: Etch the fins to form electrode regions on both sides of the first sidewall isolation layers, and the vertical projection of the fins on the substrate coincides with the vertical projections of the dummy gate layer and the first sidewall isolation layers on the substrate.

[0134] S830: Etch the edge of the first channel layer or the second channel layer from the electrode region corresponding to the P-type transistor region towards the center direction, so that first grooves are formed at both ends of the first channel layer or the second channel layer in the P-type transistor region; etch the edge of the first channel layer or the second channel layer from the electrode region corresponding to the N-type transistor region towards the center direction, so that second grooves are formed at both ends of the first channel layer or the second channel layer in the N-type transistor region.

[0135] S840: Form second sidewall isolation layers in the first grooves and the second grooves.

[0136] S850: Form a second source electrode and a second drain electrode in the electrode region corresponding to the N-type transistor region, and form a first source electrode and a first drain electrode in the electrode region corresponding to the P-type transistor region.

[0137] S860: Form an insulating region between the electrode region corresponding to the N-type transistor region and the electrode region corresponding to the P-type transistor region.

[0138] S870: Remove the dummy gate layer.

[0139] S880: Remove the etched first channel layer in the P-type transistor region, release the second channel layer in the P-type transistor region to form a first nanosheet channel, or remove the etched second channel layer in the P-type transistor region, release the first channel layer in the P-type transistor region to form a first nanosheet channel; remove the etched first channel layer in the N-type transistor region, release the second channel layer in the N-type transistor region to form a second nanosheet channel, or remove the etched second channel layer in the N-type transistor region, release the first channel layer in the N-type transistor region to form a second nanosheet channel.

[0140] S890: Form a first sacrificial stress layer on the surface of the first nanosheet channel, and / or form a second sacrificial stress layer on the surface of the second nanosheet channel; the intrinsic lattice constant of the first sacrificial stress layer is smaller than the intrinsic lattice constant of the first nanosheet channel, and the intrinsic lattice constant of the second sacrificial stress layer is larger than the intrinsic lattice constant of the second nanosheet channel.

[0141] S891: Perform a high-temperature annealing treatment on the gate-all-around device.

[0142] S892: Remove the first sacrificial stress layer, and / or remove the second sacrificial stress layer.

[0143] S893: Form a first gate surrounding the first nanosheet channel; form a second gate surrounding the second nanosheet channel.

[0144] Specifically, as Figure 20 shown, form a gate 37 surrounding the first nanosheet channel and the second nanosheet channel. The gate 37 surrounding the first nanosheet channel in the P-type transistor region 1 is the first gate, and the gate 37 surrounding the second nanosheet channel in the N-type transistor region 2 is the second gate. After forming the gate 37, subsequent middle-section and back-end processes same as those of a conventional gate-all-around device can be performed.

[0145] Optionally, on the basis of the above embodiments, Figure 21 is a flowchart of another method for manufacturing a gate-all-around device provided by an embodiment of the present invention. As Figure 21 shown, the manufacturing method includes:

[0146] S900: Form a first sacrificial stress layer on the surface of the first nanosheet channel, and / or form a first silicon-germanium sacrificial stress layer on the surface of the second nanosheet channel; the second nanosheet channel includes a silicon nanosheet channel, and the intrinsic lattice constant of the first sacrificial stress layer is smaller than the intrinsic lattice constant of the first nanosheet channel.

[0147] S910: Perform a high-temperature annealing process on the gate-all-around device.

[0148] S920: Remove the first sacrificial stress layer, and / or etch the first silicon-germanium sacrificial stress layer using a combined gas of a halogen-based oxidizing gas and a halogen-based acidic gas.

[0149] Specifically, as Figure 3 shown, after the high-temperature annealing process, at this time the second sacrificial stress layer is the first silicon-germanium sacrificial stress layer, and the first silicon-germanium sacrificial stress layer can be etched and removed using a combined gas of a halogen-based oxidizing gas and a halogen-based acidic gas, and the combined ratio of the halogen-based oxidizing gas and the halogen-based acidic gas can be 50:1.

[0150] Optionally, the technical solution of the embodiments of the present invention can be extended to traditional gate-all-around fully depleted silicon-on-insulator (FDSOI) planar devices based on GAA, as well as vertical stacked complementary field-effect transistor (CFET) devices, FDSOI-GAA devices, and junctionless field-effect transistor silicon-on-insulator devices with similar structures, all of which have similar process flows and principles.

[0151] The embodiments of the present invention disclose a gate-all-around device, wherein the gate-all-around device is prepared using the preparation method of any gate-all-around device provided in any of the above embodiments of the present invention, and has the beneficial effects of the preparation method of any gate-all-around device provided in any of the above embodiments of the present invention.

[0152] It should be understood that various forms of the processes shown above can be used, steps can be reordered, added, or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved, and no limitation is made herein.

[0153] The above specific embodiments do not constitute a limitation to the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for fabricating a gate-all-around device, characterized in that, The ring gate device includes: a substrate, the substrate is provided with a P-type transistor region and an N-type transistor region, the N-type transistor region and the P-type transistor region are insulated from each other at intervals on one side of the substrate; the P-type transistor region is provided with a first nanosheet channel, and the N-type transistor region is provided with a second nanosheet channel; The manufacturing method includes: forming a first sacrificial stress layer on the surface of the first nanosheet channel, and / or forming a second sacrificial stress layer on the surface of the second nanosheet channel; the intrinsic lattice constant of the first sacrificial stress layer is smaller than the intrinsic lattice constant of the first nanosheet channel, and the intrinsic lattice constant of the second sacrificial stress layer is larger than the intrinsic lattice constant of the second nanosheet channel; performing an annealing treatment on the ring gate device; removing the first sacrificial stress layer, and / or removing the second sacrificial stress layer.

2. The manufacturing method of the gate-all-around device according to claim 1, wherein The first nanosheet channel includes a silicon-germanium nanosheet channel; forming a first sacrificial stress layer on the surface of the first nanosheet channel includes: forming a silicon sacrificial stress layer on the surface of the first nanosheet channel.

3. The manufacturing method of the gate-all-around device according to claim 1, characterized in that, The first nanosheet channel includes a silicon nanosheet channel; forming a first sacrificial stress layer on the surface of the first nanosheet channel includes: forming a silicon carbide sacrificial stress layer on the surface of the first nanosheet channel.

4. The manufacturing method of the gate-all-around device according to claim 1, wherein, The second nanosheet channel includes a silicon nanosheet channel; forming a second sacrificial stress layer on the surface of the second nanosheet channel includes: forming a first silicon-germanium sacrificial stress layer on the surface of the second nanosheet channel.

5. The manufacturing method of the gate-all-around device according to claim 1, characterized in that, The second nanosheet channel includes a silicon-germanium nanosheet channel; forming a second sacrificial stress layer on the surface of the second nanosheet channel includes: forming a second silicon-germanium sacrificial stress layer on the surface of the second nanosheet channel, and the content of germanium element in the second silicon-germanium sacrificial stress layer is greater than the content of germanium element in the silicon-germanium nanosheet channel.

6. The manufacturing method of the gate-all-around device according to claim 4, wherein The first silicon-germanium sacrificial stress layer includes a first sub-silicon-germanium sacrificial stress layer and a second sub-silicon-germanium sacrificial stress layer; forming a first silicon-germanium sacrificial stress layer on the surface of the second nanosheet channel includes: forming the first sub-silicon-germanium sacrificial stress layer on the surface of the second nanosheet channel; forming a second sub-silicon-germanium sacrificial stress layer on the side of the first sub-silicon-germanium sacrificial stress layer away from the second nanosheet channel; the content of germanium element in the second sub-silicon-germanium sacrificial stress layer is greater than the content of germanium element in the first sub-silicon-germanium sacrificial stress layer.

7. The manufacturing method of the gate-all-around device according to claim 1, characterized in that forming a first sacrificial stress layer on the surface of the first nanosheet channel, and / or forming a second sacrificial stress layer on the surface of the second nanosheet channel includes: providing a substrate, sequentially forming an alternately stacked first channel layer and a second channel layer on one side of the substrate, etching the first channel layer and the second channel layer to form a plurality of fins distributed periodically, etching a part of the substrate to form isolation grooves, and forming a shallow trench isolation region in the isolation grooves; defining one of the adjacent fins as a P-type transistor region and the other as an N-type transistor region; forming a dummy gate layer on the surface of the fin and the shallow trench isolation region, and forming a first sidewall isolation layer on both sides of the dummy gate layer; Etch the fin to form electrode regions on both sides of the first sidewall isolation layer, and the vertical projection of the fin on the substrate coincides with the vertical projections of the dummy gate layer and the first sidewall isolation layer on the substrate; Etch the edge of the first channel layer or the second channel layer from the electrode region corresponding to the P-type transistor region towards the center direction, so as to form first grooves at both ends of the first channel layer or the second channel layer in the P-type transistor region; etch the edge of the first channel layer or the second channel layer from the electrode region corresponding to the N-type transistor region towards the center direction, so as to form second grooves at both ends of the first channel layer or the second channel layer in the N-type transistor region; Form a second sidewall isolation layer in the first grooves and the second grooves; Form a second source electrode and a second drain electrode in the electrode region corresponding to the N-type transistor region, and form a first source electrode and a first drain electrode in the electrode region corresponding to the P-type transistor region; Form an insulating region between the electrode region corresponding to the N-type transistor region and the electrode region corresponding to the P-type transistor region; Remove the dummy gate layer; Remove the etched first channel layer in the P-type transistor region, and release the second channel layer in the P-type transistor region to form a first nanosheet channel, or remove the etched second channel layer in the P-type transistor region, and release the first channel layer in the P-type transistor region to form a first nanosheet channel; remove the etched first channel layer in the N-type transistor region, and release the second channel layer in the N-type transistor region to form a second nanosheet channel, or remove the etched second channel layer in the N-type transistor region, and release the first channel layer in the N-type transistor region to form a second nanosheet channel.

8. The manufacturing method of the gate-all-around device according to claim 1, wherein, After removing the first sacrificial stress layer and / or removing the second sacrificial stress layer, further comprising: Form a first gate surrounding the first nanosheet channel; Form a second gate surrounding the second nanosheet channel.

9. The manufacturing method of the gate-all-around device according to claim 4, wherein Removing the second sacrificial stress layer includes: Etching the second sacrificial stress layer using a combined gas of a halogen-based oxidizing gas and a halogen-based acidic gas.

10. A gate-all-around device, characterized in that, Prepared by using the preparation method of the gate-all-around device according to any one of claims 1-9.

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