MOS device with field plate and manufacturing method thereof
By forming a multi-stage field plate structure on the semiconductor substrate, the problem of taking into account both the field plate height of LDMOS and DEMOS devices is solved, and the quality and reliability of the device are improved.
Patent Information
- Application Number
- CN202510447675.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-10
- Publication Date
- 2025-07-04
AI Technical Summary
Existing LDMOS and DEMOS devices have difficulties in taking into account the requirements for field plate height of different devices, especially the field plate height requirements of low-voltage devices and high-voltage devices are difficult to take into account.
Using a multi-step field plate structure, a first step dielectric layer, a second step dielectric layer and a first gate dielectric layer with different thicknesses are formed on the semiconductor substrate, and combined with the existing double gate process, a step field plate is formed, taking into account the field plate height requirements of different devices.
It realizes that without increasing process difficulty and complexity, taking into account the requirements of different devices for field plate height, and improves the quality and reliability of MOS devices.
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Figure CN120264798A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and particularly to a MOS device with a field plate and a manufacturing method thereof. Background Art
[0002] In modern electronic devices, LDMOS (Laterally Diffused Metal Oxide Semiconductor) devices and DEMOS (Drain Extended Metal Oxide Semiconductor) devices are commonly used semiconductor devices. They play important roles in many fields, such as communication, power amplifiers, and radio frequency applications.
[0003] LDMOS devices and DEMOS devices usually utilize a surface field plate to assist in the depletion of the drift region and regulate the electric field below to obtain a higher source-drain breakdown voltage (BVds) and a lower on-resistance (Ron). Different devices, such as low-voltage devices and high-voltage devices, have different requirements for the height of the field plate (the vertical distance from the substrate surface). How to balance the requirements of different devices has become the research focus of those skilled in the art. Summary of the Invention
[0004] The purpose of the present invention is to provide a MOS device with a field plate and a manufacturing method thereof to balance the requirements of different devices for the height of the field plate.
[0005] To this end, the present invention provides a manufacturing method of a MOS device with a field plate, and the manufacturing method of the MOS device with a field plate includes:
[0006] Providing a semiconductor substrate;
[0007] Forming a first stepped dielectric layer on the semiconductor substrate, the first stepped dielectric layer exposing a part of the semiconductor substrate, and the first stepped dielectric layer having a first thickness;
[0008] Thinning a part of the first stepped dielectric layer to form a second stepped dielectric layer, the second stepped dielectric layer having a second thickness;
[0009] Forming a first gate dielectric layer on the semiconductor substrate, the first gate dielectric layer having a third thickness; and,
[0010] Using the first gate dielectric layer, the second stepped dielectric layer, and / or the first stepped dielectric layer to form a stepped field plate, the stepped field plate having at least three heights.
[0011] Optionally, in the manufacturing method of the MOS device with a field plate, using the first gate dielectric layer, the second stepped dielectric layer, and / or the first stepped dielectric layer to form a stepped field plate includes:
[0012] Form a blocking layer that covers the first gate dielectric layer, the second stepped dielectric layer, and the first stepped dielectric layer; and,
[0013] Form a contact hole field plate on the blocking layer, the contact hole field plate having a first height, a second height, and a third height, and the stepped field plate includes the contact hole field plate.
[0014] Optionally, in the manufacturing method of the MOS device with a field plate, using the first gate dielectric layer, the second stepped dielectric layer, and / or the first stepped dielectric layer to form a stepped field plate further includes:
[0015] Form a metal layer field plate on the contact hole field plate, the metal layer field plate having a fourth height, and the stepped field plate includes the metal layer field plate.
[0016] Optionally, in the manufacturing method of the MOS device with a field plate, after forming the first stepped dielectric layer on the semiconductor substrate and before thinning part of the first stepped dielectric layer to form the second stepped dielectric layer, the manufacturing method of the MOS device with a field plate further includes:
[0017] Form a second gate dielectric layer on the semiconductor substrate, the second gate dielectric layer having a fourth thickness.
[0018] Optionally, in the manufacturing method of the MOS device with a field plate, when thinning part of the first stepped dielectric layer to form the second stepped dielectric layer, the manufacturing method of the MOS device with a field plate further includes:
[0019] Remove part of the second gate dielectric layer to expose the semiconductor substrate.
[0020] Optionally, in the manufacturing method of the MOS device with a field plate, using the first gate dielectric layer, the second stepped dielectric layer, and / or the first stepped dielectric layer to form a stepped field plate further includes:
[0021] Form a gate field plate on the first stepped dielectric layer, the gate field plate having a fifth height, and the stepped field plate includes the gate field plate.
[0022] Optionally, in the manufacturing method of the MOS device with a field plate, when forming a gate field plate on the second stepped dielectric layer, the manufacturing method of the MOS device with a field plate further includes:
[0023] Form a second gate electrode on the second gate dielectric layer.
[0024] Optionally, in the manufacturing method of the MOS device with a field plate, the semiconductor substrate includes a core region and an input / output region. The first gate dielectric layer is formed in both the core region and the input / output region, and the second gate dielectric layer is located in the input / output region. When forming the second gate electrode on the second gate dielectric layer, the manufacturing method of the MOS device with a field plate further includes:
[0025] Forming a first gate electrode on the first gate dielectric layer in the core region.
[0026] Optionally, in the manufacturing method of the MOS device with a field plate, an adjacent drift region and body region are formed in the semiconductor substrate of the input / output region. The second gate dielectric layer covers part of the drift region and extends to cover part of the body region. The first gate dielectric layer, the second stepped dielectric layer, and the first stepped dielectric layer cover part of the drift region.
[0027] The present invention also provides a MOS device with a field plate, which includes:
[0028] A semiconductor substrate;
[0029] A first stepped dielectric layer formed on the semiconductor substrate, the first stepped dielectric layer having a first thickness;
[0030] A second stepped dielectric layer formed on the semiconductor substrate, the second stepped dielectric layer having a second thickness;
[0031] A first gate dielectric layer formed on the semiconductor substrate, the first gate dielectric layer having a third thickness; and,
[0032] A stepped field plate located on the first gate dielectric layer, the second stepped dielectric layer, and / or the first stepped dielectric layer, the stepped field plate having at least three heights.
[0033] In the MOS device with a field plate and its manufacturing method provided by the present invention, a stepped field plate is formed by using the first gate dielectric layer, the second stepped dielectric layer, and / or the first stepped dielectric layer with different thicknesses. The stepped field plate has at least three heights, and a multi-stepped field plate is conveniently formed by using the process characteristics of the MOS device, taking into account the requirements of different devices for the height of the field plate. Description of the Drawings
[0034] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application. In the drawings:
[0035] Figure 1The flowchart shows a manufacturing method of a MOS device with a field plate according to an embodiment of the present application.
[0036] Figures 2 to 9 The structural diagrams show different stages during the execution of a manufacturing method of a MOS device with a field plate according to an embodiment of the present application.
[0037] The reference numerals are explained as follows:
[0038] 100 - semiconductor substrate; 100A - core region; 100B - input / output region; 101 - drift region; 102 - body region; 103 - drain region; 104 - N-type source region; 105 - P-type source region; 110 - first stepped dielectric layer; 120 - second gate dielectric layer; 130 - second stepped dielectric layer; 140 - first gate dielectric layer; 150 - second gate electrode; 160 - first gate electrode; 170 - gate field plate; 180 - sidewall structure; 190 - barrier layer; 200 - contact hole field plate; 210 - metal layer field plate; 220 - stepped field plate. Detailed implementation manners
[0039] The MOS device with a field plate and its manufacturing method proposed by the present invention are further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will be clearer according to the following description and the claims. It should be noted that the accompanying drawings are in very simplified forms and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.
[0040] The terms used in this invention are only for the purpose of describing specific embodiments and are not intended to limit the invention. Unless otherwise defined in this application document, the technical terms or scientific terms used in this invention shall have the ordinary meaning as understood by those of ordinary skill in the art to which this invention pertains. The terms "first", "second" and similar words used in the specification and claims of this invention do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "a" or "an" do not denote a quantity limitation, but mean that there is at least one. "Plurality" or "several" means two or more. Unless otherwise specified, words such as "front", "rear", "lower" and / or "upper" are only for convenience of description and are not limited to a position or a spatial orientation. Words such as "comprising" or "including" mean that the elements or items appearing before "comprising" or "including" cover the elements or items listed after "comprising" or "including" and their equivalents, and do not exclude other elements or items. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, and may include electrical connections, whether direct or indirect. The singular forms "a", "the" and "said" used in the specification and appended claims of this invention are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any and all possible combinations of one or more of the associated listed items.
[0041] Different devices, such as low-voltage devices and high-voltage devices, have different requirements for the height of the field plate (the vertical distance from the substrate surface), while the height of the existing field plate is usually relatively fixed and single.
[0042] This application provides a MOS device with a field plate and a manufacturing method thereof. Combining with the process of the existing MOS device, in particular, perfectly utilizing the existing Dual Gate process, a multi-step field plate is formed without increasing the process difficulty and complexity, taking into account the requirements of different devices for the height of the field plate.
[0043] Please refer to Figure 1 , which shows a schematic flow chart of a manufacturing method of a MOS device with a field plate according to an embodiment of this application. As Figure 1 shown, the manufacturing method of the MOS device with a field plate includes:
[0044] Step S10: Provide a semiconductor substrate;
[0045] Step S20: Form a first-step dielectric layer on the semiconductor substrate, the first-step dielectric layer exposing a part of the semiconductor substrate, and the first-step dielectric layer having a first thickness;
[0046] Step S30: Thinning a part of the first stepped dielectric layer to form a second stepped dielectric layer, where the second stepped dielectric layer has a second thickness;
[0047] Step S40: Forming a first gate dielectric layer on the semiconductor substrate, where the first gate dielectric layer has a third thickness; and,
[0048] Step S50: Using the first gate dielectric layer, the second stepped dielectric layer, and / or the first stepped dielectric layer to form a stepped field plate, where the stepped field plate has at least three heights.
[0049] In the embodiments of the present application, a stepped field plate is formed by using a first gate dielectric layer, a second stepped dielectric layer, and / or a first stepped dielectric layer with different thicknesses. The stepped field plate has at least three heights. By utilizing the process characteristics of MOS devices, a multi-stepped field plate is conveniently formed, taking into account the requirements of different devices for the height of the field plate.
[0050] Please refer to Figures 2 to 9 , Figures 2 to 9 which shows a schematic structural diagram of a manufacturing method of a MOS device with a field plate at different stages during execution according to an embodiment of the present application.
[0051] As Figure 2 shown, a semiconductor substrate 100 is provided. The semiconductor substrate 100 can be a bulk silicon substrate (Si), a bulk germanium substrate (Ge), a silicon germanium substrate (SiGe), a silicon-on-insulator substrate (SOI), a germanium-on-insulator substrate (GOI), etc. In the embodiments of the present application, the semiconductor substrate 100 includes a core area (core) 100A and an input / output area (I / O) 100B.
[0052] In some embodiments of the present application, the semiconductor substrate 100 can be subjected to a doping process to form one or more doped regions; in other embodiments of the present application, the semiconductor substrate 100 can be undoped. Among them, the core area 100A and the input / output area 100B can be subjected to different doping processes to form different functional regions.
[0053] As Figure 2 shown, in the embodiments of the present application, both the core area 100A and the input / output area 100B can be P-type doped to form a P-type well region (not shown in the figure). Among them, the input / output area 100B can also be N-type and / or P-type doped to form an N-type drift region (NDRF) 101 and a P-type body region (PBODY) 102. The drift region 101 and the body region 102 are juxtaposed in the horizontal direction and the drift region 101 and the body region 102 are adjacent.
[0054] The input / output region 100B can also be doped with N-type and / or P-type dopants to form an N-type drain region 103, an N-type source region 104, and a P-type source region 105. The drain region 103 is located in the drift region 101 and extends from the surface of the drift region 101 into the drift region 101. Both the N-type source region 104 and the P-type source region 105 are located in the body region 102 and extend from the surface of the body region 102 into the body region 102 respectively. The N-type source region 104 and the P-type source region 105 are juxtaposed in the horizontal direction and adjacent to each other.
[0055] Next, as Figure 3 shown, a first stepped dielectric layer 110 is formed on the semiconductor substrate 100. The first stepped dielectric layer 110 exposes a part of the semiconductor substrate 100 and has a first thickness. In some embodiments of the present application, a dielectric material layer may be deposited first. The material of the dielectric material layer may be, for example, silicon oxide, and the dielectric material layer covers the surface of the semiconductor substrate 100. Then, a patterning process, such as a dry and / or wet etching process, is performed on the dielectric material layer to form the first stepped dielectric layer 110. In the embodiments of the present application, the first stepped dielectric layer 110 may cover a part of the semiconductor substrate 100 in the core region 100A and a part of the semiconductor substrate 100 in the input / output region 100B. In other embodiments of the present application, the first stepped dielectric layer 110 may also only cover a part of the semiconductor substrate 100 in the core region 100A or a part of the semiconductor substrate 100 in the input / output region 100B.
[0056] In some embodiments of the present application, after forming the first stepped dielectric layer 110, a part of the first stepped dielectric layer may be thinned to form a second stepped dielectric layer, and the second stepped dielectric layer has a second thickness. And, a first gate dielectric layer is formed on the semiconductor substrate, and the first gate dielectric layer has a third thickness.
[0057] In the embodiments of the present application, as Figure 4 shown, after forming the first stepped dielectric layer 110, a second gate dielectric layer 120 is then formed on the semiconductor substrate 100, and the second gate dielectric layer 120 has a fourth thickness. In the embodiments of the present application, the fourth thickness is less than the first thickness. In some embodiments of the present application, the second gate dielectric layer 120 can be formed on the exposed semiconductor substrate 100 by an oxidation process, which can not only simplify the process but also repair the lattice damage on the surface of the semiconductor substrate 100, improving the quality and reliability of the formed MOS device.
[0058] AsFigure 5 As shown, in an embodiment of the present application, then, a part of the first stepped dielectric layer 110 is thinned to form a second stepped dielectric layer 130, and the second stepped dielectric layer 130 has a second thickness. In an embodiment of the present application, the second thickness is less than the first thickness, and the second thickness is greater than the fourth thickness.
[0059] In some embodiments of the present application, a patterned photoresist layer (not shown in the figure) can be used to cover a part of the first stepped dielectric layer 110 while exposing another part of the first stepped dielectric layer 110; then, the exposed first stepped dielectric layer 110 is etched to remove a part of the thickness of the first stepped dielectric layer 110 to form the second stepped dielectric layer 130.
[0060] In some embodiments of the present application, the patterned photoresist layer can be formed by using a mask in an existing dual gate process, so that the existing dual gate process can be compatible, the manufacturing process can be simplified, and the manufacturing cost can be reduced. The patterned photoresist layer can further cover a part of the second gate dielectric layer 120 and expose another part of the second gate dielectric layer 120. When etching the exposed first stepped dielectric layer 110, the exposed second gate dielectric layer 120 can be etched simultaneously. In some embodiments of the present application, the exposed second gate dielectric layer 120 is removed to expose the surface of the corresponding semiconductor substrate 100. Among them, the removed thickness in the exposed first stepped dielectric layer 110 can be, for example, the thickness of the second gate dielectric layer 120, that is, the exposed first stepped dielectric layer 110 is etched to remove the first stepped dielectric layer 110 with a fourth thickness.
[0061] Such as Figure 5As shown, in some embodiments of the present application, only the second gate dielectric layer 120 may be retained on the surface of the semiconductor substrate 100 in the input / output region 100B. The second gate dielectric layer 120 covers a part of the drift region 101 and extends to cover a part of the body region 102. In some embodiments of the present application, the first stepped dielectric layer 110 and the second stepped dielectric layer 120 may both be retained on the surface of the semiconductor substrate 100 in the core region 100A and the input / output region 100B. The first stepped dielectric layer 110 and the second stepped dielectric layer 120 may adjust the stress of the semiconductor substrate 100, etc.; the first stepped dielectric layer 110 and the second stepped dielectric layer 120 covering the surface of the semiconductor substrate 100 in the input / output region 100B may also be used to form a stepped field plate, so that the formed stepped field plate has multiple heights. Among them, the first stepped dielectric layer 110 and the second stepped dielectric layer 120 in the input / output region 100B cover a part of the drift region 101. In some embodiments of the present application, the first stepped dielectric layer 110 in the input / output region 100B includes multiple parts, and the second stepped dielectric layer 120 is adjacent to some of the first stepped dielectric layer 110.
[0062] In an embodiment of the present application, then, as Figure 6 shown, a first gate dielectric layer 140 is formed on the semiconductor substrate 100, and the first gate dielectric layer 140 has a third thickness. As Figure 6 shown, in some embodiments of the present application, the third thickness is less than the first thickness, less than the second thickness, and less than the fourth thickness. In some embodiments of the present application, the first gate dielectric layer 140 may be formed on the exposed semiconductor substrate 100 by an oxidation process, so that the process can be simplified, and the lattice damage on the surface of the semiconductor substrate 100 can be repaired, improving the quality and reliability of the formed MOS device.
[0063] As Figure 6 shown, in an embodiment of the present application, the first gate dielectric layer 140 may be formed on the surface of the semiconductor substrate 100 in both the core region 100A and the input / output region 100B. Among them, the first gate dielectric layer 140 in the input / output region 100B may be adjacent to the second stepped dielectric layer 130 and cover a part of the drift region 101. In some embodiments of the present application, the first gate dielectric layer 140 in the input / output region 100B may also be adjacent to some of the first stepped dielectric layer 110.
[0064] In the embodiments of the present application, the first gate dielectric layer 140 can be used to form a first gate structure, and the second gate dielectric layer 120 can be used to form a second gate structure. The first gate structure and the second gate structure have gate dielectric layers with different thicknesses, and the two can have different electrical properties to achieve different functions. In the embodiments of the present application, the first gate dielectric layer 140 covering the surface of the semiconductor substrate 100 of the input / output region 100B can also be used to form a stepped field plate, so that the formed stepped field plate has multiple heights.
[0065] Please refer to Figure 7 , in the embodiments of the present application, then, a second gate electrode 150 is formed on the second gate dielectric layer 120 to form a second gate structure. In some embodiments of the present application, when forming the second gate electrode 150, a first gate electrode 160 can also be formed on the first gate dielectric layer 140 in the core region 100A to form a first gate structure. In some embodiments of the present application, when forming the second gate electrode 150, a gate field plate 170 can also be formed on a part of the first stepped dielectric layer 110. The gate field plate 170 has a fifth height, and the stepped field plate includes the gate field plate 170. The fifth height is the distance from the lower surface of the gate field plate 170 to the surface of the semiconductor substrate 100. Among them, the gate field plate 170 can be connected to the second gate electrode 150. In some embodiments of the present application, the gate field plate 170, the first gate electrode 160, and the second gate electrode 150 are formed in the same process, so that the process can be simplified and the manufacturing cost can be reduced. Among them, the materials of the gate field plate 170, the first gate electrode 160, and the second gate electrode 150 can all be polysilicon, for example.
[0066] As Figure 8 shown, in some embodiments of the present application, a sidewall structure 180 can then be formed. The sidewall structure 180 can cover the sidewalls of the first gate electrode 160 and the second gate electrode 150; in some embodiments of the present application, the sidewall structure 180 can also cover the sidewalls of the gate field plate 170 to protect the gate field plate 170, the first gate electrode 160, and the second gate electrode 150.
[0067] Please continue to refer to Figure 8, in some embodiments of the present application, then, a blocking layer 190 is formed, and the blocking layer 190 covers the first gate dielectric layer 140, the second stepped dielectric layer 120, and the first stepped dielectric layer 110. In the embodiments of the present application, the blocking layer 190 covers the surfaces of the first gate dielectric layer 140, the second stepped dielectric layer 120, and the first stepped dielectric layer 110 exposed in the input / output region 100B. Wherein, the blocking layer 190 may further extend to cover a part of the gate field plate 170.
[0068] Then, a contact hole field plate 200 is formed on the blocking layer 190. The contact hole field plate 200 has a first height, a second height, and a third height. The stepped field plate includes the contact hole field plate 200. The first height, the second height, and the third height are the distances from the lower surface of the contact hole field plate 200 to the surface of the semiconductor substrate 100. In the embodiments of the present application, the first stepped dielectric layer 110, the second stepped dielectric layer 130, and the first gate dielectric layer 140 have a first thickness, a second thickness, and a third thickness respectively. Wherein, the first thickness is greater than the second thickness, and the second thickness is greater than the third thickness. Correspondingly, the contact hole field plate 200 formed by using the first stepped dielectric layer 110, the second stepped dielectric layer 130, and the first gate dielectric layer 140 has a first height, a second height, and a third height, and the first height, the second height, and the third height respectively correspond to the first thickness, the second thickness, and the third thickness. In the embodiments of the present application, the blocking layer 190 is formed. Correspondingly, the first height, the second height, and the third height are respectively the sum of the first thickness, the second thickness, and the third thickness and the thickness of the blocking layer 190.
[0069] In other embodiments of the present application, the contact hole field plate 200 may also be only located on one or both of the first stepped dielectric layer 110, the second stepped dielectric layer 130, and the first gate dielectric layer 140. Correspondingly, the contact hole field plate 200 has one or both of the first height, the second height, and the third height. In the embodiments of the present application, there is the blocking layer 190 between the contact hole field plate 200 and the first stepped dielectric layer 110, while the gate field plate 170 directly covers the first stepped dielectric layer 110. Therefore, the fifth height of the gate field plate 170 is different from the first height of the contact hole field plate 200. That is, in the embodiments of the present application, the stepped field plate includes the gate field plate 170 and the contact hole field plate 200. The stepped field plate has a first height, a second height, a third height, and a fifth height, and the stepped field plate is a four-stepped field plate.
[0070] Please refer toFigure 9 , in some embodiments of the present application, then, a metal layer field plate 210 is further formed on the contact hole field plate 200. The metal layer field plate 210 has a fourth height, and the stepped field plate includes the metal layer field plate 210. The fourth height is the distance from the lower surface of the metal layer field plate 210 to the surface of the semiconductor substrate 100. In the embodiments of the present application, the stepped field plate has a first height, a second height, a third height, a fourth height, and a fifth height, and the stepped field plate is a five-step field plate; in other embodiments of the present application, the stepped field plate can also reduce the height as needed. For example, the contact hole field plate 200 can be located only above one of the first stepped dielectric layer 110, the second stepped dielectric layer 130, and the first gate dielectric layer 140. Correspondingly, the contact hole field plate 200 has only one height, so that the stepped field plate is a three-step field plate.
[0071] In the embodiments of the present application, a stepped field plate is formed by using the first gate dielectric layer 140, the second stepped dielectric layer 130, and / or the first stepped dielectric layer 110 with different thicknesses. The stepped field plate has at least three heights, and a multi-step field plate is conveniently formed by using the process characteristics of MOS devices, taking into account the requirements of different devices for the height of the field plate.
[0072] Correspondingly, the embodiments of the present application further provide a MOS device with a field plate, such as Figure 9 shown. The MOS device with a field plate includes: a semiconductor substrate 100; a first stepped dielectric layer 110 formed on the semiconductor substrate 100, and the first stepped dielectric layer 110 has a first thickness; a second stepped dielectric layer 130 formed on the semiconductor substrate 100, and the second stepped dielectric layer 130 has a second thickness; a first gate dielectric layer 140 formed on the semiconductor substrate 100, and the first gate dielectric layer 140 has a third thickness; and a stepped field plate 220 located on the first gate dielectric layer 140, the second stepped dielectric layer 130, and / or the first stepped dielectric layer 110, and the stepped field plate 220 has at least three heights.
[0073] In the embodiments of the present application, the stepped field plate 220 includes a contact hole field plate 200, a metal layer field plate 210, and a gate field plate 170. Among them, the contact hole field plate 200 has a first height, a second height, and a third height, the metal layer field plate 210 has a fourth height, the gate field plate 170 has a fifth height, and the stepped field plate 220 is a five-step field plate, which can take into account the requirements of different devices for the height of the field plate and improve the quality and reliability of the MOS device.
[0074] In the embodiment of the present application, the semiconductor substrate 100 includes a core region 100A and an input / output region 100B. Gate structures with different gate dielectric layer thicknesses can be formed in the core region 100A and the input / output region 100B. For example, a double-gate structure can be formed to meet different functional requirements. At the same time, in the embodiment of the present application, by utilizing the process characteristics of the double-gate structure, a multi-step field plate is formed. Thus, on the basis of not increasing the process difficulty and complexity, a multi-step field plate is formed, which takes into account the requirements of different devices for the height of the field plate and avoids the increase in process cost.
[0075] The above description is only a description of the preferred embodiment of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the field of the present invention according to the above disclosure shall fall within the protection scope of the claims.
Claims
1. A manufacturing method of a MOS device with a field plate, characterized in that, The manufacturing method of the MOS device with field plates includes: Providing a semiconductor substrate; Forming a first stepped dielectric layer on the semiconductor substrate, the first stepped dielectric layer exposing a part of the semiconductor substrate, the first stepped dielectric layer having a first thickness; Thinning a part of the first stepped dielectric layer to form a second stepped dielectric layer, the second stepped dielectric layer having a second thickness; Forming a first gate dielectric layer on the semiconductor substrate, the first gate dielectric layer having a third thickness; and, Using the first gate dielectric layer, the second stepped dielectric layer and / or the first stepped dielectric layer to form a stepped field plate, the stepped field plate having at least three heights.
2. The manufacturing method of the MOS device with a field plate as described in claim 1, characterized in that, Using the first gate dielectric layer, the second stepped dielectric layer and / or the first stepped dielectric layer to form a stepped field plate includes: Forming a barrier layer, the barrier layer covering the first gate dielectric layer, the second stepped dielectric layer and the first stepped dielectric layer; and, Forming a contact hole field plate on the barrier layer, the contact hole field plate having a first height, a second height and a third height, the stepped field plate including the contact hole field plate.
3. The manufacturing method of the MOS device with field plates as described in claim 2, characterized in that, Using the first gate dielectric layer, the second stepped dielectric layer and / or the first stepped dielectric layer to form a stepped field plate further includes: Forming a metal layer field plate on the contact hole field plate, the metal layer field plate having a fourth height, the stepped field plate including the metal layer field plate.
4. The manufacturing method of the MOS device with field plates as described in claim 1, characterized in that, After forming the first stepped dielectric layer on the semiconductor substrate and before thinning a part of the first stepped dielectric layer to form a second stepped dielectric layer, the manufacturing method of the MOS device with field plates further includes: Forming a second gate dielectric layer on the semiconductor substrate, the second gate dielectric layer having a fourth thickness.
5. The manufacturing method of the MOS device with a field plate according to claim 4, characterized in that, When thinning a part of the first stepped dielectric layer to form a second stepped dielectric layer, the manufacturing method of the MOS device with field plates further includes: Removing a part of the second gate dielectric layer to expose the semiconductor substrate.
6. The manufacturing method of the MOS device with a field plate as described in claim 4, characterized in that, Using the first gate dielectric layer, the second stepped dielectric layer and / or the first stepped dielectric layer to form a stepped field plate further includes: Forming a gate field plate on the first stepped dielectric layer, the gate field plate having a fifth height, the stepped field plate including the gate field plate.
7. The manufacturing method of the MOS device with field plates as described in claim 6, characterized in that, When forming a gate field plate on the second stepped dielectric layer, the manufacturing method of the MOS device with field plates further includes: Forming a second gate electrode on the second gate dielectric layer.
8. The manufacturing method of the MOS device with field plates as described in any one of claims 4 to 7, characterized in that, The semiconductor substrate includes a core region and an input / output region, the first gate dielectric layer being formed in both the core region and the input / output region, the second gate dielectric layer being located in the input / output region; When forming a second gate electrode on the second gate dielectric layer, the manufacturing method of the MOS device with field plates further includes: Forming a first gate electrode on the first gate dielectric layer in the core region.
9. The manufacturing method of the MOS device with a field plate as claimed in claim 8, characterized in that, An adjacent drift region and body region are formed in the semiconductor substrate of the input / output region, the second gate dielectric layer covering a part of the drift region and extending to cover a part of the body region; the first gate dielectric layer, the second stepped dielectric layer and the first stepped dielectric layer covering a part of the drift region.
10. A MOS device with a field plate, characterized in that, The MOS device with a field plate includes: a semiconductor substrate; a first stepped dielectric layer formed on the semiconductor substrate, the first stepped dielectric layer having a first thickness; a second stepped dielectric layer formed on the semiconductor substrate, the second stepped dielectric layer having a second thickness; a first gate dielectric layer formed on the semiconductor substrate, the first gate dielectric layer having a third thickness; and a stepped field plate located on the first gate dielectric layer, the second stepped dielectric layer, and / or the first stepped dielectric layer, the stepped field plate having at least three heights.