Thin film transistor, array substrate, manufacturing method of array substrate and display device

Abstract

The invention discloses a thin film transistor, an array substrate, a manufacturing method of the array substrate and a display device. The thin film transistor comprises a substrate, an active layer, a gate insulating layer and a gate electrode. The active layer is located on the substrate. And the gate insulating layer is positioned on one side, far away from the substrate, of the active layer. The grid electrode is positioned on one side, far away from the substrate, of the grid insulating layer; the grid electrode comprises a main electrode and a first auxiliary electrode located between the main electrode and the grid insulating layer, and the ion blocking capability and the light transmittance of the first auxiliary electrode are higher than those of the main electrode; the orthographic projection of the main electrode on the substrate is a first projection, the orthographic projection of the first auxiliary electrode on the substrate is a second projection, and the first projection is a proper subset of the second projection.

Description

Technical Field

[0001] This application belongs to the field of display technology, and particularly relates to a thin film transistor, an array substrate, a manufacturing method thereof, and a display device. Background Art

[0002] With the popularization of ultra-high PPI (Pixels Per Inch) products and the increasing demand in the VR (Virtual Reality) market, the display effect of ultra-high PPI products has also become the focus of research. By appropriately reducing the size of the TFT (Thin Film Transistor) in the pixel region, the aperture ratio of the pixel region can be directly and effectively increased, thereby optimizing the display effect. However, when the channel length of the TFT is less than 2 micrometers, obvious short-channel effects will occur in the TFT. The short-channel effects mainly include the DIBL (drain-induced barrier lowering) effect and the diffusion effect of conductive doping, both of which will affect the characteristics of the TFT. Summary of the Invention

[0003] This application provides a thin film transistor, an array substrate, a manufacturing method thereof, and a display device, aiming to at least to some extent solve the problem that the reduction of the TFT size is affected by the short-channel effect, which limits the improvement of the aperture ratio of the pixel region.

[0004] In the first aspect of this application, a thin film transistor is provided, and the thin film transistor includes: A substrate; An active layer, located on the substrate; A gate insulating layer, located on the side of the active layer away from the substrate; A gate electrode, located on the side of the gate insulating layer away from the substrate; the gate electrode includes a main electrode and a first auxiliary electrode located between the main electrode and the gate insulating layer, and both the ion blocking ability and the light transmittance of the first auxiliary electrode are higher than those of the main electrode; the orthographic projection of the main electrode on the substrate is a first projection, and the orthographic projection of the first auxiliary electrode on the substrate is a second projection, and the first projection is a proper subset of the second projection.

[0005] In some embodiments, the main electrode is a metal thin film, and the first auxiliary electrode is a metal compound thin film.

[0006] In some embodiments, the material of the main electrode is Mo, and the material of the first auxiliary electrode is TiN.

[0007] In some embodiments, the thin film transistor further includes: A source electrode, which is spaced from the gate electrode on the same side of the active layer and is electrically connected to the active layer; the edge line of the first projection and the second projection on the side close to the source electrode do not coincide. A drain electrode, which is spaced from the gate electrode and the source electrode on the same side of the active layer and is electrically connected to the active layer; the edge line of the first projection and the second projection on the side close to the drain electrode do not coincide.

[0008] In some embodiments, the gate electrode further includes a second auxiliary electrode located between the first auxiliary electrode and the gate insulating layer. The ion blocking ability of the second auxiliary electrode is lower than that of the first auxiliary electrode, and the light transmittance of the second auxiliary electrode is higher than that of the first auxiliary electrode; the orthographic projection of the second auxiliary electrode on the substrate is a third projection, the second projection is a proper subset of the third projection, the edge line of the second projection and the third projection on the side close to the source electrode do not coincide completely, and the edge line of the second projection and the third projection on the side close to the drain electrode do not coincide completely.

[0009] In some embodiments, the second auxiliary electrode is a transparent conductive thin film.

[0010] In some embodiments, the material of the second auxiliary electrode is ITO.

[0011] In some embodiments, the orthographic projection of the gate insulating layer on the substrate coincides with the third projection; or, the orthographic projection of the active layer on the substrate is located within the orthographic projection of the gate insulating layer on the substrate.

[0012] In some embodiments, the source electrode and the drain electrode are located on opposite sides of the gate electrode. The orthographic projection of the source electrode on the substrate is a fourth projection, and the orthographic projection of the drain electrode on the substrate is a fifth projection. The direction of the line connecting the center of the fourth projection to the center of the fifth projection is a set direction; If the length of the first projection in the set direction is greater than or equal to 1.5 microns, the distance between the edge line of the first projection and the edge line of the second projection is less than 0.5 microns; If the length of the first projection in the set direction is less than or equal to 1 micron, the distance between the edge line of the first projection and the edge line of the second projection is greater than or equal to 0.5 microns.

[0013] In a second aspect of the present application, an array substrate is provided, and the array substrate includes a thin film transistor provided in any embodiment of the first aspect.

[0014] In a third aspect of the present application, a display device is provided, and the display device includes an array substrate provided in any embodiment of the second aspect.

[0015] In a fourth aspect of the present application, a method for manufacturing an array substrate is provided, and the manufacturing method includes: Providing a substrate; Successively forming an active layer, a gate insulating layer, and a gate on the substrate; the gate includes a main electrode and a first auxiliary electrode located between the main electrode and the gate insulating layer, and both the ion blocking ability and the light transmittance of the first auxiliary electrode are higher than those of the main electrode; the orthographic projection of the main electrode on the substrate is a first projection, and the orthographic projection of the first auxiliary electrode on the substrate is a second projection, and the first projection is a proper subset of the second projection.

[0016] In some embodiments, the successively forming an active layer, a gate insulating layer, and a gate on the substrate includes: Successively forming an active layer and a gate insulating layer on the substrate; Successively laying a first auxiliary electrode material layer, a main electrode material layer, and a photoresist layer on the gate insulating layer, and performing a first patterning on the photoresist layer by a photolithography process; Etching the main electrode material layer and the first auxiliary electrode material layer by using the photoresist layer after the first patterning, and the etched first auxiliary electrode material layer forms a first auxiliary electrode; Performing an ashing process on the photoresist layer after the first patterning to obtain the photoresist layer after the second patterning; Etching the main electrode material layer by using the photoresist layer after the second patterning, and the etched main electrode material layer forms a main electrode; Removing the photoresist layer.

[0017] In some embodiments, before successively laying a first auxiliary electrode material layer, a main electrode material layer, and a photoresist layer on the gate insulating layer, the method further includes: Forming a second auxiliary electrode on the gate insulating layer; the ion blocking ability of the second auxiliary electrode is lower than that of the first auxiliary electrode, and the light transmittance of the second auxiliary electrode is higher than that of the first auxiliary electrode; the orthographic projection of the second auxiliary electrode on the substrate is a third projection, and the second projection is a proper subset of the third projection.

[0018] In some embodiments, after successively forming an active layer, a gate insulating layer, and a gate on the substrate, the method further includes: An interlayer dielectric layer is formed on the gate, and a first through hole and a second through hole are opened. Both the first through hole and the second through hole extend from the side of the interlayer dielectric layer away from the substrate to the active layer. A source electrode and a drain electrode are formed on the interlayer dielectric layer. The source electrode is electrically connected to the active layer through the first through hole, and the drain electrode is electrically connected to the active layer through the second through hole.

[0019] According to the thin film transistor, array substrate, manufacturing method thereof, and display device provided by one or more embodiments of the present application, by providing a first auxiliary electrode between the main electrode and the gate insulating layer, the ion blocking ability and light transmittance of the first auxiliary electrode are both higher than those of the main electrode, and the orthographic projection of the main electrode on the substrate is a proper subset of the orthographic projection of the first auxiliary electrode on the substrate. In this way, the portion of the first auxiliary electrode that coincides with the projection of the main electrode can block ions (implanted doping ions and / or diffused impurity ions) passing through the main electrode from further entering the active layer, and the portion of the first auxiliary electrode that is increased compared to the main electrode can also block ions (implanted doping ions and / or diffused impurity ions) moving along the edge of the main electrode from entering the active layer, thereby avoiding the reduction of the channel region caused by the implanted doping ions and / or diffused impurity ions entering the active layer from the main electrode and its surrounding areas, increasing the effective channel length of the TFT, avoiding the influence of the short channel effect, and ensuring the stability of the TFT characteristics. Moreover, the light transmittance of the first auxiliary electrode is relatively high, and the influence on the aperture ratio of the pixel region is small, which will not affect the improvement of the aperture ratio of the pixel region. Description of the Drawings

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0021] Figure 1 The structural schematic diagram of the thin film transistor in one or more embodiments of the present application is shown.

[0022] Figure 2 The structural schematic diagram of the thin film transistor in another embodiment of the present application is shown.

[0023] Figure 3 The structural schematic diagram of the thin film transistor in yet another embodiment of the present application is shown.

[0024] Figure 4 The structural schematic diagram of the thin film transistor in yet another embodiment of the present application is shown.

[0025] Figure 5The flowchart shows the manufacturing method of the array substrate in one or more embodiments of the present application.

[0026] Figure 6 Shows Figure 5 A flowchart of step S102.

[0027] Figure 7 Shows Figure 6 The structural schematic diagram of the array substrate after the execution of step S201.

[0028] Figure 8 Shows Figure 6 The structural schematic diagram of the array substrate after the execution of step S202.

[0029] Figure 9 Shows Figure 6 The structural schematic diagram of the array substrate after the execution of step S203.

[0030] Figure 10 Shows Figure 6 The structural schematic diagram of the array substrate after the execution of step S204.

[0031] Figure 11 Shows Figure 6 The structural schematic diagram of the array substrate after the execution of step S205.

[0032] Figure 12 Shows Figure 6 The structural schematic diagram of the array substrate after the execution of step S205.

[0033] Figure 13 Shows Figure 5 Another flowchart of step S102.

[0034] Figure 14 Shows Figure 13 The structural schematic diagram of the array substrate after the execution of step S301.

[0035] Figure 15 Shows Figure 13 The structural schematic diagram of the array substrate after the execution of step S302.

[0036] Figure 16 Shows Figure 13 The structural schematic diagram of the array substrate after the execution of step S303.

[0037] Figure 17 Shows Figure 13 The structural schematic diagram of the array substrate after the execution of step S304.

[0038] Figure 18 Shows Figure 13Schematic structural diagram of the array substrate after the execution of step S305.

[0039] Figure 19 shows Figure 13 Schematic structural diagram of the array substrate after the execution of step S305.

[0040] Figure 20 Schematic flow chart showing the manufacturing method of an array substrate in another embodiment of the present application.

[0041] Figure 21 shows Figure 20 Schematic structural diagram of the array substrate after the execution of step S403.

[0042] Figure 22 shows Figure 20 Schematic structural diagram of the array substrate after the execution of step S404.

[0043] Explanation of reference numerals: 10 - substrate, 20 - active layer, 30 - gate insulating layer, 40 - gate, 41 - main electrode, 42 - first auxiliary electrode, 43 - second auxiliary electrode, 50 - source electrode, 60 - drain electrode, 70 - interlayer dielectric layer, 80 - photoresist layer, 91 - first via hole, 92 - second via hole. Detailed implementation manners

[0044] In order to enable those skilled in the art in the technical field to which the present application belongs to more clearly understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0045] Figure 1 Schematic structural diagram of a thin-film transistor in one or more embodiments of the present application. Please refer to Figure 1 In the first aspect embodiment of the present application, a thin-film transistor is provided. The thin-film transistor includes a substrate 10, an active layer 20, a gate insulating layer 30, and a gate 40. The active layer 20 is located on the substrate 10. The gate insulating layer 30 is located on the side of the active layer 20 away from the substrate 10. The gate 40 is located on the side of the gate insulating layer 30 away from the substrate 10. The gate 40 includes a main electrode 41 and a first auxiliary electrode 42 located between the main electrode 41 and the gate insulating layer 30. The ion blocking ability and light transmittance of the first auxiliary electrode 42 are both higher than those of the main electrode 41. The orthographic projection of the main electrode 41 on the substrate 10 is a first projection, and the orthographic projection of the first auxiliary electrode 42 on the substrate 10 is a second projection. The first projection is a proper subset of the second projection.

[0046] In this embodiment, the ion blocking ability and light transmittance of the first auxiliary electrode 42 being higher than those of the main electrode 41 mean that the ion blocking ability of the first auxiliary electrode 42 is higher than that of the main electrode 41, and the light transmittance of the first auxiliary electrode 42 is higher than that of the main electrode 41.

[0047] The first projection being a proper subset of the second projection means that the first projection is located within the second projection, and the edge lines of the first projection and the second projection do not coincide. That is, the second projection includes a part that completely coincides with the first projection and a part that does not coincide with the first projection at all.

[0048] The above thin film transistor includes a substrate 10, an active layer 20, a gate insulating layer 30, and a gate electrode 40. The active layer 20, the gate insulating layer 30, and the gate electrode 40 are sequentially stacked on the substrate 10. The gate electrode 40 includes a main electrode 41 and a first auxiliary electrode 42 located between the main electrode 41 and the gate insulating layer 30. The ion blocking ability and light transmittance of the first auxiliary electrode 42 are both higher than those of the main electrode 41, and the orthographic projection of the main electrode 41 on the substrate 10 is a proper subset of the orthographic projection of the first auxiliary electrode 42 on the substrate 10. In this way, the part of the first auxiliary electrode 42 that coincides with the projection of the main electrode 41 can block the ions (implanted doping ions and / or diffused impurity ions) passing through the main electrode 41 from further entering the active layer 20. The part of the first auxiliary electrode 42 that is increased compared to the main electrode 41 can also block the ions (implanted doping ions and / or diffused impurity ions) moving along the edge of the main electrode 41 from entering the active layer 20, thereby preventing the implanted doping ions and / or diffused impurity ions from entering the active layer 20 from the main electrode 41 and its surrounding areas, resulting in a reduction in the channel region, increasing the effective channel length of the TFT, avoiding the influence of the short channel effect, and ensuring the stability of the TFT characteristics. Moreover, the first auxiliary electrode 42 has a relatively high light transmittance, has a small impact on the aperture ratio of the pixel region, and does not affect the improvement of the aperture ratio of the pixel region.

[0049] In a first possible embodiment, please refer to Figure 1 , the projection of the gate insulating layer 30 on the substrate 10 can completely coincide with the substrate 10, that is, the gate insulating layer 30 is laid entirely on the substrate 10. At this time, the orthographic projection of the active layer 20 on the substrate 10 is located within the orthographic projection of the gate insulating layer 30 on the substrate 10.

[0050] Figure 2 For the structural schematic diagram of the thin film transistor in another embodiment of the present application, please refer to Figure 2 , in a second possible embodiment, the orthographic projection of the gate insulating layer 30 on the substrate 10 can coincide with the second projection. At this time, the orthographic projection of the gate insulating layer 30 on the substrate 10 is located within the orthographic projection of the active layer 20 on the substrate 10.

[0051] Comparing two possible embodiments, the second possible embodiment requires patterning the gate insulating layer 30, while the first possible embodiment does not require patterning the gate insulating layer 30. In practical applications, whether to pattern the gate insulating layer 30 can be selected according to process requirements.

[0052] In some embodiments, referring to Figure 1 and Figure 2 , the thin film transistor may further include a source electrode 50 and a drain electrode 60.

[0053] The source electrode 50 and the gate electrode 40 are spaced on the same side of the active layer 20 and are electrically connected to the active layer 20. The edge lines of the first projection and the second projection on the side close to the source electrode 50 do not coincide. That is, the edge line of the first projection on the side close to the source electrode 50 and the edge line of the second projection on the side close to the source electrode 50 do not coincide at all, and the distance between the edge line of the first projection on the side close to the source electrode 50 and the edge line of the second projection on the side close to the source electrode 50 is greater than 0.

[0054] The drain electrode 60 and the gate electrode 40, the source electrode 50 are spaced on the same side of the active layer 20 and are electrically connected to the active layer 20. The edge lines of the first projection and the second projection on the side close to the drain electrode 60 do not coincide. That is, the edge line of the first projection on the side close to the drain electrode 60 and the edge line of the second projection on the side close to the drain electrode 60 do not coincide at all, and the distance between the edge line of the first projection on the side close to the drain electrode 60 and the edge line of the second projection on the side close to the drain electrode 60 is greater than 0.

[0055] Ions entering the active layer 20 from between the gate electrode 40 and the source electrode 50, and between the gate electrode 40 and the drain electrode 60 will affect the effective channel length of the TFT. The non - coincidence of the edge lines of the first projection and the second projection on the side close to the source electrode 50, and the non - coincidence of the edge lines of the first projection and the second projection on the side close to the drain electrode 60 can effectively prevent the implanted doping ions and / or diffused impurity ions from entering the active layer 20, resulting in a reduction of the channel region, and increase the effective channel length of the TFT.

[0056] Exemplarily, referring to Figure 1 , the source electrode 50 and the drain electrode 60 may be located on opposite sides of the gate electrode. The positive projection of the source electrode 50 on the substrate 10 is the fourth projection, and the positive projection of the drain electrode 60 on the substrate 10 is the fifth projection. The direction of the line connecting the center of the fourth projection to the center of the fifth projection is the set direction A.

[0057] In practical applications, the length L1 of the first projection in the set direction can be determined according to the resistance requirement of the gate for the display product. For example, the length L1 of the first projection in the set direction can be greater than or equal to 1.5 microns, or can be 1 micron to 1.5 microns, or can also be less than or equal to 1 micron, etc.

[0058] The theoretical channel length of the TFT is the length L1 of the first projection in the set direction. However, in the manufacturing process of the TFT, the Doping process is used to inject ions (B+ or P-) into the non-channel region of the active layer 20 to make the non-channel region conductive. When the doping ions are injected into the non-channel region, they will also be injected along the edge of the gate 40 into the channel region of the active layer 20, making the edge of the channel region become a non-channel region. Moreover, during the film formation and high-temperature annealing of some of the above film layers, some ions (H+) will enter the channel region through diffusion, making part of the channel region become a non-channel region. Please refer to Figure 1 , the ions (injected doping ions and / or diffused impurity ions) enter the active layer 20 along the edge of the gate 40, making part of the channel region become a non-channel region.

[0059] If the second projection completely coincides with the first projection, and the length of the region changed from the channel region to the non-channel region in the set direction is △L1, then the effective channel length Leff1 of the TFT = L1 - 2×△L1. If the first projection in this application is a proper subset of the second projection, the length of the region changed from the channel region to the non-channel region in the set direction is △L2, and the distance between the edge line of the first projection and the edge line of the second projection is L2, then the effective channel length Leff2 of the TFT = L1 + 2×L2 - 2×△L2. Since L2 - △L2 > -△L1, so Leff2 > Leff1. Thus, by using the first projection as a proper subset of the second projection, the effective channel length of the TFT can be increased, and on the basis of ensuring the stability of the TFT characteristics, the aperture ratio of the pixel region of the display product can be improved.

[0060] When the length L1 of the first projection in the set direction remains unchanged, by using the first projection as a proper subset of the second projection, the effective channel length of the TFT can be increased, the stability of the TFT characteristics is improved, and the aperture ratio of the pixel region decreases slightly.

[0061] In a possible embodiment, please refer to Figure 1 , if the length L1 of the first projection in the set direction is greater than or equal to 1.5 micrometers, the distance L2 between the edge line of the first projection and the edge line of the second projection can be less than 0.5 micrometers.

[0062] When the length L1 of the first projection in the first direction is relatively large, the main electrode 41 blocks more ions, and relatively fewer ions move along the edge of the main electrode 41. The additional part of the first auxiliary electrode 42 compared to the main electrode 41 does not need to be too much. The distance L2 between the edge line of the first projection and the edge line of the second projection can be less than 0.5 microns. When the distance L2 between the edge line of the first projection and the edge line of the second projection is less than 0.5 microns, the influence of the first auxiliary electrode 42 on the aperture ratio of the pixel region is small, which is beneficial to improving the aperture ratio of the pixel region.

[0063] Exemplarily, the length L1 of the first projection in the set direction can be 1.5 microns to 3 microns, such as 1.5 microns, 1.75 microns, 2 microns, 2.25 microns, 2.5 microns, 2.75 microns, 3 microns, etc.

[0064] When the length L1 of the first projection in the set direction decreases, the first projection can be used as a proper subset of the second projection to maintain the effective channel length of the TFT, ensure the stability of the TFT characteristics, and at the same time improve the aperture ratio of the pixel region.

[0065] In another possible embodiment, please refer to Figure 1 If the length L1 of the first projection in the set direction is less than or equal to 1 micron, the distance L2 between the edge line of the first projection and the edge line of the second projection can be greater than or equal to 0.5 microns.

[0066] When the length L1 of the first projection in the first direction is relatively small, the main electrode 41 blocks fewer ions, and relatively more ions move along the edge of the main electrode 41. A larger additional part of the first auxiliary electrode 42 compared to the main electrode 41 is required to effectively block the ions (implanted doped ions and / or diffused impurity ions) moving along the edge of the main electrode 41 from entering the active layer 20. The distance L2 between the edge of the first projection line and the edge of the second projection line can be greater than or equal to 0.5 microns. When the length L1 of the first projection in the set direction is less than or equal to 1 micron, the light blocked by the main electrode 41 also decreases, and the aperture ratio of the pixel region is improved.

[0067] Exemplarily, the length L1 of the first projection in the set direction can be 1.5 microns to 3 microns, such as 1.5 microns, 1.75 microns, 2 microns, 2.25 microns, 2.5 microns, 2.75 microns, 3 microns, etc.

[0068] Exemplarily, the distance L2 between the edge line of the first projection and the edge line of the second projection can be 0.5 microns to 1 micron, such as 0.5 microns, 0.6 microns, 0.7 microns, 0.8 microns, 0.9 microns, 1 micron, etc.

[0069] In a first possible embodiment, the main electrode 41 may be a metal thin film, and the first auxiliary electrode 42 may be a metal compound thin film. The ion blocking ability and light transmittance of the metal compound thin film may both be higher than those of the metal thin film. With the main electrode 41 being a metal thin film and the first auxiliary electrode 42 being a metal compound thin film, it can be achieved that both the ion blocking ability and light transmittance of the first auxiliary electrode 42 are higher than those of the main electrode 41.

[0070] Exemplarily, the material of the main electrode 41 may be Mo, and the material of the first auxiliary electrode 42 may be TiN.

[0071] Mo has a strong blocking ability for implanted doping ions and / or diffused impurity ions. However, Mo is a columnar metal with certain columnar gaps between atomic lattices, and a small amount of doping ions and / or a small amount of diffused ions will pass through Mo along the columnar gaps between Mo lattices. The arrangement of Ti atoms in TiN is itself disordered, and it has a good blocking ability for implanted doping ions and / or diffused impurity ions. The added N can fill the gaps between Ti atoms, further enhancing the blocking ability for implanted doping ions and / or diffused impurity ions. Therefore, TiN can well block the ions passing through Mo along the columnar gaps between Mo lattices, effectively preventing doping ions and diffused ions from passing through TiN and entering the channel region of the active layer 20.

[0072] Figure 3 For a schematic structural diagram of a thin film transistor in another embodiment of the present application, please refer to Figure 3 In a second possible embodiment, the gate may further include a second auxiliary electrode 43 located between the first auxiliary electrode 42 and the gate insulating layer 30. The ion blocking ability of the second auxiliary electrode 43 is lower than that of the first auxiliary electrode 42, and the light transmittance of the second auxiliary electrode 43 is higher than that of the first auxiliary electrode 42. The orthographic projection of the second auxiliary electrode 43 on the substrate 10 is a third projection, and the second projection is a proper subset of the third projection.

[0073] In this embodiment, the fact that the ion blocking ability of the second auxiliary electrode 43 is lower than that of the first auxiliary electrode 42 means that the ion blocking ability of the second auxiliary electrode 43 is lower than the ion blocking ability of the first auxiliary electrode 42. The fact that the light transmittance of the second auxiliary electrode 43 is higher than that of the first auxiliary electrode 42 means that the light transmittance of the second auxiliary electrode 43 is higher than the light transmittance of the first auxiliary electrode 42. Since the light transmittance of the first auxiliary electrode 42 is higher than that of the main electrode 41, the light transmittance of the second auxiliary electrode 43 is also higher than that of the main electrode 41, and the light transmittance of the second auxiliary electrode 43 in the gate 40 is the highest.

[0074] The fact that the second projection is a proper subset of the third projection means that the second projection lies within the third projection and the edge lines of the second projection do not coincide with those of the third projection. That is, the third projection includes a part that completely coincides with the second projection and a part that does not coincide with the second projection at all. Since the first projection is a proper subset of the second projection, the first projection is also a proper subset of the third projection.

[0075] In the manufacturing process of the TFT, the Doping process is used to inject ions (B+ or P-) into the non-channel region of the active layer 20 to make the non-channel region conductive. While the doped ions are being injected into the non-channel region, they will also be injected along the edge of the gate 40 into the channel region of the active layer 20, causing the edge of the channel region to become a non-channel region. Moreover, during the film formation and high-temperature annealing processes of some of the above film layers, some ions (H+) will enter the channel region through diffusion, making part of the channel region become a non-channel region. Please refer to Figure 3 , although the second auxiliary electrode 43 has a certain ion-blocking ability and can block most ions (injected doped ions and / or diffused impurity ions), there are still a small number of ions passing through the second auxiliary electrode 43, and some of them will further laterally diffuse and then enter the active layer 20, making part of the channel region become a non-channel region. In addition, there are also ions (injected doped ions and / or diffused impurity ions) entering the active layer 20 along the edge of the second auxiliary electrode 43, making part of the channel region become a non-channel region. However, the channel region affected by the ions moving along the edge of the second auxiliary electrode 43 is outside the channel region affected by the ions passing through the second auxiliary electrode 43. That is, the effective channel length of the TFT is mainly determined by the channel region affected by the ions passing through the second auxiliary electrode 43. Therefore, the influence of the ions moving along the edge of the second auxiliary electrode 43 on the effective channel length can be ignored.

[0076] If the length of the region where the channel region becomes a non-channel region in the set direction is △L3, the distance between the edge line of the first projection and the edge line of the second projection is L2, and the distance between the edge line of the second projection and the edge line of the third projection is L3, then the effective channel length Leff3 of the TFT = L1 + 2×L2 + 2×L3 - 2×△L3. Since L3 - △L3 > -△L2, Leff3 > Leff2. Thus, it can be seen that adding the second auxiliary electrode 43 can further increase the effective channel length of the TFT and improve the aperture ratio of the pixel region of the display product on the basis of ensuring the stability of the TFT characteristics.

[0077] In the above embodiments, by adding a second auxiliary electrode 43 between the first auxiliary electrode 42 and the gate insulating layer 30, although the ion blocking ability of the second auxiliary electrode 43 is lower than that of the first auxiliary electrode 42, the positive projection of the first auxiliary electrode 42 on the substrate 10 is a proper subset of the positive projection of the second auxiliary electrode 43 on the substrate 10. In this way, on the one hand, the increased part of the second main electrode 43 compared with the first auxiliary electrode 42 can block some ions (implanted doping ions and / or diffused impurity ions) from passing through the second auxiliary electrode 43 and entering the active layer 20, and on the other hand, it can block the ions (implanted doping ions and / or diffused impurity ions) moving along the edge of the first auxiliary electrode 42 from entering the active layer 20. Therefore, it can further reduce the reduction of the channel region caused by the implanted doping ions and / or diffused impurity ions entering the active layer 20 from the main electrode 41 and its surrounding areas, thereby increasing the effective channel length of the TFT, avoiding the influence of the short-channel effect, and ensuring the stability of the TFT characteristics. Moreover, the light transmittance of the second auxiliary electrode 43 is higher than that of the first auxiliary electrode 42, and the light transmittance of the second auxiliary electrode 43 in the gate 40 is the highest, and the influence on the aperture ratio of the pixel region can be basically ignored, and it will not affect the improvement of the aperture ratio of the pixel region.

[0078] Exemplarily, please refer to Figure 3 , the edge lines of the second projection and the third projection close to the source electrode 50 do not coincide at all. That is, the edge line of the second projection close to the source electrode 50 and the edge line of the third projection close to the source electrode 50 do not coincide at all, and the distance between the edge line of the second projection close to the source electrode 50 and the edge line of the third projection close to the source electrode 50 is greater than 0.

[0079] Exemplarily, please refer to Figure 3 , the edge lines of the second projection and the third projection close to the drain electrode 60 do not coincide at all. That is, the edge line of the second projection close to the drain electrode 60 and the edge line of the third projection close to the drain electrode 60 do not coincide at all, and the distance between the edge line of the second projection close to the drain electrode 60 and the edge line of the third projection close to the drain electrode 60 is greater than 0.

[0080] The ions entering the active layer 20 from between the gate 40 and the source electrode 50, and between the gate 40 and the drain electrode 60 will affect the effective channel length of the TFT. The edge lines of the second projection and the third projection close to the source electrode 50 do not coincide at all, and the edge lines of the second projection and the third projection close to the drain electrode 60 do not coincide at all, which can effectively prevent the implanted doping ions and / or diffused impurity ions from entering the active layer 20 and causing the reduction of the channel region, and increase the effective channel length of the TFT.

[0081] Exemplarily, the main electrode 41 can be a metal thin film, the first auxiliary electrode 42 can be a metal compound thin film, and the second auxiliary electrode 43 can be a transparent conductive thin film.

[0082] The ion blocking ability and light transmittance of the metal compound thin film can both be higher than those of the metal thin film. The main electrode 41 is a metal thin film, and the first auxiliary electrode 42 is a metal compound thin film, so that the ion blocking ability and light transmittance of the first auxiliary electrode 42 can both be higher than those of the main electrode 41. The light transmittance of the transparent conductive thin film is very high (higher than that of the metal compound thin film), its size has little effect on the aperture ratio of the pixel area, and its ion blocking ability can be lower than that of the metal compound thin film, so that the ion blocking ability of the second auxiliary electrode 43 can be lower than that of the first auxiliary electrode 42, and the light transmittance of the second auxiliary electrode 43 is higher than that of the first auxiliary electrode 42.

[0083] Exemplarily, the material of the main electrode 41 can be Mo, the material of the first auxiliary electrode 42 can be TiN, and the material of the second auxiliary electrode 43 can be ITO.

[0084] Mo has a strong blocking ability for implanted doping ions and / or diffused impurity ions. However, Mo is a columnar metal, and there are certain columnar gaps between the atomic lattices. A small amount of doping ions and / or a small amount of diffused ions will pass through Mo along the columnar gaps between the Mo lattices. The arrangement of Ti atoms in TiN is disordered, and it has a good blocking ability for implanted doping ions and / or diffused impurity ions. The added N can fill the gaps between Ti atoms, further improving the blocking ability for implanted doping ions and / or diffused impurity ions. Therefore, TiN can well block the ions passing through Mo along the columnar gaps between the Mo lattices, effectively preventing doping ions and diffused ions from passing through TiN and entering the channel region of the active layer 20. The light transmittance of ITO is about 95%, its size has little effect on the aperture ratio of the pixel area, and it has a certain ion blocking ability.

[0085] Please refer to Figure 3 , in the first possible embodiment, the orthographic projection of the gate insulating layer 30 on the substrate 10 can coincide with the third projection. At this time, the orthographic projection of the gate insulating layer 30 on the substrate 10 is located within the orthographic projection of the active layer 20 on the substrate 10.

[0086] Figure 4 For the structural schematic diagram of the thin film transistor in another embodiment of the present application, please refer to Figure 4 , in the second possible embodiment, the projection of the gate insulating layer 30 on the substrate 10 can completely coincide with the substrate 10, that is, the gate insulating layer 30 is laid on the entire surface of the substrate 10. At this time, the orthographic projection of the active layer 20 on the substrate 10 can be located within the orthographic projection of the gate insulating layer 30 on the substrate 10.

[0087] Comparing two possible embodiments, the first possible embodiment requires patterning the gate insulating layer 30, while the second possible embodiment does not require patterning the gate insulating layer 30. In practical applications, whether to pattern the gate insulating layer 30 can be selected according to process requirements.

[0088] Please refer to Figures 1 - 4 , in some embodiments, the thin film transistor may further include an interlayer dielectric layer 70, and the interlayer dielectric layer 70 is located on a side of the gate electrode 40 away from the substrate 10.

[0089] Correspondingly, the source electrode 50 and the drain electrode 60 are located on a side of the interlayer dielectric layer 70 away from the substrate 10 and are connected to the active layer 20 through vias.

[0090] In an embodiment of the second aspect of the present application, an array substrate is provided, and the array substrate includes the thin film transistor provided in any embodiment of the first aspect.

[0091] In an embodiment of the third aspect of the present application, a display device is provided, and the display device includes the array substrate provided in any embodiment of the second aspect.

[0092] Figure 5 For a schematic flowchart of a manufacturing method of an array substrate in one or more embodiments of the present application, please refer to Figure 5 , in an embodiment of the fourth aspect of the present application, a manufacturing method of an array substrate is provided, and the manufacturing method includes the following steps S101 to step S102.

[0093] Step S101, providing a substrate.

[0094] Step S102, sequentially forming an active layer, a gate insulating layer, and a gate electrode on the substrate.

[0095] In this embodiment, the gate electrode includes a main electrode and a first auxiliary electrode located between the main electrode and the gate insulating layer. The ion blocking ability and light transmittance of the first auxiliary electrode are both higher than those of the main electrode. The orthographic projection of the main electrode on the substrate is a first projection, and the orthographic projection of the first auxiliary electrode on the substrate is a second projection. The first projection is a proper subset of the second projection.

[0096] Figure 6 For Figure 5 a schematic flowchart of step S102, please refer to Figure 6 , in the first possible embodiment, step S102 may include the following steps S201 to step S206.

[0097] Step S201, sequentially forming an active layer and a gate insulating layer on the substrate.

[0098] Figure 7 ForFigure 6 Schematic structural diagram of the array substrate after the execution of step S201, please refer to Figure 7 , the active layer 20 and the gate insulating layer 30 are stacked on the substrate 10 in sequence.

[0099] Step S202, a first auxiliary electrode material layer, a main electrode material layer, and a photoresist layer are sequentially laid on the gate insulating layer, and the photoresist layer is patterned for the first time by a photolithography process.

[0100] Figure 8 For Figure 6 Schematic structural diagram of the array substrate after the execution of step S202, please refer to Figure 8 , the first auxiliary electrode material layer 42, the main electrode material layer 41, and the photoresist layer 80 are stacked on the gate insulating layer 30 in sequence.

[0101] Step S203, the main electrode material layer and the first auxiliary electrode material layer are etched using the photoresist layer after the first patterning, and the first auxiliary electrode material layer after etching forms the first auxiliary electrode.

[0102] Figure 9 For Figure 6 Schematic structural diagram of the array substrate after the execution of step S203, please refer to Figure 9 , the pattern of the photoresist layer 80 is transferred to the main electrode material layer 41 and the first auxiliary electrode material layer 42 (i.e., the first auxiliary electrode).

[0103] Step S204, the photoresist layer after the first patterning is ashed to obtain the photoresist layer after the second patterning.

[0104] Figure 10 For Figure 6 Schematic structural diagram of the array substrate after the execution of step S204, please refer to Figure 10 , the pattern of the photoresist layer 80 becomes different from the main electrode material layer 41 and the first auxiliary electrode material layer 42.

[0105] In practical applications, the ashing process cannot remove the photoresist layer in one go, and multiple ashing processes are required to completely remove the photoresist layer. Therefore, performing one ashing process on the photoresist layer after the first patterning will only remove a part of the photoresist layer, obtaining the photoresist layer after the second patterning.

[0106] Step S205, the main electrode material layer is etched using the photoresist layer after the second patterning, and the main electrode material layer after etching forms the main electrode.

[0107] Figure 11 For Figure 6 Schematic structural diagram of the array substrate after the execution of step S205, please refer to Figure 11, the pattern of the photoresist layer 80 is only transferred to the main electrode material layer 41 (i.e., the main electrode).

[0108] In practical applications, the etching materials of the main electrode material layer and the first auxiliary electrode material layer are different. By selecting a suitable etching material, only the main electrode material layer can be etched, and the pattern of the first auxiliary electrode material layer is retained to form the first auxiliary electrode.

[0109] Step S206, removing the photoresist layer.

[0110] Figure 12 For Figure 6 the structural schematic diagram of the array substrate after the execution of step S205 of Figure 12 , the photoresist layer 80 has been removed, and the main electrode 41 and the first auxiliary electrode 42 form the gate 40.

[0111] Exemplarily, the manufacturing method may further include the following steps: patterning the gate insulating layer, and the positive projection of the patterned gate insulating layer on the substrate substrate completely coincides with the positive projection of the first auxiliary electrode on the substrate substrate.

[0112] Figure 13 For Figure 5 another process schematic diagram of step S102 of Figure 13 , in the second possible embodiment, step S102 may include the following steps S301 to step S306.

[0113] Step S301, sequentially forming an active layer, a gate insulating layer, and a second auxiliary electrode on the substrate substrate.

[0114] Figure 14 For Figure 13 the structural schematic diagram of the array substrate after the execution of step S301 of Figure 14 , the active layer 20, the gate insulating layer 30, and the second auxiliary electrode 43 are sequentially stacked on the substrate substrate 10.

[0115] Step S302, sequentially laying a first auxiliary electrode material layer, a main electrode material layer, and a photoresist layer on the second auxiliary electrode, and performing a first patterning on the photoresist layer by using a photolithography process.

[0116] Figure 15 For Figure 13 the structural schematic diagram of the array substrate after the execution of step S302 of Figure 15 , the first auxiliary electrode material layer 42, the main electrode material layer 41, and the photoresist layer 80 are sequentially stacked on the second auxiliary electrode 43.

[0117] Step S303: Etch the main electrode material layer and the first auxiliary electrode material layer using the photoresist layer after the first patterning. The etched first auxiliary electrode material layer forms the first auxiliary electrode.

[0118] Figure 16 For Figure 13 a schematic structural diagram of the array substrate after the execution of step S303, please refer to Figure 16 , the pattern of the photoresist layer 80 is transferred to the main electrode material layer 41 and the first auxiliary electrode material layer 42 (i.e., the first auxiliary electrode).

[0119] Step S304: Ash the photoresist layer after the first patterning to obtain the photoresist layer after the second patterning.

[0120] Figure 17 For Figure 13 a schematic structural diagram of the array substrate after the execution of step S304, please refer to Figure 17 , the pattern of the photoresist layer 80 becomes different from the main electrode material layer 41 and the first auxiliary electrode material layer 42.

[0121] Step S305: Etch the main electrode material layer using the photoresist layer after the second patterning. The etched main electrode material layer forms the main electrode.

[0122] Figure 18 For Figure 13 a schematic structural diagram of the array substrate after the execution of step S305, please refer to Figure 18 , the pattern of the photoresist layer 80 is only transferred to the main electrode material layer 41 (i.e., the main electrode).

[0123] Step S306: Remove the photoresist layer.

[0124] Figure 19 For Figure 13 a schematic structural diagram of the array substrate after the execution of step S305, please refer to Figure 19 , the photoresist layer 80 has been removed, and the main electrode 41, the first auxiliary electrode 42, and the second auxiliary electrode 43 form the gate 40.

[0125] Compared with the first possible embodiment, the second possible embodiment mainly adds the following steps before step S202: Form a second auxiliary electrode on the gate insulating layer. The ion blocking ability of the second auxiliary electrode is lower than that of the first auxiliary electrode, and the light transmittance of the second auxiliary electrode is higher than that of the first auxiliary electrode. The orthographic projection of the second auxiliary electrode on the substrate is the third projection, and the second projection is a proper subset of the third projection.

[0126] Exemplarily, the manufacturing method may further include the following steps: patterning the gate insulating layer, and the positive projection of the patterned gate insulating layer on the substrate completely coincides with the positive projection of the second auxiliary electrode on the substrate.

[0127] Figure 20 For a schematic flow chart of a manufacturing method of an array substrate in another embodiment of the present application, please refer to Figure 20 In some embodiments, the manufacturing method may include the following steps S401 to S404.

[0128] Step S401: Provide a substrate.

[0129] Step S402: Sequentially form an active layer, a gate insulating layer, and a gate on the substrate.

[0130] In this embodiment, the gate includes a main electrode and a first auxiliary electrode located between the main electrode and the gate insulating layer. The ion blocking ability and light transmittance of the first auxiliary electrode are both higher than those of the main electrode. The positive projection of the main electrode on the substrate is a first projection, and the positive projection of the first auxiliary electrode on the substrate is a second projection. The first projection is a proper subset of the second projection.

[0131] Step S403: Form an interlayer dielectric layer on the gate, and open a first through hole and a second through hole. Both the first through hole and the second through hole extend from the side of the interlayer dielectric layer away from the substrate to the active layer.

[0132] Figure 21 For Figure 20 a schematic structural diagram of the array substrate after performing step S403, please refer to Figure 21 , an interlayer dielectric layer 70 is disposed on the main electrode 41, and both the first through hole 91 and the second through hole 92 extend from the side of the interlayer dielectric layer 70 away from the substrate 10 to the active layer 20.

[0133] Step S404: Form a source electrode and a drain electrode on the interlayer dielectric layer. The source electrode is electrically connected to the active layer through the first through hole, and the drain electrode is electrically connected to the active layer through the second through hole.

[0134] Figure 22 For Figure 20 a schematic structural diagram of the array substrate after performing step S404, please refer to Figure 22 , a source electrode 50 and a drain electrode 60 are disposed on the interlayer dielectric layer 70. The source electrode 50 is electrically connected to the active layer 20 through the first through hole 91, and the drain electrode 60 is electrically connected to the active layer 20 through the second through hole 92.

[0135] In this application, unless otherwise clearly defined or limited, the first feature being "on" or "under" the second feature may include direct contact between the first and second features, or may include the first and second features not being in direct contact but in contact through additional features therebetween. Moreover, the first feature being "above", "over" and "on top of" the second feature includes the first feature being directly above and obliquely above the second feature, or merely indicating that the horizontal height of the first feature is higher than that of the second feature. The first feature being "under", "beneath" and "underneath" the second feature includes the first feature being directly below and obliquely below the second feature, or merely indicating that the horizontal height of the first feature is less than that of the second feature.

[0136] In the description of this application, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of this application.

[0137] In this application, unless otherwise clearly defined or limited, the terms "connected", "fixed", etc. shall be understood in a broad sense. For example, "fixed" may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and may be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0138] In addition, in this application, the descriptions such as "first", "second", etc. are only for descriptive purposes and should not be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "a plurality" is two or more, unless otherwise clearly and specifically defined.

[0139] Although the embodiments of this application have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and purposes of this application, and the scope of this application is defined by the claims and their equivalents.

Claims

1. A thin film transistor, characterized in that, The thin film transistor includes: A substrate; An active layer located on the substrate; A gate insulating layer located on a side of the active layer away from the substrate; A gate located on a side of the gate insulating layer away from the substrate; the gate includes a main electrode and a first auxiliary electrode located between the main electrode and the gate insulating layer, and both the ion blocking ability and the light transmittance of the first auxiliary electrode are higher than those of the main electrode; a positive projection of the main electrode on the substrate is a first projection, a positive projection of the first auxiliary electrode on the substrate is a second projection, and the first projection is a proper subset of the second projection.

2. The thin film transistor according to claim 1, characterized in that, The main electrode is a metal thin film, and the first auxiliary electrode is a metal compound thin film.

3. The thin film transistor according to claim 2, wherein The material of the main electrode is Mo, and the material of the first auxiliary electrode is TiN.

4. The thin film transistor according to any one of claims 1 to 3, characterized in that, The thin film transistor further includes: A source electrode, which is spaced from the gate on the same side of the active layer and is electrically connected to the active layer; the edge line of the first projection and the second projection on the side close to the source electrode do not coincide; A drain electrode, which is spaced from the gate and the source electrode on the same side of the active layer and is electrically connected to the active layer; the edge line of the first projection and the second projection on the side close to the drain electrode do not coincide.

5. The thin film transistor according to claim 4, wherein The gate further includes a second auxiliary electrode located between the first auxiliary electrode and the gate insulating layer, the ion blocking ability of the second auxiliary electrode is lower than that of the first auxiliary electrode, and the light transmittance of the second auxiliary electrode is higher than that of the first auxiliary electrode; A positive projection of the second auxiliary electrode on the substrate is a third projection, the second projection is a proper subset of the third projection, the edge line of the second projection and the third projection on the side close to the source electrode do not coincide completely, and the edge line of the second projection and the third projection on the side close to the drain electrode do not coincide completely.

6. The thin film transistor according to claim 5, wherein The second auxiliary electrode is a transparent conductive thin film.

7. The thin film transistor according to claim 6, wherein The material of the second auxiliary electrode is ITO.

8. The thin film transistor according to claim 5, wherein, A positive projection of the gate insulating layer on the substrate coincides with the third projection; or, a positive projection of the active layer on the substrate is located within a positive projection of the gate insulating layer on the substrate.

9. The thin film transistor according to claim 4, wherein The source electrode and the drain electrode are located on opposite sides of the gate, a positive projection of the source electrode on the substrate is a fourth projection, a positive projection of the drain electrode on the substrate is a fifth projection, and a direction of a line connecting the center of the fourth projection to the center of the fifth projection is a set direction; If a length of the first projection in the set direction is greater than or equal to 1.5 micrometers, a distance between an edge line of the first projection and an edge line of the second projection is less than 0.5 micrometers; If a length of the first projection in the set direction is less than or equal to 1 micrometer, a distance between an edge line of the first projection and an edge line of the second projection is greater than or equal to 0.5 micrometers.

10. An array substrate, characterized in that, The array substrate includes the thin film transistor according to any one of claims 1-9.

11. A display device, characterized in that, The display device includes the array substrate according to claim 10.

12. A manufacturing method of an array substrate, characterized in that, The manufacturing method includes: Providing a substrate; An active layer, a gate insulating layer, and a gate are sequentially formed on the substrate; the gate includes a main electrode and a first auxiliary electrode located between the main electrode and the gate insulating layer, and both the ion blocking ability and the light transmittance of the first auxiliary electrode are higher than those of the main electrode; the orthographic projection of the main electrode on the substrate is a first projection, the orthographic projection of the first auxiliary electrode on the substrate is a second projection, and the first projection is a proper subset of the second projection.

13. The manufacturing method according to claim 12, characterized in that, The sequentially forming an active layer, a gate insulating layer, and a gate on the substrate includes: sequentially forming an active layer and a gate insulating layer on the substrate; sequentially laying a first auxiliary electrode material layer, a main electrode material layer, and a photoresist layer on the gate insulating layer, and performing a first patterning on the photoresist layer by a photolithography process; etching the main electrode material layer and the first auxiliary electrode material layer by using the photoresist layer after the first patterning, and the etched first auxiliary electrode material layer forms a first auxiliary electrode; ashing the photoresist layer after the first patterning to obtain the photoresist layer after the second patterning; etching the main electrode material layer by using the photoresist layer after the second patterning, and the etched main electrode material layer forms a main electrode; removing the photoresist layer.

14. The manufacturing method according to claim 13, characterized in that, Before sequentially laying the first auxiliary electrode material layer, the main electrode material layer, and the photoresist layer on the gate insulating layer, the method further includes: forming a second auxiliary electrode on the gate insulating layer; the ion blocking ability of the second auxiliary electrode is lower than that of the first auxiliary electrode, and the light transmittance of the second auxiliary electrode is higher than that of the first auxiliary electrode; the orthographic projection of the second auxiliary electrode on the substrate is a third projection, and the second projection is a proper subset of the third projection.

15. The manufacturing method according to any one of claims 12-14, characterized in that, After sequentially forming the active layer, the gate insulating layer, and the gate on the substrate, the method further includes: forming an interlayer dielectric layer on the gate, and opening a first via hole and a second via hole, both the first via hole and the second via hole extend from the side of the interlayer dielectric layer away from the substrate to the active layer; forming a source electrode and a drain electrode on the interlayer dielectric layer, the source electrode is electrically connected to the active layer through the first via hole, and the drain electrode is electrically connected to the active layer through the second via hole.

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