Semiconductor structure for improving high-temperature and high-humidity reverse bias reliability and preparation method thereof

Abstract

The invention provides a semiconductor structure for improving high-temperature and high-humidity reverse bias reliability and a preparation method thereof, and the semiconductor structure comprises a drift layer which comprises an active region and a terminal region; the main junction is positioned in the terminal region of the drift layer; the conductive lead-out piece is positioned on one side, deviating from the drift layer, of the main junction and is connected with the main junction; the conductive extension piece is located on one side, deviating from the active area, of the conductive leading-out piece in the direction from the active area to the terminal area, the conductive extension piece is connected with the conductive leading-out piece, and the conductive extension piece is used for shielding an electric field from one end, away from the active area, of the terminal area to the conductive leading-out piece.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure for improving high-temperature and high-humidity reverse bias reliability and a preparation method thereof. Background Art

[0002] Silicon carbide (SiC) MOSFET has become a core device for high-voltage and high-power scenarios such as new energy vehicles and photovoltaic inverters due to its high withstand voltage, low conduction loss and high-temperature working ability. However, under high-temperature and high-humidity reverse bias (H3TRB) conditions (such as long-term application of reverse bias in an 85℃ / 85%RH environment), device reliability faces severe challenges: moisture penetration causes electrochemical corrosion at the passivation layer / package interface, causing a surge in device leakage current; at the same time, the SiC / SiO2 interface state density increases significantly in a high humidity environment, exacerbating the threshold voltage drift degradation. Existing technologies mostly delay moisture intrusion by increasing the thickness of the passivation layer or using silicone gel encapsulation, but the former will introduce parasitic capacitance to affect the switching speed, and the latter has the risk of reduced sealing performance after long-term aging. In addition, traditional aluminum-based bonding wires are prone to microcrack expansion under the coupling of wet heat-mechanical stress, further reducing the device's resistance to moisture corrosion. Therefore, how to build a multi-level anti-moisture diffusion barrier and optimize interface stability while maintaining the performance of SiC MOSFET has become a key bottleneck for improving high-temperature and high-humidity reverse bias reliability. Summary of the invention

[0003] The technical problem to be solved by the present invention is how to improve the reliability of semiconductor structures.

[0004] In order to solve the above technical problems, the present invention provides a semiconductor structure for improving high-temperature and high-humidity reverse bias reliability, comprising: a drift layer, the drift layer comprising an active region and a terminal region; a main junction, located in the terminal region of the drift layer; a conductive lead-out member, located on a side of the main junction away from the drift layer and connected to the main junction; a conductive extension member, located on a side of the conductive lead-out member away from the active region along a direction from the active region to the terminal region, the conductive extension member being connected to the conductive lead-out member, and the conductive extension member being used to shield the electric field from an end of the terminal region away from the active region to the conductive lead-out member.

[0005] Optionally, the material of the conductive extension member includes a semiconductor material or a doped semiconductor material; and the conductivity of the conductive extension member is less than the conductivity of the conductive lead-out member.

[0006] Optionally, the electrical conductivity of the conductive lead-out piece is 10e6S / cm to 10e7S / cm; the electrical conductivity of the conductive extension piece is 1e1S / cm to 1e4S / cm.

[0007] Optionally, the material of the conductive extension includes polysilicon or doped polysilicon.

[0008] Optionally, the material of the conductive lead-out includes metal.

[0009] Optionally, the conductive extension includes one or more spaced sub-conductive extensions, and the arrangement direction of the plurality of spaced sub-conductive extensions is parallel to the direction from the active region to the terminal region; the sub-conductive extensions are connected to the conductive lead-out.

[0010] Optionally, the sub-conductive extension includes a first conductive portion doped with N-type and a second conductive portion doped with P-type, and the second conductive portion and the first conductive portion form a PN junction; along the direction from the active region to the terminal region, the second conductive portion is located on the side of the first conductive portion away from the conductive lead-out.

[0011] Optionally, the semiconductor structure for improving the reliability of high-temperature and high-humidity reverse bias further includes: a field oxide layer located on one side of the terminal region; an isolation dielectric layer located on the side of the field oxide layer away from the terminal region; wherein, the conductive lead-out penetrates through the isolation dielectric layer and the field oxide layer; wherein, the conductive extension is located between the isolation dielectric layer and the field oxide layer; the surface of the field oxide layer on the side away from the drift layer has a stepped area; the surface of the isolation dielectric layer on the side away from the drift layer has a stepped area.

[0012] Optionally, the sub-conductive extension includes a first portion, a second portion, and a third portion, the second portion connects the first portion and the second portion, and the thickness of the field oxide layer between the third portion and the main junction is greater than the thickness of the field oxide layer between the first portion and the main junction.

[0013] Optionally, the semiconductor structure for improving the reliability of high-temperature and high-humidity reverse bias further includes: a passivation layer located on the side of the isolation dielectric layer away from the terminal region, the surface of the passivation layer facing the drift layer has a stepped area, and the stepped area of the passivation layer and the positive projection of the conductive extension on the drift layer have an overlapping area.

[0014] The present application also provides a method for manufacturing a semiconductor structure for improving the reliability of high-temperature and high-humidity reverse bias, including: forming a drift layer, the drift layer including an active region and a terminal region; forming a main junction in the terminal region of the drift layer; forming a conductive lead-out connected to the main junction on the side of the main junction away from the drift layer; forming a conductive extension; wherein, the conductive extension is located on the side of the conductive lead-out away from the active region along the direction from the active region to the terminal region, the conductive extension is connected to the conductive lead-out, and the conductive extension is used to shield the electric field from the end of the terminal region far from the active region to the conductive lead-out.

[0015] Optionally, it further includes: forming a field oxide layer on one side of the terminal region; forming a first groove and a second groove in the field oxide layer, the second groove communicating with the first groove, the first groove penetrating through the field oxide layer and exposing the main junction, and the bottom of the second groove having the field oxide layer; wherein, forming the conductive lead-out member includes: forming the conductive lead-out member in the first groove; wherein, forming the conductive extension member includes: forming the conductive extension member in the second groove and on the side of the field oxide layer on the side of the second groove away from the main junction; the preparation method further includes: forming an isolation dielectric layer on the side of the field oxide layer and the conductive extension member away from the terminal region, the isolation dielectric layer exposing the conductive lead-out member.

[0016] Optionally, the preparation method further includes: forming a passivation layer, the passivation layer being located on the side of the isolation dielectric layer away from the terminal region, the surface of the passivation layer facing the drift layer having a stepped region, and the stepped region of the passivation layer and the positive projection of the conductive extension member on the drift layer having an overlapping region.

[0017] Optionally, the material of the conductive extension member includes a semiconductor material or a doped semiconductor material; the conductivity of the electrical extension member is less than the conductivity of the conductive lead-out member.

[0018] Optionally, forming the conductive extension member includes forming one or more spaced sub-conductive extension members, the arrangement direction of the plurality of spaced sub-conductive extension members being parallel to the direction from the active region to the terminal region; the sub-conductive extension members are connected to the conductive lead-out member.

[0019] Optionally, forming the sub-conductive extension member includes forming a first conductive part doped with N-type and a second conductive part doped with P-type, the second conductive part and the first conductive part constituting a PN junction; along the direction from the active region to the terminal region, the second conductive part is located on the side of the first conductive part away from the conductive lead-out member.

[0020] The technical solution of the present application has the following technical effects:

[0021] The technical solution of the present invention provides a semiconductor structure for improving the reverse bias reliability under high temperature and high humidity. When the semiconductor structure is reverse biased, the potential on the conductive lead is set to be equal to the potential applied to the source region, and the potential at the end of the terminal region of the drift layer far away from the active region is close to the potential applied to the drain metal layer. The potential on the conductive lead and the potential at the end of the terminal region of the drift layer far away from the active region are quite different. Since a conductive extension connected to the conductive lead is provided, there is a voltage divider on the conductive extension. The conductive extension is used to shield the electric field from the end of the terminal region far away from the active region to the conductive lead, reduce the electric field near the conductive lead, alleviate the migration of metal ions in the conductive lead under high temperature, high pressure and high humidity conditions, reduce the hydrolysis effect of the conductive lead, and improve the reliability of the semiconductor structure.

[0022] Furthermore, the sub-conductive extension includes an N-type doped first conductive part and a P-type doped second conductive part, the second conductive part and the first conductive part form a PN junction; along the direction from the active region to the terminal region, the second conductive part is located on the side of the first conductive part away from the conductive lead-out part. The direction of the intrinsic electric field from the first conductive part to the second conductive part is opposite to the direction of the electric field from the end of the terminal region away from the active region to the conductive lead-out part, which can reduce the electric field near the conductive lead-out part, resolve the migration of metal ions in the conductive lead-out part under high temperature, high pressure and high humidity conditions, reduce the hydrolysis effect, and improve the reliability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 is a schematic diagram of a semiconductor structure in the related art;

[0025] Figure 2 A schematic diagram of a semiconductor structure for improving high-temperature and high-humidity reverse bias reliability in an embodiment of the present application;

[0026] Figure 3 A schematic diagram of a semiconductor structure for improving high-temperature and high-humidity reverse bias reliability in another embodiment of the present application;

[0027] Figure 4 A schematic diagram of a semiconductor structure for improving high-temperature and high-humidity reverse bias reliability in another embodiment of the present application;

[0028] Figures 5 to 7A schematic diagram of a semiconductor structure preparation process for improving high-temperature and high-humidity reverse bias reliability in another embodiment of the present application;

[0029] Figures 8 to 10 A schematic diagram of a semiconductor structure preparation process for improving high-temperature and high-humidity reverse bias reliability in another embodiment of the present application;

[0030] Figures 11 to 13 It is a schematic diagram of a semiconductor structure preparation process for improving high temperature and high humidity reverse bias reliability in another embodiment of the present application. DETAILED DESCRIPTION

[0031] Related art semiconductor structures, see Figure 1 , including: a substrate layer 100; a drift layer 110 located on one side of the substrate layer 100, the drift layer including an active area and a terminal area; a main junction 121 located in the terminal area of ​​the drift layer 110; a field limiting ring 122 located in the terminal area of ​​the drift layer 110; a field oxide layer 130 located on one side of the terminal area; an isolation dielectric layer 140 located on the side of the field oxide layer 130 away from the terminal area; a passivation layer 150 located on the side of the isolation dielectric layer 140 away from the field oxide layer 130; a conductive lead 160 located on the side of the main junction 121 away from the drift layer 110 and connected to the main junction 121, and the conductive lead 160 penetrates the passivation layer 150, the isolation dielectric layer 140 and the field oxide layer 130.

[0032] The semiconductor structure also includes: a source region located in the active region. The potential on the conductive lead 160 is set to be equal to the potential applied to the source region. Further, the potential on the conductive lead 160 is set to zero potential to prevent the potential on the main junction 121 from floating, thereby improving electrical stability.

[0033] However, when the semiconductor structure is reverse biased, there is an electric field spike near the conductive lead 160, which accelerates the migration of metal ions in the conductive lead 160 under high temperature, high pressure and high humidity conditions. The metal ions migrate to the passivation layer 150, the isolation dielectric layer 140 and the field oxide layer 130, and defects are easily generated in the passivation layer 150, the isolation dielectric layer 140 and the field oxide layer 130 and at their interfaces, causing failure of the semiconductor structure and reducing the reliability of the semiconductor structure.

[0034] On this basis, the present application provides a semiconductor structure and a preparation method thereof for improving high temperature and high humidity reverse bias reliability, thereby improving the reliability of the semiconductor structure.

[0035] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Apparently, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0036] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0037] In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can also be the communication inside two elements. It can be a wireless connection or a wired connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0038] In addition, the technical features involved in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0039] An embodiment of the present application provides a semiconductor structure for improving the reliability of reverse bias under high temperature and high humidity. Refer to Figures 2 to 4 , including:

[0040] A drift layer 210, the drift layer 210 includes an active region and a terminal region;

[0041] A main junction 221, located in the terminal region of the drift layer 210;

[0042] A conductive lead-out member 260, located on the side of the main junction 221 away from the drift layer 210 and connected to the main junction 221;

[0043] A conductive extension member 270, located on the side of the conductive lead-out member 260 away from the active region along the direction from the active region to the terminal region. The conductive extension member 270 is connected to the conductive lead-out member 260, and the conductive extension member 270 is used to shield the electric field from the end of the terminal region far from the active region to the conductive lead-out member 260.

[0044] In this embodiment, when the semiconductor structure is set in reverse bias, the potential on the conductive lead-out member 260 is set to be equal to the potential applied to the source region, while the potential at the distal end of the terminal region of the drift layer 210, which is far from the active region, approaches the potential applied to the drain metal layer. There is a large difference in potential between the potential on the conductive lead-out member 260 and the potential at the distal end of the terminal region of the drift layer 210 that is far from the active region. Since the conductive extension member 270 connected to the conductive lead-out member 260 is provided, there is a voltage division on the conductive extension member 270. The conductive extension member 270 is used to shield the electric field from one end of the terminal region far from the active region to the conductive lead-out member 260, reduce the electric field near the conductive lead-out member 260, alleviate the migration of metal ions in the conductive lead-out member 260 under high temperature, high pressure and high humidity conditions, reduce the hydrolysis effect of the conductive lead-out member 260, and improve the reliability of the semiconductor structure.

[0045] In this embodiment, the semiconductor structure further includes: a substrate layer 200, located on a side of the drift layer 210 facing away from the conductive lead-out member 260 and the conductive extension member 270.

[0046] In this embodiment, the semiconductor structure can be a silicon carbide (SiC) MOSFET.

[0047] In this embodiment, the substrate layer 200 is silicon carbide (SiC) doped with N-type conductive ions.

[0048] In one embodiment, the terminal region surrounds the active region. Figure 2 The terminal region is schematically shown, and the active region is not schematically shown.

[0049] In this embodiment, the material of the conductive lead-out member 260 includes metal.

[0050] In this embodiment, the semiconductor structure for improving the reverse bias reliability under high temperature and high humidity further includes: a drain metal layer (not shown) located on a side of the substrate layer 200 facing away from the drift layer 210.

[0051] In this embodiment, the semiconductor structure for improving the reverse bias reliability under high temperature and high humidity further includes: a well region located in the active region; a source region located in the well region; a gate structure. The gate structure is a planar gate structure or a trench gate structure. When the gate structure is a planar gate structure, the gate structure covers the JFET region between adjacent well regions and a part of the source region. When the gate structure is a trench gate structure, the gate structure is located in the active region, and the well regions are located on both sides of the gate structure. The semiconductor structure further includes: a front electrode connected to the source region; an insulating isolation layer located between the front electrode and the gate structure, and the insulating isolation layer is used to isolate the front electrode and the gate structure.

[0052] In this embodiment, when the potential applied to the source region is less than the potential applied to the drain metal layer, the semiconductor structure is reverse-biased. Specifically, a zero potential can be applied to the source region and a high potential can be applied to the drain metal layer. When the semiconductor structure is reverse-biased, the potential on the conductive lead-out member 260 is set to be equal to the potential applied to the source region. Further, the potential on the conductive lead-out member 260 is set to zero potential to avoid the floating potential on the main junction 221 and improve the electrical stability.

[0053] When the semiconductor structure is reverse-biased, the potential on the conductive lead-out member 260 is set to be equal to the potential applied to the source region, while the potential at the distal end of the terminal region of the drift layer 210 away from the active region is close to the potential applied to the drain metal layer, and there is a large potential difference between the potential on the conductive lead-out member 260 and the potential at the distal end of the terminal region of the drift layer 210 away from the active region. In this embodiment, a conductive extension member 270 connected to the conductive lead-out member 260 is provided. There is a voltage division on the conductive extension member 270. The conductive extension member 270 shields the electric field, reduces the electric field near the conductive lead-out member 260, alleviates the migration of metal ions in the conductive lead-out member 260 under high temperature, high pressure and high humidity conditions, reduces the hydrolysis effect, and improves the reliability of the semiconductor structure.

[0054] In one embodiment, the material of the conductive extension member 270 includes a semiconductor material or a doped semiconductor material. The conductivity of the conductive extension member 270 is less than the conductivity of the conductive lead-out member 260. Preferably, the conductivity of the conductive lead-out member is 10e6 S / cm to 10e7 S / cm; the conductivity of the conductive extension member is 1e1 S / cm to 1e4 S / cm. When the material of the conductive extension member 270 is a doped semiconductor material, the doping type of the conductive extension member 270 is P-type or N-type. Exemplarily, the material of the conductive extension member 270 includes polysilicon or doped polysilicon.

[0055] In this embodiment, the conductivity type of the drift layer 210 is the same as that of the substrate layer 200, and the doping concentration of the drift layer 210 is less than the doping concentration of the substrate layer 200. In one embodiment, the material of the drift layer 210 is silicon carbide doped with N-type conductive ions. The N-type conductive ions can be phosphorus ions or nitrogen ions.

[0056] In this embodiment, the conductive extension member includes one or more spaced sub-conductive extension members, and the arrangement direction of the plurality of spaced sub-conductive extension members is parallel to the direction from the active region to the terminal region; the sub-conductive extension member is connected to the conductive lead-out member. Refer to Figure 2 , the conductive extension member 270 includes a plurality of spaced sub-conductive extension members 2701, the arrangement direction of the plurality of spaced sub-conductive extension members 2701 is parallel to the direction from the active region to the terminal region, and the sub-conductive extension member 2701 is connected to the conductive lead-out member 260. Refer toFigure 3 and Figure 4 The conductive extension member 270 includes a sub-conductive extension member 2701 , and the sub-conductive extension member 2701 is connected to the conductive lead-out member 260 .

[0057] It should be noted that in Figure 2 and Figure 4 In the cross section in FIG. 1 , only one sub-conductive extension member 2701 is shown to be connected to the conductive lead-out member 260. In fact, the positions where the other sub-conductive extension members 2701 are connected to the conductive lead-out member 260 are not shown in FIG. Figure 2 and Figure 4 In the cross section, but at other locations, such as along a plane perpendicular to Figure 2 and Figure 4 Other positions in the section direction.

[0058] In one embodiment, the sub-conductive extension 2701 includes an N-type doped first conductive portion and a P-type doped second conductive portion, wherein the second conductive portion and the first conductive portion form a PN junction; along the direction from the active region to the terminal region, the second conductive portion is located on the side of the first conductive portion away from the conductive lead-out member 260. The direction of the intrinsic electric field from the first conductive portion to the second conductive portion is opposite to the direction of the electric field from the end of the terminal region away from the active region to the conductive lead-out member 260, which can reduce the electric field near the conductive lead-out member 260, resolve the migration of metal ions in the conductive lead-out member 260 under high temperature, high pressure and high humidity conditions, reduce the hydrolysis effect, and improve the reliability of the semiconductor structure.

[0059] In this embodiment, the semiconductor structure for improving the reverse bias reliability under high temperature and high humidity further includes: a field oxide layer 230, located at one side of the terminal region; an isolation dielectric layer 240, located at a side of the field oxide layer 230 away from the terminal region; wherein the conductive lead-out member 260 penetrates the isolation dielectric layer 240 and the field oxide layer 230; and the conductive extension member 270 is located between the isolation dielectric layer 240 and the field oxide layer 230. The surface of the field oxide layer 230 away from the drift layer 210 has a step region, and the orthographic projection of the step region of the field oxide layer 230 and the conductive extension member 270 on the drift layer 210 has an overlapping region; the surface of the isolation dielectric layer 240 away from the drift layer 210 has a step region, and the orthographic projection of the step region of the isolation dielectric layer 240 and the conductive extension member 270 on the drift layer 210 has an overlapping region.

[0060] The material of the field oxide layer 230 includes silicon oxide. The material of the isolation dielectric layer 240 includes borophosphosilicate glass.

[0061] Due to the arrangement of the conductive extension 270, the surface of the isolation dielectric layer 240 on the side away from the drift layer 210 has a stepped area, the surface of the field oxide layer 230 on the side away from the drift layer 210 has a stepped area, the surface of the isolation dielectric layer 240 on the side away from the drift layer 210 becomes curved, and the surface of the field oxide layer 230 on the side away from the drift layer 210 becomes curved, increasing the migration difficulty of metal ions in the conductive extension 270.

[0062] Reference Figures 2 to 4 , the sub-conductive extension 2701 is located between the isolation dielectric layer 240 and the field oxide layer 230.

[0063] Reference Figure 2 and Figure 3 , the sub-conductive extension 2701 includes a first part, a second part, and a third part. The second part connects the first part and the second part. The thickness of the field oxide layer 230 between the third part and the main junction 221 is greater than the thickness of the field oxide layer 230 between the first part and the main junction 221. The distance from the surface of the isolation dielectric layer 240 away from the first part to the drift layer is less than the distance from the surface of the isolation dielectric layer 240 away from the third part to the drift layer.

[0064] Reference Figure 4 , the surface of the sub-conductive extension 2701 on the side away from the main junction 221 is a plane.

[0065] The semiconductor structure further includes: a field limiting ring 222, located in the terminal region, and the field limiting ring 222 is located on the side of the main junction 221 away from the active region.

[0066] The semiconductor structure for improving the high-temperature and high-humidity reverse bias reliability further includes: a passivation layer 250, located on the side of the isolation dielectric layer 240 away from the terminal region. The material of the passivation layer 250 includes silicon oxide. The passivation layer 250 is used to prevent water vapor. The conductive lead-out 260 penetrates through the passivation layer 250. The surface of the passivation layer 250 on the side facing the drift layer 210 has a stepped area, and the stepped area of the passivation layer 250 and the positive projection of the conductive extension 270 on the drift layer 210 have an overlapping area.

[0067] In one embodiment, the isolation dielectric layer 240 and the insulating isolation layer are made of the same material.

[0068] Another embodiment of the present application further provides a method for manufacturing a semiconductor structure for improving the reliability of high-temperature and high-humidity reverse bias, including: forming a drift layer, where the drift layer includes an active region and a termination region; forming a main junction in the termination region of the drift layer; forming a conductive lead connected to the main junction on a side of the main junction away from the drift layer; forming a conductive extension; wherein, the conductive extension is located on a side of the conductive lead away from the active region along the direction from the active region to the termination region, the conductive extension is connected to the conductive lead, and the conductive extension is used to shield the electric field from one end of the termination region away from the active region to the conductive lead.

[0069] The following refers to Figures 5 to 7 to introduce in detail a method for manufacturing a semiconductor structure for improving the reliability of high-temperature and high-humidity reverse bias.

[0070] Refer to Figure 5 , a drift layer 210 is formed on one side of a substrate layer 200, the drift layer 210 includes an active region and a termination region; a main junction 221 is formed in the termination region of the drift layer 210; a field limiting ring 222 is formed in the termination region of the drift layer 210; a field oxide layer 230 is formed on one side of the termination region; a first groove (not shown) and a second groove G are formed in the field oxide layer 230, the second groove G communicates with the first groove, the first groove penetrates through the field oxide layer 230 and exposes the main junction 221, and the bottom of the second groove G has the field oxide layer 230.

[0071] The descriptions of the substrate layer 200 and the drift layer 210, and the main junction 221 and the field limiting ring 222 refer to the foregoing embodiments.

[0072] The process of forming the field oxide layer 230 on one side of the termination region includes an oxidation process or a deposition process.

[0073] The process of forming the first groove (not shown) and the second groove G in the field oxide layer 230 includes an etching process.

[0074] Wherein, the second groove G includes a plurality of second sub-grooves G1, and the arrangement direction of the plurality of second sub-grooves G1 is parallel to the direction from the active region to the termination region. The second sub-grooves G1 communicate with the first groove.

[0075] In this embodiment, it further includes: forming a conductive lead 260 connected to the main junction 221 on a side of the main junction 221 away from the drift layer 210; forming the conductive lead 260 includes: forming the conductive lead 260 in the first groove.

[0076] The description of the conductive lead 260 refers to the foregoing embodiments.

[0077] Refer to Figure 6, a conductive extension 270 is formed; wherein, the conductive extension 270 is located on a side of the conductive lead-out member 260 away from the active region along the direction from the active region to the terminal region, and the conductive extension 270 is connected to the conductive lead-out member 260.

[0078] Forming the conductive extension 270 includes: forming the conductive extension 270 on a side of the field oxide layer 230 in the second groove G and on the side of the second groove G away from the main junction 221.

[0079] Forming the conductive extension 270 on a side of the field oxide layer 230 in the second groove G and on the side of the second groove G away from the main junction 221 includes: forming a sub-conductive extension 2701 on a side of the field oxide layer 230 in the second sub-groove G1 and on the side of the second sub-groove G1 away from the main junction 221.

[0080] In one embodiment, the material of the conductive extension 270 includes a semiconductor material or a doped semiconductor material; the conductivity of the conductive extension 270 is less than the conductivity of the conductive lead-out member 260. Preferably, the conductivity of the conductive lead-out member is 10e6 S / cm to 10e7 S / cm; the conductivity of the conductive extension is 1e1 S / cm to 1e4 S / cm. When the material of the conductive extension 270 is a doped semiconductor material, the doping type of the conductive extension 270 is P-type or N-type. Exemplarily, the material of the conductive extension 270 includes polysilicon or doped polysilicon.

[0081] Forming the conductive extension 270 includes forming a plurality of spaced sub-conductive extensions 2701, and the arrangement direction of the plurality of spaced sub-conductive extensions 2701 is parallel to the direction from the active region to the terminal region; the sub-conductive extension is connected to the conductive lead-out member.

[0082] In one embodiment, forming the sub-conductive extension 2701 includes forming an N-type doped first conductive portion and a P-type doped second conductive portion, and the second conductive portion and the first conductive portion form a PN junction; along the direction from the active region to the terminal region, the second conductive portion is located on a side of the first conductive portion away from the conductive lead-out member 260. The direction of the intrinsic electric field from the first conductive portion to the second conductive portion is opposite to the direction of the electric field from the end of the terminal region away from the active region to the conductive lead-out member 260, so that the electric field near the conductive lead-out member 260 can be reduced, the migration of metal ions in the conductive lead-out member 260 under high temperature, high pressure and high humidity conditions can be solved, the hydrolysis effect can be reduced, and the reliability of the semiconductor structure can be improved.

[0083] The sub-conductive extension 2701 includes a first part, a second part, and a third part. The second part connects the first part and the second part. The thickness of the field oxide layer 230 between the third part and the main junction 221 is greater than the thickness of the field oxide layer 230 between the first part and the main junction 221. The distance from the surface of the isolation dielectric layer 240 facing away from the first part to the drift layer is less than the distance from the surface of the isolation dielectric layer 240 facing away from the third part to the drift layer.

[0084] Reference Figure 7 , an isolation dielectric layer 240 is formed on one side of the field oxide layer 230 and the conductive extension 270 facing away from the terminal region. The isolation dielectric layer 240 exposes the conductive lead-out member 260; a passivation layer 250 is formed on one side of the isolation dielectric layer 240 facing away from the terminal region, and the passivation layer 250 exposes the conductive lead-out member 260. The surface of the passivation layer 250 facing the drift layer 210 side has a stepped region, and the stepped region of the passivation layer 250 and the orthographic projection of the conductive extension 270 on the drift layer 210 have an overlapping region.

[0085] The description of the isolation dielectric layer 240 and the conductive lead-out member 260 refers to the foregoing embodiments.

[0086] Next, with reference to Figures 8 to 10 Another preparation method of a semiconductor structure for improving the reliability of high-temperature and high-humidity reverse bias will be introduced in detail.

[0087] Reference Figure 8 , a drift layer 210 is formed on one side of the substrate layer 200. The drift layer 210 includes an active region and a terminal region; a main junction 221 is formed in the terminal region of the drift layer 210; a field limiting ring 222 is formed in the terminal region of the drift layer 210; a field oxide layer 230 is formed on one side of the terminal region; a first groove (not shown) and a second groove G are formed in the field oxide layer 230. The second groove G communicates with the first groove. The first groove penetrates through the field oxide layer 230 and exposes the main junction 221, and the bottom of the second groove G has the field oxide layer 230.

[0088] Among them, the second groove G includes a second sub-groove G1. The second sub-groove G1 communicates with the first groove.

[0089] In this embodiment, it further includes: forming a conductive lead-out member 260 connected to the main junction 221 on the side of the main junction 221 facing away from the drift layer 210; forming the conductive lead-out member 260 includes: forming the conductive lead-out member 260 in the first groove.

[0090] Reference Figure 9, forming a conductive extension 270; wherein the conductive extension 270 is located on a side of the conductive lead-out member 260 away from the active area along the direction from the active area to the terminal area, and the conductive extension 270 is connected to the conductive lead-out member 260.

[0091] The forming of the conductive extension member 270 includes: forming the conductive extension member 270 in the second groove G and on a side of the second groove G that is away from the main junction 221 .

[0092] Forming the conductive extension 270 in the second groove G and on the side of the field oxide layer 230 away from the main junction 221 includes: forming a sub-conductive extension 2701 in the second sub-groove G1 and on the side of the field oxide layer 230 away from the main junction 221 .

[0093] In one embodiment, the material of the conductive extension 270 includes a semiconductor material or a doped semiconductor material; the conductivity of the conductive extension 270 is less than the conductivity of the conductive lead 260. Preferably, the conductivity of the conductive lead is 10e6S / cm to 10e7S / cm; the conductivity of the conductive extension is 1e1S / cm to 1e4S / cm. When the material of the conductive extension 270 is a doped semiconductor material, the doping type of the conductive extension 270 is P-type or N-type. Exemplarily, the material of the conductive extension 270 includes polysilicon or doped polysilicon.

[0094] Forming the conductive extension 270 includes forming a sub-conductive extension 2701 ; the sub-conductive extension 2701 is connected to the conductive lead-out member 260 .

[0095] In one embodiment, forming the sub-conductive extension 2701 includes forming an N-type doped first conductive portion and a P-type doped second conductive portion, wherein the second conductive portion and the first conductive portion form a PN junction; along the direction from the active region to the terminal region, the second conductive portion is located on the side of the first conductive portion away from the conductive lead-out member 260. The direction of the intrinsic electric field from the first conductive portion to the second conductive portion is opposite to the direction of the electric field from the end of the terminal region away from the active region to the conductive lead-out member 260, which can reduce the electric field near the conductive lead-out member 260, resolve the migration of metal ions in the conductive lead-out member 260 under high temperature, high pressure and high humidity conditions, reduce the hydrolysis effect, and improve the reliability of the semiconductor structure.

[0096] The sub-conductive extension 2701 includes a first part, a second part, and a third part. The second part connects the first part and the second part. The thickness of the field oxide layer 230 between the third part and the main junction 221 is greater than the thickness of the field oxide layer 230 between the first part and the main junction 221. The distance from the surface of the isolation dielectric layer 240 facing away from the first part to the drift layer is less than the distance from the surface of the isolation dielectric layer 240 facing away from the third part to the drift layer.

[0097] Reference Figure 10 , an isolation dielectric layer 240 is formed on one side of the field oxide layer 230 and the conductive extension 270 facing away from the terminal region. The isolation dielectric layer 240 exposes the conductive lead-out member 260; a passivation layer 250 is formed on one side of the isolation dielectric layer 240 facing away from the terminal region, and the passivation layer 250 exposes the conductive lead-out member 260. The surface of the passivation layer 250 facing the drift layer 210 side has a stepped area, and the stepped area of the passivation layer 250 and the orthographic projection of the conductive extension 270 on the drift layer 210 have an overlapping area.

[0098] The description of the isolation dielectric layer 240 and the conductive lead-out member 260 refers to the foregoing embodiments.

[0099] Next, refer to Figures 11 to 13 Another manufacturing method of a semiconductor structure for improving the reliability of high-temperature and high-humidity reverse bias is introduced in detail.

[0100] Reference Figure 11 , a drift layer 210 is formed on one side of the substrate layer 200. The drift layer 210 includes an active region and a terminal region; a main junction 221 is formed in the terminal region of the drift layer 210; a field limiting ring 222 is formed in the terminal region of the drift layer 210; a field oxide layer 230 is formed on one side of the terminal region; a first groove (not shown) and a second groove G are formed in the field oxide layer 230. The second groove G communicates with the first groove. The first groove penetrates through the field oxide layer 230 and exposes the main junction 221. The bottom of the second groove G has the field oxide layer 230.

[0101] In this embodiment, it further includes: forming a conductive lead-out member 260 connected to the main junction 221 on the side of the main junction 221 facing away from the drift layer 210; forming the conductive lead-out member 260 includes: forming the conductive lead-out member 260 in the first groove.

[0102] Wherein, forming the conductive lead-out member 260 includes: forming the conductive lead-out member 260 in the first groove.

[0103] Reference Figure 12, forming a conductive extension 270; wherein the conductive extension 270 is located on a side of the conductive lead-out member 260 away from the active area along the direction from the active area to the terminal area, and the conductive extension 270 is connected to the conductive lead-out member 260.

[0104] The forming of the conductive extension member 270 includes: forming the conductive extension member 270 in the second groove G. The conductive extension member 270 includes one or more sub-conductive extension members 2701 . Figure 12 In the figure, the conductive extension member 270 including a sub-conductive extension member 2701 is taken as an example.

[0105] The surface of the sub-conductive extension 2701 facing away from the main junction 221 is a plane.

[0106] In one embodiment, the material of the conductive extension 270 includes a semiconductor material or a doped semiconductor material; the conductivity of the conductive extension 270 is less than the conductivity of the conductive lead 260. Preferably, the conductivity of the conductive lead is 10e6S / cm to 10e7S / cm; the conductivity of the conductive extension is 1e1S / cm to 1e4S / cm. When the material of the conductive extension 270 is a doped semiconductor material, the doping type of the conductive extension 270 is P-type or N-type. Exemplarily, the material of the conductive extension 270 includes polysilicon or doped polysilicon.

[0107] Forming the conductive extension 270 includes forming one or more spaced sub-conductive extensions 2701, wherein the arrangement direction of the plurality of spaced sub-conductive extensions 2701 is parallel to the direction from the active area to the terminal area; and the sub-conductive extensions are connected to the conductive lead-out member.

[0108] In one embodiment, forming the sub-conductive extension 2701 includes forming an N-type doped first conductive portion and a P-type doped second conductive portion, wherein the second conductive portion and the first conductive portion form a PN junction; along the direction from the active region to the terminal region, the second conductive portion is located on the side of the first conductive portion away from the conductive lead-out member 260. The direction of the intrinsic electric field from the first conductive portion to the second conductive portion is opposite to the direction of the electric field from the end of the terminal region away from the active region to the conductive lead-out member 260, which can reduce the electric field near the conductive lead-out member 260, resolve the migration of metal ions in the conductive lead-out member 260 under high temperature, high pressure and high humidity conditions, reduce the hydrolysis effect, and improve the reliability of the semiconductor structure.

[0109] refer to Figure 13, an isolation dielectric layer 240 is formed on a side of the conductive extension 270 facing away from the terminal region in the field oxide layer 230, and the isolation dielectric layer 240 exposes the conductive lead-out member 260; a passivation layer 250 is formed on a side of the isolation dielectric layer 240 facing away from the terminal region, and the passivation layer 250 exposes the conductive lead-out member 260. A surface of the passivation layer 250 facing the drift layer 210 has a stepped region, and an overlapping region exists between the stepped region of the passivation layer 250 and a positive projection of the conductive extension 270 on the drift layer 210.

[0110] The descriptions of the isolation dielectric layer 240 and the conductive lead-out member 260 refer to the foregoing embodiments.

[0111] Obviously, the above embodiments are merely examples given for clear illustration and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all the implementation manners here. And the obvious changes or modifications derived therefrom still fall within the protection scope of the present invention.

Claims

1. A semiconductor structure for improving the reliability of reverse bias under high temperature and high humidity, characterized in that, Comprising: A drift layer, the drift layer including an active region and a terminal region; A main junction located in the terminal region of the drift layer; A conductive lead located on a side of the main junction facing away from the drift layer and connected to the main junction; A conductive extension located on a side of the conductive lead facing away from the active region along the direction from the active region to the terminal region, the conductive extension being connected to the conductive lead, and the conductive extension being configured to shield an electric field from an end of the terminal region far from the active region to the conductive lead.

2. The semiconductor structure for improving the reliability of high-temperature and high-humidity reverse bias according to claim 1, wherein The material of the conductive extension includes a semiconductor material or a doped semiconductor material; the conductivity of the electrical extension is less than the conductivity of the conductive lead; Preferably, the conductivity of the conductive lead is 10e6 S / cm to 10e7 S / cm; the conductivity of the conductive extension is 1e1 S / cm to 1e4 S / cm; Preferably, the material of the conductive extension includes polysilicon or doped polysilicon.

3. The semiconductor structure for improving the reliability of high-temperature and high-humidity reverse bias according to claim 1, wherein The material of the conductive lead includes a metal.

4. The semiconductor structure for improving the reliability of high-temperature and high-humidity reverse bias according to claim 1, wherein The conductive extension includes one or more spaced sub-conductive extensions, and the arrangement direction of the plurality of spaced sub-conductive extensions is parallel to the direction from the active region to the terminal region; the sub-conductive extensions are connected to the conductive lead.

5. The semiconductor structure for improving the reliability of high-temperature and high-humidity reverse bias according to claim 4, wherein The sub-conductive extension includes an N-type doped first conductive portion and a P-type doped second conductive portion, and the second conductive portion and the first conductive portion form a PN junction; along the direction from the active region to the terminal region, the second conductive portion is located on a side of the first conductive portion facing away from the conductive lead.

6. The semiconductor structure for improving the reliability of high-temperature and high-humidity reverse bias according to claim 4, wherein The semiconductor structure for improving high-temperature and high-humidity reverse bias reliability further includes: a field oxide layer located on one side of the terminal region; an isolation dielectric layer located on a side of the field oxide layer facing away from the terminal region; wherein, the conductive lead penetrates through the isolation dielectric layer and the field oxide layer; Wherein, the conductive extension is located between the isolation dielectric layer and the field oxide layer; the surface of the field oxide layer facing away from the drift layer has a stepped region; the surface of the isolation dielectric layer facing away from the drift layer has a stepped region. Preferably, the sub-conductive extension includes a first portion, a second portion, and a third portion, the second portion connecting the first portion and the second portion, and the thickness of the field oxide layer between the third portion and the main junction is greater than the thickness of the field oxide layer between the first portion and the main junction; Preferably, the semiconductor structure for improving high-temperature and high-humidity reverse bias reliability further includes: a passivation layer located on a side of the isolation dielectric layer facing away from the terminal region, the surface of the passivation layer facing the drift layer has a stepped region, and the stepped region of the passivation layer and the positive projection of the conductive extension on the drift layer have an overlapping region.

7. A method for preparing a semiconductor structure for improving the reliability of high-temperature and high-humidity reverse bias, characterized in that, Comprising: Forming a drift layer, the drift layer including an active region and a terminal region; Forming a main junction in the terminal region of the drift layer; Forming a conductive lead connected to the main junction on a side of the main junction facing away from the drift layer; Forming a conductive extension; The conductive extension piece is located on a side of the conductive lead-out piece away from the active area along the direction from the active area to the terminal area, and the conductive extension piece is connected to the conductive lead-out piece. The conductive extension piece is used to shield the electric field from the end of the terminal area away from the active area to the conductive lead-out piece.

8. The manufacturing method of the semiconductor structure for improving the reliability of high-temperature and high-humidity reverse bias according to claim 7, characterized in that, Also includes: forming a field oxide layer on one side of the terminal region; forming a first groove and a second groove in the field oxide layer, the second groove is connected to the first groove, the first groove penetrates the field oxide layer and exposes the main junction, and the bottom of the second groove has the field oxide layer; Wherein, forming the conductive lead-out member comprises: forming the conductive lead-out member in the first groove; Wherein, forming the conductive extension comprises: forming the conductive extension in the second groove and on a side of the field oxide layer at a side of the second groove away from the main junction; The preparation method further comprises: forming an isolation dielectric layer on a side of the field oxide layer and the conductive extension away from the terminal region, wherein the isolation dielectric layer exposes the conductive lead-out member; Preferably, the preparation method further includes: forming a passivation layer, wherein the passivation layer is located on a side of the isolation dielectric layer away from the terminal region, the surface of the passivation layer facing the drift layer has a step region, and the step region of the passivation layer and the orthographic projection of the conductive extension on the drift layer have an overlapping region.

9. The method for preparing a semiconductor structure for improving the reliability of reverse bias at high temperature and high humidity according to claim 7, characterized in that, The material of the conductive extension member includes a semiconductor material or a doped semiconductor material; the conductivity of the conductive extension member is less than the conductivity of the conductive lead-out member.

10. The method for preparing a semiconductor structure for improving the reliability of high-temperature and high-humidity reverse bias according to claim 7, wherein Forming the conductive extension includes forming one or more spaced sub-conductive extensions, wherein the arrangement direction of the plurality of spaced sub-conductive extensions is parallel to the direction from the active area to the terminal area; the sub-conductive extension is connected to the conductive lead-out member; Preferably, forming the sub-conductive extension includes forming an N-type doped first conductive part and a P-type doped second conductive part, the second conductive part and the first conductive part constitute a PN junction; along the direction from the active area to the terminal area, the second conductive part is located on the side of the first conductive part away from the conductive lead-out part.

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