Semiconductor device and manufacturing method, power module, power conversion circuit and vehicle

Abstract

The present invention discloses a semiconductor device and a manufacturing method, a power module, a power conversion circuit, and a vehicle. The semiconductor device includes: a semiconductor body, the semiconductor body including a first surface and a second surface disposed opposite each other, the semiconductor body including a well region and a first region, the first region being located on the first surface, and the well region being located on a side of the first region away from the first surface; a gate trench provided on the first surface, the gate trench extending from the first surface into the semiconductor body; a first epitaxial layer located at the bottom of the gate trench; a first insulating layer located on the sidewalls of the gate trench and on a side of the first epitaxial layer close to the first surface; a gate located within the gate trench and on a side of the first insulating layer away from the semiconductor body; a source electrode located on the first surface; and a drain electrode located on the second surface. The present invention can effectively shield high electric fields at the bottom and corners of the gate trench.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Trench-type metal oxide semiconductor field effect transistor (MOSFET) semiconductor devices have advantages such as high current density and small cell size. However, the high electric field at the bottom and corners of the gate trench leads to a high electric field on the gate oxide layer, which in turn makes the gate oxide layer very susceptible to breakdown.

[0003] To better protect the gate oxide layer, one approach is to use a dual-trench structure in trench MOSFET semiconductor devices. This involves constructing dual source trenches on both sides of the gate trench to shield the electric field at the bottom of the gate trench. However, this dual-trench structure requires the fabrication of additional source trenches, which is complex. Another approach is to use an asymmetric gate trench structure in trench MOSFET semiconductor devices. This structure reduces the electric field at the bottom of the gate trench by embedding a P+ or N+ doped region at the bottom of the gate trench. However, this asymmetric structure sacrifices half of the conductive trench, thereby reducing the on-state current. Summary of the Invention

[0004] The present invention provides a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle, so as to solve the problem that the gate oxide layer of a trench MOSFET semiconductor device is extremely easy to break down.

[0005] In a first aspect, the present invention provides a semiconductor device, comprising:

[0006] A semiconductor body of a first conductivity type is provided, the semiconductor body including a first surface and a second surface disposed opposite to each other, the semiconductor body including a well region of the second conductivity type and a first region of the first conductivity type, the first region being located on the first surface, and the well region being located on a side of the first region away from the first surface; a gate trench is provided on the first surface, the gate trench extending from the first surface into the semiconductor body;

[0007] A first epitaxial layer is configured as a second conductivity type and is located at the bottom of the gate trench;

[0008] a first insulating layer, located on the sidewalls of the gate trench and on a side of the first epitaxial layer close to the first surface;

[0009] a gate located in the gate trench and on a side of the first insulating layer away from the semiconductor body;

[0010] a source electrode located on the first surface;

[0011] A drain is located on the second surface.

[0012] Optionally, the doping concentration of the first epitaxial layer is greater than the doping concentration of the well region.

[0013] Optionally, the thickness of the first insulating layer located on a side of the first epitaxial layer close to the first surface is greater than the thickness of the first insulating layer located on a sidewall of the gate trench.

[0014] Optionally, the semiconductor device further comprises a second insulating layer located on a side of the gate away from the semiconductor body, wherein a vertical projection of the second insulating layer on the first surface covers a vertical projection of the gate on the first surface;

[0015] The source is located on the first surface of the semiconductor body, is connected to the first region, and a vertical projection of the source on the first surface covers a vertical projection of the second insulating layer on the first surface.

[0016] In a second aspect, the present invention provides a method for preparing a semiconductor device, the method comprising:

[0017] A semiconductor body of a first conductivity type is provided, the semiconductor body including a first surface and a second surface disposed opposite to each other, the semiconductor body including a well region of the second conductivity type and a first region of the first conductivity type, the first region being located on the first surface, and the well region being located on a side of the first region away from the first surface; a gate trench being provided on the first surface, the gate trench extending from the first surface into the semiconductor body;

[0018] forming a first epitaxial layer at the bottom of the gate trench, wherein the first epitaxial layer is set to be of the second conductivity type;

[0019] forming a first insulating layer on the sidewall of the gate trench and on a side of the first epitaxial layer close to the first surface;

[0020] forming a gate in the gate trench and on a side of the first insulating layer away from the semiconductor body;

[0021] forming a source electrode on the first surface;

[0022] A drain electrode is formed on the second surface.

[0023] Optionally, forming a first epitaxial layer at the bottom of the gate trench includes:

[0024] epitaxially growing a first epitaxial layer on the bottom and sidewalls of the gate trench and the first surface;

[0025] forming a mask layer on a side of the first epitaxial layer at the bottom of the gate trench away from the semiconductor body;

[0026] Using the mask layer as a mask, removing the first epitaxial layer located on the first surface and at least a portion of the first epitaxial layer located on the sidewall of the gate trench;

[0027] The mask layer is removed.

[0028] Optionally, forming a mask layer on a side of the first epitaxial layer at the bottom of the gate trench away from the semiconductor body includes:

[0029] A silicon dioxide mask layer is formed on a side of the first epitaxial layer at the bottom of the gate trench away from the semiconductor body.

[0030] Optionally, forming a first insulating layer on the sidewalls of the gate trench and on a side of the first epitaxial layer close to the first surface includes:

[0031] The first epitaxial layer at the bottom of the gate trench is thermally oxidized, and the semiconductor body at the sidewall of the gate trench is thermally oxidized to form a first insulating layer; the oxidation rate of the first epitaxial layer is greater than the oxidation rate of the semiconductor body.

[0032] In a third aspect, the present invention provides a power module, which includes a substrate and at least one semiconductor device provided in the first aspect, wherein the substrate is used to carry the semiconductor device.

[0033] In a fourth aspect, the present invention provides a power conversion circuit, wherein the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction;

[0034] The power conversion circuit includes a circuit board and at least one semiconductor device provided by the first aspect, wherein the semiconductor device is electrically connected to the circuit board.

[0035] In a fifth aspect, the present invention provides a vehicle comprising a load and a power conversion circuit as provided in the fourth aspect above, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0036] The technical solution of the embodiment of the present invention is to set a first epitaxial layer at the bottom and groove corner of the gate trench. The first epitaxial layer can serve as an electric field shielding layer, which can effectively shield the high electric field at the bottom and groove corner of the gate trench and reduce the electric field strength at the bottom and groove corner of the gate trench. The semiconductor device provided by the embodiment of the present invention does not need to set a source trench. By setting the first epitaxial layer, it can effectively shield the high electric field at the bottom and groove corner of the gate trench and reduce the electric field strength at the bottom and groove corner of the gate trench. Therefore, the embodiment of the present invention effectively simplifies the preparation process of the semiconductor device, increases the contact area between the second region and the source, and reduces the contact resistance between the source and the second region. In addition, the embodiment of the present invention does not need to adopt an asymmetric gate trench structure, effectively avoiding the problem that the asymmetric gate trench structure sacrifices half of the conductive trench, thereby reducing the on-state current. The technical solution of the embodiment of the present invention effectively solves the problem that the strong electric field at the bottom and groove corner of the gate trench leads to a high electric field on the gate oxide layer, which in turn causes the gate oxide layer to be easily broken down, and effectively improves the reliability of the semiconductor device.

[0037] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0039] Figure 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0040] Figure 2 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0041] Figure 3-Figure 8 It is a structural diagram corresponding to each step in a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0042] Figure 9 is a flow chart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0043] Figure 10-12 It is a structural diagram corresponding to some steps in another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0044] Figure 13is a flow chart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0045] Figure 14 is a flow chart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0046] Figure 15-17 This is a structural diagram corresponding to some steps in another method for manufacturing a semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0047] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0048] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0049] In order to solve the problem that the high electric field at the bottom and corner of the gate trench of a trench MOSFET semiconductor device causes a high electric field on the gate oxide layer, which in turn makes the gate oxide layer extremely easy to break down, and to improve the reliability of the trench MOSFET semiconductor device, the embodiments of the present invention provide the following technical solutions:

[0050] Figure 1 Schematic diagram of a semiconductor device according to an embodiment of the present invention. Figure 1As shown, the semiconductor device includes: a semiconductor body 1 of a first conductivity type, the semiconductor body 1 including a first surface 101 and a second surface 102 arranged opposite to each other, the semiconductor body 1 including a well region 13 of the second conductivity type and a first region 14 of the first conductivity type, the first region 14 being located on the first surface 101, and the well region 13 being located on a side of the first region 14 away from the first surface 101. A gate trench is provided on the first surface 101, extending from the first surface 101 into the semiconductor body 1. A first epitaxial layer 16 of the second conductivity type is located at the bottom of the gate trench. A first insulating layer 17 is located on the sidewalls of the gate trench and on a side of the first epitaxial layer 16 close to the first surface 101. A gate 2 is located within the gate trench and on the side of the first insulating layer 17 away from the semiconductor body 1. A source 4 is located on the first surface 101. A drain 5 is located on the second surface 102.

[0051] Alternatively, as Figure 1 As shown, the semiconductor body 1 may further include a second region 15 . The doping concentration of the second region 15 is greater than the doping concentration of the well region 13 , and may form a good ohmic contact with the source 4 .

[0052] It should be noted that the MOSFET semiconductor device may include an N-channel MOSFET semiconductor device or a P-channel MOSFET semiconductor device. Exemplarily, for an N-channel MOSFET semiconductor device, the first conductivity type is N-type and the second conductivity type is P-type. The semiconductor body 1 is an N-type semiconductor body, the well region 13 is a P-type well region, the first region 14 is an N+ doped region, the second region 15 is a P+ doped region, and the first epitaxial layer 16 is a P+ epitaxial layer. For a P-channel MOSFET semiconductor device, the first conductivity type is P-type and the second conductivity type is N-type. The semiconductor body 1 is a P-type semiconductor body, the well region 13 is an N-type well region, the first region 14 is a P+ doped region, the second region 15 is an N+ doped region, and the first epitaxial layer 16 is an N+ epitaxial layer.

[0053] For example, Figure 1As shown, the semiconductor body 1 may further include a substrate 11 and a second epitaxial layer 12. For an N-channel MOSFET semiconductor device, the substrate 11 includes an N+ substrate, and the second epitaxial layer 12 includes an N-epitaxial layer. For a P-channel MOSFET semiconductor device, the substrate 11 includes a P+ substrate, and the second epitaxial layer 12 includes a P-epitaxial layer. In some embodiments of the present invention, the semiconductor body 1 may further include only the second epitaxial layer 12. In other embodiments of the present invention, the semiconductor body 1 may further include a substrate 11 and semiconductor layers formed by other processes. The second epitaxial layer 12 is a semiconductor layer formed on the basis of the substrate 11 through a single epitaxial process, and the epitaxial process includes processes such as chemical vapor epitaxy (CVE), molecular beam epitaxy (MBE), and atomic layer epitaxy (ALE). The conductivity types of the first epitaxial layer 16 and the second epitaxial layer 12 may be different.

[0054] The semiconductor device may further include a first insulating layer 17, which is located on the sidewalls of the gate trench and on a side of the first epitaxial layer 16 close to the first surface 101, and may further extend to the first surface 101. The first insulating layer 17 may include a gate oxide layer.

[0055] The first epitaxial layer 16 can be a semiconductor layer formed at the bottom of the gate trench through a single epitaxial growth process. The first epitaxial layer 16 has the advantages of controllable thickness and doping area, and it forms a neat boundary with the second epitaxial layer 12. The first epitaxial layer 16 is provided at the bottom and corners of the gate trench. The first epitaxial layer 16 can serve as an electric field shield, effectively shielding the high electric field at the bottom and corners of the gate trench, thereby reducing the electric field strength at the bottom and corners of the gate trench.

[0056] The technical solution of the embodiment of the present invention is to set a first epitaxial layer 16 at the bottom and groove corner of the gate trench. The first epitaxial layer 16 can serve as an electric field shielding layer, which can effectively shield the high electric field at the bottom and groove corner of the gate trench and reduce the electric field strength at the bottom and groove corner of the gate trench. The semiconductor device provided by the embodiment of the present invention does not need to set a source trench. By setting the first epitaxial layer 16, it can effectively shield the high electric field at the bottom and groove corner of the gate trench and reduce the electric field strength at the bottom and groove corner of the gate trench. Therefore, the embodiment of the present invention effectively simplifies the preparation process of the semiconductor device, increases the contact area between the second region 15 and the source 4, and reduces the contact resistance between the source 4 and the second region 15. In addition, the embodiment of the present invention does not need to adopt an asymmetric gate trench structure, effectively avoiding the problem that the asymmetric gate trench structure sacrifices half of the conductive trench, thereby reducing the on-state current. The technical solution of the embodiment of the present invention effectively solves the problem that the strong electric field at the bottom and groove corner of the gate trench leads to a high electric field on the gate oxide layer, which in turn causes the gate oxide layer to be easily broken down, effectively improving the reliability of the semiconductor device.

[0057] Optionally, based on the above embodiments, continue to refer to Figure 1 The thickness of the first insulating layer 17 located on the side of the first epitaxial layer 16 close to the first surface 101 is greater than the thickness of the first insulating layer 17 located on the sidewall of the gate trench.

[0058] Specifically, the thickness of the first insulating layer 17 located at the bottom of the gate trench and on the side of the first epitaxial layer 16 close to the first surface 101 is relatively thick, and the thickness of the first insulating layer 17 located on the sidewall of the gate trench is relatively thin. By setting the thickness of the first insulating layer 17 on the side of the first epitaxial layer 16 close to the first surface 101 to be relatively thick, the voltage resistance of the semiconductor device can be effectively improved, and the problem of the high electric field at the bottom and groove corner of the gate trench of the trench MOSFET semiconductor device causing the electric field on the first insulating layer 17 to be very high, thereby causing the first insulating layer 17 to be extremely easy to break down, is further solved.

[0059] Optionally, based on the above embodiments, continue to refer to Figure 1 , the doping concentration of the first epitaxial layer 16 is greater than the doping concentration of the well region 13 .

[0060] Specifically, the first insulating layer 17 can be formed by thermally oxidizing the first epitaxial layer 16 at the bottom of the gate trench and the second epitaxial layer 12, the well region 13, and the first region 14 on the sidewalls of the gate trench. The doping concentration of the first epitaxial layer 16 is greater than the doping concentration of the well region 13, greater than the doping concentration of the second epitaxial layer 12, and may also be greater than the doping concentration of the first region 14. This causes the oxidation rate of the first epitaxial layer 16 to be greater than the oxidation rate of the second epitaxial layer 12, the well region 13, and the first region 14. As a result, the thickness of the first insulating layer 17 formed by thermal oxidation of the first epitaxial layer 16 at the bottom of the gate trench is relatively thick, while the thickness of the first insulating layer 17 formed by thermal oxidation of the second epitaxial layer 12, the well region 13, and the first region 14 on the sidewalls of the gate trench is relatively thin. This ensures that the thickness of the first insulating layer 17 at the bottom of the gate trench on the side of the first epitaxial layer 16 close to the first surface 101 is greater than the thickness of the first insulating layer 17 at the sidewalls of the gate trench.

[0061] By providing the first epitaxial layer 16 at the bottom of the gate trench, the first insulating layer 17 formed by thermally oxidizing the first epitaxial layer 16 at the bottom of the gate trench is thicker than the first insulating layer 17 formed by thermally oxidizing the second epitaxial layer 12 at the bottom of the gate trench. This arrangement can effectively improve the withstand voltage capability of the semiconductor device and further solve the problem that the high electric field at the bottom and corner of the gate trench of the trench MOSFET semiconductor device causes a high electric field on the first insulating layer 17, which makes the first insulating layer 17 extremely easy to break down.

[0062] Optionally, based on the above embodiments, continue to refer to Figure 1The semiconductor device further includes a second insulating layer 3 located on a side of the gate 2 away from the semiconductor body 1. The vertical projection of the second insulating layer 3 on the first surface 101 covers the vertical projection of the gate 2 on the first surface 101. The source 4 is located on the first surface 101 of the semiconductor body 1. The source 4 is connected to the first region 14, and the vertical projection of the source 4 on the first surface 101 covers the vertical projection of the second insulating layer 3 on the first surface 101.

[0063] Specifically, for a single-trench MOSFET semiconductor device, its source structure is a planar source structure, that is, there is no need to set a source trench. The vertical projection of the first insulating layer 17 on the first surface 101 can coincide with the vertical projection of the second insulating layer 3 on the first surface 101. The second insulating layer 3 may include an interlayer dielectric layer, and the second insulating layer 3 is used to insulate and isolate the gate 2 and the source 4. The source 4 is located on the first surface 101 of the semiconductor body 1. The material of the source 4 may be metal, and the source 4 is electrically connected to the first region 14. The manufacturing process of the single-trench MOSFET semiconductor device is simple, which can effectively simplify the manufacturing process of the MOSFET semiconductor device, thereby effectively reducing the time cost. At the same time, the embodiment of the present invention increases the contact area between the second region 15 and the source 4, and reduces the contact resistance between the source 4 and the second region 15.

[0064] Figure 2 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention, Figure 3-Figure 8 is a structural diagram corresponding to each step in a method for manufacturing a semiconductor device provided by an embodiment of the present invention, such as Figure 2 As shown, the preparation method includes:

[0065] S100: Provide a semiconductor body of the first conductive type, the semiconductor body including a first surface and a second surface arranged opposite to each other, the semiconductor body including a well region set to the second conductive type and a first region set to the first conductive type, the first region is located on the first surface, and the well region is located on a side of the first region away from the first surface; a gate trench is provided on the first surface, and the gate trench extends from the first surface into the semiconductor body.

[0066] Specifically, such as Figure 3 As shown, a semiconductor body 1 is first provided. The semiconductor body 1 may include a substrate 11 and a second epitaxial layer 12. In some embodiments of the present invention, the semiconductor body 1 may also include only the second epitaxial layer 12. In other embodiments of the present invention, the semiconductor body 1 may also include the substrate 11 and semiconductor layers formed by other processes. The second epitaxial layer 12 is a semiconductor layer formed on the substrate 11 through a single epitaxial process. The epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBE), and atomic layer epitaxy (ALE).

[0067] The semiconductor body 1 may further include a well region 13, a first region 14, and a second region 15. The well region 13, the first region 14, and the second region 15 are formed on the side of the second epitaxial layer 12 away from the substrate 11 through processes such as doping, and then the doped impurities are activated through an annealing process. A gate trench 20 is formed on the first surface 101 through processes such as photolithography and etching. The gate trench 20 may penetrate the well region 13 and the first region 14 and extend into the second epitaxial layer 12.

[0068] MOSFET semiconductor devices may include N-channel MOSFET semiconductor devices or P-channel MOSFET semiconductor devices. Exemplarily, for N-channel MOSFET semiconductor devices, the first conductivity type is N-type and the second conductivity type is P-type. The semiconductor body 1 is an N-type semiconductor body, the well region 13 is a P-type well region, the first region 14 is an N+ doped region, the second region 15 is a P+ doped region, the substrate 11 is an N+ substrate, and the second epitaxial layer 12 is an N-epitaxial layer. For P-channel MOSFET semiconductor devices, the first conductivity type is P-type and the second conductivity type is N-type. The semiconductor body 1 is a P-type semiconductor body, the well region 13 is an N-type well region, the first region 14 is a P+ doped region, the second region 15 is an N+ doped region, the substrate 11 is a P+ substrate, and the second epitaxial layer 12 is a P-epitaxial layer.

[0069] S110 : forming a first epitaxial layer at the bottom of the gate trench, wherein the first epitaxial layer is set to be of the second conductivity type.

[0070] Specifically, such as Figure 4 As shown, the conductivity types of the first epitaxial layer 16 and the second epitaxial layer 12 may be different. For an N-channel MOSFET semiconductor device, the first epitaxial layer 16 may be a P+ epitaxial layer. For a P-channel MOSFET semiconductor device, the first epitaxial layer 16 may be an N+ epitaxial layer.

[0071] The first epitaxial layer 16 can be a semiconductor layer formed at the bottom of the gate trench through a single epitaxial growth process. The first epitaxial layer 16 has the advantages of controllable thickness and doping area, and it forms a neat boundary with the second epitaxial layer 12. The first epitaxial layer 16 is provided at the bottom and corners of the gate trench. The first epitaxial layer 16 can serve as an electric field shield, effectively shielding the high electric field at the bottom and corners of the gate trench, thereby reducing the electric field strength at the bottom and corners of the gate trench.

[0072] S120 : forming a first insulating layer on the sidewalls of the gate trench and on a side of the first epitaxial layer close to the first surface.

[0073] Specifically, such as Figure 5As shown, the semiconductor device may further include a first insulating layer 17, which is located on the sidewalls of the gate trench and on a side of the first epitaxial layer 16 close to the first surface 101, and may further extend to the first surface 101. The first insulating layer 17 may include a gate oxide layer.

[0074] S130 : forming a gate in the gate trench and on a side of the first insulating layer away from the semiconductor body.

[0075] Specifically, such as Figure 6 As shown, a gate 2 is formed in the gate trench and on a side of the first insulating layer 17 away from the semiconductor body 1. For example, the first insulating layer 17 may include a silicon dioxide insulating layer, and the gate 2 may include a doped polysilicon gate.

[0076] Specifically, such as Figure 7 As shown, after forming the gate 2, a second insulating layer 3 can be formed on the side of the gate 2 away from the semiconductor body 1. The vertical projection of the second insulating layer 3 on the first surface 101 can overlap with the vertical projection of the first insulating layer 17 on the first surface 101, and the vertical projection of the second insulating layer 3 on the first surface 101 must cover the vertical projection of the gate 2 on the first surface 101, thereby effectively insulating the source and gate 2. The second insulating layer 3 may include an interlayer dielectric layer.

[0077] S140: forming a source electrode on the first surface.

[0078] Specifically, such as Figure 8 As shown, the source structure is a planar source structure, i.e., no source trench is required. The source electrode 4 is located on the first surface 101 of the semiconductor body 1. Exemplarily, metal is deposited on the first surface 101 to form the source electrode 4. The source electrode 4 is electrically connected to the first region 14, and the vertical projection of the source electrode 4 on the first surface 101 can cover the vertical projection of the second insulating layer 3 on the first surface 101.

[0079] S150: forming a drain electrode on the second surface.

[0080] Specifically, such as Figure 1 As shown, a drain electrode 5 is formed on the second surface 102 . Exemplarily, the drain electrode 5 is formed by depositing metal on the second surface 102 .

[0081] The technical solution of the embodiment of the present invention forms a first epitaxial layer 16 at the bottom and corner of the gate trench through a single epitaxial process. The first epitaxial layer 16 can serve as an electric field shielding layer, which can effectively shield the high electric field at the bottom and corner of the gate trench, and reduce the electric field strength at the bottom and corner of the gate trench. The semiconductor device provided by the embodiment of the present invention does not need to set a source trench. By setting the first epitaxial layer 16, it can effectively shield the high electric field at the bottom and corner of the gate trench, and reduce the electric field strength at the bottom and corner of the gate trench. Therefore, the embodiment of the present invention effectively simplifies the preparation process of the semiconductor device, increases the contact area between the second region 15 and the source 4, and reduces the contact resistance between the source 4 and the second region 15. In addition, the embodiment of the present invention does not need to adopt an asymmetric gate trench structure, which effectively avoids the problem that the asymmetric gate trench structure sacrifices half of the conductive trench, thereby reducing the on-state current. The technical solution of the embodiment of the present invention effectively solves the problem that the electric field at the bottom and corner of the gate trench is strong, resulting in a very high electric field on the gate oxide layer, which in turn makes the gate oxide layer extremely easy to break down, thereby effectively improving the reliability of the semiconductor device.

[0082] Optionally, based on the above embodiments, Figure 9 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention, Figure 10-12 FIG. 1 is a structural diagram corresponding to some steps in another method for preparing a semiconductor device provided by an embodiment of the present invention, such as Figure 9 As shown, the preparation method includes:

[0083] S200: Provide a semiconductor body of a first conductive type, the semiconductor body including a first surface and a second surface arranged opposite to each other, the semiconductor body including a well region set to the second conductive type and a first region set to the first conductive type, the first region being located on the first surface, and the well region being located on a side of the first region away from the first surface; a gate trench being provided on the first surface, and the gate trench extending from the first surface into the semiconductor body.

[0084] S210 : epitaxially growing a first epitaxial layer on the bottom and sidewalls of the gate trench and the first surface.

[0085] Specifically, such as Figure 10 As shown, a first epitaxial layer 16 is epitaxially grown on the bottom and sidewalls of the gate trench 20 and the first surface 101 . The doping concentration of the first epitaxial layer 16 may be greater than the doping concentration of the well region 13 .

[0086] S220 : forming a mask layer on a side of the first epitaxial layer at the bottom of the gate trench away from the semiconductor body.

[0087] Specifically, such as Figure 11As shown, a mask layer 7 is formed on the side of the first epitaxial layer 16 at the bottom of the gate trench 20 away from the semiconductor body 1. Exemplarily, the mask layer 7 can be formed on the entire surface of the first epitaxial layer 16 away from the semiconductor body 1, and then a full-surface etch-back process is performed to leave a small amount of mask layer 7 on the side of the first epitaxial layer 16 at the bottom of the gate trench 20 away from the semiconductor body 1.

[0088] S230: Using the mask layer as a mask, remove the first epitaxial layer located on the first surface and at least a portion of the first epitaxial layer located on the sidewalls of the gate trench.

[0089] Specifically, such as Figure 12 As shown, the first epitaxial layer 16 located on the first surface 101 and at least a portion of the sidewalls of the gate trench 20 is removed using the mask layer 7 as a mask, and the first epitaxial layer 16 at the bottom of the gate trench 20 is retained.

[0090] S240: removing the mask layer.

[0091] Specifically, such as Figure 4 As shown, the mask layer is removed by a process such as wet etching.

[0092] S250 : forming a first insulating layer on the sidewall of the gate trench and on a side of the first epitaxial layer close to the first surface.

[0093] S260 : forming a gate in the gate trench and on a side of the first insulating layer away from the semiconductor body.

[0094] S270: forming a second insulating layer on a side of the gate away from the semiconductor body, wherein a vertical projection of the second insulating layer on the first surface covers a vertical projection of the gate on the first surface.

[0095] S280: forming a source electrode on the first surface.

[0096] S290: forming a drain on the second surface.

[0097] Optionally, based on the above embodiments, Figure 13 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention, such as Figure 13 As shown, the preparation method includes:

[0098] S300: Provide a semiconductor body of the first conductive type, the semiconductor body including a first surface and a second surface arranged opposite to each other, the semiconductor body including a well region set to the second conductive type and a first region set to the first conductive type, the first region being located on the first surface, and the well region being located on a side of the first region away from the first surface; a gate trench being provided on the first surface, and the gate trench extending from the first surface into the semiconductor body.

[0099] S310 : epitaxially growing a first epitaxial layer on the bottom and sidewalls of the gate trench and the first surface.

[0100] S320: forming a silicon dioxide mask layer on a side of the first epitaxial layer at the bottom of the gate trench away from the semiconductor body.

[0101] Specifically, such as Figure 11 As shown, a mask layer 7 is formed on the side of the first epitaxial layer 16 at the bottom of the gate trench 20 away from the semiconductor body 1. Exemplarily, the mask layer 7 can be a silicon dioxide mask layer.

[0102] S330: Using the silicon dioxide mask layer as a mask, remove the first epitaxial layer located on the first surface and at least a portion of the first epitaxial layer located on the sidewall of the gate trench.

[0103] S340: removing the silicon dioxide mask layer.

[0104] S350: forming a first insulating layer on the sidewall of the gate trench and on a side of the first epitaxial layer close to the first surface.

[0105] S360: forming a gate in the gate trench and on a side of the first insulating layer away from the semiconductor body.

[0106] S370: forming a second insulating layer on a side of the gate away from the semiconductor body, wherein a vertical projection of the second insulating layer on the first surface covers a vertical projection of the gate on the first surface.

[0107] S380: forming a source electrode on the first surface.

[0108] S390: forming a drain on the second surface.

[0109] Optionally, based on the above embodiments, Figure 14 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention. Figure 15-17 FIG. 1 is a structural diagram corresponding to some steps in another method for manufacturing a semiconductor device provided by an embodiment of the present invention, such as Figure 14 As shown, the preparation method includes:

[0110] S400: Provide a semiconductor body of the first conductive type, the semiconductor body including a first surface and a second surface arranged opposite to each other, the semiconductor body including a well region set to the second conductive type and a first region set to the first conductive type, the first region being located on the first surface, and the well region being located on a side of the first region away from the first surface; a gate trench being provided on the first surface, and the gate trench extending from the first surface into the semiconductor body.

[0111] S410 : epitaxially growing a first epitaxial layer on the bottom and sidewalls of the gate trench and the first surface.

[0112] S420: forming a mask layer on a side of the first epitaxial layer at the bottom of the gate trench away from the semiconductor body.

[0113] S430: Using the mask layer as a mask, remove the first epitaxial layer located on the first surface and at least a portion of the first epitaxial layer located on the sidewall of the gate trench.

[0114] S440: removing the mask layer.

[0115] S450: thermally oxidizing the first epitaxial layer at the bottom of the gate trench and thermally oxidizing the semiconductor body at the sidewall of the gate trench to form a first insulating layer, wherein the oxidation rate of the first epitaxial layer is greater than the oxidation rate of the semiconductor body.

[0116] Specifically, such as Figure 15 As shown, the first epitaxial layer 16 at the bottom of the gate trench 20 can be thermally oxidized, and the second epitaxial layer 12, the well region 13 and the first region 14 on the sidewall of the gate trench 20 can be thermally oxidized, as well as the first region 14 and the second region 15 on the first surface can be thermally oxidized to form a first insulating layer 17.

[0117] The doping concentration of the first epitaxial layer 16 is greater than the doping concentration of the well region 13, greater than the doping concentration of the second epitaxial layer 12, and can also be greater than the doping concentration of the first region 14, so that the oxidation rate of the first epitaxial layer 16 is greater than the oxidation rate of the second epitaxial layer 12, the well region 13 and the first region 14. Therefore, the thickness of the first insulating layer 17 formed by thermal oxidation of the first epitaxial layer 16 at the bottom of the gate trench is thicker, while the thickness of the first insulating layer 17 formed by thermal oxidation of the second epitaxial layer 12, the well region 13 and the first region 14 on the sidewalls of the gate trench is thinner, so that the thickness of the first insulating layer 17 located at the bottom of the gate trench close to the first surface 101 is greater than the thickness of the first insulating layer 17 located on the sidewalls of the gate trench.

[0118] By providing the first epitaxial layer 16 at the bottom of the gate trench, the first insulating layer 17 formed by thermally oxidizing the first epitaxial layer 16 at the bottom of the gate trench is thicker than the first insulating layer 17 formed by thermally oxidizing the second epitaxial layer 12 at the bottom of the gate trench. This arrangement can effectively improve the withstand voltage capability of the semiconductor device and further solve the problem that the high electric field at the bottom and corner of the gate trench of the trench MOSFET semiconductor device causes a high electric field on the first insulating layer 17, which makes the first insulating layer 17 extremely easy to break down.

[0119] S460 : forming a gate in the gate trench and on a side of the first insulating layer away from the semiconductor body.

[0120] Specifically, such as Figure 16As shown, a gate 2 is formed in the gate trench and on a side of the first insulating layer 17 away from the semiconductor body 1. Exemplarily, the gate 2 may include a polysilicon gate, and doped polysilicon may be first deposited on the entire surface of the gate trench and on a side of the first insulating layer 17 of the first surface 101 away from the first surface 101, and then the entire surface is etched back to form the gate 2 in the gate trench.

[0121] S470: forming a second insulating layer on a side of the gate away from the semiconductor body, wherein a vertical projection of the second insulating layer on the first surface covers a vertical projection of the gate on the first surface.

[0122] Specifically, such as Figure 17 As shown, the second insulating layer 3 may be formed on a side of the gate 2 away from the semiconductor body 1 and a side of the first insulating layer 17 of the first surface 101 away from the first surface 101 .

[0123] like Figure 7 As shown, part of the second insulating layer 3 on the first surface 101 and part of the first insulating layer 17 on the first surface 101 are removed. The width of the second insulating layer 3 must be greater than the width of the gate trench, and the first region 14 must be exposed.

[0124] S480: forming a source electrode on the first surface.

[0125] S490: forming a drain on the second surface.

[0126] An embodiment of the present invention provides a power module, wherein the power module includes a substrate and at least one semiconductor device provided by any of the above embodiments of the present invention, and the substrate is used to support the at least one semiconductor device provided by any of the above embodiments of the present invention.

[0127] The power module provided by any of the above embodiments of the present invention includes the semiconductor device provided by any of the above embodiments of the present invention, and has the beneficial effects of the semiconductor device provided by any of the above embodiments of the present invention.

[0128] An embodiment of the present invention provides a power conversion circuit, wherein the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction.

[0129] The power conversion circuit includes a circuit board and at least one semiconductor device provided by any one of the above embodiments of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0130] The power conversion circuit provided by any of the above embodiments of the present invention includes the semiconductor device provided by any of the above embodiments of the present invention, and has the beneficial effects of the semiconductor device provided by any of the above embodiments of the present invention.

[0131] An embodiment of the present invention provides a vehicle, wherein the vehicle includes a load and a power conversion circuit provided by any of the above embodiments of the present invention, the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0132] The vehicle provided in any of the above embodiments of the present invention includes the power conversion circuit provided in any of the above embodiments of the present invention, and the power conversion circuit provided in any of the above embodiments of the present invention includes the semiconductor device provided in any of the above embodiments of the present invention, so the vehicle provided in any of the above embodiments of the present invention has the beneficial effects of the semiconductor device provided in any of the above embodiments of the present invention.

[0133] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0134] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body of a first conductivity type is provided, the semiconductor body including a first surface and a second surface arranged opposite to each other, the semiconductor body including a well region of the second conductivity type and a first region of the first conductivity type, the first region being located on the first surface, and the well region being located on a side of the first region away from the first surface; a gate trench is provided on the first surface, the gate trench extending from the first surface into the semiconductor body; A first epitaxial layer, configured as the second conductivity type, is located at the bottom and corner of the gate trench; a first insulating layer, located on the sidewalls of the gate trench and a side of the first epitaxial layer close to the first surface; a gate located in the gate trench and on a side of the first insulating layer away from the semiconductor body; a source electrode located on the first surface; a drain electrode located on the second surface; The first insulating layer near the bottom of the gate trench is obtained by thermal oxidation of the first epitaxial layer, and the thickness of the first insulating layer near the bottom of the gate trench is greater than the thickness of the first insulating layer located on the sidewall of the gate trench.

2. The semiconductor device according to claim 1, wherein The doping concentration of the first epitaxial layer is greater than the doping concentration of the well region.

3. The semiconductor device according to claim 1, wherein It also includes a second insulating layer located on a side of the gate away from the semiconductor body, wherein a vertical projection of the second insulating layer on the first surface covers a vertical projection of the gate on the first surface; The source is located on the first surface of the semiconductor body, the source is connected to the first region, and a vertical projection of the source on the first surface covers a vertical projection of the second insulating layer on the first surface.

4. A method for preparing a semiconductor device, characterized in that: include: A semiconductor body of a first conductivity type is provided, the semiconductor body including a first surface and a second surface disposed opposite to each other, the semiconductor body including a well region of the second conductivity type and a first region of the first conductivity type, the first region being located on the first surface, and the well region being located on a side of the first region away from the first surface; a gate trench being provided on the first surface, the gate trench extending from the first surface into the semiconductor body; forming a first epitaxial layer at the bottom and corner of the gate trench, wherein the first epitaxial layer is set to the second conductivity type; forming a first insulating layer on the sidewalls of the gate trench and on a side of the first epitaxial layer close to the first surface; forming a gate in the gate trench and on a side of the first insulating layer away from the semiconductor body; forming a source electrode on the first surface; forming a drain electrode on the second surface; The first insulating layer near the bottom of the gate trench is obtained by thermal oxidation of the first epitaxial layer, and the thickness of the first insulating layer near the bottom of the gate trench is greater than the thickness of the first insulating layer located on the sidewall of the gate trench.

5. The method for preparing a semiconductor device according to claim 4, wherein: forming a first epitaxial layer at the bottom of the gate trench, comprising: epitaxially growing the first epitaxial layer on the bottom and sidewalls of the gate trench and the first surface; forming a mask layer on a side of the first epitaxial layer at the bottom of the gate trench away from the semiconductor body; Using the mask layer as a mask, removing the first epitaxial layer located on the first surface and at least a portion of the first epitaxial layer located on the sidewall of the gate trench; The mask layer is removed.

6. The method for preparing a semiconductor device according to claim 5, wherein: Forming a mask layer on a side of the first epitaxial layer at the bottom of the gate trench away from the semiconductor body, comprising: A silicon dioxide mask layer is formed on a side of the first epitaxial layer at the bottom of the gate trench away from the semiconductor body.

7. The method for preparing a semiconductor device according to claim 4, wherein: Forming a first insulating layer on the sidewall of the gate trench and on a side of the first epitaxial layer close to the first surface, comprising: The first epitaxial layer at the bottom of the gate trench is thermally oxidized, and the semiconductor body at the sidewall of the gate trench is thermally oxidized to form the first insulating layer, wherein the oxidation rate of the first epitaxial layer is greater than the oxidation rate of the semiconductor body.

8. A power module, characterized in that: The method comprises a substrate and at least one semiconductor device according to any one of claims 1 to 3, wherein the substrate is used to carry the semiconductor device.

9. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of claims 1 to 3, wherein the semiconductor device is electrically connected to the circuit board.

10. A vehicle, characterized in that: The invention comprises a load and a power conversion circuit as claimed in claim 9, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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