Charge coupled device (CCD) structure with annular loop gridding drive link

Abstract

The invention discloses a CCD (charge coupled device) structure with an annular loop gridding driving link, which comprises a silicon epitaxial substrate and an insulating dielectric layer, a driving gate structure is arranged in the insulating dielectric layer, the driving gate structure comprises at least two driving gate groups, and each driving gate group comprises a plurality of parallel polycrystalline silicon driving gates; a grid driving link is arranged above the driving grid structure, the grid driving link comprises at least two branch grid links, and each polycrystalline silicon driving grid in each driving grid group is connected with the corresponding branch grid link through a plurality of driving grid connecting holes. In the invention, a driving mode of meshing the driving link by the annular loop is adopted, so that the wiring channels are arranged in parallel, the impedance of the driving link is greatly reduced, the signal establishment time is shortened, the line frequency driving of the large-area-array CCD is improved, and the special scene of high line frequency application of the large-area-array CCD is met.

Description

Technical Field

[0001] The present invention belongs to the field of charge-coupled devices, and particularly relates to a CCD structure with an annular loop grid driving link. Background Art

[0002] In a traditional CCD (Charge Coupled Device), after a pixel senses light, a photoelectron signal is generated. The photoelectron signal is stored in the potential well of a vertical transfer gate and is driven downward to a horizontal CCD through a vertical transfer timing drive. After bit-by-bit transfer in the horizontal CCD, the signal of each row is read out through an amplifier. For a large-area CCD, its vertical transfer gate is made of polysilicon, and the length of each phase is relatively long, with a large path resistance and capacitance. The resistance is about 100 kΩ, the capacitance is about 1 nF, and the signal establishment time (edge delay time) is about 100 μs, which cannot ensure the signal drive at a line frequency of 100 kHz and above, greatly limiting the high line frequency application of large-area CCDs. Summary of the Invention

[0003] Aiming at the deficiencies of the above-mentioned prior art, the technical problem to be solved by the present invention is to provide a CCD structure with an annular loop grid driving link.

[0004] To solve the above technical problem, the present invention provides the following technical solution:

[0005] A CCD structure with an annular loop grid driving link includes a silicon epitaxial substrate and an insulating dielectric layer provided on the silicon epitaxial substrate. An active region is provided on the upper part of the silicon epitaxial substrate, and a pixel array is formed in the active region; a driving gate structure is provided in the region directly above the active region of the insulating dielectric layer. The driving gate structure includes at least two driving gate groups, and each driving gate group includes a plurality of parallel polysilicon driving gates; a grid driving link is provided above the driving gate structure. The grid driving link includes at least two branch grid links, and the branch grid links correspond to the driving gate groups one by one. Each polysilicon driving gate in each driving gate group is connected to the corresponding branch grid link through a plurality of driving gate connection holes.

[0006] Further, the branch grid link includes an outer annular bus provided directly above the driving gate group and an internal horizontal metal wiring and an internal vertical metal wiring provided inside the annular bus; both ends of each internal horizontal metal wiring and internal vertical metal wiring are connected to the annular bus through an end wiring connection hole.

[0007] Furthermore, by adjusting the sizes of the internal transverse metal wiring and the internal longitudinal metal wiring of each driving gate group, the proportion of each pixel in the pixel array blocked by the grid driving link is made the same.

[0008] Furthermore, overlapping positions of each internal transverse metal wiring and each internal longitudinal metal wiring in the branch grid link are respectively connected through an internal wiring connection hole.

[0009] Furthermore, each of the internal transverse metal wirings is arranged at a boundary region between two adjacent rows of pixels in the pixel array, and each of the internal longitudinal metal wirings is arranged at a boundary region between two adjacent columns of pixels in the pixel array.

[0010] Furthermore, the internal transverse metal wiring of each of the branch grid links is arranged at intervals according to a predetermined first period, and the first period is greater than or equal to twice the transverse spacing between pixels; the internal longitudinal metal wiring of each of the branch grid links is arranged at intervals according to a predetermined second period, and the second period is greater than or equal to twice the longitudinal spacing between pixels.

[0011] Furthermore, the polysilicon driving gate and the internal transverse metal wiring are both arranged along a first direction, and the internal longitudinal metal wiring is arranged along a second direction perpendicular to the first direction.

[0012] Furthermore, the internal lateral metal wiring is disposed above a polysilicon driving gate of the corresponding driving gate group, and is connected to the polysilicon driving gate through a plurality of periodically arranged driving gate connection holes.

[0013] Furthermore, the ring bus includes two external transverse metal wirings arranged along the first direction and two external longitudinal metal wirings arranged along the second direction, and the two external transverse metal wirings and the two external longitudinal metal wirings are connected to form a rectangular structure; the two ends of each internal transverse metal wiring in each branch grid link are respectively connected to the two external longitudinal metal wirings of its ring bus, and the two ends of each internal longitudinal metal wiring in each branch grid link are respectively connected to the two external transverse metal wirings of its ring bus.

[0014] Furthermore, the width of the external transverse metal wiring is greater than the width of the internal transverse metal wiring; the width of the external longitudinal metal wiring is greater than the width of the internal longitudinal metal wiring.

[0015] In the present invention, a driving method of a ring-loop grid driving link is adopted, so that the wiring channels are all arranged in parallel, greatly reducing the impedance of the driving link, and the path resistance can be reduced to the order of Ω. In the case of the same load capacitance of 1 nF, the signal establishment time can be reduced to the order of ns, thus greatly shortening the signal establishment time, improving the line frequency driving of the large-area array type CCD, increasing the line frequency of the existing driving ability to above MHz, and meeting the special scenario of the high line frequency application of the large-area array type CCD. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings described herein are used to provide a further understanding of the present application, and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application, and do not constitute an improper limitation of the present application. In the drawings:

[0017] Figure 1 FIG. 9 is a schematic structural diagram of a polysilicon driving gate and metal wiring of an existing CCD structure.

[0018] Figure 2 FIG. 13 is a schematic structural diagram of a polysilicon driving gate and metal wiring of another existing CCD structure.

[0019] Figure 3 FIG. 17 is a schematic structural diagram of an embodiment of a CCD structure with a ring-loop grid driving link according to the present invention.

[0020] Figure 4 FIG. Figure 3 24 is a schematic cross-sectional view taken along the line A-A' in FIG.

[0021] Figure 5 FIG. 27 is a schematic diagram of the metal wiring of the grid driving link.

[0022] Figure 6 FIG. 31 is a schematic diagram of the transmission channel of the grid driving link.

[0023] The reference numerals in the specification drawings are as follows:

[0024] Silicon epitaxial substrate - 100; insulating dielectric layer - 110; active region - 120; region directly above the active region - 121;

[0025] First grid driving network - 210; first internal horizontal metal wiring - 211; first internal vertical metal wiring - 212; first external horizontal metal wiring - 213; first external vertical metal wiring - 214; first end wiring connection hole - 215; first internal wiring connection hole - 216;

[0026] Second meshed driving network - 220; Second internal horizontal metal wiring - 221; Second internal vertical metal wiring - 222; Second external horizontal metal wiring - 223; Second external vertical metal wiring - 224; Second end wiring connection hole - 225; Second internal wiring connection hole - 226;

[0027] Third meshed driving network - 230; Third internal horizontal metal wiring - 231; Third internal vertical metal wiring - 232; Third external horizontal metal wiring - 233; Third external vertical metal wiring - 234; Third end wiring connection hole - 235; Third internal wiring connection hole - 236;

[0028] First polysilicon driving gate - 310; First driving gate connection hole - 311; Second polysilicon driving gate - 320; Second driving gate connection hole - 321; Third polysilicon driving gate - 330; Third driving gate connection hole - 331;

[0029] First horizontal polysilicon gate - 901; Second horizontal polysilicon gate - 902; Third horizontal polysilicon gate - 903; Metal lead - out wiring - 910; Lead - out wiring connection hole - 911; Vertical metal line - 920; Vertical wiring connection hole - 921. Detailed implementation mode

[0030] The following uses specific specific examples to illustrate the implementation mode of the present invention. The diagrams provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0031] Based on the existing driving wiring technology, there are generally two types of existing driving wiring structures for large - area - array CCDs: The first type is that the wiring structure of the traditional large - area - array CCD uses the method of leading out on one side or both sides of the horizontal polysilicon gate; it includes multiple groups of horizontal polysilicon gates. One end or both ends of each horizontal polysilicon gate in the same group are connected together through a lead - out wiring connection hole 911 to the metal lead - out wiring 910, so as to be led out through the metal lead - out wiring 910. Please refer to Figure 1 , in a wiring structure of a traditional large - area - array CCD of this type, it includes three groups of horizontal polysilicon gates, namely the first horizontal polysilicon gate 901, the second horizontal polysilicon gate 902, and the third horizontal polysilicon gate 903. Each group of horizontal polysilicon gates forms a vertical transfer gate driving phase. Since the length of the polysilicon gate of each phase (i.e., the vertical transfer gate driving phase) is relatively long, its path resistance and capacitance are relatively large. The resistance is about 100 kΩ magnitude, the capacitance is about 1 nF magnitude, and the signal establishment time (edge delay time) is about 10 μs magnitude. Calculated according to the delay time ≤ 10% of the signal frequency, this driving method cannot guarantee the signal driving of the line frequency above 1 kHz, which greatly limits the high - line - frequency application of large - area - array CCDs.

[0032] The wiring structure of the second traditional large area array type CCD adds longitudinal metal lines 920 distributed within a certain period on the basis of the first CCD wiring structure. Please refer to Figure 2 , in the wiring structure of this large area array type CCD, on the basis of the wiring structure in Figure 1 , longitudinal metal lines 920 are added. Between each horizontal polysilicon gate of the same driving gate group, they are respectively connected through multiple periodically arranged longitudinal metal lines 920. Each of the longitudinal metal lines 920 is connected to each horizontal polysilicon gate of the same group through multiple longitudinal wiring connection holes 921. However, the length of each phase of the polysilicon gate is relatively long, with a resistance of about 100 kΩ magnitude and a capacitance of about 1 nF magnitude. Although the longitudinal metal lines 920 distributed within a certain period are in parallel with the transfer gates of multiple polysilicon gates, reducing the impedance accordingly, the equivalent impedance of each phase still reaches a resistance of about 1 kΩ - 10 kΩ magnitude. Calculated according to the equivalent capacitance of 1 nF magnitude, the signal establishment time (edge delay time) is about 100 ns - 1 μs magnitude. Calculated according to the delay time ≤ 10% of the signal frequency, it is impossible to ensure the signal driving of a line frequency of 100 kHz and above, still restricting the high line frequency application of the large area array type CCD.

[0033] Therefore, due to the limitations of the existing technology, the existing driving wiring structure cannot ensure the signal driving of a line frequency of 100 kHz and above, becoming a limiting bottleneck for the high line frequency application of the large area array type CCD.

[0034] Please refer to Figure 3 , Figure 4 and Figure 5 , an embodiment of the CCD structure with a looped grid driving link of the present invention includes a silicon epitaxial substrate 100 and an insulating dielectric layer 110 provided on the silicon epitaxial substrate 100. An active region 120 is provided on the upper part of the silicon epitaxial substrate 100, and a pixel array (not shown in the figure) is formed in the active region 120; the insulating dielectric layer 110 is provided with a driving gate structure in the region 121 directly above the active region, and the driving gate structure includes at least two driving gate groups. Each of the driving gate groups includes multiple parallel polysilicon driving gates; a grid driving link is provided above the driving gate structure, and the grid driving link includes at least two branch grid links. The branch grid links correspond to the driving gate groups one by one, and each polysilicon driving gate in each driving gate group is connected to the corresponding branch grid link through multiple driving gate connection holes. It should be noted that the connection holes in this embodiment (including: end wiring connection holes, internal wiring connection holes, driving gate connection holes) are all metallized connection holes with good electrical conductivity.

[0035] Next, in this embodiment, the driving gate structure includes three driving gate groups as an example for illustration. Of course, in other embodiments, the driving gate structure may also include two driving gate groups, four driving gate groups, or other numbers of driving gate groups. In this embodiment, the three driving gate groups are the first driving gate group, the second driving gate group, and the third driving gate group respectively; among them, the first driving gate group includes a plurality of first polysilicon driving gates 310, the second driving gate group includes a plurality of second polysilicon driving gates 320, and the third driving gate group includes a plurality of third polysilicon driving gates 330. Similarly, the grid-shaped driving link also includes three branch grid links, namely the first branch grid link, the second branch grid link, and the third branch grid link; among them, the first branch grid link corresponds to the first driving gate group, the second branch grid link corresponds to the second driving gate group, and the third branch grid link corresponds to the third driving gate group.

[0036] The branch grid link includes an annular bus arranged on the periphery directly above the driving gate group and a plurality of internal horizontal metal wirings and a plurality of internal vertical metal wirings arranged inside the annular bus. That is, the first branch grid link includes a first annular bus, a plurality of first internal horizontal metal wirings 211, and a plurality of first internal vertical metal wirings 212, the second branch grid link includes a second annular bus, a plurality of second internal horizontal metal wirings 221, and a plurality of second internal vertical metal wirings 222, and the third branch grid link includes a third annular bus, a plurality of third internal horizontal metal wirings 231, and a plurality of third internal vertical metal wirings 232.

[0037] The polysilicon driving gates (including the first polysilicon driving gate 310, the second polysilicon driving gate 320, and the third polysilicon driving gate 330) and the internal horizontal metal wirings (including the first internal horizontal metal wiring 211, the second internal horizontal metal wiring 221, and the third internal horizontal metal wiring 231) are all arranged along the first direction (i.e., Figure 3 the x-axis direction in Figure 3 ); the internal vertical metal wirings (including the first internal vertical metal wiring 212, the second internal vertical metal wiring 222, and the third internal vertical metal wiring 232) are arranged along the second direction perpendicular to the first direction (i.e., Figure 4 the y-axis direction in

[0038] ); that is, the first internal vertical metal wiring 212, the second internal vertical metal wiring 222, and the third internal vertical metal wiring 232 are all arranged along the second direction.

[0038] In this embodiment, the internal horizontal metal wiring is disposed above a polysilicon driving gate corresponding to a driving gate group and is connected to the polysilicon driving gate through a plurality of driving gate connection holes arranged periodically. For example, the first internal horizontal metal wiring 211 is disposed above the first polysilicon driving gate 310 and is connected to the first polysilicon driving gate 310 through a plurality of first driving gate connection holes 311 arranged periodically, so as to realize the parallel connection of the first internal horizontal metal wiring 211 and the first polysilicon driving gate 310. Similarly, the second internal horizontal metal wiring 221 is disposed above the second polysilicon driving gate 320 and is connected to the second polysilicon driving gate 320 through a plurality of second driving gate connection holes 321 arranged periodically to realize parallel connection; the third internal horizontal metal wiring 231 is disposed above the third polysilicon driving gate 330 and is connected to the third polysilicon driving gate 330 through a plurality of third driving gate connection holes 331 arranged periodically to realize parallel connection.

[0039] The ring bus includes two external horizontal metal wirings arranged along the first direction and two external vertical metal wirings arranged along the second direction, and the two external horizontal metal wirings and the two external vertical metal wirings are connected to form a rectangular structure. That is, the first ring bus includes two first external horizontal metal wirings 213 arranged along the first direction and two first external vertical metal wirings 214 arranged along the second direction, the second ring bus includes two second external horizontal metal wirings 223 arranged along the first direction and two second external vertical metal wirings 224 arranged along the second direction, and the third ring bus includes two third external horizontal metal wirings 233 arranged along the first direction and two third external vertical metal wirings 234 arranged along the second direction.

[0040] Both ends of each of the internal horizontal metal wirings and the internal vertical metal wirings are respectively connected to the ring bus through an end wiring connection hole. In this embodiment, both ends of each of the internal horizontal metal wirings in each branch grid link are respectively connected to two external vertical metal wirings of its ring bus, and both ends of each of the internal vertical metal wirings in each branch grid link are respectively connected to two external horizontal metal wirings of its ring bus. That is, each end of each of the first internal horizontal metal wirings 211 is respectively connected to a first external vertical metal wiring 214 through a first end wiring connection hole 215, and each end of each of the first internal vertical metal wirings 212 is respectively connected to a first external horizontal metal wiring 213 through a first end wiring connection hole 215. Each end of each of the second internal horizontal metal wirings 221 is respectively connected to a second external vertical metal wiring 224 through a second end wiring connection hole 225, and each end of each of the second internal vertical metal wirings 222 is respectively connected to a second external horizontal metal wiring 223 through a second end wiring connection hole 225. Each end of each of the third internal horizontal metal wirings 231 is respectively connected to a third external vertical metal wiring 234 through a third end wiring connection hole 235, and each end of each of the third internal vertical metal wirings 232 is respectively connected to a third external horizontal metal wiring 233 through a third end wiring connection hole 235.

[0041] Please refer to Figure 6 , after adopting the structure of the grid-driven link of this embodiment, two first external horizontal metal wirings 213 and two first external vertical metal wirings 214 of the first branch grid link are connected to form a rectangular frame. A plurality of first internal horizontal metal wirings 211 and a plurality of first internal vertical metal wirings 212 are mutually connected inside the frame through first internal wiring connection holes 216, and after being connected to the two first external horizontal metal wirings 213 and the two first external vertical metal wirings 214 through first end wiring connection holes 215, their equivalent circuit forms a grid-shaped first grid-driven network 210. Since the wiring channels of the first polysilicon drive gate 310 are all parallel, its path resistance is greatly reduced, and the path resistance of the first polysilicon drive gate 310 can be reduced to the Ω level.

[0042] Similarly, after the multiple second internal horizontal metal wirings 221, multiple second internal vertical metal wirings 222, two second external horizontal metal wirings 223, and two second external vertical metal wirings 224 of the second branch grid link are connected, their equivalent circuit forms a grid-shaped second grid drive network 220. After the multiple third internal horizontal metal wirings 231, multiple third internal vertical metal wirings 232, two third external horizontal metal wirings 233, and two third external vertical metal wirings 234 of the third branch grid link are connected, their equivalent circuit forms a grid-shaped third grid drive network 230. This enables the path resistance of both the second polysilicon drive gate 320 and the third polysilicon drive gate 330 to be reduced to the Ω level.

[0043] The width of the external horizontal metal wiring (i.e., the first external horizontal metal wiring 213, the second external horizontal metal wiring 223, and the third external horizontal metal wiring 233) is greater than the width of the internal horizontal metal wiring (i.e., the first internal horizontal metal wiring 211, the second internal horizontal metal wiring 221, and the third internal horizontal metal wiring 231). The width of the external vertical metal wiring (i.e., the first external vertical metal wiring 214, the second external vertical metal wiring 224, and the third external vertical metal wiring 234) is greater than the width of the internal vertical metal wiring (i.e., the first internal vertical metal wiring 212, the second internal vertical metal wiring 222, and the third internal vertical metal wiring 232).

[0044] In this embodiment, the width of the external horizontal metal wiring is equal to the width of the external vertical metal wiring, and the width of the internal horizontal metal wiring is equal to the width of the internal vertical metal wiring. That is, the widths of the first external horizontal metal wiring 213, the second external horizontal metal wiring 223, the third external horizontal metal wiring 233, the first external vertical metal wiring 214, the second external vertical metal wiring 224, and the third external vertical metal wiring 234 are all equal. The widths of the first internal horizontal metal wiring 211, the second internal horizontal metal wiring 221, the third internal horizontal metal wiring 231, the first internal vertical metal wiring 212, the second internal vertical metal wiring 222, and the third internal vertical metal wiring 232 are all equal.

[0045] At the overlapping positions of each internal horizontal metal wiring and each internal vertical metal wiring in the branch grid link, they are respectively connected through an internal wiring connection hole. That is, at the overlapping positions of each first internal horizontal metal wiring 211 and each first internal vertical metal wiring 212, they are respectively connected through a first internal wiring connection hole 216; at the overlapping positions of each second internal horizontal metal wiring 221 and each second internal vertical metal wiring 222, they are respectively connected through a second internal wiring connection hole 226; at the overlapping positions of each third internal horizontal metal wiring 231 and each third internal vertical metal wiring 232, they are respectively connected through a third internal wiring connection hole 236.

[0046] Each of the internal horizontal metal wirings is arranged in the junction area between two adjacent rows of pixels in the pixel array, so that each internal horizontal metal wiring covers the isolation position between two adjacent rows of pixels and covers as little as possible the photosensitive area of the pixels. Each of the internal vertical metal wirings is arranged in the junction area between two adjacent columns of pixels in the pixel array, so that each internal vertical metal wiring covers the isolation position between two adjacent columns of pixels and covers as little as possible the photosensitive area of the pixels.

[0047] In addition, by adjusting the sizes of the internal horizontal metal wiring and the internal vertical metal wiring of the three driving gate groups, the proportion of each pixel in the pixel array blocked by the grid driving link can be made the same.

[0048] The internal horizontal metal wirings of each of the branch grid links are arranged at intervals according to a predetermined first period, and the first period is greater than or equal to twice the pixel horizontal pitch; the internal vertical metal wirings of each of the branch grid links are arranged at intervals according to a predetermined second period, and the second period is greater than or equal to twice the pixel vertical pitch. Please continue to refer to Figure 5 In this embodiment, the internal horizontal metal wirings are arranged at periodic intervals in the order of the first internal horizontal metal wiring 211, the second internal horizontal metal wiring 221, and the third internal horizontal metal wiring 231, and the center interval d1 between two adjacent internal horizontal metal wirings is the first period; the internal vertical metal wirings are arranged at periodic intervals in the order of the first vertical horizontal metal wiring 212, the second internal vertical metal wiring 222, and the third internal vertical metal wiring 232, and the center interval d2 between two adjacent internal vertical metal wirings is the second period.

[0049] In this embodiment, to solve the problems of high driving link impedance, long signal establishment time, and inability to drive at high line frequencies, a driving method using a ring-loop grid driving link is proposed, adopting a wiring method with an external ring bus and an internal criss-cross wiring structure, so that the wiring channels are all arranged in parallel, greatly reducing the driving link impedance, and the path resistance can be reduced to the order of Ω. In the case of the same load capacitance of 1 nF, the signal establishment time can be reduced to the order of ns, thus greatly shortening the signal establishment time, improving the line frequency driving of large-area array type CCDs, and increasing the existing driving ability from Figure 2 the line frequency of 10 kHz to 100 kHz in the middle structure to above MHz, meeting the special scenario of high line frequency applications of large-area array type CCDs.

[0050] The above embodiments only express the preferred implementation modes of the present invention, and the description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention patent shall be subject to the appended claims.

Claims

1. A CCD structure with a ring-loop grid-driven link, characterized in that: It includes a silicon epitaxial substrate and an insulating dielectric layer disposed on the silicon epitaxial substrate. An active region is provided on the upper part of the silicon epitaxial substrate, and a pixel array is formed in the active region. The insulating dielectric layer is provided with a driving gate structure in the region directly above the active region. The driving gate structure includes at least two driving gate groups, and each driving gate group includes multiple polysilicon driving gates arranged in parallel. A grid-shaped driving link is provided above the driving gate structure. The grid-shaped driving link includes at least two branch grid links, and the branch grid links correspond to the driving gate groups one by one. Each polysilicon driving gate in each driving gate group is connected to the corresponding branch grid link through multiple driving gate connection holes.

2. The CCD structure with a ring-loop grid-driven link according to claim 1, characterized in that: The branch grid link includes an annular bus disposed on the periphery directly above the driving gate group, and internal horizontal metal wirings and internal vertical metal wirings disposed inside the annular bus. Both ends of each internal horizontal metal wiring and each internal vertical metal wiring are respectively connected to the annular bus through an end wiring connection hole.

3. The CCD structure with a ring-loop grid-driven link as described in claim 2, wherein: By adjusting the dimensions of the internal horizontal metal wirings and internal vertical metal wirings of each driving gate group, the proportion of each pixel in the pixel array blocked by the grid-shaped driving link is the same.

4. The CCD structure with a ring-loop grid-driven link as described in claim 2, characterized in that: At the overlapping positions of the respective internal horizontal metal wirings and the respective internal vertical metal wirings in the branch grid link, they are respectively connected through an internal wiring connection hole.

5. The CCD structure with a looped circuit grid-driven link according to claim 2, characterized in that: Each internal horizontal metal wiring is disposed in the boundary region between two adjacent rows of pixels in the pixel array, and each internal vertical metal wiring is disposed in the boundary region between two adjacent columns of pixels in the pixel array.

6. The CCD structure with a ring-loop grid-driven link as described in claim 2, wherein: The internal horizontal metal wirings of each branch grid link are arranged intermittently at a predetermined first period, and the first period is greater than or equal to twice the horizontal pixel pitch. The internal vertical metal wirings of each branch grid link are arranged intermittently at a predetermined second period, and the second period is greater than or equal to twice the vertical pixel pitch.

7. The CCD structure with a looped circuit grid-driven link according to claim 2, characterized in that: The polysilicon driving gates and the internal horizontal metal wirings are both arranged in a first direction, and the internal vertical metal wirings are arranged in a second direction perpendicular to the first direction.

8. The CCD structure with an annular loop grid-driven link as described in claim 7, characterized in that: The internal horizontal metal wiring is disposed above a polysilicon driving gate of the corresponding driving gate group and is connected to the polysilicon driving gate through multiple periodically arranged driving gate connection holes.

9. The CCD structure with an annular loop grid-driven link according to claim 7, characterized in that: The annular bus includes two external horizontal metal wirings arranged in the first direction and two external vertical metal wirings arranged in the second direction. The two external horizontal metal wirings and the two external vertical metal wirings are connected to form a rectangular structure. Both ends of the respective internal horizontal metal wirings in each branch grid link are respectively connected to the two external vertical metal wirings of its annular bus, and both ends of the respective internal vertical metal wirings in each branch grid link are respectively connected to the two external horizontal metal wirings of its annular bus.

10. The CCD structure with a ring-loop grid-driven link as described in claim 9, wherein: The width of the external horizontal metal wiring is greater than the width of the internal horizontal metal wiring; the width of the external vertical metal wiring is greater than the width of the internal vertical metal wiring.

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