Preparation method of mixed passivation back contact battery

Abstract

The invention discloses a preparation method of a hybrid passivation back contact battery, and the preparation method comprises the following steps: providing a silicon wafer which comprises a first surface and a second surface which are oppositely arranged, and the second surface comprises a first region and a second region; a tunneling oxide layer and a doped polycrystalline silicon layer are sequentially deposited on the second surface, the doped polycrystalline silicon layer is annealed, a PSG mask is formed on the surface of the doped polycrystalline silicon layer, the annealing temperature ranges from 800 DEG C to 900 DEG C, and the annealing time ranges from 1800 s to 2200 s; and carrying out graphical film opening on the PSG mask on the first region, and removing the tunneling oxide layer and the doped polycrystalline silicon layer on the first region. By optimizing the annealing process of the doped polycrystalline silicon layer, prolonging the annealing time and reducing the annealing temperature, the crystallization rate of polycrystalline silicon can be reduced, the photoelectric conversion efficiency of the cell is remarkably improved, and meanwhile, the electrical properties such as contact resistivity and the like are also remarkably improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of solar energy, and particularly relates to a preparation method of a hybrid passivated back contact (HTBC) cell. Background Art

[0002] Silicon heterojunction solar cells have reached record efficiencies, especially in solar cells with back contacts. Nevertheless, the passivated contacts of amorphous silicon thin films still have parasitic absorption and series resistance losses.

[0003] In TOPCon cells and HTBC (hybrid passivated back contact) cells, the structural properties of the doped polysilicon layer also have a great influence on the efficiency of the cells. At present, the main research focuses on the phosphorus doping concentration and the tunneling oxide layer. However, the bandgap of the doped polysilicon layer is closely related to its crystallization rate. The higher the crystallization rate, the smaller the bandgap of the polysilicon, which will lead to the accumulation of holes, increase the recombination rate, and cause an obvious loss of cell efficiency.

[0004] Therefore, in view of the above technical problems, it is necessary to provide a preparation method of a hybrid passivated back contact (HTBC) cell. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a preparation method of a hybrid passivated back contact cell to improve the photoelectric conversion efficiency.

[0006] In order to achieve the above purpose, the technical solution provided by an embodiment of the present invention is as follows:

[0007] A preparation method of a hybrid passivated back contact cell, the preparation method comprising the following steps:

[0008] Provide a silicon wafer, including a first surface and a second surface arranged opposite to each other, and the second surface includes a first region and a second region;

[0009] Deposit a tunneling oxide layer and a doped polysilicon layer on the second surface in sequence, and anneal the doped polysilicon layer to form a PSG mask on the surface of the doped polysilicon layer, the annealing temperature is 800°C to 900°C, and the annealing time is 1800s to 2200s;

[0010] Perform patterning and opening of the PSG mask on the first region, and remove the tunneling oxide layer and the doped polysilicon layer on the first region;

[0011] Remove the PSG mask on the doped polysilicon layer;

[0012] Deposit a first passivation layer and all or part of the doped first microcrystalline silicon layer on the second surface of the silicon wafer in sequence;

[0013] Deposit a second passivation layer and all or part of a doped second microcrystalline silicon layer in sequence on the first surface of the silicon wafer;

[0014] Remove the first passivation layer and the first microcrystalline silicon layer on part of the second region to form an electrode window;

[0015] Fabricate a first electrode structure on the first microcrystalline silicon layer and fabricate a second electrode structure in the electrode window on the doped polysilicon layer.

[0016] In one embodiment, the annealing step for the doped polysilicon layer includes:

[0017] Place the silicon wafer deposited with the tunneling oxide layer and the doped polysilicon layer on a quartz boat and transfer it to an annealing furnace;

[0018] Raise the temperature in the annealing furnace from the standby temperature To to the annealing temperature Tmax. The heating time is t1, and the heating rate gradually decreases;

[0019] Maintain the annealing temperature Tmax in the annealing furnace unchanged, and the maintaining time is t2;

[0020] Lower the temperature in the annealing furnace from the annealing temperature Tmax to the standby temperature To. The cooling time is t3, and the cooling rate gradually increases;

[0021] Wherein, the annealing temperature Tmax is 800°C to 900°C, the standby temperature To is 550°C to 650°C, the heating time t1 is 600 s to 800 s, the maintaining time t2 is 400 s to 600 s, the cooling time t3 is 600 s to 800 s, the total annealing time t1 + t2 + t3 is 1800 s to 2200 s, the average heating rate is 0.25°C / s to 0.5°C / s, and the average cooling rate is 0.25°C / s to 0.5°C / s.

[0022] In one embodiment, in the annealing step for the doped polysilicon layer:

[0023] The annealing temperature Tmax is 800°C to 850°C, and the total annealing time t1 + t2 + t3 is 2000 s to 2200 s; or,

[0024] The annealing temperature Tmax is 850°C to 900°C, and the total annealing time t1 + t2 + t3 is 1800 s to 2000 s.

[0025] In one embodiment, the annealing step for the doped polysilicon layer further includes:

[0026] Before heating, evacuate and clean the annealing furnace, control the air pressure in the annealing furnace to be 50 mbar to 200 mbar, and introduce nitrogen with a flow rate of 1000 scccm to 2000 scccm for a duration of 200 s to 600 s; and / or,

[0027] Before heating, control the air pressure in the annealing furnace to 900 mbar to 1100 mbar, and check for leaks in the annealing furnace; and / or,

[0028] During the annealing process, the air pressure in the annealing furnace is 900 mbar to 1100 mbar.

[0029] In one embodiment, the tunneling oxide layer is deposited by PECVD process; and / or,

[0030] The doped polysilicon layer is deposited by PECVD process and doped by in-situ doping process; and / or,

[0031] The tunneling oxide layer is any one or a combination of silicon oxide layer and silicon oxynitride layer; and / or,

[0032] The thickness of the tunneling oxide layer is 1 nm to 2 nm; and / or,

[0033] The thickness of the doped polysilicon layer is 120 nm to 200 nm; and / or,

[0034] The doped polysilicon layer is N-type doped with a doping concentration of 1E21 cm -3 ~1E22 cm -3 .

[0035] In one embodiment, the deposition of the first microcrystalline silicon layer includes:

[0036] Deposit a first inner microcrystalline silicon layer on the first passivation layer, and the first inner microcrystalline silicon layer is an intrinsic microcrystalline silicon layer;

[0037] Deposit a first middle microcrystalline silicon layer on the first inner microcrystalline silicon layer, and the first middle microcrystalline silicon layer is P-type doped;

[0038] Deposit a first outer microcrystalline silicon layer on the first middle microcrystalline silicon layer, and the first middle microcrystalline silicon layer is P-type doped.

[0039] In one embodiment, the deposition of the first microcrystalline silicon layer includes:

[0040] Using PECVD process, introducing silane, hydrogen and carbon dioxide, and the flow ratio of silane to hydrogen is (6 - 8):(2500 - 2900), deposit a first inner microcrystalline silicon layer on the first passivation layer;

[0041] Using PECVD process, introducing borane, silane, hydrogen and carbon dioxide, and the flow ratio of borane, silane to hydrogen is (3 - 3.8):(6 - 8):(2500 - 2900), deposit a boron-doped first middle microcrystalline silicon layer on the first inner microcrystalline silicon layer;

[0042] Using the PECVD process, borane, silane, hydrogen, and carbon dioxide are introduced. The flow rate ratio of borane, silane, and hydrogen is (6.5 - 7.5):(6 - 8):(2500 - 2900), and a boron-doped first outer microcrystalline silicon layer is deposited on the first microcrystalline silicon layer.

[0043] In one embodiment, during the deposition of the first microcrystalline silicon layer:

[0044] The pressure in the PECVD chamber is 3 Torr - 5 Torr; and / or,

[0045] The deposition power is 4000 W - 7000 W; and / or,

[0046] The deposition temperature of the first inner microcrystalline silicon layer is 158 °C - 162 °C, the deposition time is 18 s - 22 s, and the thickness is 1 nm - 3 nm; and / or,

[0047] The deposition temperature of the first middle microcrystalline silicon layer is 158 °C - 162 °C, the deposition time is 155 s - 165 s, the thickness is 20 nm - 24 nm, and the boron doping concentration is 1E17 cm -3 ~1E19 cm -3 ; and / or,

[0048] The deposition temperature of the first outer microcrystalline silicon layer is 170 °C - 175 °C, the deposition time is 65 s - 75 s, the thickness is 5 nm - 7 nm, and the boron doping concentration is 1E19 cm -3 ~1E20 cm -3 .

[0049] In one embodiment, the deposition of the second microcrystalline silicon layer includes:

[0050] Depositing a seed layer on the second passivation layer;

[0051] Depositing a second outer microcrystalline silicon layer on the seed layer;

[0052] Among them, both the seed layer and the second outer microcrystalline silicon layer are hydrogen-containing doped microcrystalline silicon layers, and the hydrogen content in the seed layer is greater than that in the second outer microcrystalline silicon layer.

[0053] In one embodiment, the deposition of the second microcrystalline silicon layer includes:

[0054] Using the PECVD process, phosphine, silane, hydrogen, and carbon dioxide are introduced. The flow rate of silane and hydrogen is 1:(700 - 900), and a seed layer is deposited on the second passivation layer;

[0055] Using the PECVD process, phosphine, silane, hydrogen, and carbon dioxide are introduced. The flow rate of silane and hydrogen is 1:(350 - 380), and a second outer microcrystalline silicon layer is deposited on the seed layer.

[0056] In one embodiment, during the deposition of the second microcrystalline silicon layer:

[0057] The pressure in the PECVD chamber is 3 Torr to 5 Torr; and / or,

[0058] The deposition power is 3000 W ～ to 5000 W; and / or,

[0059] The deposition temperature of the seed layer is 190°C to 205°C, the deposition time is 10 s to 25 s, and the thickness is 2 nm to 5 nm; and / or,

[0060] The deposition temperature of the second outer microcrystalline silicon layer is 190°C to 205°C, the deposition time is 260 s to 300 s, and the thickness is 27 nm to 35 nm.

[0061] In one embodiment, the deposition of the first passivation layer includes:

[0062] Using the PECVD process, silane and hydrogen are introduced. The silane flow rate is 500 sccm to 700 sccm, the hydrogen flow rate is 800 sccm to 1000 sccm. An amorphous silicon layer is deposited on the first surface of the silicon wafer. The deposition temperature is 200°C to 210°C, the deposition time is 50 s to 65 s, the deposition thickness is 5 nm to 7 nm, the pressure in the PECVD chamber is 0.5 Torr to 0.6 Torr, and the deposition power is 300 W to 500 W;

[0063] and / or,

[0064] The deposition of the second passivation layer includes:

[0065] Using the PECVD process, silane and hydrogen are introduced. The silane flow rate is 500 sccm to 700 sccm, the hydrogen flow rate is 800 sccm to 1000 sccm. An amorphous silicon layer is deposited on the second surface of the silicon wafer. The deposition temperature is 190°C to 205°C, the deposition time is 80 s to 100 s, the deposition thickness is 4.5 nm to 6 nm, the pressure in the PECVD chamber is 0.5 Torr to 0.6 Torr, and the deposition power is 150 W to 300 W.

[0066] The present invention has the following beneficial effects:

[0067] By optimizing the annealing process of the doped polycrystalline silicon layer, increasing the annealing time and reducing the annealing temperature, the present invention can reduce the crystallization rate of polycrystalline silicon, significantly improve the photoelectric conversion efficiency of the battery, and at the same time, the electrical properties such as contact resistivity are also significantly improved. Description of the Drawings

[0068] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings described below are only some embodiments recorded in the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0069] Figure 1 It is a schematic structural diagram of an HTBC battery in a specific embodiment of the present invention;

[0070] Figure 2 It is a schematic structural diagram of a heterostructure on the first region of the second surface of an HTBC battery in a specific embodiment of the present invention;

[0071] Figure 3 It is a schematic structural diagram of a second passivation structure on the first surface of an HTBC battery in a specific embodiment of the present invention;

[0072] Figures 4a to 4j It is a process flow chart for manufacturing an HTBC battery in a specific embodiment of the present invention;

[0073] Figure 5 It is a time - temperature curve diagram in the annealing process of the prior art;

[0074] Figure 6 It is a time - temperature curve diagram in the annealing process of the present invention. Specific Embodiments

[0075] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0076] In the present invention, unless otherwise clearly specified and limited, the first feature being "on" or "under" the second feature may be that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on" the second feature may be that the first feature is directly above or obliquely above the second feature, or merely indicates that the first feature has a higher horizontal height than the second feature. The first feature being "under", "below" and "beneath" the second feature may be that the first feature is directly below or obliquely below the second feature, or merely indicates that the first feature has a lower horizontal height than the second feature.

[0077] The present invention also discloses a preparation method of a hybrid passivated back contact battery, characterized in that the preparation method comprises the following steps:

[0078] Provide a silicon wafer, including a first surface and a second surface arranged opposite to each other, and the second surface includes a first region and a second region;

[0079] Deposit a tunneling oxide layer and a doped polysilicon layer on the second surface in sequence, and anneal the doped polysilicon layer to form a PSG mask on the surface of the doped polysilicon layer. The annealing temperature is 800°C to 900°C, and the annealing time is 1800s to 2200s;

[0080] Perform patterning and opening of the PSG mask on the first region, and remove the tunneling oxide layer and the doped polysilicon layer on the first region;

[0081] Remove the PSG mask on the doped polysilicon layer;

[0082] Deposit a first passivation layer and all or part of a doped first microcrystalline silicon layer on the second surface of the silicon wafer in sequence;

[0083] Deposit a second passivation layer and all or part of a doped second microcrystalline silicon layer on the first surface of the silicon wafer in sequence;

[0084] Remove part of the first passivation layer and the first microcrystalline silicon layer on the second region to form an electrode window;

[0085] Prepare a first electrode structure on the first microcrystalline silicon layer, and prepare a second electrode structure in the electrode window on the doped polysilicon layer.

[0086] The present invention will be further described below in conjunction with specific embodiments.

[0087] Refer Figure 1 As shown, the HTBC battery in the present invention includes:

[0088] A silicon wafer 10, the silicon wafer is a doped silicon wafer, including a first surface S1 and a second surface arranged opposite to each other, the second surface includes a first region S21 and a second region S22, and the area of the first region S21 is larger than the area of the second region S22;

[0089] A heterostructure, including at least a first passivation layer 21 stacked on the first region S21 and at least part of a doped first microcrystalline silicon layer 22, and the doping type of the first microcrystalline silicon layer 22 is opposite to the doping type of the silicon wafer 10;

[0090] A first electrode structure, located on the first microcrystalline silicon layer 22 in the heterostructure;

[0091] The first passivation structure includes a tunneling oxide layer 31 and a doped polysilicon layer 32 stacked on the second region S22, and the doping type of the doped polysilicon layer 32 is the same as that of the silicon wafer 10;

[0092] The second electrode structure is located on the doped polysilicon layer 32 in the first passivation structure, and the first electrode structure and the second electrode structure are electrically isolated by an isolation groove 70;

[0093] The second passivation structure includes at least a second passivation layer 41 stacked on the first surface S1 of the silicon wafer and at least partially doped second microcrystalline silicon layer 42, and the doping type of the second microcrystalline silicon layer is opposite to that of the first microcrystalline silicon layer.

[0094] Exemplarily, in this embodiment, the silicon wafer 10 is taken as an example of an N-type silicon wafer (i.e., N-type doping) for illustration. The doping type of the first microcrystalline silicon layer 22 is opposite to that of the silicon wafer 10, which is P-type doping (such as boron doping, etc.), and the doping type of the doped polysilicon layer 32 is the same as that of the silicon wafer 10, which is N-type doping (such as phosphorus doping, etc.).

[0095] In this embodiment, the first region S21 is a back emitter (P-Emitter), and the area of the first region S21 is 70% - 95% of the area of the second surface. Preferably, the area of the first region S21 is 80% - 85% of the area of the second surface.

[0096] Further, in the heterostructure of this embodiment, the first passivation layer 21 is an intrinsic hydrogenated amorphous silicon layer with a thickness of 4.5 nm - 6 nm; the first microcrystalline silicon layer 22 is partially P-type doped with a thickness of 25 nm - 40 nm and an overall crystallization rate of 62% - 69%.

[0097] Combined Figure 2 As shown, the first microcrystalline silicon layer 22 in this embodiment includes a first inner microcrystalline silicon layer 221, a first middle microcrystalline silicon layer 222, and a first outer microcrystalline silicon layer 223 stacked in sequence on the first passivation layer. The first inner microcrystalline silicon layer 221 is an intrinsic microcrystalline silicon layer, and the first middle microcrystalline silicon layer 222 and the first outer microcrystalline silicon layer 223 are P-type doped microcrystalline silicon layers. Preferably:

[0098] The thickness of the first inner microcrystalline silicon layer 221 is 1 nm - 5 nm;

[0099] The thickness of the first middle microcrystalline silicon layer 222 is 20 nm - 28 nm, and the doping concentration is 1E17 cm -3 ~1E19 cm -3 ;

[0100] The thickness of the first outer microcrystalline silicon layer 223 is 4 nm - 7 nm, and the doping concentration is 1E19 cm -3 ~1E20 cm -3。

[0101] In this embodiment, the second region S22 is a back surface passivation region (n-BSF). In the first passivation structure, the tunneling oxide layer 31 is any one or a combination of a silicon oxide layer (SiOx) and a silicon oxynitride layer (SiNxOy), with a thickness of 1 nm to 2 nm. The doped polysilicon layer 32 is N-type doped, with a thickness of 120 nm to 200 nm and a doping concentration of 1E21 cm -3 ~1E22 cm -3 。

[0102] Preferably, in this embodiment, the first passivation layer 21 and the first microcrystalline silicon layer 22 are stacked on all of the first region S21 and on the first passivation structure of a part of the second region S22. An electrode window that is not covered by the first passivation layer 21 and the first microcrystalline silicon layer 22 is formed on the doped polysilicon layer 32.

[0103] In addition, the first electrode structure in this embodiment includes a first TCO layer 51 and a first electrode 61. The first TCO layer is at least located on the first microcrystalline silicon layer 22 of the first region S21. The first electrode is in electrical contact with the first TCO layer. The second electrode structure includes a second TCO layer 52 and a second electrode 62. The second TCO layer 52 is at least located in the electrode window on the second region S22. The second electrode 62 is in electrical contact with the second TCO layer 52. Among them, the first TCO layer 51 and the second TCO layer 52 are electrically isolated by an isolation groove 70.

[0104] Specifically, the TCO (transparent conductive oxide) layer can be one or more of ITO, AZO, IWO, etc. The first electrode 61 and the second electrode 62 are metal grid electrodes, and their materials can be Ag or an Ag / Cu alloy.

[0105] The isolation groove 70 in this embodiment is formed on the second region S22. By providing the isolation groove, the first TCO layer 51 and the second TCO layer 52 can be isolated, avoiding a short circuit between the two electrodes. The depth of the isolation groove is greater than or equal to the thickness of the TCO layer, and the width is 20 μm to 100 μm. In other embodiments, the isolation groove 70 can also be formed on the first region S21, or partially formed on the first region S21 and partially formed on the second region S22, and their isolation effects are the same, so details will not be elaborated here.

[0106] Furthermore, an insulating layer (not shown) is formed in all or part of the region in the isolation groove 70. By providing the insulating layer, the isolation effect can be further improved. In this embodiment, the isolation groove 70 extends to the surface of the first microcrystalline silicon layer 22, and an extremely thin (about 1 nm thick) natural oxide layer (i.e., a silicon oxide layer) is formed on the bottom wall and side walls of the isolation groove.

[0107] In this embodiment, the first surface S1 is a front surface field (FSF), and the second passivation structure thereon includes a second passivation layer 41 stacked on the first surface S1 and a partially doped second microcrystalline silicon layer 42.

[0108] In this embodiment, the second passivation layer 41 is an intrinsic hydrogenated amorphous silicon layer with a thickness of 5 nm to 7 nm.

[0109] Furthermore, in this embodiment, the second microcrystalline silicon layer 42 is N-type doped, with a thickness of 29 nm to 40 nm and an overall crystallization rate of 70% to 78%.

[0110] Combined Figure 3 As shown, the second microcrystalline silicon layer 42 in this embodiment includes a seed layer 421 and a second outer microcrystalline silicon layer 422 stacked in sequence on the second passivation layer 41. Both the seed layer 421 and the second outer microcrystalline silicon layer 422 are doped microcrystalline silicon layers containing hydrogen (H), and the hydrogen content in the seed layer 421 is greater than that in the second outer microcrystalline silicon layer. Preferably:

[0111] The thickness of the seed layer 421 is 2 nm to 5 nm;

[0112] The thickness of the second outer microcrystalline silicon layer 422 is 27 nm to 35 nm, and the doping concentration is 1E17 cm -3 ~1E19 cm -3 .

[0113] Furthermore, an antireflection layer 43 is also deposited on the second microcrystalline silicon layer 42. The antireflection layer 43 includes one or a combination of a TCO layer, a SiNx layer, a SiNxOy layer, etc., and is preferably a SiNx layer.

[0114] Exemplarily, the first surface S1 and the first region S21 in this embodiment are pyramid-structured textured surfaces, and the light trapping effect is improved through the pyramid textured surface structure. The second region S22 is a polished surface. In other embodiments, the first surface S1 and the first region S21 can also be polished surfaces, and the second region S22 can also be a pyramid textured surface structure, which will not be elaborated here one by one.

[0115] Both the front and back surfaces of the HTBC battery of the present invention adopt a passivation structure to reduce the surface recombination rate. The first region and the second region on the back surface respectively adopt the passivation structures in HJT batteries and TOPCon batteries, with good passivation effects and the ability to improve the photoelectric conversion efficiency.

[0116] Refer Figures 4a to 4j As shown, a method for manufacturing an HTBC battery in a specific embodiment of the present invention includes the following steps:

[0117] 1. Refer Figure 4aAs shown, a silicon wafer 10 is provided. The silicon wafer is an N-type silicon wafer, including a first surface S1 and a second surface which are oppositely arranged. The second surface includes a first region S21 and a second region S22, and the area of the first region S21 is larger than the area of the second region S22.

[0118] In this embodiment, the first surface S1 of the silicon wafer is a front surface field (FSF), the first region S21 in the second surface is a back emitter (P-Emitter), the second region S22 is a back surface field passivation region (n-BSF), and the area of the first region S21 is 70% - 95% of the area of the second surface, preferably 80% - 85%.

[0119] Exemplarily, in this embodiment, first in a tank cleaning machine, the front and back surfaces of the silicon wafer are polished with a polishing liquid (such as NaOH solution) to form a smooth surface.

[0120] 2. Refer Figure 4b As shown, a tunneling oxide layer 31 and a doped polysilicon layer 32 are sequentially deposited on the second surface, and the doped polysilicon layer 32 is annealed.

[0121] Exemplarily, the tunneling oxide layer 31 is a silicon dioxide layer with a thickness of 1nm - 2nm, the doped polysilicon layer 32 is a phosphorus-doped amorphous silicon layer with a thickness of 120nm - 200nm, and the doping concentration is 1E21cm -3 ~1E22cm -3 .

[0122] Among them, the preparation of the tunneling oxide layer can adopt processes such as LPCVD (low-pressure chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), ALD (atomic layer deposition), etc.;

[0123] The preparation of the polysilicon layer can adopt processes such as LPCVD (low-pressure chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), PVD (physical vapor deposition), APCVD (atmospheric pressure chemical vapor deposition), etc.;

[0124] The phosphorus doping of the polysilicon layer can be through an in-situ doping process or a non-in-situ doping process. In-situ doping means that the polysilicon layer deposition and the phosphorus doping of the polysilicon layer are completed in the same process step. Non-in-situ doping means that after the polysilicon layer is deposited, phosphorus doping is carried out by a diffusion furnace or an ion implantation method.

[0125] The deposition of the tunneling oxide layer and the polysilicon layer and the doping process of the polysilicon layer are all prior arts and will not be elaborated here. In this embodiment, the PECVD (plasma-enhanced chemical vapor deposition) process is used for the deposition of the tunneling oxide layer and the polysilicon layer, and phosphine is introduced during the deposition process of the polysilicon layer to achieve in-situ doping of the polysilicon layer.

[0126] Thereafter, the doped polysilicon layer is annealed in an annealing furnace. Meanwhile, a first mask 80 can be formed on the surface of the doped polysilicon layer 32, and this mask is a PSG (phosphosilicate glass) mask.

[0127] Refer Figure 5 The figure shows the time-temperature curve in the annealing process of the prior art. The annealing temperature is 1050 °C, the annealing time is 1500 s, and the heating rate and cooling rate are fixed rates. In the annealing process of the prior art, the crystallization rate of polysilicon is high, and a large number of pinholes will appear during the high-temperature rapid annealing process. Carriers will accumulate near the pinholes and tend to directly pass through the silicon dioxide layer rather than through tunneling, greatly increasing the recombination of carriers. The existence of pinholes will reduce the passivation performance.

[0128] Refer Figure 6 The figure shows the time-temperature curve of the annealing process of the present invention. The annealing temperature is 800 °C to 900 °C, and the annealing time is 1800 s to 2200 s. By optimizing the annealing temperature and annealing time, the crystallization rate of the present invention is lower under the low-temperature slow annealing process, the bandgap width of the formed polysilicon layer increases, so that a large number of holes in the polysilicon layer will flow into the single crystal silicon, the hole concentration at the interface decreases, and the electron-hole recombination decreases, thereby improving the electrical performance of the battery.

[0129] In this embodiment, the annealing process of the doped polysilicon layer is specifically as follows:

[0130] 2.1. Place the silicon wafer deposited with the tunneling oxide layer and the doped polysilicon layer on a quartz boat and transfer it to the annealing furnace.

[0131] In addition, introduce nitrogen with a flow rate of 7000 sccm into the annealing furnace. The standby temperature To is 550 °C to 650 °C, and the pressure is maintained at 900 mbar to 1100 mbar.

[0132] Furthermore, evacuate and clean the annealing furnace, control the air pressure in the annealing furnace to 50 mbar to 200 mbar, introduce nitrogen with a flow rate of 1000 scccm to 2000 sccm, and the duration is 200 s to 600 s to ensure that there is no pollution or impurity gas in the annealing furnace.

[0133] 2.2. Heat the temperature in the annealing furnace from the standby temperature To to the annealing temperature Tmax. The heating time is t1, and the heating rate gradually decreases.

[0134] Before heating, control the air pressure in the annealing furnace to 900 mbar to 1100 mbar, and leak-check the annealing furnace to ensure the normal progress of the subsequent process.

[0135] 2.3. Keep the annealing temperature Tmax in the annealing furnace unchanged, and the maintenance time is t2.

[0136] 2.4. Cool the temperature in the annealing furnace from the annealing temperature Tmax to the standby temperature To, with the cooling time being t3 and the cooling rate increasing gradually.

[0137] After cooling, fill with nitrogen to restore pressure and take out the boat to complete the entire annealing process.

[0138] Among them, the annealing temperature Tmax is 800°C to 900°C, the standby temperature To is 550°C to 650°C, the heating time t1 is 600s to 800s, the holding time t2 is 400s to 600s, the cooling time t3 is 600s to 800s, the total annealing time t1 + t2 + t3 is 1800s to 2200s, the average heating rate is 0.25°C / s to 0.5°C / s, and the average cooling rate is 0.25°C / s to 0.5°C / s.

[0139] When the annealing temperature Tmax is 800°C to 850°C, the total annealing time t1 + t2 + t3 is 2000s to 2200s; when the annealing temperature Tmax is 850°C to 900°C, the total annealing time t1 + t2 + t3 is 1800s to 2000s.

[0140] 3. Refer Figure 4c As shown, perform pattern opening of the first mask 80 on the first region S21 and remove the tunneling oxide layer 31 and doped polysilicon layer 32 on the first region S21.

[0141] The pattern opening can be carried out by a laser process to completely remove the tunneling oxide layer 31 and doped polysilicon layer 32 on the first region S21.

[0142] 4. Refer Figure 4d As shown, remove the first mask 80 on the second surface of the silicon wafer.

[0143] In this embodiment, in a chain cleaning machine, place the back side of the silicon wafer after the laser process in a hydrofluoric acid solution to remove the PSG mask on the back side of the silicon wafer.

[0144] Preferably, in this embodiment, in a texturing cleaning machine, treat the first region S21 and the first surface S1 of the second surface of the silicon wafer through an alkali (such as a NaOH solution) texturing process to form a pyramid texture structure, and the pyramid size is 0.5μm to 5μm.

[0145] 5. Refer Figure 4e As shown, through the PECVD (Plasma Enhanced Chemical Vapor Deposition) process, sequentially deposit the first passivation layer 21 and the first microcrystalline silicon layer 22 on the second surface of the silicon wafer, and sequentially deposit the second passivation layer 41 and the second microcrystalline silicon layer 42 on the first surface of the silicon wafer.

[0146] The deposition of each layer is described in detail below.

[0147] 5.1. The deposition process of the first passivation layer 21 is specifically as follows:

[0148] Using the PECVD process, silane and hydrogen are introduced. The silane flow rate is 500 sccm to 700 sccm, and the hydrogen flow rate is 800 sccm to 1000 sccm. An amorphous silicon layer is deposited on the first surface of the silicon wafer. The deposition temperature is 200 °C to 210 °C, the deposition time is 50 s to 65 s, the deposition thickness is 5 nm to 7 nm, the pressure in the PECVD chamber is 0.5 Torr to 0.6 Torr, and the deposition power is 300 W to 500 W.

[0149] 5.2. The deposition process of the first microcrystalline silicon layer 22 is specifically as follows:

[0150] Control the pressure in the PECVD chamber to be 3 Torr to 5 Torr, and the deposition power to be 4000 W to 7000 W.

[0151] 5.21. Deposit the first inner microcrystalline silicon layer on the first passivation layer. The first inner microcrystalline silicon layer is an intrinsic microcrystalline silicon layer.

[0152] Using the PECVD process, silane, hydrogen, and carbon dioxide are introduced. The flow rate ratio of silane to hydrogen is (6 - 8):(2500 - 2900). Deposit the first inner microcrystalline silicon layer on the first passivation layer. The deposition temperature is 158 °C to 162 °C, the deposition time is 18 s to 22 s, and the thickness is 1 nm to 3 nm.

[0153] Exemplarily, the silane flow rate is 60 sccm to 80 sccm, the hydrogen flow rate is 25000 sccm to 29000 sccm, and the carbon dioxide flow rate is 15 sccm to 20 sccm.

[0154] 5.22. Deposit the first middle microcrystalline silicon layer on the first inner microcrystalline silicon layer. The first middle microcrystalline silicon layer is P-type doped.

[0155] Using the PECVD process, borane, silane, hydrogen, and carbon dioxide are introduced. The flow rate ratio of borane, silane, and hydrogen is (3 - 3.8):(6 - 8):(2500 - 2900). Deposit the boron-doped first middle microcrystalline silicon layer on the first inner microcrystalline silicon layer. The deposition temperature is 158 °C to 162 °C, the deposition time is 155 s to 165 s, the thickness is 20 nm to 24 nm, and the boron doping concentration is 1E17 cm -3 ~1E19 cm -3 .

[0156] Exemplarily, the flow rate of borane is 30 sccm to 38 sccm, the flow rate of silane is 60 sccm to 80 sccm, the flow rate of hydrogen is 25000 sccm to 29000 sccm, and the flow rate of carbon dioxide is 15 sccm to 20 sccm.

[0157] 5.23 Deposit a first outer microcrystalline silicon layer on the first inner microcrystalline silicon layer, and the first inner microcrystalline silicon layer is P-type doped.

[0158] Using the PECVD process, introduce borane, silane, hydrogen, and carbon dioxide. The flow rate ratio of borane, silane, and hydrogen is (6.5 - 7.5):(6 - 8):(2500 - 2900). Deposit a boron-doped first outer microcrystalline silicon layer on the first inner microcrystalline silicon layer. The deposition temperature is 170°C to 175°C, the deposition time is 65 s to 75 s, the thickness is 5 nm to 7 nm, and the boron doping concentration is 1E19 cm -3 ~1E20 cm -3 .

[0159] Exemplarily, the flow rate of borane is 65 sccm to 75 sccm, the flow rate of silane is 60 sccm to 80 sccm, the flow rate of hydrogen is 25000 sccm to 29000 sccm, and the flow rate of carbon dioxide is 15 sccm to 20 sccm.

[0160] Through the above deposition process, the overall crystallization rate of the first microcrystalline silicon layer can be controlled to be 62% - 69%.

[0161] 5.3 The deposition process of the second passivation layer 41 is specifically as follows:

[0162] Using the PECVD process, introduce silane and hydrogen. The flow rate of silane is 500 sccm to 700 sccm, the flow rate of hydrogen is 800 sccm to 1000 sccm. Deposit an amorphous silicon layer on the second surface of the silicon wafer. The deposition temperature is 190°C to 205°C, the deposition time is 80 s to 100 s, the deposition thickness is 4.5 nm to 6 nm, the pressure in the PECVD chamber is 0.5 Torr to 0.6 Torr, and the deposition power is 150 W to 300 W.

[0163] 5.4 The deposition process of the second microcrystalline silicon layer 42 is specifically as follows:

[0164] Control the pressure in the PECVD chamber to be 3 Torr to 5 Torr, and the deposition power to be 3000 W to 5000 W.

[0165] 5.41 Deposit a seed layer on the second passivation layer.

[0166] Using the PECVD process, phosphine, silane, hydrogen, and carbon dioxide are introduced. The flow rate ratio of silane to hydrogen is 1:(700 - 900). A seed layer is deposited on the second passivation layer. The deposition temperature is 190°C - 205°C, the deposition time is 10s - 25s, and the thickness is 2nm - 5nm.

[0167] Exemplarily, the phosphine flow rate is 1sccm - 5sccm, the silane flow rate is 25sccm - 35sccm, the hydrogen flow rate is 22000sccm - 28000sccm, and the carbon dioxide flow rate is 10sccm - 20sccm.

[0168] 5.42. Deposit a second outer microcrystalline silicon layer on the seed layer. The second outer microcrystalline silicon layer is a doped microcrystalline silicon layer.

[0169] Using the PECVD process, phosphine, silane, hydrogen, and carbon dioxide are introduced. The flow rate ratio of silane to hydrogen is 1:(350 - 380). A second outer microcrystalline silicon layer is deposited on the seed layer. The deposition temperature is 190°C - 205°C, the deposition time is 260s - 300s, and the thickness is 27nm - 35nm.

[0170] Exemplarily, the phosphine flow rate is 150sccm - 200sccm, the silane flow rate is 40sccm - 50sccm, the hydrogen flow rate is 15000sccm - 17000sccm, and the carbon dioxide flow rate is 50sccm - 60sccm.

[0171] Through the above deposition process, the overall crystallization rate of the second microcrystalline silicon layer can be controlled to 70% - 78%.

[0172] It should be understood that the present invention does not limit the deposition sequence of the first passivation layer 21 and the first microcrystalline silicon layer 22 and the second passivation layer 41 and the second microcrystalline silicon layer 42. It is possible to first deposit the first passivation layer 21 and the first microcrystalline silicon layer 22 on the back surface, and then deposit the second passivation layer 41 and the second microcrystalline silicon layer 42 on the front surface. It is also possible to first deposit the second passivation layer 41 and the second microcrystalline silicon layer 42 on the front surface, and then deposit the first passivation layer 21 and the first microcrystalline silicon layer 22 on the back surface. Or deposit the first passivation layer 21 and the second passivation layer 41 on the front and back surfaces simultaneously, and then deposit the first microcrystalline silicon layer 22 on the back surface and the second microcrystalline silicon layer 42 on the front surface respectively.

[0173] 6. Refer Figure 4f As shown, a low - temperature antireflection layer 43 is continuously deposited on the first surface S1 of the silicon wafer through a tube - type PECVD or PVD device.

[0174] Exemplarily, the antireflection layer 43 in this embodiment is a SiNx layer, and in other embodiments, it can also be a TCO layer, etc.

[0175] 7. ReferFigure 4g As shown, the first passivation layer 21 and the first microcrystalline silicon layer 22 on part of the second region S22 are removed to form an electrode window 23.

[0176] Patterned film opening can be carried out by a laser process, and at least processed to the surface of the doped polysilicon layer 32 to ensure that the doped polysilicon layer 32 below the electrode window 23 is exposed.

[0177] 8. Refer Figure 4h As shown, in a PVD (Physical Vapor Deposition) apparatus, a TCO layer 50 is prepared in the first microcrystalline silicon layer 22 and the electrode window 23.

[0178] 9. Refer Figure 4i As shown, part of the TCO layer on the first region S21 and / or the second region S22 is removed to form an electrically isolated first TCO layer 51 and a second TCO layer 52 in the first microcrystalline silicon layer and the electrode window. The first TCO layer 51 and the second TCO layer 52 are electrically isolated by an isolation groove 70 formed by a laser process.

[0179] 10. Refer Figure 4j As shown, a first electrode 61 in electrical contact with the first TCO layer is prepared on the first TCO layer 51, and a second electrode 62 in electrical contact with the second TCO layer is prepared on the second TCO layer 52.

[0180] Preferably, the metal electrode (the first electrode 61 or the second electrode 62) is prepared by screen printing using a conductive paste. The conductive paste uses a low-temperature silver paste or a silver-copper paste, and the curing temperature is 190°C to 220°C.

[0181] In addition, the antireflection layer in this embodiment includes one or a combination of a TCO layer, a SiNx layer, and a SiNxOy layer. If the antireflection layer uses a TCO layer, the preparation of this layer can be carried out in the same process as the preparation of the back TCO layer; if the antireflection layer uses a SiNx layer or a SiNxOy layer, an additional process is required, but the antireflection effect of the SiNx layer or the SiNxOy layer is better than that of the TCO layer.

[0182] By optimizing parameters such as the annealing temperature and annealing time in the annealing process of the doped polysilicon layer, the present invention can control the crystallization rate of polysilicon to improve the optoelectronic performance and efficiency of the battery.

[0183] In a comparative example and multiple embodiments, the standby temperature To is controlled to be 600°C, and the pressure in the annealing furnace during the annealing process is 1060 mabr. The crystallization rate, efficiency Eff, and contact resistivity under different annealing parameters are shown in the following table:

[0184]

[0185]

[0186] It can be seen that by optimizing the annealing process of the doped polysilicon layer, increasing the annealing time (1800 s to 2200 s) and reducing the annealing temperature (800 °C to 900 °C), the crystallization rate of polysilicon can be reduced, the photoelectric conversion efficiency of the battery can be significantly improved (0.15% to 0.21%), and at the same time, the electrical properties such as contact resistivity are also significantly improved.

[0187] In addition, the contact of the amorphous silicon layer in the prior art will cause parasitic absorption and series resistance loss. The microcrystalline silicon layer can replace the doped amorphous silicon layer in the prior art. Although a sufficiently thin high-crystallinity layer can reduce parasitic absorption, a high crystallization rate does not necessarily mean better conductivity. On the contrary, it will also lead to a relatively high contact resistivity with the transparent conductive oxide layer (TCO), resulting in a loss of photoelectric conversion efficiency. The prior art only emphasizes the crystallinity and ignores the influence of the resulting contact resistivity.

[0188] Through process improvements and in combination with the characteristics of HTBC cells, the present invention replaces the doped amorphous silicon layers on the front and back of the cell with microcrystalline silicon layers, and controls the crystallization rates of the front and back through processes to improve the optoelectronic performance of the cell.

[0189] In a comparative example and multiple embodiments, the pressure in the PECVD chamber was controlled to be 5 Torr, the deposition power was 5000 W, and diborane (B2H6), silane (SiH4), hydrogen (H2), and carbon dioxide (CO2) were introduced to prepare a microcrystalline silicon layer with inner, middle, and outer three-layer structures. The silane flow rate was 70 sccm, the hydrogen flow rate was 27000 sccm, and the CO2 flow rate was 18 sccm.

[0190] Among them, the deposition temperature of the comparative example was 175 °C, the deposition temperatures of the inner and middle microcrystalline silicon layers in each embodiment were 160 °C, the deposition temperature of the outer microcrystalline silicon layer was 173 °C, and the inner microcrystalline silicon layer was not doped with diborane, the deposition time was 18 s to 22 s, the middle microcrystalline silicon layer was introduced with a low diborane flow rate of 30 sccm to 38 sccm, the deposition time was 155 s to 165 s, the outer microcrystalline silicon layer was doped with a high diborane flow rate of 65 sccm to 75 sccm, and the deposition time was 45 s to 52 s.

[0191] The crystallization rates and electrical properties corresponding to different diborane flow rates and deposition thicknesses are shown in the following table:

[0192]

[0193] It can be seen that by reducing the deposition temperature of the intrinsic microcrystalline silicon layer and not doping with borane, the crystallization rate of the intrinsic microcrystalline silicon layer can be increased. The high-borane doping of the extrinsic microcrystalline silicon layer can improve the contact performance with the TCO. When the crystallization rate of the overall microcrystalline silicon layer is controlled at 62% - 69%, the photoelectric conversion efficiency of the battery can be significantly improved (by 0.7% - 0.19%), and at the same time, the dark conductivity of the thin film is also significantly improved.

[0194] In another comparative example and multiple embodiments, the pressure in the PECVD chamber was controlled at 4 Torr, the deposition power was 5000 W, and phosphine (PH3), silane (SiH4), hydrogen (H2), and carbon dioxide (CO2) were introduced to prepare the second microcrystalline silicon layer. Among them, the seed layer was not deposited in the comparative example, and the seed layer was deposited first in each embodiment. In the deposition process of the seed layer, the flow rates of phosphine, silane, and hydrogen were 3 sccm, 30 sccm, and 25000 sccm respectively.

[0195] In the process of depositing the second extrinsic microcrystalline silicon layer, the flow rate ratio of silane to hydrogen was 1:(350 - 380), the flow rate of phosphine was 350 sccm, the deposition temperature was 200 °C, the deposition time was 280 s, and the deposition thickness was 30 nm.

[0196] The crystallization rates and electrical properties corresponding to different flow rate ratios of phosphine, silane, and hydrogen are shown in the following table:

[0197]

[0198] In other embodiments, the flow rate ratio of silane to hydrogen in the seed layer deposition process can be controlled at 1:(700 - 900), and the flow rate ratio of silane to hydrogen in the second extrinsic microcrystalline silicon layer deposition process can be controlled at 1:(350 - 380). By controlling the growth of the seed layer and the high hydrogen dilution ratio of the outer layer, the overall crystallization rate of the second microcrystalline silicon layer can be controlled at 70% - 78%, which can significantly improve the photoelectric conversion efficiency of the battery (by 0.7% - 0.14%). At the same time, the increase in the film crystallinity can reduce the parasitic absorption on the front side, and the current can also be significantly improved.

[0199] From the above technical solutions, it can be seen that the present invention has the following beneficial effects:

[0200] By optimizing the annealing process of the doped polycrystalline silicon layer, increasing the annealing time and reducing the annealing temperature, the present invention can reduce the crystallization rate of the polycrystalline silicon, significantly improve the photoelectric conversion efficiency of the battery, and at the same time, the electrical properties such as the contact resistivity are also significantly improved.

[0201] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above-described exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention. Therefore, in any regard, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be encompassed within the present invention. Any reference signs in the claims should not be construed as limiting the claims involved.

[0202] In addition, it should be understood that although this specification is described according to embodiments, not every embodiment only contains an independent technical solution. This narrative manner of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A preparation method of a hybrid passivated back-contact battery, characterized in that, The preparation method includes the following steps: Provide a silicon wafer, including a first surface and a second surface arranged opposite to each other, and the second surface includes a first region and a second region; Deposit a tunneling oxide layer and a doped polysilicon layer on the second surface in sequence, and anneal the doped polysilicon layer to form a PSG mask on the surface of the doped polysilicon layer. The annealing temperature is 800°C to 900°C, and the annealing time is 1800 s to 2200 s; Perform patterning and opening of the PSG mask on the first region, and remove the tunneling oxide layer and the doped polysilicon layer on the first region; Remove the PSG mask on the doped polysilicon layer; Deposit a first passivation layer and all or part of the doped first microcrystalline silicon layer on the second surface of the silicon wafer in sequence; Deposit a second passivation layer and all or part of the doped second microcrystalline silicon layer on the first surface of the silicon wafer in sequence; Remove part of the first passivation layer and the first microcrystalline silicon layer on the second region to form an electrode window; Fabricate a first electrode structure on the first microcrystalline silicon layer, and fabricate a second electrode structure in the electrode window on the doped polysilicon layer.

2. The preparation method according to claim 1, wherein The annealing step of the doped polysilicon layer includes: Place the silicon wafer deposited with the tunneling oxide layer and the doped polysilicon layer on a quartz boat and transfer it to an annealing furnace; Raise the temperature in the annealing furnace from the standby temperature To to the annealing temperature Tmax. The temperature rising time is t1, and the temperature rising rate gradually decreases; Maintain the annealing temperature Tmax in the annealing furnace unchanged, and the maintaining time is t2; Lower the temperature in the annealing furnace from the annealing temperature Tmax to the standby temperature To. The temperature lowering time is t3, and the temperature lowering rate gradually increases; Wherein, the annealing temperature Tmax is 800°C to 900°C, the standby temperature To is 550°C to 650°C, the temperature rising time t1 is 600 s to 800 s, the maintaining time t2 is 400 s to 600 s, the temperature lowering time t3 is 600 s to 800 s, the total annealing time t1 + t2 + t3 is 1800 s to 2200 s, the average temperature rising rate is 0.25°C / s to 0.5°C / s, and the average temperature lowering rate is 0.25°C / s to 0.5°C / s.

3. The preparation method according to claim 2, characterized in that, In the annealing step of the doped polysilicon layer: The annealing temperature Tmax is 800°C to 850°C, and the total annealing time t1 + t2 + t3 is 2000 s to 2200 s; or, The annealing temperature Tmax is 850°C to 900°C, and the total annealing time t1 + t2 + t3 is 1800 s to 2000 s.

4. The preparation method according to claim 2, characterized in that, The annealing step of the doped polysilicon layer further includes: Before heating, evacuate and clean the annealing furnace, control the air pressure in the annealing furnace to 50 mbar to 200 mbar, introduce nitrogen with a flow rate of 1000 scccm to 2000 scccm, and the duration is 200 s to 600 s; and / or, Before heating, control the air pressure in the annealing furnace to 900 mbar to 1100 mbar and leak-check the annealing furnace; and / or, The air pressure in the annealing furnace during the annealing process is 900 mbar to 1100 mbar.

5. The preparation method according to claim 1, characterized in that, The tunneling oxide layer is deposited by PECVD process; and / or, The doped polysilicon layer is deposited by PECVD process and doped by in-situ doping process; and / or, The tunneling oxide layer is any one or a combination of silicon oxide layer and silicon oxynitride layer; and / or, The thickness of the tunneling oxide layer is 1nm - 2nm; and / or, The thickness of the doped polysilicon layer is 120nm - 200nm; and / or, The doped polysilicon layer is N-type doped with a doping concentration of 1E21 cm -3 ~1E22 cm -3 .

6. The preparation method according to claim 1, wherein The deposition of the first microcrystalline silicon layer includes: Depositing a first inner microcrystalline silicon layer on the first passivation layer, and the first inner microcrystalline silicon layer is an intrinsic microcrystalline silicon layer; Depositing a first middle microcrystalline silicon layer on the first inner microcrystalline silicon layer, and the first middle microcrystalline silicon layer is P-type doped; Depositing a first outer microcrystalline silicon layer on the first middle microcrystalline silicon layer, and the first middle microcrystalline silicon layer is P-type doped.

7. The preparation method according to claim 6, wherein, The deposition of the first microcrystalline silicon layer includes: Using PECVD process, introducing silane, hydrogen and carbon dioxide, and the flow ratio of silane to hydrogen is (6 - 8):(2500 - 2900), and depositing a first inner microcrystalline silicon layer on the first passivation layer; Using PECVD process, introducing borane, silane, hydrogen and carbon dioxide, and the flow ratio of borane, silane to hydrogen is (3 - 3.8):(6 - 8):(2500 - 2900), and depositing a boron-doped first middle microcrystalline silicon layer on the first inner microcrystalline silicon layer; Using PECVD process, introducing borane, silane, hydrogen and carbon dioxide, and the flow ratio of borane, silane to hydrogen is (6.5 - 7.5):(6 - 8):(2500 - 2900), and depositing a boron-doped first outer microcrystalline silicon layer on the first middle microcrystalline silicon layer.

8. The preparation method according to claim 7, characterized in that, During the deposition process of the first microcrystalline silicon layer: The pressure in the PECVD chamber is 3 Torr - 5 Torr; and / or, The deposition power is 4000W - 7000W; and / or, The deposition temperature of the first inner microcrystalline silicon layer is 158℃ - 162℃, the deposition time is 18s - 22s, and the thickness is 1nm - 3nm; and / or, The deposition temperature of the first microcrystalline silicon layer is 158°C to 162°C, the deposition time is 155 s to 165 s, the thickness is 20 nm to 24 nm, and the boron doping concentration is 1E17 cm -3 ~1E19 cm -3 ; and / or, The deposition temperature of the first amorphous microcrystalline silicon layer is 170°C to 175°C, the deposition time is 65 s to 75 s, the thickness is 5 nm to 7 nm, and the boron doping concentration is 1E19 cm -3 ~1E20 cm -3 .

9. The preparation method according to claim 1, wherein, The deposition of the second microcrystalline silicon layer includes: Depositing a seed layer on the second passivation layer; Depositing a second outer microcrystalline silicon layer on the seed layer; Wherein, both the seed layer and the second outer microcrystalline silicon layer are hydrogen-containing doped microcrystalline silicon layers, and the hydrogen content in the seed layer is greater than that in the second outer microcrystalline silicon layer.

10. The preparation method according to claim 9, characterized in that, The deposition of the second microcrystalline silicon layer includes: Using PECVD process, introducing phosphine, silane, hydrogen and carbon dioxide, and the flow rate of silane to hydrogen is 1:(700 - 900), and depositing a seed layer on the second passivation layer; Using PECVD process, introducing phosphine, silane, hydrogen and carbon dioxide, and the flow rate of silane to hydrogen is 1:(350 - 380), and depositing a second outer microcrystalline silicon layer on the seed layer.

11. The preparation method according to claim 10, wherein During the deposition process of the second microcrystalline silicon layer: The pressure in the PECVD chamber is 3 Torr - 5 Torr; and / or, The deposition power is 3000W ～ 5000W; and / or, The deposition temperature of the seed layer is 190℃ - 205℃, the deposition time is 10s - 25s, and the thickness is 2nnm - 5nm; and / or, The deposition temperature of the second outer microcrystalline silicon layer is 190℃ - 205℃, the deposition time is 260s - 300s, and the thickness is 27nm - 35nm.

12. The preparation method according to claim 1, characterized in that, The deposition of the first passivation layer includes: Using the PECVD process, silane and hydrogen are introduced. The silane flow rate is 500 sccm to 700 sccm, and the hydrogen flow rate is 800 sccm to 1000 sccm. An amorphous silicon layer is deposited on the first surface of the silicon wafer. The deposition temperature is 200 °C to 210 °C, the deposition time is 50 s to 65 s, the deposition thickness is 5 nm to 7 nm, the pressure in the PECVD chamber is 0.5 Torr to 0.6 Torr, and the deposition power is 300 W to 500 W; and / or, The deposition of the second passivation layer includes: Using the PECVD process, silane and hydrogen are introduced. The silane flow rate is 500 sccm to 700 sccm, and the hydrogen flow rate is 800 sccm to 1000 sccm. An amorphous silicon layer is deposited on the second surface of the silicon wafer. The deposition temperature is 190 °C to 205 °C, the deposition time is 80 s to 100 s, the deposition thickness is 4.5 nm to 6 nm, the pressure in the PECVD chamber is 0.5 Torr to 0.6 Torr, and the deposition power is 150 W to 300 W.

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