Preparation method of P-region double-tunneling passivation contact TBC battery and battery

Abstract

A preparation method of a p-region double-tunneling passivation contact TBC battery comprises the steps that a first tunneling oxide layer, a first intrinsic amorphous silicon layer, a low-doping p-type amorphous silicon layer, a second tunneling oxide layer, a high-doping p-type amorphous silicon layer and a silicon dioxide mask layer are sequentially deposited in a P region on the back face of a silicon wafer, and then the p-type amorphous silicon layer is converted into p-type polycrystalline silicon through high-temperature annealing crystallization treatment. According to the invention, the preparation of the p-region double-tunneling passivation contact structure of the TBC battery is realized, the doping level and passivation performance of p-type polycrystalline silicon in the p region are improved, the conversion efficiency of the TBC battery is improved, and the preparation cost is reduced.

Description

Technical Field

[0001] The invention belongs to the field of photovoltaic manufacturing, and in particular relates to a preparation method of a P-region double tunnel passivation contact TBC battery and a battery. Background Art

[0002] As the global demand for clean energy continues to grow, solar cell technology has become a research hotspot. As a cutting-edge technology, the double tunneling passivated contact (TBC) cell is based on the principle of quantum tunneling. By constructing a passivated contact structure in the p-region and n-region of the cell, it effectively suppresses carrier recombination and significantly improves the photoelectric conversion efficiency. This feature makes TBC cells widely used in many fields. In large-scale ground photovoltaic power stations, its efficient power generation capacity can ensure a stable power supply; in distributed rooftop photovoltaic power generation systems, TBC cells can make full use of scattered space to provide users with green electricity; in the aerospace field, energy efficiency is extremely demanding. With its own advantages, TBC batteries have become an ideal choice for powering spacecraft.

[0003] At present, the common preparation method of the p-region of TBC batteries is: first use low-pressure chemical vapor deposition (LPCVD) technology. Under low-pressure environment, gaseous source materials are deposited on the surface of silicon wafers through chemical reaction to form an intrinsic polysilicon layer. This layer is in an intrinsic state and is the basis for subsequent doping. Its quality directly affects the final performance of the p-region. Afterwards, a boron diffusion process is used to diffuse boron atoms into the intrinsic polysilicon lattice in a solid state at high temperature (1040°C) to complete the preparation of p-type polysilicon, thereby constructing the p-region of the TBC battery and realizing the basic working functions of the battery.

[0004] However, the p-type polysilicon doping concentration in the existing preparation method is low, which cannot meet the high conductivity requirements of high-efficiency batteries and limits the carrier transfer efficiency. At the same time, this method is difficult to achieve layered precise doping, and cannot be flexibly adjusted according to the different requirements of different regions of the battery for carrier concentration, which hinders the optimization of the overall performance of the battery. In terms of passivation performance, the passivation effect of the p-region is poor, and the high surface recombination rate causes some photogenerated carriers to recombine and lose on the surface of the battery, greatly reducing the photoelectric conversion efficiency, resulting in actual power generation lower than expected. When the LPCVD equipment is running, polysilicon is continuously deposited on the quartz tube wall. The thermal stress difference between polysilicon and quartz is large. The frequent heating and cooling of the equipment causes the stress to accumulate continuously, causing the quartz tube to be extremely easy to break and need to be replaced frequently, which not only increases the equipment maintenance cost, but also reduces the production continuity and efficiency. The boron diffusion process has a great impact on the material and structural stability of the quartz tube due to the high temperature (1040℃). The frequent high temperature shortens the life of the quartz tube, which also needs to be replaced frequently, greatly increasing the production cost. These performance and cost issues have seriously restricted the large-scale promotion and application of TBC batteries. Summary of the invention

[0005] The object of the present invention is to provide a preparation method of a P-region double-tunneling passivated contact TBC battery, so as to solve the technical problems of improving the battery conversion efficiency and reducing the battery production cost.

[0006] To achieve the above object, the specific technical solution of a preparation method of a P-region double-tunneling passivated contact TBC battery of the present invention is as follows:

[0007] A preparation method of a passivated contact TBC battery with double tunneling in the p-region includes the following steps:

[0008] S1. Silicon wafer surface treatment: The silicon wafer is successively subjected to alkali washing, polishing, acid washing, water washing and drying;

[0009] S2. Deposit a first tunneling oxide layer, a first intrinsic amorphous silicon layer, a low-doped p-type amorphous silicon layer, a second tunneling oxide layer, a high-doped p-type amorphous silicon layer, and a silicon dioxide mask layer on the back surface of the silicon wafer in sequence;

[0010] S3. Anneal and crystallize the silicon wafer, and the low-doped p-type amorphous silicon layer is converted into a low-doped p-type polycrystalline silicon layer, and the high-doped p-type amorphous silicon layer is converted into a high-doped p-type polycrystalline silicon layer;

[0011] S4. Remove the silicon dioxide mask layer in the n-region on the back surface of the silicon wafer by laser etching;

[0012] S5. Remove the silicon dioxide mask layer plated around the front surface of the silicon wafer by acid etching;

[0013] S6. Polish the n-region on the back surface of the silicon wafer by alkali etching, and remove the first tunneling oxide layer, the first intrinsic amorphous silicon layer, the low-doped p-type amorphous silicon layer, the second tunneling oxide layer, and the high-doped p-type amorphous silicon layer in the n-region on the back surface of the silicon wafer and the silicon dioxide mask layer plated around the front surface of the silicon wafer;

[0014] S7. Deposit a third tunneling oxide layer and a second intrinsic amorphous silicon layer on the back surface of the silicon wafer in sequence;

[0015] S8. Perform phosphorus diffusion treatment on the silicon wafer to convert the second intrinsic amorphous silicon layer into a polycrystalline silicon layer, and form a PSG layer on the back surface of the silicon wafer;

[0016] S9. Remove the PSG layer in the p-region on the back surface of the silicon wafer and the spacer region between the p-region and the n-region by laser etching;

[0017] S10. Remove the PSG layer plated around the front surface of the silicon wafer by acid etching;

[0018] S11. Remove the third tunneling oxide layer and polysilicon layer on the front of the silicon wafer, the p-region on the back of the silicon wafer, and the spacer region between the p-region and n-region on the back of the silicon wafer, form a textured structure on the surfaces of the front of the silicon wafer and the spacer region between the p-region and n-region on the back of the silicon wafer, and then sequentially perform pickling to remove the silicon dioxide mask layer on the p-region on the back of the silicon wafer and the PSG layer on the n-region, followed by water washing and hot drying;

[0019] S12. Deposit an alumina layer on both sides of the silicon wafer;

[0020] S13. Deposit an antireflection film on both sides of the silicon wafer;

[0021] S14. Complete the fabrication of the front and back electrodes of the silicon wafer through screen printing and sintering;

[0022] S15. The silicon wafer undergoes light injection treatment to activate the H atoms from the passivation layer, obtaining a P-region double tunneling passivated contact TBC cell.

[0023] As a further improvement of the present invention, in S1, the weight reduction of the silicon wafer is controlled within 0.3 - 0.5 g / wafer, and the reflectivity is controlled within 43% - 47%, including the following steps:

[0024] S1.1. Alkaline washing: Place the silicon wafer in an alkaline mixed solution for cleaning the surface oil stain. The volume fraction of NaOH in the alkaline mixed solution is 0.5% - 1.5%, the volume fraction of H2O2 is 4% - 10%, the temperature is 60 - 70 °C, and the cleaning time is 100 - 250 s;

[0025] S1.2. Polishing: Perform silicon wafer polishing treatment in an NaOH solution. The volume fraction of NaOH in the NaOH solution is 8% - 12%, the temperature is 78 - 85 °C, and the polishing time is 120 - 180 s;

[0026] S1.3. Pickling: Neutralize the NaOH solution, and clean metal ions and the oxide layer in a mixed acid solution;

[0027] S1.4. Water washing and hot drying treatment.

[0028] As a further improvement of the present invention, in S2, a coating equipment is used to deposit a first tunneling oxide layer, a first intrinsic amorphous silicon layer, a low-doped p-type amorphous silicon layer, a second tunneling oxide layer, a high-doped p-type amorphous silicon layer, and a silicon dioxide mask layer on the back of the silicon wafer in sequence at a temperature of 350 - 430 °C using SiH4, N2O, B2H6, and H2 gases;

[0029] In S7, a coating equipment is used to deposit a third tunneling oxide layer and a second intrinsic amorphous silicon layer on the back of the silicon wafer in sequence at a temperature of 600 - 650 °C using SiH4 and O2 gases.

[0030] As a further improvement of the present invention, in S4, a green picosecond laser is used to etch and remove the silicon dioxide mask layer in the n-region on the back side of the silicon wafer according to the designed pattern. The laser spot width is 100 - 200 um, and the laser power is 80 - 200 W;

[0031] In S9, a green picosecond laser is used to etch and remove the PSG layer in the p-region on the back side of the silicon wafer and the PSG layer in the interval region between the p-region and the n-region according to the designed pattern. The laser spot width is 100 - 200 um, and the laser power is 80 - 200 W.

[0032] As a further improvement of the present invention, in S5, a chain cleaning device is used to clean the silicon dioxide mask layer coated around the front side of the silicon wafer in an HF solution. The volume fraction of HF is 30% - 40%, and then drying is carried out;

[0033] In S10, a chain cleaning device is used to clean the PSG layer coated around the front side of the silicon wafer in an HF solution. The volume fraction of HF is 30% - 40%, and then drying is carried out.

[0034] As a further improvement of the present invention, the polishing in S6 includes the following steps:

[0035] S6.1: Use a tank cleaning device to place the silicon wafer in a polishing solution for cleaning and etching. The volume fraction of the alkaline solution in the polishing solution is 3 - 6%, the volume fraction of the additive is 0.6 - 1.0%, the temperature is 70 - 80 °C, and the polishing time is 300 - 500 s;

[0036] S6.2: Neutralize the alkaline solution and clean metal ions in an acidic solution;

[0037] S6.3: Carry out water washing and hot drying treatment.

[0038] As a further improvement of the present invention, in S3, the silicon wafer is placed in a tube annealing furnace for high-temperature annealing and crystallization treatment. The annealing and crystallization temperature is 900 - 960 °C, the nitrogen flow rate is 5000 - 7000 sccm, the pressure is 700 - 900 mbar, the crystallization annealing time is 3000 - 4200 s, and the sheet resistance on the back side of the silicon wafer after annealing and crystallization is controlled within 70 - 150 Ω / □.

[0039] As a further improvement of the present invention, in S11, the weight reduction of the silicon wafer is controlled within 0.2 - 0.4 g / sheet, and the surface texture reflectance is controlled within 9% - 11%. It includes the following steps:

[0040] S11.1: Use a tank cleaning device to place the silicon wafer in a texturing solution. The volume fraction of the alkaline solution in the texturing solution is 0.9 - 1.3%, the volume fraction of the additive is 0.4 - 0.8%, the temperature is 80 - 85 °C, and the texturing time is 400 - 500 s;

[0041] S11.2. Remove the silicon dioxide mask layer in the p-region and the PSG layer in the n-region on the back of the silicon wafer with the pickling solution. The volume fraction of the acid in the pickling solution is 15-25%, the temperature is 20-30°C, and the pickling time is 100-150 s;

[0042] S11.3. Perform water washing and heat drying treatments.

[0043] As a further improvement of the present invention, in S8, put the silicon wafer into a tube-type phosphorus diffusion furnace, fill it with nitrogen, phosphorus source and oxygen for phosphorus diffusion treatment to convert the second intrinsic amorphous silicon layer into a polycrystalline silicon layer, and form a PSG layer on the back surface of the silicon wafer; the phosphorus diffusion temperature is 800-930°C, the phosphorus diffusion time is 1000-2000 s, the gas flow ratio of nitrogen:phosphorus source:oxygen is 1:1.8:0.6-1:2.2:1.0, and the sheet resistance of the n-region after phosphorus diffusion is controlled at 30-60 Ω / □.

[0044] As a further improvement of the present invention, in S12, use a tube-type ALD atomic layer deposition equipment to deposit alumina on the front and back of the silicon wafer. The deposition temperature is 250-350°C, the TMA flow rate is 15-25 sccm, the pure water flow rate is 15-25 sccm, the number of cycles is 30-50 times, and the alumina thickness is controlled at 4-6 nm;

[0045] In S14, use the screen printing process to make the front and back electrodes according to the designed printing pattern. Silver-aluminum paste is used for printing in the p-region, and pure silver paste is used for printing in the n-region; after printing, use an infrared industrial belt sintering furnace to perform rapid sintering at a peak temperature of 730-800°C to form a metal contact electrode;

[0046] In S15, use an industrial belt light injection furnace to perform light injection treatment at a temperature of 600-680°C to activate the H atoms from the passivation layer.

[0047] As a further improvement of the present invention, in S2, use a PECVD tube-type coating equipment to deposit the first tunneling oxide layer, the first intrinsic amorphous silicon layer, the low-doped p-type amorphous silicon layer, the second tunneling oxide layer, the high-doped p-type amorphous silicon layer, and the silicon dioxide mask layer on the back of the silicon wafer in sequence at a temperature of 350-430°C, including the following deposition parameters:

[0048] First tunneling oxide layer: The N2O flow rate is 10000-12000 sccm, the radio frequency power is 13000-16000 W, the duty cycle is 1:(80-120), the deposition time is 80-150 s, and the film thickness is controlled at 1-2 nm;

[0049] First intrinsic amorphous silicon layer: The flow rate of SiH4 is 2500 - 3500 sccm, the flow rate of H2 is 9000 - 15000 sccm; the RF power is 11000 - 15000 W, the duty cycle is 1:(10 - 20), the deposition time is 150 - 300 s, and the film thickness is controlled to be 15 - 30 nm;

[0050] Low-doped p-type amorphous silicon layer: The flow rate of SiH4 is 2500 - 3500 sccm, the flow rate of H2 is 9000 - 15000 sccm, the ratio of the flow rate of B2H6 to the flow rate of SiH4 is 1:(3 - 5), the RF power is 11000 - 15000 W, the duty cycle is 1:(10 - 20), the deposition time is 200 - 400 s, and the film thickness is controlled to be 20 - 40 nm;

[0051] Second tunneling oxide layer: The flow rate of N2O is 10000 - 12000 sccm, the RF power is 13000 - 16000 W, the duty cycle is 1:(80 - 120), the deposition time is 80 - 150 s, and the film thickness is controlled to be 1 - 2 nm;

[0052] High-doped p-type amorphous silicon: The flow rate of SiH4 is 2500 - 3500 sccm, the flow rate of H2 is 9000 - 15000 sccm, the ratio of the flow rate of B2H6 to the flow rate of SiH4 is 1:(1 - 2), the RF power is 11000 - 15000 W, the duty cycle is 1:(10 - 20), the deposition time is 900 - 1300 s, and the film thickness is controlled to be 100 - 140 nm;

[0053] Silicon dioxide mask layer: The flow rate of SiH4 is 1800 - 2200 sccm, the flow rate of N2O is 7500 - 10000 sccm, the RF power is 11000 - 15000 W, the duty cycle is 1:(15 - 25), the deposition time is 60 - 120 s, and the film thickness is controlled to be 5 - 10 nm.

[0054] As a further improvement of the present invention, in S7, an LPCVD tube coating device is used to sequentially deposit a third tunneling oxide layer and a second intrinsic amorphous silicon layer on the back of the silicon wafer at a temperature of 600 - 650 °C, including the following deposition parameters:

[0055] Third tunneling oxide layer: The flow rate of O2 is 30000 - 40000 sccm, the deposition time is 400 - 600 s, and the film thickness is controlled to be 1 - 3 nm;

[0056] Second intrinsic amorphous silicon layer: The flow rate of SiH4 is 1300 - 1500 sccm, the deposition time is 1500 - 1800 s, and the film thickness is controlled to be 120 - 160 nm.

[0057] As a further improvement of the present invention, the front film layer of the silicon wafer in S13 is a multi-layer SiN x / SiO x N y / SiO2 structure, which successively includes the following structures and deposition parameters:

[0058] The first layer of SiN x The deposition temperature is 450 - 500 °C, the silane flow rate is 2300 - 2600 sccm, the ammonia flow rate is 7000 - 9000 sccm, the power is 10000 - 13000 W, the deposition time is 100 - 130 s, the film thickness is controlled to be 10 - 15 nm, and the refractive index is controlled to be 2.2 - 2.3%;

[0059] The second layer of SiN x The deposition temperature is 450 - 500 °C, the silane flow rate is 1700 - 1900 sccm, the ammonia flow rate is 11000 - 13000 sccm, the power is 12000 - 15000 W, the deposition time is 180 - 220 s, the film thickness is controlled to be 15 - 20 nm, and the refractive index is controlled to be 2.1 - 2.2%;

[0060] The third layer of SiN x The deposition temperature is 450 - 500 °C, the silane flow rate is 1100 - 1500 sccm, the ammonia flow rate is 11000 - 15000 sccm, the power is 13000 - 15000 W, the deposition time is 200 - 250 s, the film thickness is controlled to be 17 - 24 nm, and the refractive index is controlled to be 2 - 2.1%;

[0061] The first layer of SiO x N y The deposition temperature is 450 - 500 °C, the silane flow rate is 900 - 1100 sccm, the ammonia flow rate is 4000 - 6000 sccm, the nitrous oxide flow rate is 5000 - 7000 sccm, the power is 14000 - 16000 W, the deposition time is 130 - 150 s, the film thickness is controlled to be 10 - 15 nm, and the refractive index is controlled to be 1.8 - 2%;

[0062] The second layer of SiO x N y The deposition temperature is 450 - 500 °C, the silane flow rate is 700 - 900 sccm, the ammonia flow rate is 3500 - 4500 sccm, the nitrous oxide flow rate is 7000 - 9000 sccm, the power is 14000 - 16000 W, the deposition time is 140 - 160 s, the film thickness is controlled to be 10 - 15 nm, and the refractive index is controlled to be 1.6 - 1.8%;

[0063] The SiO2 deposition temperature is 450 - 500 °C, the silane flow rate is 700 - 900 sccm, the nitrous oxide flow rate is 9000 - 11000 sccm, the power is 14000 - 16000 W, the deposition time is 80 - 120 s, the film thickness is controlled at 5 - 10 nm, and the refractive index is controlled at 1.4 - 1.6%;

[0064] The back film layer of the silicon wafer is a multi-layer SiN x structure, which successively includes the following structures and deposition parameters:

[0065] The first layer of SiN x The deposition temperature is 500 - 550 °C, the silane flow rate is 2500 - 2900 sccm, the ammonia flow rate is 8000 - 11000 sccm, the power is 14000 - 16000 W, the deposition time is 130 - 150 s, the film thickness is controlled at 15 - 25 nm, and the refractive index is controlled at 2.2 - 2.3%;

[0066] The second layer of SiN x The deposition temperature is 500 - 550 °C, the silane flow rate is 1700 - 2100 sccm, the ammonia flow rate is 13000 - 15000 sccm, the power is 14500 - 16500 W, the deposition time is 170 - 210 s, the film thickness is controlled at 20 - 30 nm, and the refractive index is controlled at 2.1 - 2.2%;

[0067] The third layer of SiN x The deposition temperature is 500 - 550 °C, the silane flow rate is 1300 - 1500 sccm, the ammonia flow rate is 12000 - 15000 sccm, the power is 15000 - 19000 W, the deposition time is 250 - 300 s, the film thickness is controlled at 30 - 40 nm, and the refractive index is controlled at 2 - 2.1%.

[0068] A P-region double-tunneling passivated contact TBC cell is prepared by the above preparation method.

[0069] Beneficial effects:

[0070] In the S1 silicon wafer surface treatment stage, through the carefully designed processes of alkali washing, polishing, acid washing, water washing and drying, the oil stains, impurities and oxide layers on the silicon wafer surface can be effectively removed, providing an extremely ideal surface foundation for subsequent processes such as thin film deposition, and greatly improving the adhesion between the thin film and the silicon wafer and the film formation quality in the subsequent processes. In S2, by precisely regulating the doping concentration in different regions, the different requirements of different parts of the battery for carrier transport and recombination are met. Compared with the traditional preparation method, the battery performance can be more effectively optimized, such as enhancing the carrier mobility, reducing the interface recombination, and then improving the overall photoelectric conversion efficiency of the battery.

[0071] The double tunneling oxide layer can effectively reduce the carrier recombination probability, enhance the passivation effect of the battery, significantly improve the open-circuit voltage and short-circuit current of the battery, and ultimately increase the photoelectric conversion efficiency of the battery. Laser etching can achieve precise high-precision patterning etching, accurately remove the unwanted film layers, avoid unnecessary damage to other areas, and at the same time, compared with the traditional photolithography process, it has a higher material utilization rate, reduces material waste, and lowers the production cost. Acid etching and alkali etching can not only accurately remove the unwanted film layers, but also polish the back n-region, improve the surface state, provide a good foundation for subsequent process steps, and enhance the battery performance. When the phosphorus diffusion and PSG layer are properly processed, appropriate phosphorus diffusion conditions can precisely control the electrical properties of the n-region, and subsequent processing of the PSG layer, such as laser etching to remove the PSG layer in specific areas in S9, can optimize the electrical structure of the battery, reduce problems such as unnecessary leakage, and improve the performance stability of the battery. The alumina layer can effectively improve the passivation performance of the battery and reduce the surface recombination rate. The multi-layer antireflection films deposited on the front and back of the silicon wafer in S13 can significantly reduce the light reflectivity and improve the light absorption efficiency by precisely controlling the deposition parameters of each layer, thereby increasing the photoelectric conversion efficiency of the battery.

[0072] Electrode fabrication ensures good Ohmic contact between the electrode and the cell, reducing the contact resistance. Light injection treatment activates the H atoms from the passivation layer, further optimizing the passivation performance of the battery, and improving the long-term stability and photoelectric conversion efficiency of the battery.

[0073] In summary, compared with the preparation method of the tunneling polycrystalline passivation structure in the p-region of the TBC battery prepared by the traditional LPCVD + boron diffusion technology, the preparation method of the TBC battery of the present invention realizes a double tunneling passivation contact structure, improves the p-type polysilicon doping level and passivation performance in the p-region, and the efficiency can be increased by 0.1% - 0.2%; the preparation of the double tunneling passivation contact structure avoids the use of LPCVD equipment and high-temperature boron diffusion, avoids frequent replacement of quartz tubes due to breakage, improves the production stability and yield, and reduces the production cost of the TBC battery. Brief Description of the Drawings

[0074] Figure 1 It is a schematic structural diagram of a P-region double tunneling passivation contact TBC battery of the present invention;

[0075] Explanation of the marks in the figure: 1. First tunneling oxide layer; 2. First intrinsic amorphous silicon layer; 3. Low-doped p-type polysilicon layer; 4. Second tunneling oxide layer; 5. High-doped p-type polysilicon layer; 6. Alumina layer; 71. Back antireflection film; 72. Front antireflection film; 8. Third tunneling oxide layer; 9. Polysilicon layer; 10. Positive electrode; 11. Negative electrode; 12. Silicon wafer. Detailed Description of the Invention

[0076] To better understand the purpose, structure and function of the present invention, the following further describes in detail a method for preparing a P-region double-tunneling passivated contact TBC cell of the present invention with reference to the accompanying drawings.

[0077] Example 1:

[0078] As Figure 1 shown, for a P-region double-tunneling passivated contact TBC cell, a first tunneling oxide layer 1, a first intrinsic amorphous silicon layer 2, a low-doped p-type polycrystalline silicon layer 3, a second tunneling oxide layer 4, and a high-doped p-type polycrystalline silicon layer 5 are sequentially arranged on the p-region of the back surface of the silicon wafer 12. A third tunneling oxide layer 8 and a polycrystalline silicon layer 9 are arranged in the n-region. Alumina layers 6 and antireflection films 72 on the front side and antireflection film 71 on the back side are arranged on both outer sides, realizing the preparation of the double-tunneling passivated contact structure in the p-region of the TBC cell, improving the p-type polycrystalline silicon doping level and passivation performance in the p-region, enhancing the conversion efficiency of the TBC cell, and reducing the preparation cost. The preparation method of this cell is as follows:

[0079] Step 1: Place the n-type silicon wafer in a mixed solution of NaOH and H2O2 for cleaning the surface oil stain. The volume fraction of NaOH in the mixed solution is 1.0%, the volume fraction of H2O2 is 7.5%, the temperature is 66 °C, and the cleaning time is 150 s. Then, perform silicon wafer polishing treatment in the NaOH solution. The volume fraction of NaOH is 10.3%, the temperature is 80 °C, and the polishing time is 150 s. Then, perform neutralization of the NaOH solution, cleaning of metal ions and oxide layers in a mixed acid solution of HCl and HF. Finally, complete water washing and hot drying treatment. During this process, the weight loss of the silicon wafer is controlled within 0.4 g / wafer, and the reflectivity is controlled within 45%.

[0080] Step 2: Using a PECVD tube coating equipment, at a temperature of 380 °C, with SiH4, N2O, B2H6, and H2 gases, deposit a first tunneling oxide layer, a first intrinsic amorphous silicon layer, a low-doped p-type amorphous silicon layer, a second tunneling oxide layer, a highly doped p-type amorphous silicon layer, and a silicon dioxide mask layer on the back of the silicon wafer in sequence. The N2O flow rate for the first tunneling oxide layer is 11000 sccm, the RF power is 14000 W, the duty cycle is 1:100, the deposition time is 125 s, and the film thickness is controlled at 1.6 nm; the SiH4 flow rate for the first intrinsic amorphous silicon layer is 3000 sccm, and the H2 flow rate is 11000 sccm; the RF power is 13000 W, the duty cycle is 1:15, the deposition time is 200 s, and the film thickness is controlled at 20 nm; the SiH4 flow rate for the low-doped p-type amorphous silicon layer is 3000 sccm, the H2 flow rate is 11000 sccm, the ratio of the B2H6 flow rate to the SiH4 flow rate is 1:4, the RF power is 13000 W, the duty cycle is 1:15, the deposition time is 310 s, and the film thickness is controlled at 30 nm; the N2O flow rate for the second tunneling oxide layer is 11000 sccm, the RF power is 14000 W, the duty cycle is 1:100, the deposition time is 125 s, and the film thickness is controlled at 1.6 nm; the SiH4 flow rate for the highly doped p-type amorphous silicon layer is 3000 sccm, the H2 flow rate is 12000 sccm, the ratio of the B2H6 flow rate to the SiH4 flow rate is 1:1.5, the RF power is 14000 W, the duty cycle is 1:15, the deposition time is 1100 s, and the film thickness is controlled at 120 nm; the SiH4 flow rate for the silicon dioxide mask layer is 2000 sccm, the N2O flow rate is 9000 sccm, the RF power is 13000 W, the duty cycle is 1:20, the deposition time is 90 s, and the film thickness is controlled at 8 nm.

[0081] Step 3: Place the silicon wafer in a tube annealing furnace for high-temperature annealing and crystallization treatment, converting the low-doped p-type amorphous silicon layer into a low-doped p-type polycrystalline silicon layer and the highly doped p-type amorphous silicon layer into a highly doped p-type polycrystalline silicon layer. The annealing and crystallization temperature is 930 °C, the nitrogen flow rate is 6000 sccm, the pressure is 800 mbar, the crystallization annealing time is 3600 s, and the back surface sheet resistance after annealing and crystallization is controlled at 100 Ω / □.

[0082] Step 4: Use a green picosecond laser to etch and remove the silicon dioxide mask layer in the n-region of the battery according to the designed pattern. The laser spot width is 150 um, and the laser power is 120 W.

[0083] Step 5: Use a chain cleaning equipment to clean off the silicon dioxide mask layer sputtered on the front of the silicon wafer in an HF solution. The volume fraction of HF is 35%, and then dry it.

[0084] Step 6: Place the silicon wafer in a trough-type cleaning equipment and clean and etch it in a polishing solution. The volume fraction of the alkaline solution in the polishing solution is 4.5%, the volume fraction of the additive is 0.8%, the temperature is 75°C, and the alkaline polishing time is 400 s. Since the amorphous silicon layer covered with a silicon dioxide mask of more than 5 nm has alkali corrosion resistance under the protection of the additive, the p-type amorphous silicon layer and the tunneling oxide layer in the p region will not be corroded. The p-type amorphous silicon layer and the tunneling oxide layer in the n region are removed, and the n-region amorphous silicon layer is polished for the second time. At the same time, the p-type amorphous silicon layer and the tunneling layer plated on the front are removed. Then, neutralize the NaOH solution and clean metal ions in the HCl solution. Complete the water washing and heat drying processes.

[0085] Step 7: Use an LPCVD tube coating equipment to deposit a third tunneling oxide layer and a second intrinsic amorphous silicon layer on the back of the silicon wafer in sequence at a temperature of 630°C using O2 and SiH4 gases. The O2 flow rate of the tunneling oxide layer is 36000 sccm, the deposition time is 520 s, and the film thickness is controlled at 2 nm. The SiH4 flow rate of the second intrinsic amorphous silicon layer is 1400 sccm, the deposition time is 1650 s, and the film thickness is controlled at 140 nm.

[0086] Step 8: Place the silicon wafer in a tube-type phosphorus diffusion furnace for phosphorus diffusion to form a polysilicon layer on the second intrinsic amorphous silicon layer in the n region and form a PSG layer on the back surface of the silicon wafer. The phosphorus diffusion temperature is 905°C, the process time is 1600 s, and the gas flow ratio of nitrogen: phosphorus source: oxygen is 1:2:0.8. After phosphorus diffusion, the sheet resistance in the n region is controlled at 45 Ω / □.

[0087] Step 9: Use a green picosecond laser to etch and remove the PSG layer in the p region of the battery and the interval region between the p region and the n region according to the designed pattern. The laser spot width is 130 um, and the laser power is 100 W.

[0088] Step 10: Use a chain-type cleaning equipment to clean the PSG layer plated on the front of the silicon wafer in an HF solution. The volume fraction of HF is 35%, and then dry it.

[0089] Step 11: Place the silicon wafer in a mixed solution of NaOH and additives using a trough-type cleaning equipment for front surface texturing. The volume fraction of the additive in the texturing solution is 0.6%, the volume fraction of NaOH is 1.1%, the temperature is 82°C, and the texturing time is 450 s. Since the polysilicon layer covered with PSG has alkali corrosion resistance under the protection of the additive, the n-region phosphorus-doped polysilicon layer and the third tunneling oxide layer will not be corroded. The phosphorus-doped polysilicon layer and the third tunneling oxide layer in the p-region, the p-region and the n-region spacer are removed, and a textured surface structure is formed on the p-region, the p-region and the n-region spacer, and the front surface. Pickle in an HF solution to remove the p-region silicon dioxide mask layer. The volume fraction of HF in the pickling solution is 20%, the temperature is 25°C, and the pickling time is 130 s. Then, complete the water washing and hot drying processes. In this step, the weight loss of the silicon wafer is controlled within 0.3 g / wafer, and the reflectivity of the textured surface is controlled at 9.8%.

[0090] Step 12: Use a tube-type ALD atomic layer deposition equipment to deposit a layer of alumina on the entire front and back surfaces of the silicon wafer simultaneously. The deposition temperature is 295°C, the TMA flow rate is 20 sccm, the pure water flow rate is 20 sccm, the number of cycles is 40 times, and the alumina thickness is controlled at 5 nm.

[0091] Step 13: Use a tube-type PECVD equipment to deposit the front anti-reflection film first. The front film layer is a multi-layer SiN x / SiO x N y / SiO2 structure. The deposition temperature of the first layer of SiN x is 475°C, the silane flow rate is 2450 sccm, the ammonia flow rate is 8000 sccm, the power is 12000 W, the deposition time is 110 s, the film thickness is controlled at 12 nm, and the refractive index is controlled at 2.25%. The deposition temperature of the second layer of SiN x is 475°C, the silane flow rate is 1800 sccm, the ammonia flow rate is 12000 sccm, the power is 13500 W, the deposition time is 200 s, the film thickness is controlled at 17 nm, and the refractive index is controlled at 2.15%. The deposition temperature of the third layer of SiN x is 475°C, the silane flow rate is 1400 sccm, the ammonia flow rate is 13000 sccm, the power is 14000 W, the deposition time is 220 s, the film thickness is controlled at 18 nm, and the refractive index is controlled at 2.05%. The deposition temperature of the first layer of SiO x N y is 475°C, the silane flow rate is 1000 sccm, the ammonia flow rate is 5000 sccm, the nitrous oxide flow rate is 6000 sccm, the power is 15000 W, the deposition time is 140 s, the film thickness is controlled at 12 nm, and the refractive index is controlled at 1.9%. The deposition temperature of the second layer of SiO x N yThe deposition temperature is 475 °C, the silane flow rate is 800 sccm, the ammonia flow rate is 4000 sccm, the nitrous oxide flow rate is 8000 sccm, the power is 15000 W, the deposition time is 150 s, the film thickness is controlled to be 11 nm, and the refractive index is controlled to be 1.7%; for SiO2 deposition, the temperature is 475 °C, the silane flow rate is 800 sccm, the nitrous oxide flow rate is 10000 sccm, the power is 15000 W, the deposition time is 100 s, the film thickness is controlled to be 7 nm, and the refractive index is controlled to be 1.5%.

[0092] After the front-side coating is completed, the silicon wafer is taken out, turned over, and then put back into the PECVD equipment. An antireflection film is deposited on the back side, and the back-side film layer is a multi-layer SiN x structure; the first layer of SiN x The deposition temperature is 530 °C, the silane flow rate is 2700 sccm, the ammonia flow rate is 9500 sccm, the power is 15000 W, the deposition time is 140 s, the film thickness is controlled to be 20 nm, and the refractive index is controlled to be 2.28%; the second layer of SiN x The deposition temperature is 530 °C, the silane flow rate is 1900 sccm, the ammonia flow rate is 14000 sccm, the power is 15000 W, the deposition time is 190 s, the film thickness is controlled to be 26 nm, and the refractive index is controlled to be 2.17%; the third layer of SiN x The deposition temperature is 530 °C, the silane flow rate is 1400 sccm, the ammonia flow rate is 13000 sccm, the power is 17000 W, the deposition time is 280 s, the film thickness is controlled to be 37 nm, and the refractive index is controlled to be 2.06%.

[0093] Step 14: The front and back electrodes are fabricated using the screen printing process. According to the designed printing pattern, silver-aluminum paste is used for printing in the p region, and pure silver paste is used for printing in the n region; after printing, a rapid sintering is carried out using an infrared industrial belt sintering furnace at a peak temperature of 780 °C to form the metal contact electrodes, the positive electrode 10 and the negative electrode 11.

[0094] Step 15: The silicon wafer is subjected to light injection treatment using an industrial belt light injection furnace at a temperature of 650 °C to activate the H atoms from the passivation layer, and finally a passivated contact cell with a double-tunneling polysilicon layer in the P region is obtained.

[0095] Example 2

[0096] This example provides a method for preparing a passivated contact TBC cell with a double-tunneling in the P region. Except that the deposition time of the first tunneling oxide layer in step 2 is shortened to 118 s and the deposition time of the second tunneling oxide layer is shortened to 118 s; in step S3, the annealing crystallization temperature is reduced to 920 °C and the crystallization annealing time is extended to 4200 s, the rest of the steps and conditions are the same as those in Example 1.

[0097] Example 3

[0098] This embodiment provides a method for preparing a P-region double-tunneling passivated contact TBC cell. Except that the deposition time of the first tunneling oxide layer in step 2 is extended to 133 s, and the deposition time of the second tunneling oxide layer is extended to 133 s; the crystallization annealing time in step 3 is extended to 4200 s, the remaining steps and conditions are the same as those in Embodiment 1.

[0099] Embodiment 4

[0100] This embodiment provides a method for preparing a P-region double-tunneling passivated contact TBC cell. Except that the deposition time of the second tunneling oxide layer in step 2 is extended to 133 s, and the deposition time of the first intrinsic amorphous silicon layer is extended to 230 s; the crystallization annealing time in step 3 is extended to 4200 s, the remaining steps and conditions are the same as those in Embodiment 1.

[0101] Embodiment 5

[0102] This embodiment provides a method for preparing a P-region double-tunneling passivated contact TBC cell. Except that the deposition time of the second tunneling oxide layer in step 2 is extended to 133 s, the deposition time of the first intrinsic amorphous silicon layer is extended to 230 s, the ratio of the B2H6 flow rate to the B2H6 flow rate of the lightly doped p-type amorphous silicon layer is adjusted to 1:3.8, and the ratio of the B2H6 flow rate to the SiH4 flow rate of the highly doped p-type amorphous silicon layer is adjusted to 1:1.4; the crystallization annealing time in step 3 is extended to 4200 s, the remaining steps and conditions are the same as those in Embodiment 1.

[0103] Embodiment 6

[0104] This embodiment provides a method for preparing a P-region double-tunneling passivated contact TBC cell. Except that the deposition time of the second tunneling oxide layer in step 2 is extended to 133 s, the deposition time of the first intrinsic amorphous silicon layer is extended to 250 s, the deposition time of the lightly doped p-type amorphous silicon layer is extended to 340 s, the ratio of the B2H6 flow rate to the SiH4 flow rate is adjusted to 1:3.8, the deposition time of the highly doped p-type amorphous silicon layer is extended to 11450 s, and the ratio of the B2H6 flow rate to the SiH4 flow rate is adjusted to 1:1.4; the crystallization annealing time in step 3 is extended to 4200 s, the remaining steps and conditions are the same as those in Embodiment 1.

[0105] Embodiment 7

[0106] This embodiment provides a method for preparing a P-region double-tunneling passivated contact TBC cell. Except that the deposition time of the second tunneling oxide layer in step 2 is extended to 133 s, the deposition time of the second tunneling oxide layer is extended to 140 s, the deposition time of the first intrinsic amorphous silicon layer is extended to 230 s, the ratio of the B2H6 flow rate to the SiH4 flow rate in the low-doped p-type amorphous silicon layer is adjusted to 1:3.8, the deposition time of the high-doped p-type amorphous silicon layer is extended to 1055 s, and the ratio of the B2H6 flow rate to the SiH4 flow rate is adjusted to 1:1.35; in step 3, the crystallization annealing time is extended to 4200 s, and the remaining steps and conditions are the same as those in Example 1.

[0107] Example 8

[0108] This embodiment provides a method for preparing a P-region double-tunneling passivated contact TBC cell. Except that the deposition time of the first tunneling oxide layer in step 2 is shortened to 80 s, the remaining steps and conditions are the same as those in Example 1.

[0109] Example 9

[0110] This embodiment provides a method for preparing a P-region double-tunneling passivated contact TBC cell. Except that the deposition time of the second tunneling oxide layer in step 2 is extended to 150 s, the remaining steps and conditions are the same as those in Example 1.

[0111] Example 10

[0112] This embodiment provides a method for preparing a P-region double-tunneling passivated contact TBC cell. Except that the deposition time of the first intrinsic amorphous silicon layer in step 2 is extended to 300 s, the remaining steps and conditions are the same as those in Example 1.

[0113] Example 11

[0114] This embodiment provides a method for preparing a P-region double-tunneling passivated contact TBC cell. Except that the deposition time of the low-doped p-type amorphous silicon layer in step 2 is extended to 400 s, the remaining steps and conditions are the same as those in Example 1.

[0115] Example 12

[0116] This embodiment provides a method for preparing a P-region double-tunneling passivated contact TBC cell. Except that the ratio of the B2H6 flow rate to the SiH4 flow rate in the low-doped p-type amorphous silicon layer in step 2 is adjusted to 1:3, the remaining steps and conditions are the same as those in Example 1.

[0117] Example 13

[0118] This embodiment provides a method for preparing a P-region double-tunneling passivated contact TBC cell. Except that the deposition time of the high-doped p-type amorphous silicon layer in step 2 is extended to 1300 s, the remaining steps and conditions are the same as those in Example 1.

[0119] Example 14

[0120] This example provides a preparation method for a P-region double-tunneling passivated contact TBC cell. Except that the annealing crystallization temperature in step 3 is increased to 960 °C, the other steps and conditions are the same as those in Example 1.

[0121] The specific electrical performance parameters of the cell wafers in different examples are shown in Table 1. It can be seen that for the TBC cell prepared in Example 7, Voc reaches 0.7471 V, Isc reaches 14.163 A, FF reaches 84.93%, and the photoelectric conversion efficiency Eta reaches 26.98%. The average efficiency is far higher than the industry level. This is because the double-tunneling passivated contact structure has better passivation performance. In addition, precise doping is achieved in the p-type polysilicon layer, resulting in higher carrier transport and collection efficiency, thereby improving the electrical performance.

[0122]

[0123] Table 1 Electrical performance parameters of cell wafers prepared in examples and comparative examples

[0124] Compared with the traditional preparation method of the tunneling polycrystalline passivation structure in the p-region of the TBC cell by LPCVD + boron diffusion technology, the present invention realizes a double-tunneling passivated contact structure, improves the p-type polysilicon doping level and passivation performance in the p-region, and the efficiency can be increased by 0.1% - 0.2%. The preparation of the double-tunneling passivated contact structure avoids the use of LPCVD equipment and high-temperature boron diffusion, avoids frequent replacement of quartz tubes due to breakage, improves production stability and yield, and reduces the production cost of TBC cells.

[0125] It can be understood that the present invention is described through some examples. Those skilled in the art know that without departing from the spirit and scope of the present invention, various changes or equivalent replacements can be made to these features and examples. In addition, under the teaching of the present invention, these features and examples can be modified to adapt to specific situations and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific examples disclosed herein, and all examples falling within the scope of the claims of this application belong to the scope protected by the present invention.

Claims

1. A preparation method of a passivated contact TBC cell with p-region double tunneling, characterized in that It includes the following steps: S1. Wafer surface treatment: The wafer is successively subjected to alkali cleaning, polishing, acid pickling, water washing and drying. S2. Deposit a first tunneling oxide layer, a first intrinsic amorphous silicon layer, a low-doped p-type amorphous silicon layer, a second tunneling oxide layer, a high-doped p-type amorphous silicon layer, and a silicon dioxide mask layer on the back surface of the wafer in sequence. S3. Perform annealing crystallization treatment on the wafer, and the low-doped p-type amorphous silicon layer is converted into a low-doped p-type polycrystalline silicon layer, and the high-doped p-type amorphous silicon layer is converted into a high-doped p-type polycrystalline silicon layer. S4. Remove the silicon dioxide mask layer in the n-region on the back surface of the wafer by laser etching. S5. Remove the silicon dioxide mask layer deposited around the front surface of the wafer by acid etching. S6. Polish the n-region on the back surface of the wafer by alkali etching, and remove the first tunneling oxide layer, the first intrinsic amorphous silicon layer, the low-doped p-type amorphous silicon layer, the second tunneling oxide layer, and the high-doped p-type amorphous silicon layer in the n-region on the back surface of the wafer and the silicon dioxide mask layer deposited around the front surface of the wafer. S7. Deposit a third tunneling oxide layer and a second intrinsic amorphous silicon layer on the back surface of the wafer in sequence. S8. Perform phosphorus diffusion treatment on the wafer to convert the second intrinsic amorphous silicon layer into a polycrystalline silicon layer, and form a PSG layer on the back surface of the wafer. S9. Remove the PSG layer in the p-region on the back surface of the wafer and the spacer region between the p-region and the n-region by laser etching. S10. Remove the PSG layer deposited around the front surface of the wafer by acid etching. S11. Remove the third tunneling oxide layer and the polycrystalline silicon layer on the front surface of the wafer, in the p-region on the back surface of the wafer, and in the spacer region between the p-region and the n-region on the back surface of the wafer, form a textured structure on the front surface of the wafer, in the p-region on the back surface of the wafer, and in the spacer region between the p-region and the n-region on the back surface of the wafer, and then successively perform acid pickling to remove the silicon dioxide mask layer in the p-region on the back surface of the wafer and the PSG layer in the n-region, water washing, and hot drying. S12. Deposit an alumina layer on both sides of the wafer. S13. Deposit an antireflection film on both sides of the wafer. S14. Complete the production of the front and back electrodes of the wafer by screen printing and sintering. S15. The wafer is subjected to light injection treatment to activate the H atoms from the passivation layer to obtain a P-region double tunneling passivated contact TBC cell.

2. The preparation method of the P-region double-tunneling passivated contact TBC cell according to claim 1, wherein, In S1, the weight reduction of the wafer is controlled at 0.3 - 0.5 g / wafer, and the reflectivity is controlled at 43% - 47%. It includes the following steps: S1.

1. Alkali cleaning: Place the wafer in an alkaline mixed solution for cleaning the surface oil stain. The volume fraction of NaOH in the alkaline mixed solution is 0.5% - 1.5%, the volume fraction of H2O2 is 4% - 10%, the temperature is 60 - 70 °C, and the cleaning time is 100 - 250 s. S1.

2. Polishing: Perform wafer polishing treatment in a NaOH solution. The volume fraction of NaOH in the NaOH solution is 8% - 12%, the temperature is 78 - 85 °C, and the polishing time is 120 - 180 s. S1.

3. Acid pickling: Neutralize the NaOH solution, and clean metal ions and the oxide layer in a mixed acid solution. S1.

4. Water washing and hot drying treatment.

3. The preparation method of the P-region double-tunneling passivated contact TBC battery according to claim 1, characterized in that, In S2, a coating equipment is used to deposit a first tunneling oxide layer, a first intrinsic amorphous silicon layer, a low-doped p-type amorphous silicon layer, a second tunneling oxide layer, a high-doped p-type amorphous silicon layer, and a silicon dioxide mask layer on the back side of the silicon wafer in sequence at a temperature of 350 - 430 °C using SiH4, N2O, B2H6, and H2 gases. In S7, a coating equipment is used to deposit a third tunneling oxide layer and a second intrinsic amorphous silicon layer on the back side of the silicon wafer in sequence at a temperature of 600 - 650 °C using SiH4 and O2 gases.

4. The preparation method of the P-region double-tunneling passivated contact TBC cell according to claim 1, characterized in that, In S4, a green picosecond laser is used to etch and remove the silicon dioxide mask layer in the n-region on the back side of the silicon wafer according to a designed pattern. The laser spot width is 100 - 200 um, and the laser power is 80 - 200 W. In S9, a green picosecond laser is used to etch and remove the PSG layer in the p-region and the interval region between the p-region and the n-region on the back side of the silicon wafer according to a designed pattern. The laser spot width is 100 - 200 um, and the laser power is 80 - 200 W.

5. The preparation method of the P-region double-tunneling passivated contact TBC cell according to claim 1, characterized in that, In S5, a chain cleaning equipment is used to clean off the silicon dioxide mask layer sputtered on the front side of the silicon wafer in an HF solution. The volume fraction of HF is 30% - 40%, and then drying is carried out. In S10, a chain cleaning equipment is used to clean off the PSG layer sputtered on the front side of the silicon wafer in an HF solution. The volume fraction of HF is 30% - 40%, and then drying is carried out.

6. The preparation method of the P-region double-tunneling passivated contact TBC cell according to claim 1, wherein The polishing in S6 includes the following steps: S6.1: Using a tank cleaning equipment to place the silicon wafer in a polishing solution for cleaning and etching. The volume fraction of the alkaline solution in the polishing solution is 3 - 6%, the volume fraction of the additive is 0.6 - 1.0%, the temperature is 70 - 80 °C, and the polishing time is 300 - 500 s. S6.2: Neutralizing the alkaline solution and cleaning metal ions in an acidic solution. S6.3: Water washing and heat drying treatment.

7. The preparation method of the P-region double-tunneling passivated contact TBC battery according to claim 1, characterized in that, In S3, the silicon wafer is put into a tube annealing furnace for high-temperature annealing and crystallization treatment. The annealing and crystallization temperature is 900 - 960 °C, the nitrogen flow rate is 5000 - 7000 sccm, the pressure is 700 - 900 mbar, the crystallization annealing time is 3000 - 4200 s, and the sheet resistance on the back side of the silicon wafer after annealing and crystallization is controlled at 70 - 150 Ω / □.

8. The preparation method of the P-region double-tunneling passivated contact TBC battery according to claim 1, wherein, In S11, the weight reduction of the silicon wafer is controlled at 0.2 - 0.4 g / wafer, and the surface texture reflectivity is controlled at 9% - 11%. It includes the following steps: S11.1: Using a tank cleaning equipment to place the silicon wafer in a texturing solution. The volume fraction of the alkaline solution in the texturing solution is 0.9 - 1.3%, the volume fraction of the additive is 0.4 - 0.8%, the temperature is 80 - 85 °C, and the texturing time is 400 - 500 s. S11.2: Removing the silicon dioxide mask layer in the p-region and the PSG layer in the n-region on the back side of the silicon wafer in a pickling solution. The volume fraction of the acid in the pickling solution is 15 - 25%, the temperature is 20 - 30 °C, and the pickling time is 100 - 150 s. S11.3: Water washing and heat drying treatment.

9. The preparation method of the P-region double-tunneling passivated contact TBC cell according to claim 1, characterized in that, In S8, the silicon wafer is placed in a tube-type phosphorus diffusion furnace and filled with nitrogen, a phosphorus source, and oxygen for phosphorus diffusion treatment to convert the second intrinsic amorphous silicon layer into a polycrystalline silicon layer, and a PSG layer is formed on the back surface of the silicon wafer; the phosphorus diffusion temperature is 800 - 930 °C, the phosphorus diffusion time is 1000 - 2000 s, the gas flow ratio of nitrogen:phosphorus source:oxygen is 1:1.8:0.6 - 1:2.2:1.0, and the sheet resistance of the n-region after phosphorus diffusion is controlled at 30 - 60 Ω / □.

10. The preparation method of the P-region double-tunneling passivated contact TBC battery according to claim 1, wherein, In S12, a tube-type ALD atomic layer deposition device is used to deposit aluminum oxide on the front and back surfaces of the silicon wafer. The deposition temperature is 250 - 350 °C, the flow rate of TMA is 15 - 25 sccm, the flow rate of pure water is 15 - 25 sccm, the number of cycles is 30 - 50 times, and the thickness of the aluminum oxide is controlled at 4 - 6 nm; In S14, a screen printing process is used to fabricate the front and back electrodes according to the designed printing pattern. Silver-aluminum paste is used for printing in the p-region, and pure silver paste is used for printing in the n-region; After printing, an infrared industrial belt sintering furnace is used to perform rapid sintering at a peak temperature of 730 - 800 °C to form metal contact electrodes; In S15, an industrial belt light injection furnace is used to perform light injection treatment at a temperature of 600 - 680 °C to activate the H atoms from the passivation layer.

11. The preparation method of the P-region double-tunneling passivated contact TBC battery according to claim 1, wherein In S2, a PECVD tube-type coating device is used to sequentially deposit a first tunneling oxide layer, a first intrinsic amorphous silicon layer, a low-doped p-type amorphous silicon layer, a second tunneling oxide layer, a high-doped p-type amorphous silicon layer, and a silicon dioxide mask layer on the back surface of the silicon wafer at a temperature of 350 - 430 °C, including the following deposition parameters: First tunneling oxide layer: The flow rate of N2O is 10000 - 12000 sccm, the radio frequency power is 13000 - 16000 W, the duty cycle is 1:(80 - 120), the deposition time is 80 - 150 s, and the film thickness is controlled at 1 - 2 nm; First intrinsic amorphous silicon layer: The flow rate of SiH4 is 2500 - 3500 sccm, the flow rate of H2 is 9000 - 15000 sccm; the radio frequency power is 11000 - 15000 W, the duty cycle is 1:(10 - 20), the deposition time is 150 - 300 s, and the film thickness is controlled at 15 - 30 nm; Low-doped p-type amorphous silicon layer: The flow rate of SiH4 is 2500 - 3500 sccm, the flow rate of H2 is 9000 - 15000 sccm, the ratio of the flow rate of B2H6 to the flow rate of SiH4 is 1:(3 - 5), the radio frequency power is 11000 - 15000 W, the duty cycle is 1:(10 - 20), the deposition time is 200 - 400 s, and the film thickness is controlled at 20 - 40 nm; Second tunneling oxide layer: The flow rate of N2O is 10000 - 12000 sccm, the radio frequency power is 13000 - 16000 W, the duty cycle is 1:(80 - 120), the deposition time is 80 - 150 s, and the film thickness is controlled at 1 - 2 nm; Highly doped p-type amorphous silicon: The flow rate of SiH4 is 2500 - 3500 sccm, the flow rate of H2 is 9000 - 15000 sccm, the ratio of the flow rate of B2H6 to the flow rate of SiH4 is 1:(1 - 2), the radio frequency power is 11000 - 15000 W, the duty cycle is 1:(10 - 20), the deposition time is 900 - 1300 s, and the film thickness is controlled to be 100 - 140 nm; Silicon dioxide mask layer: The flow rate of SiH4 is 1800 - 2200 sccm, the flow rate of N2O is 7500 - 10000 sccm, the radio frequency power is 11000 - 15000 W, the duty cycle is 1:(15 - 25), the deposition time is 60 - 120 s, and the film thickness is controlled to be 5 - 10 nm.

12. The preparation method of the P-region double-tunneling passivated contact TBC battery according to claim 1, characterized in that, In S7, a LPCVD tube coating equipment is used to sequentially deposit a third tunneling oxide layer and a second intrinsic amorphous silicon layer on the back of the silicon wafer at a temperature of 600 - 650 °C, including the following deposition parameters: Third tunneling oxide layer: The flow rate of O2 is 30000 - 40000 sccm, the deposition time is 400 - 600 s, and the film thickness is controlled to be 1 - 3 nm; Second intrinsic amorphous silicon layer: The flow rate of SiH4 is 1300 - 1500 sccm, the deposition time is 1500 - 1800 s, and the film thickness is controlled to be 120 - 160 nm.

13. The preparation method of the P-region double-tunneling passivated contact TBC battery according to claim 1, wherein, The front film layer of the silicon wafer in S13 is a multi-layer SiN x / SiO x N y / SiO2 structure, which successively includes the following structures and deposition parameters: The first layer of SiN x The deposition temperature is 450 - 500 °C, the silane flow rate is 2300 - 2600 sccm, the ammonia flow rate is 7000 - 9000 sccm, the power is 10000 - 13000 W, the deposition time is 100 - 130 s, the film thickness is controlled to be 10 - 15 nm, and the refractive index is controlled to be 2.2 - 2.3%; The second layer of SiN x The deposition temperature is 450 - 500 °C, the silane flow rate is 1700 - 1900 sccm, the ammonia flow rate is 11000 - 13000 sccm, the power is 12000 - 15000 W, the deposition time is 180 - 220 s, the film thickness is controlled to be 15 - 20 nm, and the refractive index is controlled to be 2.1 - 2.2%; The third layer of SiN x The deposition temperature is 450 - 500 °C, the silane flow rate is 1100 - 1500 sccm, the ammonia flow rate is 11000 - 15000 sccm, the power is 13000 - 15000 W, the deposition time is 200 - 250 s, the film thickness is controlled at 17 - 24 nm, and the refractive index is controlled at 2 - 2.1%. The first layer of SiO x N y The deposition temperature is 450 - 500 °C, the silane flow rate is 900 - 1100 sccm, the ammonia flow rate is 4000 - 6000 sccm, the nitrous oxide flow rate is 5000 - 7000 sccm, the power is 14000 - 16000 W, the deposition time is 130 - 150 s, the film thickness is controlled to be 10 - 15 nm, and the refractive index is controlled to be 1.8 - 2%; The second layer of SiO x N y The deposition temperature is 450 - 500 °C, the silane flow rate is 700 - 900 sccm, the ammonia flow rate is 3500 - 4500 sccm, the nitrous oxide flow rate is 7000 - 9000 sccm, the power is 14000 - 16000 W, the deposition time is 140 - 160 s, the film thickness is controlled to be 10 - 15 nm, and the refractive index is controlled to be 1.6 - 1.8%; The deposition temperature of SiO2 is 450 - 500 °C, the flow rate of silane is 700 - 900 sccm, the flow rate of nitrous oxide is 9000 - 11000 sccm, the power is 14000 - 16000 W, the deposition time is 80 - 120 s, the film thickness is controlled to be 5 - 10 nm, and the refractive index is controlled to be 1.4 - 1.6%; The back film layer of the silicon wafer is a multi-layer SiN x structure, which successively includes the following structures and deposition parameters: The first layer of SiN x The deposition temperature is 500 - 550 °C, the silane flow rate is 2500 - 2900 sccm, the ammonia flow rate is 8000 - 11000 sccm, the power is 14000 - 16000 W, the deposition time is 130 - 150 s, the film thickness is controlled to be 15 - 25 nm, and the refractive index is controlled to be 2.2 - 2.3%; The second layer of SiN x The deposition temperature is 500 - 550 °C, the silane flow rate is 1700 - 2100 sccm, the ammonia flow rate is 13000 - 15000 sccm, the power is 14500 - 16500 W, the deposition time is 170 - 210 s, the film thickness is controlled to be 20 - 30 nm, and the refractive index is controlled to be 2.1 - 2.2%. The third layer of SiN x The deposition temperature is 500 - 550 °C, the silane flow rate is 1300 - 1500 sccm, the ammonia flow rate is 12000 - 15000 sccm, the power is 15000 - 19000 W, the deposition time is 250 - 300 s, the film thickness is controlled to be 30 - 40 nm, and the refractive index is controlled to be 2 - 2.1%.

14. A P-region double-tunneling passivated contact TBC cell, characterized in that, Prepared by the preparation method according to any one of claims 1 - 13.

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