Back contact solar cell and preparation method thereof

Abstract

The method comprises the following steps: depositing a first passivation layer on the back surface of a silicon wafer, attaching a first mask to the back surface, exposing a first preset area corresponding to a first patterned opening of the first mask, removing the first passivation layer corresponding to the first preset area, and depositing a first conductive composite layer; removing the first mask to obtain a first preset functional layer; a second mask is attached to the back face, a second preset area corresponding to a second patterning opening of the second mask is exposed, a second conductive composite layer is deposited after a second passivation layer corresponding to the second preset area is removed, and a second preset functional layer is formed after the second mask is removed; and preparing an electrode on the back to obtain the back-contact solar cell. Wherein a gap is formed between the first conductive region and the second conductive region, the first preset region and the second preset region comprise the first conductive region and the second conductive region which are opposite in conductive type, and the first preset region and / or the second preset region further comprises a communication region. According to the invention, the PN junction is formed, and the preparation of the communication function layer and the isolation region is completed at the same time.

Description

Technical Field

[0001] This application relates to the technical field of solar cell manufacturing, and more specifically, to a back-contact solar cell and a method for manufacturing the same. Background Art

[0002] During the actual use of a photovoltaic module made of a back-contact solar cell, when an obstacle covers the back-contact solar cell, the local temperature will rise and a hot-spot effect will occur, which easily leads to problems such as delamination of the photovoltaic module, burning of the backsheet, and bursting of the glass. In severe cases, it may lead to the scrapping of the photovoltaic module. Summary of the Invention

[0003] This application provides a back-contact solar cell and a method for manufacturing the same. In the manufacturing process, the patterning of the P region, N region, PN isolation region, and connection region is alternately achieved in a masking manner, making the entire manufacturing process simple and easy to implement, providing convenience for subsequent process treatments, and reducing the hot-spot risk.

[0004] To achieve the above object, the technical solutions adopted in the embodiments of this application are as follows:

[0005] On the one hand, an embodiment of this application provides a method for manufacturing a back-contact solar cell, including:

[0006] Providing a pretreated N-type silicon wafer substrate;

[0007] Depositing a first passivation layer on the back surface of the silicon wafer;

[0008] Attaching a first mask to the back surface of the silicon wafer, exposing a first preset area corresponding to a first patterned opening, and the first preset area includes a first conductive region;

[0009] Removing the first passivation layer corresponding to the first preset area to expose the N-type silicon wafer substrate;

[0010] Depositing a first conductive composite layer on the back surface of the silicon wafer, and mechanically removing the first mask to obtain a first preset functional layer, and the first preset functional layer includes a first conductive functional layer;

[0011] Attaching a second mask to the back surface of the silicon wafer, exposing a second preset area corresponding to a second patterned opening, the second preset area includes a second conductive region, and there is a gap between the first conductive region and the second conductive region;

[0012] Removing the first passivation layer corresponding to the second preset area to expose the N-type silicon wafer substrate;

[0013] Deposit a second conductive composite layer on the back side of the silicon wafer, mechanically remove the second mask to form a second preset functional layer, the second preset functional layer includes a second conductive functional layer with a conductive type opposite to that of the first conductive functional layer, and there are an isolation region functional layer and a connection region functional layer between the first conductive functional layer and the second conductive functional layer;

[0014] Perform electrode preparation on the back side of the silicon wafer to obtain a back-contact solar cell.

[0015] In some embodiments, the first conductive region is a P region, the first conductive composite layer is a P-type conductive composite layer, the second conductive region is an N region, and the second conductive composite layer is an N-type conductive composite layer;

[0016] Or, the first conductive region is an N region, the first conductive composite layer is an N-type conductive composite layer, the second conductive region is a P region, and the second conductive composite layer is a P-type conductive composite layer.

[0017] In some embodiments, the P region includes a plurality of P-region finger regions extending along a first direction, the N region includes a plurality of N-region finger regions extending along the first direction, and the P-region finger regions and the N-region finger regions are alternately arranged; the P region further includes a P-region connection region extending along a second direction, the P-region connection region is connected to a plurality of the P-region finger regions, the N region further includes an N-region connection region extending along the second direction, and the N-region connection region is connected to a plurality of the N-region finger regions,

[0018] Wherein, the connection region is arranged between the P-region finger region and the N finger region, and / or between the P-region connection region and the N-region finger region, and / or between the N-region connection region and the P-region finger region.

[0019] In some embodiments, in the extending direction of the P-region connection region or the N-region connection region, one connection region is arranged within 3 - 15 mm, and in the direction perpendicular to the extending direction of the P-region connection region or the N-region connection region, one or more connection regions are arranged between adjacent connection regions.

[0020] In some embodiments, the P region includes a plurality of P-region finger regions extending along a first direction, the N region includes a plurality of N-region finger regions extending along the first direction, and the P-region finger regions and the N-region finger regions are alternately arranged, wherein the connection region is arranged between the P-region finger region and the N finger region.

[0021] In some embodiments, the first passivation layer is any one or more of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer.

[0022] In some embodiments, deposit the P-type conductive composite layer first, then deposit the N-type conductive composite layer, and an annealing step is further included thereafter,

[0023] Among them, the deposited P-type conductive composite layer includes a tunneling oxide layer and a boron-doped polysilicon layer deposited in sequence.

[0024] The deposited N-type conductive composite layer includes a tunneling oxide layer and a phosphorus-doped polysilicon layer deposited in sequence.

[0025] In some embodiments, the deposited P-type conductive composite layer includes an intrinsic amorphous silicon layer, and a P-type amorphous silicon layer or a microcrystalline silicon layer deposited in sequence;

[0026] The deposited N-type composite layer includes an intrinsic amorphous silicon layer, and an N-type amorphous silicon layer or a microcrystalline silicon layer deposited in sequence.

[0027] In some embodiments, the N-type conductive composite layer is deposited first, and then the P-type conductive composite layer is deposited.

[0028] The deposited N-type conductive composite layer includes a tunneling oxide layer and a phosphorus-doped polysilicon layer deposited in sequence;

[0029] The deposited N-type conductive composite layer includes an intrinsic amorphous silicon layer, and a P-type amorphous silicon layer or a microcrystalline silicon layer deposited in sequence; among them, an annealing step is further included after the deposition of the N-type conductive composite layer.

[0030] In some embodiments, the first preset region further includes a connecting region extending from the first conductive region to the second conductive region; and / or the second preset region further includes a connecting region extending from the second conductive region to the first conductive region; the connecting region connects the first conductive region and the second conductive region;

[0031] The first preset functional layer further includes a connecting functional layer extending from the first conductive functional layer to the second conductive functional layer; and / or the second preset functional layer further includes a connecting functional layer extending from the second conductive functional layer to the first conductive functional layer.

[0032] On the one hand, an embodiment of the present application provides a method for manufacturing a back-contact solar cell, including: providing a pre-treated N-type silicon wafer substrate;

[0033] Depositing a first passivation layer on the back surface of the silicon wafer;

[0034] Attaching a first mask on the back surface of the silicon wafer to expose a first preset region corresponding to a first patterned opening, and the first preset region is a first conductive region;

[0035] Removing the first passivation layer corresponding to the first preset region to expose the N-type silicon wafer substrate;

[0036] Depositing a first conductive composite layer on the back surface of the silicon wafer, and mechanically removing the first mask to obtain a first preset functional layer;

[0037] Attach a second mask to the back side of the silicon wafer, exposing a second preset area corresponding to the second patterned opening, and the second preset area is a second conductive region;

[0038] Remove the second passivation layer corresponding to the second preset area to expose the N-type silicon wafer substrate;

[0039] Deposit a second conductive composite layer on the back side of the silicon wafer, and mechanically remove the second mask to form a second preset functional layer;

[0040] Attach a fourth mask to the back side of the silicon wafer, exposing a fourth preset area corresponding to the fourth patterned opening, and the fourth preset area is a communication area;

[0041] Remove the first passivation layer corresponding to the fourth preset area to expose the N-type silicon wafer substrate;

[0042] Deposit a third conductive composite layer, and mechanically remove the fourth mask to obtain a communication area functional layer.

[0043] In some embodiments, the first mask and / or the second mask and / or the fourth mask includes a polymer film layer and an adhesive layer that are attached to each other, and the polymer film layer is attached to the back side of the silicon wafer through the adhesive layer.

[0044] On the other hand, an embodiment of the present application provides a back-contact solar cell, which is prepared by using the preparation method of the back-contact solar cell in any one of the foregoing.

[0045] The beneficial effects of the embodiments of the present application include:

[0046] The embodiments of the present application provide a preparation method for a back-contact solar cell, which can complete the preparation of the communication functional layer. Each communication functional layer has electrical conductivity, and its two ends are respectively connected to the P region and the N region. Even if the back-contact battery is blocked, the current can be transmitted through the P region, the communication functional layer, and the N region, reducing the hot spot risk of the photovoltaic module. Description of the Drawings

[0047] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0048] Figure 1 It is one of the schematic diagrams of the preparation process of a back-contact solar cell provided by the embodiments of the present application;

[0049] Figure 2Schematic diagram II of the preparation process of a back-contact solar cell provided by an embodiment of the present application;

[0050] Figure 3 Schematic diagram III of the preparation process of a back-contact solar cell provided by an embodiment of the present application;

[0051] Figure 4 Schematic diagram IV of the preparation process of a back-contact solar cell provided by an embodiment of the present application;

[0052] Figure 5 Schematic diagram V of the preparation process of a back-contact solar cell provided by an embodiment of the present application;

[0053] Figure 6 Schematic diagram VI of the preparation process of a back-contact solar cell provided by an embodiment of the present application;

[0054] Figure 7 Schematic diagram VII of the preparation process of a back-contact solar cell provided by an embodiment of the present application;

[0055] Figure 8 Schematic diagram VIII of the preparation process of a back-contact solar cell provided by an embodiment of the present application;

[0056] Figure 9 Schematic diagram IX of the preparation process of a back-contact solar cell provided by an embodiment of the present application;

[0057] Figure 10 Schematic diagram X of the preparation process of a back-contact solar cell provided by an embodiment of the present application;

[0058] Figure 11 Schematic diagram XI of the preparation process of a back-contact solar cell provided by an embodiment of the present application;

[0059] Figure 12 Schematic diagram I of the preparation process of a back-contact solar cell provided by another embodiment of the present application.

[0060] Description of reference numerals:

[0061] 100 - N-type silicon wafer substrate; 110 - First passivation layer; 120 - P-type conductive composite layer; 130 - N-type conductive composite layer; 200 - First mask; 300 - Second mask; 20 - P-region functional layer; 30 - N-region functional layer; 40 - Isolation region functional layer; 50 - Connecting region functional layer; 51 - First connecting region functional layer; 52 - Second connecting region functional layer;

[0062] A - First preset region; B - P region; C1 - First connecting region; C2 - Second connecting region; D - Second preset region; F - N region. Detailed implementation manners

[0063] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some, but not all, of the embodiments of the present application. It should be noted that, without conflict, the various features in the embodiments of the present application may be combined with each other, and the combined embodiments are still within the protection scope of the present application.

[0064] In the description of the present application, it should be noted that unless otherwise clearly defined, the orientation or positional relationship indicated by the terms "upper", "lower", "left", "right", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, and thus cannot be construed as a limitation to the present application. In addition, unless otherwise clearly defined, the terms "first", "second", "third", etc. are only used for descriptive distinction and cannot be construed as indicating or implying relative importance.

[0065] In the following description, for a silicon wafer substrate and a silicon wafer substrate that has only been pretreated, the silicon wafer substrate is described; for the semi-finished product in the process of manufacturing a back-contact solar cell, the silicon wafer is described; for the finished product after electrode preparation, the battery is described; the battery has an opposite light-receiving surface and backlight surface, and the surface corresponding to the backlight surface of the battery is described as the back surface; those skilled in the art can understand that the silicon wafer substrate and the silicon wafer can represent the same state description in a specific application scenario. Back-contact (BC) batteries generally have the following classifications: TBC (Tunnel oxide passivated contact BackContact), that is, a tunnel oxide passivated back-contact battery; HBC (Heterojunction Back Contact), that is, a heterojunction back-contact battery; HTBC (Heterojunction and Tunnel oxide passivated contact BackContact), that is, a hybrid back-contact battery applying tunnel oxide passivation and heterojunction technology.

[0066] On the one hand, an embodiment of the present application provides a method for manufacturing a back-contact solar cell, as Figure 1 shown, the method for manufacturing a back-contact solar cell according to the embodiment of the present application includes:

[0067] S001. Provide a pretreated N-type silicon wafer substrate.

[0068] It should be noted that on the back of the N-type silicon wafer substrate, a first conductive functional layer and a second conductive functional layer that intersect with each other are to be prepared. There is a gap between adjacent first conductive functional layers and second conductive functional layers. A connection area functional layer is provided at some of the gap positions between the first conductive functional layer and the second conductive functional layer, and an isolation area functional layer is provided at the remaining positions. Among them, the structure of the connection area functional layer can be the same as that of the first conductive functional layer, extending from the first conductive functional layer to the second conductive functional layer. The connection area functional layer can also be the same as the second conductive functional layer, extending from the second conductive functional layer to the first conductive functional layer. Or, the connection area functional layer extends from the first conductive functional layer to the second conductive functional layer. The part close to the first conductive functional layer is the same as the first conductive functional layer, and the part close to the second conductive functional layer is the same as the second conductive functional layer. The isolation area functional layer is a non-conductive functional layer. Hereinafter, the area corresponding to the first conductive functional layer on the silicon wafer substrate is called the first conductive area, the area corresponding to the second conductive functional layer is called the second conductive area, the area corresponding to the connection area functional layer is called the connection area, and the area corresponding to the isolation area functional layer is called the isolation area. The conductivity type of the first conductive functional layer is opposite to that of the second conductive functional layer, that is, they have opposite polarities. For example, they can be N-type doping and P-type doping respectively, and are called the N-region functional layer and the P-region functional layer, and their corresponding regions are called the N-region and the P-region respectively.

[0069] S002. Deposit a first passivation layer on the back of the silicon wafer;

[0070] S003. Attach a first mask to the back of the silicon wafer. The first mask has a first patterned opening. After attaching the first mask to the back of the silicon wafer, the first preset area is exposed at the position of the first patterned opening. Among them, the first preset area includes the first conductive area and may also include the connection area.

[0071] The first mask is a mask obtained by patterning and hollowing out a mask to form a mask with a first patterned opening.

[0072] S004. Remove the first passivation layer in the first preset area to expose the N-type silicon wafer substrate at the corresponding position.

[0073] S005. Deposit a first conductive composite layer on the back of the silicon wafer, and mechanically remove the first mask to form a first preset functional layer. Among them, the first preset functional layer includes the first conductive functional layer and may also include the connection area functional layer.

[0074] S006. Attach a second mask to the back of the silicon wafer. The second mask has a second patterned opening. After attaching the second mask to the back of the silicon wafer, the second preset area is exposed at the position of the second patterned opening. The second preset area includes the second conductive area and may also include the connection area.

[0075] The second mask is a patterned and hollowed mask, forming a mask with second patterned openings.

[0076] Wherein, there is a gap between the first conductive region and the second conductive region, and the connection region is located at a partial position of this gap.

[0077] S007. Remove the first passivation layer in the second preset region, and expose the N-type silicon wafer substrate at the corresponding position.

[0078] S008. Deposit a second conductive composite layer, and mechanically remove the second mask to form a second preset functional layer; wherein, the second preset functional layer includes a second conductive functional layer, and may also include a connection region functional layer.

[0079] Wherein, the second conductive composite layer is deposited on the entire back surface of the silicon wafer, will be deposited on the second mask entity, and will also be deposited in the region corresponding to the second patterned opening of the second mask. Removing the second mask can achieve the removal of the second conductive composite layer on the entity, that is, the region other than the region corresponding to the second patterned opening.

[0080] At this time, a first conductive functional layer, a second conductive functional layer, and a connection region functional layer are formed. And because there is a gap between the adjacent first conductive region and the second conductive region, no conductive functional layer is formed at the positions of this gap except for the position of the connection region functional layer, and the corresponding first passivation layer is retained, thereby achieving an isolation effect and naturally forming an isolation region functional layer.

[0081] The first conductive composite layer and the second conductive composite layer may include one or more of a tunneling passivation layer, a doped polysilicon layer, a doped amorphous silicon layer, or a doped nanocrystalline silicon layer sequentially arranged from the silicon wafer substrate outward; the first conductive composite layer and the second conductive composite layer may also include an intrinsic amorphous silicon layer and a doped amorphous silicon layer sequentially arranged from the silicon wafer substrate outward.

[0082] Wherein, the conductive types of the first conductive composite layer and the second conductive composite layer are opposite. For example, the first conductive composite layer is N-type and the second conductive composite layer is P-type, or the first conductive composite layer is P-type and the second conductive composite layer is N-type.

[0083] S010. Prepare an electrode on the back surface of the silicon wafer to obtain a back-contact solar cell.

[0084] Optionally, before S010, it further includes S009 annealing treatment. Specifically, the annealing temperature is between 800 °C and 950 °C. As an implementation manner, when the first conductive composite layer or the second conductive composite layer includes a tunneling passivation layer and a doped polysilicon layer sequentially arranged from the silicon wafer substrate outward, annealing treatment is required.

[0085] Among them, steps S003 to S005 and steps S006 to S008 are respectively used to form a first conductive functional layer and a second conductive functional layer that cross each other on an N-type silicon wafer substrate. Of course, an isolation region functional layer and a connection region functional layer between the first conductive functional layer and the second conductive functional layer are also formed simultaneously.

[0086] It should be noted that the connection regions of the first preset region and the connection regions of the second preset region can be located at different positions and extend towards the corresponding opposite conductive regions until they are connected; they can also be located at the same or adjacent positions and extend towards each other to form a connection in the connection region, as long as a connection can be formed.

[0087] It should be noted that at least one of the first preset functional layer or the second preset functional layer includes a connection region functional layer; in other words, at least one of the first preset region and the second preset region includes a connection region; in other words, at least one of the first patterned opening or the second patterned opening includes an opening corresponding to the connection region.

[0088] For a clearer description of the method steps, specific examples are used for specific illustration below.

[0089] Embodiment 1

[0090] The preparation method of the back-contact solar cell according to the embodiment of the present application includes:

[0091] S101, as Figure 1 shown, provide a pretreated N-type silicon wafer substrate 100.

[0092] First, perform pretreatment on the N-type silicon wafer substrate 100, such as processes like texturing and polishing.

[0093] S102, as Figure 2 shown, deposit a first passivation layer 110 on the back surface of the silicon wafer.

[0094] Deposit a first passivation layer 110 on the back surface of the silicon wafer, that is, the N-type silicon wafer substrate 100, so as to provide a whole-layer or whole-surface protection for the N-type silicon wafer substrate 100. In this way, when in subsequent steps, it is necessary to mechanically remove the layers above the first passivation layer 110, such as removing the mask layer or removing the layer including the mask and the layer covering the mask, even if the torn layer is adhered to the first passivation layer 110, due to the existence of the first passivation layer 110, the N-type silicon wafer substrate 100 can be effectively protected from being damaged or injured during the tearing process.

[0095] Similarly, in subsequent steps, before the layer to be torn off is formed, in order to protect the underlying layer, a passivation layer can be preset to protect against the adverse effects that the tearing action may cause. Among them, the material of the set passivation layer can be the same as that of the first passivation layer 110 or different, and the thickness can also be set as needed, as long as the set passivation layer can protect the underlying layer when tearing off its upper layer.

[0096] Specifically, the first passivation layer 110 is any one or more of a silicon nitride layer, a silicon oxide layer, or a silicon oxynitride layer, and the thickness of the first passivation layer 110 is between 20 and 80 nm.

[0097] The first passivation layer 110 is formed by depositing a silicon nitride material (SiNx) or a silicon oxide material (SiOx), and the thickness of the first passivation layer 110 is controlled between 20 and 80 nm.

[0098] S103. Refer to Figure 3 , attach the first mask 200 to the back of the silicon wafer. The first mask 200 has a first patterned opening; after the first mask 200 is attached to the first passivation layer 110, the position corresponding to the first patterned opening exposes a first preset area A, where the first preset area includes a first conductive area and also includes a first connection area C1. In this embodiment, the first conductive area is described as the P region B, and the second conductive area is the N region F.

[0099] Those skilled in the art should understand that the fitting size of the first mask 200 on the back of the silicon wafer should generally be basically the same as or slightly larger than the size of the N-type silicon wafer substrate 100, so as to cover completely and be easy to tear off. After the first mask 200 is attached, the first patterned opening of the first mask 200 corresponds to the first preset area A.

[0100] In this embodiment, a back-contact solar cell with a main grid is to be prepared. Correspondingly, both the P region and the N region include interdigitated regions extending along the first direction ( Figure 11 horizontal direction), and the interdigitated regions of the two are arranged alternately. The P region and the N region can also respectively include connection regions along the second direction ( Figure 11 vertical direction), which are respectively connected to a plurality of finger portions of the same polarity. Those skilled in the art can understand that fine grid electrodes will be prepared at the positions corresponding to the interdigitated regions, and main grid electrodes will be prepared at the positions corresponding to the connection regions. Those skilled in the art should know that the solution of the present application is also applicable to the preparation of back-contact solar cells without a main grid.

[0101] It should be noted that for the bonding of the first mask 200 to the back surface of the silicon wafer, those skilled in the art can, according to actual working needs, choose to bond the mask to the back surface of the silicon wafer first and then perform patterning and hollowing on the film layer to obtain the first mask 200, or choose to perform patterning and hollowing on the mask first to form the first mask 200 and then bond it to the back surface of the silicon wafer. In the embodiments of the present application, for example, first perform patterning and hollowing on the mask to form the first mask 200, and then bond the first mask 200 to the back surface of the silicon wafer. In this way, on the one hand, patterning the first mask 200 on an external device can avoid damaging the first passivation layer 110 on the back surface of the silicon wafer or the N-type silicon wafer substrate 100 under the first passivation layer 110 during the patterning process; on the other hand, performing dedicated patterning on an external device is also beneficial to the accuracy of the pattern formation on the first mask 200.

[0102] The first mask 200 is a mask obtained by patterning and hollowing a mask to form a mask with a first patterned opening. Specifically, the first mask 200 can be formed by using a laser to perform patterning and hollowing on the mask.

[0103] It should also be noted that in the embodiments of the present application, a laser is used to perform patterning and hollowing on the mask to obtain the first mask 200. For example, in the embodiments of the present application, the laser used for patterning is a laser beam with a wavelength of 0.3 μm to 12 μm, and it is carried out in a pulse mode, a quasi-continuous mode or a continuous mode according to needs. The laser pulse width is ps (picosecond) or ns (nanosecond), and the light energy distribution is a Gaussian distribution or a flat-top distribution. A circular spot or a square spot is selected, and the spot size is usually between 10 and 500 μm.

[0104] The first mask 200 includes a polymer film layer and an adhesive layer that are bonded to each other, and the polymer film layer is bonded to the back surface of the silicon wafer through the adhesive layer.

[0105] In order to make the first mask 200 better bond to the back surface of the silicon wafer, the first mask 200 includes a polymer film layer and an adhesive layer that are bonded to each other, and the polymer film layer is bonded to the back surface of the silicon wafer through the adhesive layer. In this way, it is equivalent to adding an adhesive layer to ensure that the effective structural layer of the first mask 200 is closely bonded to the back surface of the silicon wafer. Moreover, the effective structural layer of the first mask 200 is selected as a polymer material film layer.

[0106] Optionally, the polymer film layer is prepared from a material with a temperature resistance greater than 350 °C. The thickness of the polymer film layer is between 5 and 100 μm, preferably between 5 and 50 μm, and the thickness of the adhesive layer is between 3 and 10 μm.

[0107] The polymer film layer is prepared from a material with a heat resistance greater than 350 °C to ensure that the film layer material will not be adversely affected during the laser patterning and hollowing process, and also effectively improve the accuracy of forming the first mask 200 by patterning. Specifically, the heat resistance usually refers to the glass transition temperature of the polymer film layer. The thickness of the polymer film layer is set between 5 and 100 μm, preferably between 5 and 50 μm, and the thickness of the adhesive layer is between 3 and 10 μm, ensuring that the polymer film layer has sufficient thickness to form a mask pattern, ensuring the bonding force of the adhesive layer and avoiding the adverse impact of an overly thick adhesive layer on the accuracy of the mask pattern. At the same time, the polymer film uses a material with a heat resistance greater than 350 °C, which is also more friendly to the subsequent process of depositing the back amorphous silicon layer.

[0108] Similarly, the second mask 300 can also adopt the same material and layer thickness settings as the first mask 200 described above.

[0109] S104. Solution cleaning to remove the first passivation layer 110 of A in the first preset area, and the N-type silicon wafer substrate 100 is exposed at the corresponding position.

[0110] As Figure 4 shown, for example, the N-type silicon wafer substrate 100 attached to the first mask 200 is cleaned with an HF solution. The first passivation layer 110 corresponding to the first patterned opening in the first mask 200 reacts with the HF solution and is removed, and the N-type silicon wafer substrate 100 is directly exposed in the first patterned opening area. The first passivation layer 110 in other positions is retained due to the coverage of the first mask 200.

[0111] S105. Refer to Figure 5 and Figure 6 , deposit a P-type conductive composite layer 120 on the back of the silicon wafer, and mechanically remove the first mask 200. The P-type conductive composite layer 120 on the first mask 200 is removed, and the P-type conductive composite layer 120 in the area corresponding to the first patterned opening is retained, obtaining a P-region functional layer 20 and a first communication-region functional layer 51.

[0112] Then, as Figure 6 shown, the first mask 200 is removed mechanically. Since the solid material of the first mask 200 is located in the N region and the isolation region, after removing the first mask 200, the part of the P-type conductive composite layer 120 in the N region and the isolation region that is located on the first mask 200 is removed accordingly, and the P-type conductive composite layer 120 forms a pattern corresponding to the first patterned opening. Among them, due to the design of the first mask 200, the isolation region and the communication region always exist between the P region and the N region before the first mask 200 is torn off. Thus, during the preparation process of the P region and the N region, the preparation of the isolation-region functional layer and the communication-region functional layer is completed simultaneously.

[0113] It should be noted that, for example, after depositing the P-type conductive composite layer 120 on the back surface of the silicon wafer, in order to facilitate the integrity and convenience of the mechanical removal of the first mask 200, a passivation layer can be deposited again. The re-deposited passivation layer is made of the same material as the first passivation layer 110. In this way, the re-deposited passivation layer can protect the underlying P-type conductive composite layer 120 and prevent substances such as colloids from remaining on the P-type conductive composite layer 120 when the first mask 200 is mechanically torn off, thus being more conducive to the thoroughness and integrity of the formed pattern. At the same time, this re-deposited passivation layer can increase the thickness of the isolation region functional layer 40 and achieve a better electrical isolation effect.

[0114] Specifically, in this embodiment, depositing the P-type conductive composite layer 120 includes in-situ doping methods, such as successively depositing a tunneling oxide layer and a boron-doped polysilicon layer using related equipment and technologies such as LPCVD, PECVD, and HWCVD.

[0115] S106, as Figure 7 shown, attach the second mask 300 to the back surface of the silicon wafer. The second mask 300 has a second patterned opening; after attaching the second mask 300 to the back surface of the silicon wafer, the second preset region D is exposed. In this embodiment, the second preset region D includes the N region F and the second communication region C2;

[0116] There is a gap between the adjacent P region B and the N region F. The positions corresponding to this gap include communication regions such as the first communication region C1 and the second communication region C2, and the remaining positions are isolation regions.

[0117] Those skilled in the art should understand that the attachment size of the second mask 300 on the back surface of the silicon wafer should generally be basically the same as or slightly larger than the size of the N-type silicon wafer substrate 100 to ensure complete coverage and easy removal. After attaching the second mask 300, the second patterned opening of the second mask 300 corresponds to the second preset region D.

[0118] The second mask 300 is a mask formed by patterning and hollowing out the mask to form a mask with a second patterned opening. Specifically, the second mask 300 can be formed by patterning and hollowing out the mask using a laser method.

[0119] Similarly, for the attachment of the second mask 300 on the back surface of the silicon wafer and the laser patterning and hollowing out process of the second mask 300, those skilled in the art can choose the preparation sequence according to the actual working needs.

[0120] It should also be noted that the sequence of patterning the P region through the first mask 200 and patterning the N region through the second mask 300 is not limited to the sequence shown in the embodiments of the present application. The P region and the N region need to be prepared separately in sequence, and the sequence is not limited.

[0121] S107. Perform solution cleaning to remove the first passivation layer 110 in the second preset region D, and expose the N-type silicon wafer substrate 100 at the corresponding position.

[0122] As Figure 8 shown, for example, use an HF solution to clean the N-type silicon wafer substrate 100 forming the second mask 300. The first passivation layer 110 corresponding to the second patterned opening of the second mask 300 reacts with the HF solution and is removed, and the N-type silicon wafer substrate 100 is directly exposed in the second patterned opening region. The first passivation layer 110 or the P-region functional layer 20 and the first communication region functional layer 51 at other positions are retained due to the coverage of the first mask 200.

[0123] S108. Refer to Figure 9 and Figure 10 . Deposit an N-type conductive composite layer 130 on the back of the silicon wafer, and mechanically remove the second mask 300. The N-type conductive composite layer 130 on the second mask 300 is removed, and the N-type conductive composite layer 130 in the second patterned opening region is retained, obtaining the N-region functional layer 30 and the second communication region functional layer 52. It can be understood that there is a gap between adjacent P regions B and N regions F. Between the P region B and the N region F, except for the passivation layer at the positions of the first communication region C1 and the second communication region C2 being retained, it naturally constitutes the isolation region functional layer 40.

[0124] As Figure 9 shown, deposit an N-type conductive composite layer 130 on the back of the silicon wafer after solution cleaning.

[0125] Then, as Figure 10 shown, use a mechanical method to remove the second mask 300. Since the solid material of the second mask 300 is located in the P region and the isolation region, after removing the second mask 300, the part of the N-type conductive composite layer 130 in the P region and the isolation region that is located on the second mask 300 is removed accordingly, and the N-type conductive composite layer 130 is formed into a pattern corresponding to the second patterned opening. In this way, during the entire process, the isolation region and the communication region are always located between the P region and the N region. While preparing the P-region functional layer 20 and the N-region functional layer 30, the isolation region functional layer 40 and the communication region functional layer 50 are also prepared.

[0126] Similarly, after depositing the N-type conductive composite layer 130, in order to facilitate the integrity and convenience of the mechanical removal of the second mask 300, a passivation layer may be further deposited on the N-type conductive composite layer 130. The re-deposited passivation layer is made of the same material as the first passivation layer 110. In this way, the re-deposited passivation layer can protect the underlying N-type conductive composite layer 130 from being contaminated or damaged during the manufacturing process, and can prevent substances such as colloids from remaining on the N-type conductive composite layer 130 when the second mask 300 is mechanically removed, thus being more conducive to the thoroughness and integrity of the formed pattern.

[0127] Specifically, in this embodiment, depositing the N-type conductive composite layer 130 includes in-situ doping methods, such as successively depositing a tunneling oxide layer and a phosphorus-doped polysilicon layer using relevant equipment and technologies such as LPCVD, PECVD, and HWCVD.

[0128] S109. Annealing treatment. Among them, the annealing temperature is between 800 °C and 950 °C.

[0129] The annealing treatment includes annealing to form a P+ polysilicon layer and an N+ polysilicon layer.

[0130] S200. Prepare the second passivation layer.

[0131] The second passivation layer can be prepared on the front and back sides of the silicon wafer. A first antireflection layer can be deposited on the front side of the silicon wafer, or a second antireflection layer can be deposited on the back side of the silicon wafer. Those skilled in the art know that the antireflection layer also has a passivation effect, realizing the preparation of the second passivation layer on the front and back sides of the silicon wafer. Among them, the first antireflection layer is formed of alumina, silicon nitride, or silicon oxide materials into at least one layer or a combination of multiple layers, and the second antireflection layer is formed of silicon oxide, silicon nitride, or silicon oxynitride materials into at least one layer or a combination of multiple layers.

[0132] Specifically, as an alternative implementation, it includes,

[0133] S201. Deposit a first antireflection layer on the front side of the silicon wafer. The first antireflection layer is formed of alumina, silicon nitride, or silicon oxide materials into at least one layer.

[0134] S202. Deposit a second antireflection layer on the back side of the silicon wafer. The second antireflection layer is formed of silicon oxide, silicon nitride, or silicon oxynitride materials into at least one layer.

[0135] S110. Prepare electrodes on the back side of the silicon wafer to obtain a back-contact solar cell.

[0136] Specifically, print positive and negative electrodes by contact or non-contact methods and perform drying and sintering and other treatments to complete the electrode preparation.

[0137] It should also be noted that in the method for preparing the back-contact solar cell according to the embodiment of the present application, other steps such as cleaning, polishing, and planarization may also be included. For example, after the annealing treatment step, a cleaning step for the formed sample may be included, and the sample can also be cleaned with an HF solution to remove the material of the first passivation layer 110 still remaining on the surface of the sample.

[0138] It should be noted that in this embodiment, both the first preset region A and the second preset region D include a communication region, and the first communication region C1 of the first preset region A and the second communication region C2 of the second preset region D are located at different positions. During implementation, as long as either the first preset region A or the second preset region D includes a communication region, or only the positions of the first patterned opening and the second patterned opening of the first mask 200 and the second mask 300 need to be correspondingly set.

[0139] In another implementation manner, both the first preset region A and the second preset region D have a communication region, and the two communication regions together form a communication region connecting from the P region to the N region. The communication region of the first preset region A and the communication region of the second preset region D extend towards each other and are connected to form a communication region.

[0140] Both the P region and the N region include a P-region finger region and an N-region finger region extending along the first direction, and the two are alternately arranged. The P region and the N region also respectively include a P-region connection region and an N-region connection region along the second direction, which are respectively connected to the corresponding multiple P-region finger regions and N-region finger regions.

[0141] Although as Figure 10 shown in the embodiment, the communication region is located between the P-region finger region and the N-region connection region, the present application is not limited thereto, and it may be located between the P-region finger region and the N-region finger region, or between the N-region finger region and the P-region connection region. Refer to Figure 11 , which shows the situation where the communication region is located at different positions.

[0142] It should be noted that the isolation region is located between the P region and the N region. Those skilled in the art should know that generally, in order to make the effective areas of the P region and the N region as large as possible, the isolation region should occupy as small an area as possible on the basis of ensuring the isolation effect, so as to ensure the electrical performance of the battery. By using the method of the present application, the set width of the isolation region is between 20 and 60 μm, preferably 20 to 40 μm, and more preferably, the width of the isolation region can be set between 20 and 30 μm.

[0143] Actually, the connected regions are also located between the P region and the N region. Preferably, there are multiple connected regions, and they are arranged at intervals with the isolation regions. The width of the connected regions is the same as that of the isolation regions, and the length can be 50 - 500 μm, and the range value or point value therein is preferably 50 - 150 μm. Among them, for the case with connection regions, in the extending direction of the connection regions, one connected region is arranged within 3 - 15 mm; in the direction perpendicular to the extending direction of the connection regions, one or multiple connected regions can be arranged between adjacent connection regions.

[0144] As another implementation manner, the structures of the P region and the N region are as follows. Refer to Figure 12 , in this embodiment, a back-contact solar cell without a main grid is to be prepared. Correspondingly, both the P region and the N region include finger regions extending along the first direction, and the finger regions of the two are alternately arranged in the second direction. Those skilled in the art can understand that fine grid electrodes will be prepared at the positions corresponding to the finger regions. At this time, the connected regions are arranged between the finger regions of the P region and the N region, and a connected region is arranged between every two adjacent finger regions. A connected region can also be arranged between some of the finger regions of the P region and the N region.

[0145] Those skilled in the art can understand that by adopting the technical solution of Embodiment 1, the preparation of the TBC solar cell can be completed.

[0146] Embodiment 2

[0147] The rest of this embodiment is the same as that of Embodiment 1, and the differences lie in steps S105, S108, S109, and S110.

[0148] As another implementation manner, the preparation of the HBC solar cell can be carried out. The rest of this embodiment is similar to that of Embodiment 1, and the differences lie in S105 and S108, and S109, S110.

[0149] S105. Depositing a P-type conductive composite layer 120 on the back surface of the silicon wafer is

[0150] Successively depositing an intrinsic amorphous silicon i-a Si layer and a P-type amorphous silicon P a-Si layer or a P-type microcrystalline silicon Pμ-Si layer by chemical vapor deposition, such as a boron-doped amorphous silicon layer or a boron-doped microcrystalline silicon layer.

[0151] Among them, the chemical vapor deposition method can be, for example, plasma-enhanced chemical vapor deposition (PECVD), hot-wire chemical vapor deposition (HWCVD), etc., and no specific limitation is made in this embodiment of the present application.

[0152] S108. Depositing an N-type conductive composite layer 130 on the back surface of the silicon wafer includes

[0153] An intrinsic amorphous silicon ia Si layer, and an N-type amorphous silicon Na-Si layer or an N-type microcrystalline silicon Nμ-Si layer, such as a phosphorus-doped amorphous silicon layer or a phosphorus-doped microcrystalline silicon layer, are sequentially deposited by chemical vapor deposition.

[0154] Similarly, chemical vapor deposition methods such as plasma enhanced chemical vapor deposition (PECVD), hot wire chemical vapor deposition (HWCVD), etc. can also be used, which is not specifically limited in the embodiments of the present application.

[0155] In this embodiment, step S109 does not need to be performed.

[0156] S110, preparing electrodes on the back side of the silicon wafer to obtain a back-contact solar cell.

[0157] The specific method is to prepare a transparent conductive film such as a TCO film, and then print positive and negative electrodes in a contact or non-contact manner and perform drying and sintering to complete the electrode preparation.

[0158] It is understandable that when preparing the TCO film, the TCO film in the remaining area except the N area can be removed by laser etching after the entire surface is deposited. It can also be made by a mask method, where a third mask is attached to the first passivation layer 110, and the third mask has a third patterned opening; after the third mask is attached to the first passivation layer 110, a third preset area is exposed through the third patterned opening, and the third preset area is the target position of the TCO film.

[0159] Example 3

[0160] The rest of this embodiment is similar to Embodiment 2, except that step S105 and step S108 are interchanged, that is, the N-region conductive functional layer is prepared first, and then the P-region conductive functional layer is prepared.

[0161] Example 4

[0162] As another embodiment, a HTBC solar cell can be prepared. The rest of this embodiment is the same as that of embodiment 1, except for S105, S108, S109 and S110. This embodiment also prepares the N region first and then the P region.

[0163] Among them, S105, in order to deposit an N-type conductive composite layer on the back side of the silicon wafer, the first mask is mechanically removed, the N-type conductive composite layer located on the first mask is removed, and the N-type conductive composite layer in the area corresponding to the first patterned opening is retained to obtain an N-region functional layer.

[0164] Depositing the N-type conductive composite layer includes,

[0165] In this embodiment, the deposition of the N-type conductive composite layer 130 includes sequentially depositing a tunneling oxide layer and a phosphorus-doped polysilicon layer by means of in-situ doping, such as using related equipment and technologies like LPCVD, PECVD, HWCVD, etc.

[0166] After step S105, step S109 is further included.

[0167] S108 is to deposit a P-type conductive composite layer on the back of the silicon wafer, mechanically remove the second mask, the P-type conductive composite layer on the second mask is removed, and the P-type conductive composite layer in the corresponding area of the second patterned opening is retained to obtain the P-region functional layer.

[0168] Deposit an intrinsic amorphous silicon i-a Si layer and a P-type amorphous silicon P a-Si layer or a microcrystalline silicon Pμ-Si layer in sequence by chemical vapor deposition, such as a boron-doped amorphous silicon layer or a boron-doped microcrystalline silicon layer.

[0169] Among them, the chemical vapor deposition method can be, for example, plasma-enhanced chemical vapor deposition (PECVD), hot-wire chemical vapor deposition (HWCVD), etc., which are not specifically limited in the embodiments of the present application.

[0170] S110. Prepare electrodes on the back of the silicon wafer to obtain a back-contact solar cell.

[0171] The specific method is to prepare a TCO thin film. Among them, only prepare the TCO thin film at the corresponding position of the N region, and then contact or non-contact print the positive and negative electrodes and perform drying and sintering and other treatments to complete the electrode preparation.

[0172] It can be understood that when preparing the TCO thin film, after depositing the whole surface, the TCO thin film in the regions other than the N region can be removed by laser etching. It can also be made by the mask method. Attach a third mask to the silicon wafer. The third mask has a third patterned opening; after attaching the third mask to the silicon wafer, expose the third preset region through the third patterned opening, and the third preset region is the target position of the TCO thin film.

[0173] A back-contact solar cell and its preparation method provided by the present application complete the preparation of the isolation region functional layer and the connection region functional layer while preparing the N region and the P region, making the entire preparation process simple and easy to implement, providing convenience for subsequent process treatments, and reducing the hot spot risk.

[0174] On the other hand, an embodiment of the present application provides a preparation method of a back-contact solar cell, the rest being the same as the foregoing embodiment, except that neither the first preset region A nor the second preset region D includes a connection region, and the connection region is formed by an independent step. The connection region functional layer structure can be the same as or different from the P-region functional layer structure or the N-region functional layer structure.

[0175] Specifically, the steps include providing a pre-treated N-type silicon wafer substrate;

[0176] Depositing a first passivation layer on the back surface of the N-type silicon wafer substrate;

[0177] Bonding a first mask on the first passivation layer, wherein the first mask has a first patterned opening. After bonding the first mask on the first passivation layer, a first preset area corresponding to the first patterned opening is exposed, and the first preset area is a first conductive region;

[0178] Removing the first passivation layer corresponding to the first preset area to expose the N-type silicon wafer substrate;

[0179] Depositing a first conductive composite layer and mechanically removing the first mask to obtain a first preset functional layer;

[0180] Bonding a second mask on the silicon wafer, wherein the second mask has a second patterned opening. After bonding the second mask on the first passivation layer, a second preset area corresponding to the second patterned opening is exposed, and the second preset area is a second conductive region;

[0181] Removing the second passivation layer corresponding to the second preset area to expose the N-type silicon wafer substrate;

[0182] Depositing a second conductive composite layer and mechanically removing the second mask to form a second preset functional layer;

[0183] Bonding a fourth mask on the silicon wafer, wherein the fourth mask has a fourth patterned opening. After bonding the fourth mask on the silicon wafer, a fourth preset area corresponding to the fourth patterned opening is exposed, and the fourth preset area is a communication area;

[0184] Removing the first passivation layer corresponding to the fourth preset area to expose the N-type silicon wafer substrate;

[0185] Depositing a third conductive composite layer and mechanically removing the fourth mask to obtain a communication area functional layer.

[0186] By using this method, during the process of preparing the P region and the N region, the preparation of the isolation area functional layer is completed, and by using a similar mask process, the preparation of the communication area functional layer is completed, reducing the hot spot risk.

[0187] On the other hand, an embodiment of the present application provides a back-contact solar cell prepared by using the preparation method of the back-contact solar cell in any one of the foregoing.

[0188] The back-contact solar cell provided by the embodiment of the present application includes, but is not limited to, the TBC cell, HBC cell, and HTBC cell exemplified above, and is prepared by using the preparation method of the back-contact solar cell of any one of the foregoing. Since the mask preparation process unique to the present application is adopted in the preparation method, the patterning of the P region, N region, PN isolation region, and connection region is alternately realized in the form of a thin-film mask in the preparation process, making the entire preparation process simple and easy to implement, providing convenience for subsequent process treatment, and reducing the risk of hot spots. The above description is based on the N-type silicon wafer substrate 100 as an example, but the embodiment of the present application is not limited thereto, and the P-type silicon wafer substrate is also applicable to the technical solution of the present application.

[0189] The foregoing is only the preferred embodiment of the present application and is not used to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a back-contact solar cell, characterized in that, Comprising: Providing a pre-treated N-type silicon wafer substrate; Depositing a first passivation layer on the back side of the silicon wafer; Bonding a first mask on the back side of the silicon wafer to expose a first preset area corresponding to a first patterned opening, the first preset area including a first conductive region; Removing the first passivation layer corresponding to the first preset area to expose the N-type silicon wafer substrate; Depositing a first conductive composite layer on the back side of the silicon wafer, and mechanically removing the first mask to obtain a first preset functional layer, the first preset functional layer including a first conductive functional layer; Bonding a second mask on the back side of the silicon wafer to expose a second preset area corresponding to a second patterned opening, the second preset area including a second conductive region, and there is a gap between the first conductive region and the second conductive region; Removing the first passivation layer corresponding to the second preset area to expose the N-type silicon wafer substrate; Depositing a second conductive composite layer on the back side of the silicon wafer, and mechanically removing the second mask to form a second preset functional layer, the second preset functional layer including a second conductive functional layer with a conductive type opposite to that of the first conductive functional layer, and there is an isolation region functional layer and a connection region functional layer between the first conductive functional layer and the second conductive functional layer; Performing electrode preparation on the back side of the silicon wafer to obtain a back-contact solar cell.

2. The preparation method of the back-contact solar cell according to claim 1, characterized in that, The first conductive region is a P region, the first conductive composite layer is a P-type conductive composite layer, the second conductive region is an N region, and the second conductive composite layer is an N-type conductive composite layer; Or, the first conductive region is an N region, the first conductive composite layer is an N-type conductive composite layer, the second conductive region is a P region, and the second conductive composite layer is a P-type conductive composite layer.

3. The preparation method of the back-contact solar cell according to claim 2, characterized in that, The P region includes a plurality of P-region finger regions extending in a first direction, the N region includes a plurality of N-region finger regions extending in the first direction, and the P-region finger regions and the N-region finger regions are alternately arranged; the P region further includes a P-region connection region extending in a second direction, the P-region connection region is connected to a plurality of the P-region finger regions, the N region further includes an N-region connection region extending in the second direction, and the N-region connection region is connected to a plurality of the N-region finger regions, Wherein, the connection region is arranged between the P-region finger region and the N finger region, and / or between the P-region connection region and the N-region finger region, and / or between the N-region connection region and the P-region finger region.

4. The preparation method of the back contact solar cell according to claim 3, characterized in that: In the extending direction of the P-region connection region or the N-region connection region, one connection region is arranged within 3 to 15 mm, and in the direction perpendicular to the extending direction of the P-region connection region or the N-region connection region, one or more connection regions are arranged between adjacent connection regions.

5. The preparation method of the back-contact solar cell according to claim 2, characterized in that, The P region includes a plurality of P-region finger regions extending in a first direction, the N region includes a plurality of N-region finger regions extending in the first direction, and the P-region finger regions and the N-region finger regions are alternately arranged, wherein the connection region is arranged between the P-region finger region and the N finger region.

6. The preparation method of the back-contact solar cell according to claim 1, characterized in that, The first passivation layer is any one or more of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer.

7. The method for manufacturing a back-contact solar cell according to claim 2, wherein, The deposited P-type conductive composite layer includes a tunneling oxide layer and a boron-doped polysilicon layer deposited in sequence. The deposited N-type conductive composite layer includes a tunneling oxide layer and a phosphorus-doped polysilicon layer deposited in sequence.

8. The method for preparing a back-contact solar cell according to claim 2, wherein The deposited P-type conductive composite layer includes an intrinsic amorphous silicon layer, and a P-type amorphous silicon layer or a microcrystalline silicon layer deposited in sequence. The deposited N-type composite layer includes an intrinsic amorphous silicon layer, and an N-type amorphous silicon layer or a microcrystalline silicon layer deposited in sequence.

9. The manufacturing method of the back-contact solar cell according to claim 2, characterized in that: Deposit the N-type conductive composite layer first, and then deposit the P-type conductive composite layer. The deposited N-type conductive composite layer includes a tunneling oxide layer and a phosphorus-doped polysilicon layer deposited in sequence. The deposited P-type conductive composite layer includes an intrinsic amorphous silicon layer, and a P-type amorphous silicon layer or a microcrystalline silicon layer deposited in sequence; wherein, an annealing step after depositing the N-type conductive composite layer is further included.

10. The manufacturing method of the back-contact solar cell according to claim 1, characterized in that, The first preset region further includes a connecting region extending from the first conductive region to the second conductive region; and / or the second preset region further includes a connecting region extending from the second conductive region to the first conductive region; the connecting region connects the first conductive region and the second conductive region. The first preset functional layer further includes a connecting functional layer extending from the first conductive functional layer to the second conductive functional layer; and / or the second preset functional layer further includes a connecting functional layer extending from the second conductive functional layer to the first conductive functional layer.

11. A method for preparing a back-contact solar cell, characterized in that, Comprising: Provide a pre-treated N-type silicon wafer substrate. Deposit a first passivation layer on the back surface of the silicon wafer. Attach a first mask on the back surface of the silicon wafer, exposing a first preset region corresponding to a first patterned opening, and the first preset region is a first conductive region. Remove the first passivation layer corresponding to the first preset region, exposing the N-type silicon wafer substrate. Deposit a first conductive composite layer on the back surface of the silicon wafer, and mechanically remove the first mask to obtain a first preset functional layer. Attach a second mask on the back surface of the silicon wafer, exposing a second preset region corresponding to a second patterned opening, and the second preset region is a second conductive region. Remove the second passivation layer corresponding to the second preset region, exposing the N-type silicon wafer substrate. Deposit a second conductive composite layer on the back surface of the silicon wafer, and mechanically remove the second mask to form a second preset functional layer. Attach a fourth mask on the back surface of the silicon wafer, exposing a fourth preset region corresponding to a fourth patterned opening, and the fourth preset region is a connecting region. Remove the first passivation layer corresponding to the fourth preset region, exposing the N-type silicon wafer substrate. Deposit a third conductive composite layer, and mechanically remove the fourth mask to obtain a connecting region functional layer.

12. The method for preparing a back-contact solar cell according to any one of claims 1 to 11, wherein The first mask and / or the second mask and / or the fourth mask includes a polymer film layer and an adhesive layer that are attached to each other, and the polymer film layer is attached to the back surface of the silicon wafer through the adhesive layer.

13. A back-contact solar cell, characterized in that, Prepared by using the method for preparing a back-contact solar cell according to any one of claims 1 to 12.

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