Preparation method of local passivation structure and solar cell
By forming a tunneling layer and an intrinsic amorphous silicon layer on the silicon substrate and selective etching after oxidation and doping treatment, the problem of using a mask in the prior art is solved, and the process steps are simplified and cost reduction is achieved.
Patent Information
- Application Number
- CN202510432288.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-08
- Publication Date
- 2025-07-04
AI Technical Summary
The prior art requires the use of masks when preparing local passivation contact structures, resulting in increased production costs, and how to simplify process steps without using masks.
By sequentially forming a tunneling layer and an intrinsic amorphous silicon layer on the front and/or the back of the silicon substrate, the first part is subjected to oxidation and the second part is doped, respectively, and then the doped silicon oxide is selectively etched using an acid solution to remove the doped polysilicon, retaining the doped polysilicon.
The mask preparation and removal process is omitted, greatly simplifying the process steps and reducing production costs.
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Figure CN120264920A_ABST
Abstract
Description
Technical Field
[0001] This application mainly relates to the field of photovoltaic technology, and particularly relates to a preparation method of a local passivation structure and a solar cell. Background Art
[0002] Tunnel Oxide Passivated Contact (TOPcon) is a technology based on the principle of selective carrier passivation to reduce surface recombination and improve electrode contact. Using heavily doped polysilicon on the front side of a solar cell will lead to an increase in absorption loss. Currently, there are mainly two methods to reduce absorption loss: (1) thinning the front-side doped polysilicon layer; (2) selectively setting tunnel oxide passivated contact structures in local areas on the front side. Method (2) is the current mainstream method. Currently, methods for preparing local passivation contact structures all require the aid of a mask, which results in an increase in production cost. How to prepare local passivation contact structures without using a mask is one of the hot research topics in this field. Summary of the Invention
[0003] The technical problem to be solved by this application is to provide a preparation method of a local passivation structure and a solar cell, and the preparation method of the local passivation structure and the solar cell do not require the use of a mask during the preparation of the local passivation structure, which greatly simplifies the production process.
[0004] To solve the above technical problem, this application provides a preparation method of a local passivation structure, including: providing a silicon substrate having opposite front and back sides; sequentially forming a tunneling layer and an intrinsic amorphous silicon layer on the front side and / or the back side of the silicon substrate, the intrinsic amorphous silicon layer including an alternating first part and a second part; performing an oxidation treatment on the first part, and the first part is transformed into silicon oxide after the oxidation treatment; performing a doping treatment on the second part and the silicon oxide, and the second part and the silicon oxide are respectively transformed into doped polysilicon and doped silicon oxide after the doping treatment; and selectively etching and removing the doped silicon oxide using an acidic solution, and retaining the doped polysilicon.
[0005] In an embodiment of this application, the step of performing an oxidation treatment on the first part includes: injecting oxygen ions into the first part using an oxygen ion implantation process, and using an ion beam shadow mask to block the oxygen ions injected into the second part.
[0006] In an embodiment of this application, the dose of oxygen ion implantation is 1×10 15 atoms / cm 2 ~1×10 18 atoms / cm 2, the energy of oxygen ion implantation is 10 keV to 100 keV, the temperature of oxygen ion implantation is 25 °C to 200 °C, and the depth of oxygen ion implantation is 50 nm to 200 nm.
[0007] In one embodiment of the present application, the acidic solution includes one or more of hydrofluoric acid, hydrochloric acid, and phosphoric acid, and the concentration of the acid solution is 3 vol% to 10 vol%.
[0008] In one embodiment of the present application, the thickness of the intrinsic amorphous silicon layer is 50 nm to 200 nm, and the method for forming the intrinsic amorphous silicon layer includes low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, or physical vapor deposition.
[0009] In one embodiment of the present application, the step of doping the second part and the silicon oxide includes: using a high-temperature diffusion process to dope the second part and the silicon oxide.
[0010] In one embodiment of the present application, the temperature of the high-temperature diffusion process is 800 °C to 1000 °C, the driving time is 5 min to 60 min, and the surface peak doping concentration of the doped polysilicon is 1×10 19 cm -3 ~1×10 21 cm -3 , and the junction depth is 0.1 μm to 0.3 μm.
[0011] In one embodiment of the present application, the tunneling layer includes silicon dioxide, and the method for forming the tunneling layer includes thermal oxidation method, wet oxidation method, nitric acid oxidation method, ozone oxidation method, or vapor deposition method.
[0012] On the other hand, the present application also proposes a solar cell, which includes a silicon substrate, a local passivation structure including a tunneling layer and a doped polysilicon layer, and an electrode. The feature is that the local passivation structure is prepared by the preparation method described above.
[0013] In one embodiment of the present application, the tunneling layer is disposed on a local area of the front surface and / or the back surface of the silicon substrate, and exposes a part of the front surface and / or the back surface.
[0014] Compared with the prior art, the present application has the following advantages: The present application does not require the use of a mask during the preparation of the local passivation structure, which omits the process of preparing and removing the mask and greatly simplifies the process steps. Description of the Drawings
[0015] The accompanying drawings are provided to provide a further understanding of the present application. They are incorporated and constitute a part of the present application. The accompanying drawings illustrate the embodiments of the present application and, together with the description of the present application, serve to explain the principles of the present application. In the accompanying drawings:
[0016] Figure 1 is a schematic flow chart of a method for preparing a local passivation structure in an embodiment of the present application;
[0017] Figures 2 to 6 is a schematic cross-sectional view of an intermediate product of the preparation method in an embodiment of the present application;
[0018] Figure 7 is a schematic cross-sectional view of a solar cell in an embodiment of the present application.
[0019] Reference numerals:
[0020] Silicon substrate 210, silicon oxide 240
[0021] Front side 211, doped polysilicon 250
[0022] Back side 212, doped silicon oxide 260
[0023] Tunneling layer 220, gap 270
[0024] Intrinsic amorphous silicon layer 230, doped polysilicon 280
[0025] First part 231, electrode 290
[0026] Second part 232 Detailed implementation manners
[0027] To more clearly illustrate the technical solutions of the embodiments of the present application, the accompanying drawings required for the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some examples or embodiments of the present application. For those of ordinary skill in the art, without creative efforts, the present application can also be applied to other similar scenarios based on these drawings. Unless obvious from the language context or otherwise stated, the same reference numerals in the figures represent the same structures or operations.
[0028] As shown in the present application and the claims, unless the context clearly indicates an exceptional situation, words such as "a", "an", "one" and / or "the" are not specifically singular, but may also include plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of the clearly identified steps and elements, and these steps and elements do not constitute an exclusive list. The method or device may also include other steps or elements.
[0029] Unless otherwise specifically stated, the relative arrangements of components and steps, numerical expressions, and numerical values set forth in these embodiments do not limit the scope of this application. At the same time, it should be understood that, for the sake of convenience in description, the dimensions of the various parts shown in the drawings are not drawn in actual proportional relationship. Technologies, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such technologies, methods, and devices should be regarded as part of the authorization specification. In all the examples shown and discussed here, any specific value should be construed as merely exemplary and not as a limitation. Therefore, other examples of the exemplary embodiments may have different values. It should be noted that like reference numerals and letters denote like items in the following drawings, and thus, once an item is defined in one drawing, further discussion thereof is not required in subsequent drawings.
[0030] In the description of this application, it should be understood that the orientation or positional relationship indicated by orientation terms such as "front, rear, upper, lower, left, right", "lateral, vertical, perpendicular, horizontal", and "top, bottom" is generally based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing this application and simplifying the description. Without contrary description, these orientation terms do not indicate and imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, it should not be construed as limiting the protection scope of this application; the orientation terms "inside, outside" refer to the inside and outside relative to the contour of each component itself.
[0031] For the convenience of description, spatial relative terms such as "above...", "over...", "on the upper surface of...", "above" can be used here to describe the spatial positional relationship between a device or feature shown in the drawings and other devices or features. It should be understood that the spatial relative terms are intended to include different orientations in use or operation in addition to the orientation described in the drawings for the device. For example, if the device in the drawing is inverted, the device described as "above other devices or structures" or "over other devices or structures" will then be positioned "below other devices or structures" or "under other devices or structures". Thus, the exemplary term "above" can include both the orientations of "above" and "below". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and corresponding interpretations should be made for the spatial relative descriptions used here.
[0032] In addition, it should be noted that the use of terms such as "first" and "second" to limit components is only for the convenience of differentiating the corresponding components. Without further declaration, the above terms have no special meaning, so it should not be construed as a limitation on the protection scope of this application. In addition, although the terms used in this application are selected from well-known and commonly used terms, some of the terms mentioned in the specification of this application may be selected by the applicant according to his or her judgment, and their detailed meanings are described in the relevant parts of this description. In addition, it is required to understand this application not only through the actual terms used, but also through the meanings implied by each term.
[0033] In this application, flowcharts are used to illustrate the operations performed by the systems according to the embodiments of this application. It should be understood that the operations before or below do not necessarily need to be executed precisely in sequence. On the contrary, they can be executed in reverse order or simultaneously. At the same time, other operations can be added to these processes, or one or several operations can be removed from these processes.
[0034] Next, the preparation method of the local passivation structure and the solar cell of this application will be described through embodiments.
[0035] Reference Figure 1 to the schematic flowchart of the preparation method in an embodiment shown, the preparation method in this embodiment includes the following steps S110 to S150.
[0036] S110: Provide a silicon substrate having opposite front and back surfaces;
[0037] S120: Sequentially form a tunneling layer and an intrinsic amorphous silicon layer on the front and / or back surface of the silicon substrate, and the intrinsic amorphous silicon layer includes an alternating first part and a second part;
[0038] S130: Perform an oxidation treatment on the first part, and the first part is transformed into silicon oxide after the oxidation treatment;
[0039] S140: Perform a doping treatment on the second part and the silicon oxide, and the second part and the silicon oxide are respectively transformed into doped polysilicon and doped silicon oxide after the doping treatment; and
[0040] S150: Selectively etch and remove the doped silicon oxide using an acidic solution, and retain the doped polysilicon.
[0041] Next, steps S110 to S150 will be specifically described.
[0042] As shown in FIG. 2, in step S110, a silicon substrate 210 is provided. The silicon substrate 210 has opposite front surface 211 and back surface 212. When the solar cell is operating, the front surface 211 faces the sun and the back surface faces away from the sun. The silicon substrate 210 can be an N-type single crystal silicon or a P-type single crystal silicon, and the present application does not limit this. The front surface 211 and / or the back surface 212 can be a textured surface, a polished surface or an etched surface.
[0043] As shown in Figure 2 and Figure 3 FIG. 2, in step S120, a tunneling layer 220 and an intrinsic amorphous silicon layer 230 are sequentially formed on the front surface 211 of the silicon substrate 210. The intrinsic amorphous silicon layer 230 includes alternately arranged first part 231 and second part 232. The present application does not limit the width of the first part 231 and the width of the second part 232, and they can be set according to actual requirements.
[0044] It should be noted that in Figure 2 this, the tunneling layer 220 and the intrinsic amorphous silicon layer 230 are not formed on the back surface 212, but this does not constitute a limitation to the present application. The present application can also form the tunneling layer 220 and the intrinsic amorphous silicon layer 230 on the back surface 212 at the same time, or only form the tunneling layer 220 and the intrinsic amorphous silicon layer 230 on the back surface 212. Hereinafter, taking the formation of the tunneling layer 220 and the intrinsic amorphous silicon layer 230 on the front surface 211 as an example, the preparation method of the present application will be described.
[0045] The tunneling layer 220 can be silicon dioxide. The thickness of the tunneling layer 220 can be 0.5 nm to 2 nm, for example, the thickness is 0.5 nm, 1 nm, 1.5 nm or 2 nm. The method for forming the tunneling layer 220 can include thermal oxidation method, wet oxidation method, nitric acid oxidation method, ozone oxidation method or vapor deposition method. Preferably, the tunneling layer 220 is prepared by the thermal oxidation method.
[0046] The thickness of the intrinsic amorphous silicon layer 230 can be 50 nm to 200 nm. For example, the thickness is 50 nm, 100 nm, 150 nm or 200 nm. The method for forming the intrinsic amorphous silicon layer 230 can include low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) or physical vapor deposition (PVD). Preferably, the intrinsic amorphous silicon layer 230 is prepared by the physical vapor deposition process.
[0047] As shown in Figure 3 and Figure 4 FIG. 2, in step S130, the first part 231 is oxidized. After the first part 231 is oxidized, it is transformed into silicon oxide 240. When the first part 231 is oxidized, the second part 232 is not affected by the oxidation treatment and the second part 232 remains as intrinsic amorphous silicon.
[0048] In one embodiment, the step of oxidizing the first part 231 includes: injecting oxygen ions into the first part 231 using an oxygen ion implantation process, and using an ion beam mask to block the oxygen ions injected into the second part 232. In this way, when the first part 231 is oxidized using the oxygen ion implantation process, the first part 231 is transformed into silicon oxide, and the second part 232 is not affected by the oxygen ions due to the shielding of the ion beam mask. In the present application, when oxidizing the first part 231, selective oxidation treatment of the first part 231 can be completed without the aid of a mask, which reduces the process steps of preparing and removing the mask.
[0049] In one embodiment, the process parameters for injecting oxygen ions into the first part 231 using the oxygen ion implantation process are as follows: the dose of oxygen ion implantation is 1×10 15 atoms / cm 2 ~1×10 18 atoms / cm 2 , for example, the dose is 1×10 15 atoms / cm 2 、1×10 16 atoms / cm 2 、1×10 17 atoms / cm 2 or 1×10 18 atoms / cm 2 , preferably 1×10 17 atoms / cm 2 ~1×10 18 atoms / cm 2 ; the energy of oxygen ion implantation is 10 keV to 100 keV, for example, the energy is 10 keV, 30 keV, 50 keV, 70 keV, 90 keV or 100 keV, preferably 10 keV to 50 keV; the temperature of oxygen ion implantation is 25°C to 200°C, for example, the temperature is 25°C, 50°C, 75°C, 100°C, 125°C, 150°C, 175°C or 200°C, preferably 25°C; the depth of oxygen ion implantation is 50 nm to 200 nm, for example, the depth is 50 nm, 100 nm, 150 nm or 200 nm, preferably 50 nm to 100 nm, particularly preferably 100 nm.
[0050] Reference Figure 4 and Figure 5As shown, in step S140, the second part 232 and the silicon oxide 240 are doped. After doping, the second part 232 and the silicon oxide 240 are respectively transformed into doped polysilicon 250 and doped silicon oxide 260. The doping type of the doped polysilicon 250 is the same as that of the doped silicon oxide 260, and both can be N-type doping or P-type doping.
[0051] In one embodiment, the step of doping the second part 232 and the silicon oxide 240 includes: using a high-temperature diffusion process to dope the second part 232 and the silicon oxide 240. The temperature of the high-temperature diffusion process can be 800°C to 1000°C. For example, the temperature is 800°C, 900°C, or 1000°C, preferably 850°C to 950°C; the drive-in time can be 5 min to 60 min. For example, the time is 5 min, 20 min, 40 min, or 60 min, preferably 5 min to 20 min; the surface peak doping concentration of the doped polysilicon 250 is 1×10 19 cm -3 ~1×10 21 cm -3 , for example, the surface peak doping concentration is 1×10 19 cm -3 、1×10 20 cm -3 or 1×10 21 cm -3 ; the junction depth is 0.1 μm to 0.3 μm. For example, the junction depth is 0.1 μm, 0.2 μm, or 0.3 μm.
[0052] Refer to Figure 5 and Figure 6 As shown, in step S150, the doped silicon oxide 260 is selectively etched and removed using an acidic solution, and the doped polysilicon 250 is retained. When etching with the acidic solution, the etching selectivity ratios of the acidic solution for the doped polysilicon 250 and the doped silicon oxide 260 are different, and the silicon oxide will be etched while the doped polysilicon will not be etched. Refer to Figure 5 and Figure 6 As shown, in some embodiments, the silicon oxide 220 located below the doped silicon oxide 260 can also be removed.
[0053] The acidic solution can include one or more of hydrofluoric acid, hydrochloric acid, and phosphoric acid, and the concentration of the acid solution can be 3 vol% to 10 vol%. For example, the concentration is 3 vol%, 5 vol%, 7 vol%, 9 vol%, or 10 vol%, preferably 8 vol%.
[0054] As Figure 5 and Figure 6As shown, in step S150, a gap 270 is formed at the position where the original doped silicon oxide 260 was located. The process of removing the doped silicon oxide 260 in this application does not require the use of a mask, which omits the process of preparing and removing the mask and greatly simplifies the process steps.
[0055] The preparation method of this application may further include the step of preparing an electrode. Refer to Figure 6 As shown, an electrode (not shown in the figure) electrically connected to the doped polysilicon 250 is formed.
[0056] Refer to Figure 7 As shown, on the other hand, this application also proposes a solar cell, which includes a silicon substrate 210, a local passivation structure including a tunneling layer 220 and doped polysilicon 280, and an electrode 290. The silicon substrate 210 has opposite front 211 and back 212 surfaces. The tunneling layer 220 is disposed on the front 211 surface, and the doped polysilicon 280 is disposed on at least a partial region of the tunneling layer 220. The electrode 290 is electrically connected to the doped polysilicon 220. Among them, the local passivation structure is prepared by the preparation method described above.
[0057] In Figure 7 , the tunneling layer located between adjacent doped polysilicon 280s is removed, that is, the tunneling layer 220 is disposed on a partial region of the front 211 surface, and the front 211 surface located between adjacent doped polysilicon 280s is exposed. In some other embodiments, the tunneling layer located between adjacent doped polysilicon 280s may not be removed. For example, the tunneling layer 220 covers the entire front 211 surface.
[0058] It should be noted that a tunneling layer and a doped polysilicon layer may also be formed on the back 212 surface, or only a tunneling layer and a doped polysilicon layer are formed on the back 212 surface, which will not be elaborated here.
[0059] The basic concepts have been described above. Obviously, for those skilled in the art, the above application disclosure is only an example and does not constitute a limitation to this application. Although not explicitly stated here, those skilled in the art may make various modifications, improvements, and corrections to this application. Such modifications, improvements, and corrections are proposed in this application, so such modifications, improvements, and corrections still fall within the spirit and scope of the exemplary embodiments of this application.
[0060] Meanwhile, this application uses specific terms to describe the embodiments of this application. For example, "an embodiment", "one embodiment", and / or "some embodiments" mean a certain feature, structure, or characteristic related to at least one embodiment of this application. Therefore, it should be emphasized and noted that the "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or more at different positions in this specification does not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of this application can be appropriately combined.
[0061] Similarly, it should be noted that, in order to simplify the description of this application disclosure and thus help the understanding of one or more application embodiments, in the previous description of the embodiments of this application, sometimes multiple features are grouped into one embodiment, drawing, or description thereof. However, this disclosure method does not mean that the features required by the object of this application are more than those mentioned in the claims. In fact, the features of the embodiment are less than all the features of the single embodiment disclosed above.
[0062] In some embodiments, numbers are used to describe the components and the quantity of attributes. It should be understood that such numbers used in the description of embodiments are, in some examples, modified by the modifiers "about", "approximately", or "substantially". Unless otherwise specified, "about", "approximately", or "substantially" indicate that the said numbers allow a variation of ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, and these approximate values can change according to the characteristics required by individual embodiments. In some embodiments, the numerical parameters should consider the specified significant digits and adopt the method of retaining the general number of digits. Although the numerical ranges and parameters used in some embodiments of this application to confirm the breadth of their scope are approximate values, in specific embodiments, such numerical settings are as precise as possible within the feasible range.
[0063] Although this application has been described with reference to the current specific embodiments, those of ordinary skill in the art in this technical field should recognize that the above embodiments are only used to illustrate this application, and various equivalent changes or substitutions can be made without departing from the spirit of this application. Therefore, as long as the changes and modifications to the above embodiments are within the scope of the spirit of this application, they will fall within the scope of the claims of this application.
Claims
1. A preparation method of a local passivation structure, characterized in that, Comprising: Providing a silicon substrate having opposite front and back surfaces; Successively forming a tunneling layer and an intrinsic amorphous silicon layer on the front surface and / or the back surface of the silicon substrate, the intrinsic amorphous silicon layer including an alternately arranged first part and a second part; Performing an oxidation treatment on the first part, and the first part is transformed into silicon oxide after the oxidation treatment; Performing a doping treatment on the second part and the silicon oxide, and the second part and the silicon oxide are respectively transformed into doped polysilicon and doped silicon oxide after the doping treatment; And Selectively etching and removing the doped silicon oxide using an acidic solution, and retaining the doped polysilicon.
2. The preparation method according to claim 1, characterized in that, The step of performing an oxidation treatment on the first part includes: injecting oxygen ions into the first part using an oxygen ion implantation process, and using an ion beam mask to block the oxygen ions injected into the second part.
3. The preparation method according to claim 2, characterized in that, The dose of oxygen ion implantation is 1×10 15 atoms / cm 2 ~1×10 18 atoms / cm 2 , the energy of oxygen ion implantation is 10 keV to 100 keV, the temperature of oxygen ion implantation is 25 °C to 200 °C, and the depth of oxygen ion implantation is 50 nm to 200 nm.
4. The preparation method according to claim 1, characterized in that, The acidic solution includes one or more of hydrofluoric acid, hydrochloric acid, and phosphoric acid, and the acid solution concentration is 3 vol% to 10 vol%.
5. The preparation method according to claim 1, wherein The thickness of the intrinsic amorphous silicon layer is 50 nm to 200 nm, and the method for forming the intrinsic amorphous silicon layer includes low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, or physical vapor deposition.
6. The preparation method according to claim 1, characterized in that, The step of performing a doping treatment on the second part and the silicon oxide includes: performing a doping treatment on the second part and the silicon oxide using a high-temperature diffusion process.
7. The preparation method according to claim 6, characterized in that, The temperature of the high-temperature diffusion process is 800°C to 1000°C, the driving time is 5 minutes to 60 minutes, and the surface peak doping concentration of the doped polysilicon is 1×10 19 cm -3 ~1×10 21 cm -3 , and the junction depth is 0.1 μm to 0.3 μm.
8. The preparation method according to claim 1, characterized in that, The tunneling layer includes silicon dioxide, and the method for forming the tunneling layer includes thermal oxidation, wet oxidation, nitric acid oxidation, ozone oxidation, or vapor deposition.
9. A solar cell, the solar cell comprising a silicon substrate, a local passivation structure including a tunneling layer and a doped polysilicon layer, and an electrode, characterized in that, The local passivation structure is prepared by the preparation method according to any one of claims 1 to 8.
10. The solar cell according to claim 9, characterized in that, The tunneling layer is disposed on a local area of the front surface and / or the back surface of the silicon substrate, and exposes a part of the front surface and / or the back surface.