Display panel and method of manufacturing the same

Abstract

The invention relates to a display panel and a method of manufacturing the same. The display panel includes a display element layer having a light emitting element and an optical structure layer. The optical structure layer includes: a light control layer including a bank having a first bank opening and a first light control pattern disposed in the first bank opening; and a color filter layer including a first color filter disposed in the first filter region. A first bank region defined by the first bank opening includes: a first sub-region having a first width and a first length; and a second sub-region having a second width greater than the first width. The first filter region overlaps a portion of the first sub-region and a portion of the second sub-region. A width of the first filter region is less than or substantially equal to the first width, and a length of the first filter region is greater than or substantially equal to the first length.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority and the benefit of Korean Patent Application No. 10 - 2024 - 0001512, filed on January 4, 2024, with the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0003] In this document, the present disclosure relates to a display panel and a method of manufacturing a display panel, and more particularly, to a display panel having improved resolution and improved manufacturing process efficiency and a method of manufacturing the same. Background Art

[0004] Display panels include transmissive display panels that selectively transmit source light generated from a light source and emissive display panels that generate source light themselves. Display panels may include different types of light control patterns depending on pixels to produce a color image. The light control patterns may transmit only some wavelength ranges of the source light or change the color of the source light. Some light control patterns may change the characteristics of light without changing the color of the source light. Summary of the Invention

[0005] The present disclosure provides a display panel capable of achieving high resolution and having improved manufacturing process efficiency.

[0006] The present disclosure also provides a method of manufacturing a display panel having improved manufacturing process efficiency.

[0007] Embodiments of the present disclosure provide a display panel including: a display element layer including a light - emitting element that outputs source light; and an optical structure layer disposed on the light - emitting element and transmitting the source light or converting the source light into light of a different wavelength. The optical structure layer includes: a light control layer disposed above the light - emitting element and including a bank having a first bank opening and a first light control pattern disposed in the first bank opening; and a color filter layer disposed above the light control layer and including a first color filter disposed in a first filter region. The first bank region defined by the first bank opening includes: a first sub - region having a first width in a first direction and a first length in a second direction intersecting the first direction; and a second sub - region having a second width greater than the first width in the first direction. The first filter region overlaps with the first sub - region and a part of the second sub - region. The width of the first filter region in the first direction is less than or substantially equal to the first width, and the length of the first filter region in the second direction is greater than or substantially equal to the first length.

[0008] In an embodiment, the dam may further include a second dam opening spaced apart from the first dam opening and a third dam opening spaced apart from each of the first dam opening and the second dam opening. The light control layer may further include a second light control pattern disposed in the second dam opening and a third light control pattern disposed in the third dam opening.

[0009] In an embodiment, the second dam region defined by the second dam opening may include: a third sub-region having a third width in a first direction and a second length in a second direction; and a fourth sub-region having a fourth width in the first direction. The fourth width may be greater than the third width.

[0010] In an embodiment, the third dam region may be defined by the third dam opening. The widths of the first sub-region, the third sub-region, and the third dam region in the first direction may be substantially equal to each other.

[0011] In an embodiment, the first dam region, the second dam region, and the third dam region may be arranged in sequence in the first direction. The first sub-region and the third sub-region may be spaced apart from each other by a first spacing distance in the first direction, and the third sub-region and the third dam region may be spaced apart from each other by a second spacing distance in the first direction. The first spacing distance and the second spacing distance may be substantially equal to each other.

[0012] In an embodiment, the color filter layer may further include: a second color filter disposed in a second color filter region spaced apart from the first light filter region; and a third color filter disposed in a third color filter region spaced apart from the first light filter region and the second color filter region.

[0013] In an embodiment, the second light filter region may overlap with the third sub-region and a part of the fourth sub-region. The width of the second light filter region in the first direction may be less than or substantially equal to the third width, and the length of the second light filter region in the second direction may be greater than or substantially equal to the second length.

[0014] In an embodiment, the widths of the first light filter region, the second light filter region, and the third light filter region in the first direction may be substantially equal to each other. The length of the first light filter region in the second direction may be greater than the length of the second light filter region in the second direction. The length of the second light filter region in the second direction may be greater than the length of the third light filter region in the second direction.

[0015] In an embodiment, the second length may be shorter than the first length.

[0016] In an embodiment, the third dam region may be defined by the third dam opening. The third dam region may have a rectangular shape in a plane.

[0017] In an embodiment, the second bank region is defined by a second bank opening. The length of the third bank region in the second direction may be shorter than the length of each of the first bank region and the second bank region in the second direction.

[0018] In an embodiment, the first light control pattern may include first quantum dots that convert source light into light of a first wavelength. The second light control pattern may include second quantum dots that convert source light into light of a second wavelength.

[0019] In an embodiment, the third light control pattern may include a photosensitive resin.

[0020] In an embodiment, the display panel may further include a circuit element layer including a pixel circuit electrically connected to a light-emitting element. The light-emitting element may include: a first electrode disposed on the circuit element layer; an intermediate layer disposed on the first electrode and including a light-emitting layer; and a second electrode disposed on the intermediate layer. The display element layer may further include an auxiliary electrode disposed on the circuit element layer and electrically connected to the second electrode. At least a part of the connection region where the auxiliary electrode may be disposed may overlap with the second sub-region in a plane.

[0021] In an embodiment, the first sub-region may include a (1-1) side and a (1-2) side that extend in the second direction and are spaced apart from each other in the first direction. The second sub-region may include a (2-1) side and a (2-2) side that extend in the second direction and are spaced apart from each other in the first direction. The (1-2) side and the (2-2) side may be aligned with each other on the same straight line in the second direction.

[0022] In an embodiment, the second sub-region may include a first chamfered portion that is recessed from the (2-1) side of the second sub-region toward the inside of the second sub-region.

[0023] In an embodiment, the first filter region may include: a first sub-filter region that overlaps with the first sub-region; and a second sub-filter region that overlaps with the second sub-region. The width of the second sub-filter region in the first direction may be greater than the width of the first sub-filter region in the first direction.

[0024] In an embodiment, the display element layer may be divided into a display region where a light-emitting element is disposed and a non-display region surrounding at least a part of the display region. The first bank region may include: a (1-1) bank region disposed in the display region; and a (1-2) bank region disposed in the non-display region.

[0025] In an embodiment of the present disclosure, a display panel includes: a light-emitting element that outputs source light; and an optical structure layer disposed on the light-emitting element and transmitting the source light or converting the source light into light of different wavelengths. The optical structure layer includes: a light control layer including a bank disposed on the light-emitting element and having a first bank opening, a second bank opening, and a third bank opening, a first light control pattern disposed in the first bank opening, a second light control pattern disposed in the second bank opening, and a third light control pattern disposed in the third bank opening; and a color filter layer disposed on the light control layer and including a first color filter overlapping with the first light control pattern, a second color filter overlapping with the second light control pattern, and a third color filter overlapping with the third light control pattern. The first bank region defined by the first bank opening includes a first sub-region and a second sub-region, the first sub-region having a first width in a first direction, and the second sub-region having a second width in the first direction. The second bank region defined by the second bank opening includes a third sub-region and a fourth sub-region, the third sub-region having a third width in the first direction, and the fourth sub-region having a fourth width in the first direction. The second width is greater than the first width, and the fourth width is greater than the third width. The third bank region is defined by the third bank opening. The widths of the first sub-region, the third sub-region, and the third bank region in the first direction are substantially equal to each other.

[0026] In an embodiment of the present disclosure, a method of manufacturing a display panel includes: preparing a display element layer including a light-emitting element that outputs source light; and forming an optical structure layer on the light-emitting element. Forming the optical structure layer includes: forming a bank having a first bank opening, a second bank opening, and a third bank opening above the light-emitting element; patterning a photoresist material in the third bank opening to form a third light control pattern; and forming a first light control pattern and a second light control pattern in the first bank opening and the second bank opening respectively by an inkjet process. The first bank region defined by the first bank opening includes a first sub-region and a second sub-region, the first sub-region having a first width in a first direction, and the second sub-region having a second width in the first direction. The second bank region defined by the second bank opening includes a third sub-region and a fourth sub-region, the third sub-region having a third width in the first direction, and the fourth sub-region having a fourth width in the first direction. The second width is greater than the first width, and the fourth width is greater than the third width.

[0027] The technical objectives achieved by the present disclosure are not limited to those described herein, and those skilled in the art will clearly understand other technical objectives not mentioned herein from the description of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the description, are used to explain the principles of the present disclosure. In the drawings:

[0029] Figure 1A is a schematic perspective view of a display panel according to an embodiment of the present disclosure;

[0030] Figure 1B is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure;

[0031] Figure 1C is a schematic plan view of a display panel according to an embodiment of the present disclosure;

[0032] Figure 2 is a schematic enlarged plan view of a part of a display panel according to an embodiment of the present disclosure;

[0033] Figure 3 is a schematic cross-sectional view of a part of a display panel according to an embodiment of the present disclosure;

[0034] Figures 4A to 4D is a schematic cross-sectional view of a part of a display panel according to an embodiment of the present disclosure;

[0035] Figure 5 is a schematic cross-sectional view of a light-emitting element according to an embodiment of the present disclosure;

[0036] Figure 6A is a schematic enlarged plan view of a part of a display panel according to an embodiment of the present disclosure;

[0037] Figure 6B is a schematic enlarged plan view of a part of a display panel according to an embodiment of the present disclosure;

[0038] Figure 7 is a schematic cross-sectional view of a part of a display panel according to an embodiment of the present disclosure;

[0039] Figures 8A to 8D Each of is a schematic enlarged plan view of a part of a display panel according to an embodiment of the present disclosure;

[0040] Figure 9 is a schematic enlarged plan view of a part of a display panel according to an embodiment of the present disclosure; and

[0041] Figures 10A to 10D is a schematic cross-sectional view showing some steps of a method of manufacturing a display panel according to an embodiment of the present disclosure. Detailed Embodiments

[0042] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0043] In this specification, it will be understood that when an element (or region, layer, portion, etc.) is referred to as being "on," "connected to," or "coupled to" another element, it can be directly on, directly connected to, or directly coupled to the other element, or there may be intervening elements between them.

[0044] The same reference numerals or symbols throughout the specification denote the same elements. Additionally, in the drawings, the thickness, proportions, and dimensions of elements may be exaggerated for the purpose of effectively describing the technical content. As used herein, the term "and / or" includes any and all combinations that the associated configuration may define.

[0045] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element. Similarly, a second element may also be referred to as a first element. Unless otherwise specified, the singular forms of the terms include the plural forms.

[0046] Furthermore, for ease of description, terms such as "below," "under," "above," "over," etc. are used herein to describe the relationship of one element to another as shown in the figures. The above terms are relative concepts and are described based on the directions indicated in the drawings.

[0047] It will be understood that when used in this specification, the terms "comprises," "comprising," and / or "has" specify the presence of the stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0048] When an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly" on, "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. For this reason, the term "connected" can refer to physical connection, electrical connection, and / or fluid connection with or without intervening elements.

[0049] Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), as used herein, "about" or "approximately" includes the recited value and means within an acceptable deviation of the particular value as determined by a person of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the recited value.

[0050] For the purposes of this disclosure, the phrase "at least one of A and B" can be construed to mean only A, only B, or any combination of A and B. Additionally, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be construed to mean only X, only Y, only Z, or any combination of two or more of X, Y, and Z.

[0051] Unless otherwise defined or implied herein, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by a person of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms (such as those defined in common dictionaries) should be construed to have a meaning consistent with their meaning in the context of the relevant art and will not be construed in an idealized or overly formal sense unless expressly so defined herein.

[0052] Hereinafter, a display panel and a method of manufacturing a display panel according to an embodiment of the present disclosure will be described with reference to the accompanying drawings.

[0053] Figure 1A is a schematic perspective view of a display panel according to an embodiment of the present disclosure. Figure 1B is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure. Figure 1C is a schematic plan view of a display panel according to an embodiment of the present disclosure.

[0054] As Figure 1A shown, the display panel DP can display an image through a display surface DP-IS. The display surface DP-IS can be parallel to a plane defined by a first direction DR1 and a second direction DR2. The display surface DP-IS can include a display area DA and a non-display area NDA. Pixels PX can be disposed in the display area DA, and pixels PX can not be disposed in the non-display area NDA. The non-display area NDA can be defined along an edge of the display surface DP-IS. The non-display area NDA can surround the display area DA. However, without limitation thereto, in an embodiment of the present disclosure, the non-display area NDA can be omitted or can be disposed only on one side of the display area DA.

[0055] The normal direction of the display surface DP-IS (e.g., the thickness direction of the display panel DP) is represented by the third direction DR3. The front surface (or upper surface) and the back surface (or lower surface) of each layer or part described below are divided by the third direction DR3. However, the first direction DR1, the second direction DR2, and the third direction DR3 shown in this embodiment are merely examples.

[0056] In the embodiments of the present disclosure, although a display panel DP having a flat display surface DP-IS is shown, the embodiments of the present disclosure are not limited thereto. The display panel DP may include a curved display surface or a three-dimensional display surface. The three-dimensional display surface may include display regions indicating different directions.

[0057] As Figure 1B shown, the display panel DP may include a base substrate BS, a circuit element layer DP-CL, a display element layer DP-LED, and an optical structure layer OSL. The base substrate BS may include a synthetic resin substrate or a glass substrate. The circuit element layer DP-CL may include at least one insulating layer and circuit elements. The circuit elements may include signal lines, pixel driving circuits, etc. The circuit element layer DP-CL may be formed by processes for forming insulating layers, semiconductor layers, and conductive layers such as coating and deposition, and processes for patterning insulating layers, semiconductor layers, and conductive layers by photolithography. The display element layer DP-LED may include at least one display element. The optical structure layer OSL may convert the color of light provided by the display element. The optical structure layer OSL may include light control patterns and structures configured to improve the light conversion efficiency.

[0058] Figure 1C The planar arrangement relationship of the signal lines GL1 to GLn and DL1 to DLm and the pixels PX11 to PXnm is shown. The signal lines GL1 to GLn and DL1 to DLm may include gate lines GL1 to GLn and data lines DL1 to DLm.

[0059] Each of the pixels PX11 to PXnm may be connected to a corresponding gate line among the gate lines GL1 to GLn and a corresponding data line among the data lines DL1 to DLm. Each of the pixels PX11 to PXnm may include a pixel driving circuit and a display element. Depending on the configuration of the pixel driving circuits of the pixels PX11 to PXnm, more types of signal lines may be provided in the display panel DP.

[0060] The gate driving circuit GDC may be integrated into the display panel DP by a silicon oxide gate driving circuit (OSG) process or an amorphous silicon gate driving circuit (ASG) process.

[0061] Figure 2 is a schematic enlarged plan view of a part of a display panel according to an embodiment of the present disclosure.Figure 3 is a schematic cross-sectional view of a part of a display panel according to an embodiment of the present disclosure. Figures 4A to 4D is a schematic cross-sectional view of a part of a display panel according to an embodiment of the present disclosure. Figure 3 shows a cross-section corresponding to the line I-I' shown in Figure 2 . Figures 4A to 4D shows a cross-section corresponding to the line II-II' shown in Figure 2 .

[0062] Figure 2 shows the arrangement relationship of pixel regions PXA-R, PXA-G, and PXA-B provided in a display area DA of a display panel DP (see Figure 1A ). In an embodiment of the present disclosure, Figure 2 the shapes of the pixel regions PXA-R, PXA-G, and PXA-B shown in Figure 1A can be repeatedly provided throughout the display area DA (see

[0063] Referring to Figure 2 , a peripheral region NPXA can be provided around the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B. The peripheral region NPXA can define the boundaries of the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B. The peripheral region NPXA can surround the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B.

[0064] The first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B can correspond to a first filter region FA1, a second filter region FA2, and a third filter region FA3. Each of the first filter region FA1, the second filter region FA2, and the third filter region FA3 can be a region defined by a color filter to be described below.

[0065] A structure (such as a pixel defining film PDL (see Figure 3 ) or a bank BMP (see Figure 3 )) for preventing color mixing between the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B can be provided in the peripheral region NPXA. Two or more of the color filters to be described below can be provided to overlap each other in the peripheral region NPXA.

[0066] As Figure 2As shown, each of the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B may have a rectangular shape. Each of the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B may have a rectangular shape having a short side extending in a first direction DR1 and a long side extending in a second direction DR2. The areas of the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B may be set according to the color of the emitted light. Among the primary colors, the area of the pixel region emitting red light may be the largest, and the area of the pixel region emitting blue light may be the smallest. For example, the area of the first pixel region PXA-R emitting red light may be the largest, and the area of the third pixel region PXA-B emitting blue light may be the smallest. However, the present disclosure is not limited thereto, and the area of the pixel region may be modified within the scope of the spirit of the present disclosure.

[0067] Figure 2 The first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B having a rectangular shape are shown, but the embodiments of the present disclosure are not limited thereto. On a plane, some of the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B may have different polygonal shapes (including substantially polygonal shapes). In an embodiment of the present disclosure, the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B may have a rectangular shape (substantially rectangular shape) with rounded corners on the plane.

[0068] One of the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B may provide red light, another of the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B may provide blue light, and the remaining pixel region of the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B may provide green light. In this embodiment, the first pixel region PXA-R may provide red light, the second pixel region PXA-G may provide green light, and the third pixel region PXA-B may provide blue light. The first pixel region PXA-R may emit light having an emission wavelength in the range of about 620 nm to about 700 nm, the second pixel region PXA-G may emit light having an emission wavelength in the range of about 520 nm to about 600 nm, and the third pixel region PXA-B may emit light having an emission wavelength in the range of about 410 nm to about 480 nm.

[0069] Although not shown, the dam trap region may be defined in the display region DA. The dam trap region may be a region where dams are formed to prevent defects caused by misalignment in the process of printing some of the light control patterns CCP-R, CCP-G, and CCP-B (see Figure 4A ) included in the light control layer CCL (see Figure 4A ). For example, the dam trap region may be a region where dam traps formed by removing a part of the dam BMP (see Figure 4A ) are defined.

[0070] Referring to Figure 3 , a display panel DP according to an embodiment of the present disclosure may include a base substrate BS, a circuit element layer DP-CL disposed on the base substrate BS, and a display element layer DP-LED disposed on the circuit element layer DP-CL. In the present specification, the base substrate BS, the circuit element layer DP-CL, and the display element layer DP-LED may be collectively referred to as the lower panel.

[0071] The base substrate BS may be a member that provides a reference surface on which components included in the circuit element layer DP-CL are disposed. In an embodiment of the present disclosure, the base substrate BS may be a glass substrate, a metal substrate, a polymer substrate, etc. However, the embodiments of the present disclosure are not limited thereto, and the base substrate BS may be an inorganic layer, a functional layer, or a composite material layer.

[0072] The base substrate BS may have a multilayer structure. For example, the base substrate BS may have a three-layer structure of a polymer resin layer, an adhesive layer, and a polymer resin layer. Specifically, the polymer resin layer may include a polyimide-based resin. The polymer resin layer may include at least one of an acrylic-based resin, a methacrylic-based resin, a polyisoprene-based resin, a vinyl resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a silicone-based resin, a polyamide-based resin, and a binaphthyl-based resin. In the present specification, an "α-based" resin means a functional group including "α".

[0073] The circuit element layer DP-CL may be disposed on the base substrate BS. The circuit element layer DP-CL may include a transistor T-D as a circuit element. According to the design of the driving circuit of the pixel PX (see Figure 1A ), the configuration of the circuit element layer DP-CL may vary, and as an example, Figure 3 shows the transistor T-D. As an example, the layout relationship of the active portion A-D, the source electrode S-D, the drain electrode D-D, and the gate electrode G-D constituting the transistor T-D is shown. The active portion A-D, the source electrode S-D, and the drain electrode D-D may be divided according to the doping concentration or conductivity of the semiconductor pattern.

[0074] The circuit element layer DP-CL may include a lower buffer layer BRL, a first insulating layer 10, a second insulating layer 20, and a third insulating layer 30 disposed on a base substrate BS. For example, the lower buffer layer BRL, the first insulating layer 10, and the second insulating layer 20 may be inorganic layers, and the third insulating layer 30 may be an organic layer.

[0075] The display element layer DP-LED may include a light-emitting element LED as a display element. The light-emitting element LED may generate source light. In an embodiment of the present disclosure, the source light may be white light or blue light. In this embodiment, the display element layer DP-LED may include an organic light-emitting diode as the light-emitting element LED. For example, a light-emitting layer EML included in the light-emitting element LED may include an organic light-emitting material as a light-emitting material.

[0076] The light-emitting element LED may include a first electrode EL1, a second electrode EL2, and a light-emitting layer EML disposed therebetween. In this embodiment, the display element layer DP-LED may include an organic light-emitting diode as the light-emitting element LED. In an embodiment of the present disclosure, the light-emitting element LED may include a quantum dot light-emitting diode. For example, a light-emitting layer EML included in the light-emitting element LED may include an organic light-emitting material as a light-emitting material, or the light-emitting layer EML may include quantum dots as a light-emitting material. As another example, in this embodiment, the display element layer DP-LED may include an ultra-small light-emitting element described below as the light-emitting element LED. The ultra-small light-emitting element may include, for example, a micro-LED element and / or a nano-LED element. The ultra-small light-emitting element may have a micron-scale or nano-scale size and include an active layer disposed between semiconductor layers.

[0077] The first electrode EL1 may be disposed on the third insulating layer 30. The first electrode EL1 may be directly or indirectly connected to the transistor T-D, and the connection structure between the first electrode EL1 and the transistor T-D is not shown in Figure 3 it.

[0078] The display element layer DP-LED may include a pixel defining film PDL. For example, the pixel defining film PDL may be an organic layer. A light-emitting opening OH may be defined in the pixel defining film PDL. The light-emitting opening OH of the pixel defining film PDL may expose at least a portion of the first electrode EL1. In this embodiment, a first light-emitting region EA1 may be defined by the light-emitting opening OH.

[0079] The hole control layer HTR, the light-emitting layer EML, and the electron control layer ETR may at least overlap with the first pixel region PXA-R. Each of the hole control layer HTR, the light-emitting layer EML, the electron control layer ETR, and the second electrode EL2 may be commonly provided in the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B (see Figure 4A ). Each of the hole control layer HTR, the light-emitting layer EML, the electron control layer ETR, and the second electrode EL2 that overlap with the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B (see Figure 4A ) may have an integral shape. However, not limited thereto, at least one of the hole control layer HTR, the light-emitting layer EML, and the electron control layer ETR may be separately formed in each of the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B (see Figure 4A ). In an embodiment of the present disclosure, the light-emitting layer EML may be patterned in the light-emitting opening OH and separately formed in each of the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B (see Figure 4A ).

[0080] The hole control layer HTR may include a hole transport layer and may further include a hole injection layer.

[0081] The light-emitting layer EML may generate third light as source light. The light-emitting layer EML may generate blue light. The blue light may include light having a wavelength in the range of about 410 nm to about 480 nm. The emission spectrum of the blue light may have a maximum peak in the wavelength range of about 440 nm to about 460 nm.

[0082] The electron control layer ETR may include an electron transport layer and may further include an electron injection layer.

[0083] The display element layer DP-LED may include a thin film encapsulation layer TFE that protects the second electrode EL2. The thin film encapsulation layer TFE may include an organic material or an inorganic material. The thin film encapsulation layer TFE may have a multilayer structure in which an inorganic layer and an organic layer are repeated. In this embodiment, the thin film encapsulation layer TFE may include a first inorganic encapsulation layer IOL1 / organic encapsulation layer OL / second inorganic encapsulation layer IOL2. The first inorganic encapsulation layer IOL1 and the second inorganic encapsulation layer IOL2 may protect the light-emitting element LED from external moisture, and the organic encapsulation layer OL may prevent defects caused by the light-emitting element LED being punctured due to foreign substances introduced during the manufacturing process. Although not shown, the display panel DP may further include a refractive index control layer on the upper side of the thin film encapsulation layer TFE to improve the light extraction efficiency.

[0084] As shown Figure 3 in Figure 3 , the optical structure layer OSL may be disposed on the thin film encapsulation layer TFE. The optical structure layer OSL may include a light control layer CCL, a color filter layer CFL, and a base layer BL. In this specification, the optical structure layer OSL may be referred to as the upper panel.

[0085] The light control layer CCL may be disposed on the display element layer DP-LED including the light emitting element LED. The light control layer CCL may include a bank BMP, a first light control pattern CCP-R, and a first barrier layer CAP1.

[0086] The bank BMP may include a base resin and additives. The base resin may be composed of various resin compositions that may generally be referred to as binders. The additives may include a coupling agent and / or a photoinitiator. The additives may further include a dispersant.

[0087] The bank BMP may include a black colorant to block light. The bank BMP may include a black dye and a black pigment mixed in the base resin. In an embodiment of the present disclosure, the black colorant may include carbon black, or may include a metal such as chromium or its oxide.

[0088] The bank BMP may include a first bank opening BOH1 corresponding to the light emitting opening OH. In a plane, the first bank opening BOH1 may overlap the light emitting opening OH and have an area larger than that of the light emitting opening OH. For example, the first bank opening BOH1 may have an area larger than the first light emitting area EA1 defined by the light emitting opening OH. In this specification, the expression "one element corresponds to another element" means that when observed in the third direction DR3 of the display panel DP, the two elements overlap each other, and the two elements are not limited to having the same area.

[0089] The first light control pattern CCP-R may be disposed within the first bank opening BOH1. The first light control pattern CCP-R may change the optical properties of the source light.

[0090] The first light control pattern CCP-R may include quantum dots to change the optical properties of the source light. The first light control pattern CCP-R may include first quantum dots that convert the source light into light of a different wavelength. In the first light control pattern CCP-R overlapping with the first pixel region PXA-R, the first quantum dots may convert the source light into red light.

[0091] In this specification, a "quantum dot" refers to a crystal of a semiconductor compound. Quantum dots can emit light of various emission wavelengths according to the size of the crystal. Quantum dots can emit light of various emission wavelengths by adjusting the element ratio in the quantum dot compound.

[0092] The diameter of the quantum dots can be, for example, in the range of about 1 nm to about 10 nm.

[0093] The quantum dots can be synthesized by, for example, a wet chemical process, a metalorganic chemical vapor deposition process, a molecular beam epitaxy process, or a process similar thereto.

[0094] The wet chemical process can be a method of mixing an organic solvent and a precursor material with each other and growing quantum dot particle crystals. When the crystals grow, the organic solvent can naturally act as a dispersant coordinated on the surface of the quantum dot crystals and control the growth of the crystals. Therefore, the wet chemical process can be easier than vapor deposition methods such as the metalorganic chemical vapor deposition (MOCVD) process or the molecular beam epitaxy (MBE) process, and can control the growth of quantum dot particles by a low-cost process.

[0095] The core of the quantum dots can be selected from group II-VI compounds, group III-V compounds, group III-VI compounds, group I-III-VI compounds, group II-IV-V compounds, group IV-VI compounds, group IV elements, group IV compounds, and combinations thereof.

[0096] The group II-VI compounds can be selected from the group consisting of binary compounds, ternary compounds, and quaternary compounds, wherein the binary compounds are selected from the group consisting of CdSe, CdTe, CdS, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS, and mixtures thereof; the ternary compounds are selected from the group consisting of CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS, and mixtures thereof; the quaternary compounds are selected from the group consisting of HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe, and mixtures thereof. The group II-VI compounds can also include group I metals and / or group IV elements. The group I-II-VI compounds can be selected from CuSnS or CuZnS, and the group II-IV-VI compounds can be selected from ZnSnS, etc. The group I-II-IV-VI compounds can be selected from quaternary compounds, and the quaternary compounds are selected from the group consisting of Cu2ZnSnS2, Cu2ZnSnS4, Cu2ZnSnSe4, Ag2ZnSnS2, and mixtures thereof.

[0097] III-VI compounds may include binary compounds such as In2S3 and In2Se3, ternary compounds such as InGaS3 and InGaSe3, or any combination thereof.

[0098] I-III-VI compounds may be selected from ternary compounds or quaternary compounds. The ternary compounds are selected from the group consisting of AgInS, AgInS2, CuInS, CuInS2, AgGaS2, CuGaS2, CuGaO2, AgGaO2, AgAlO2, and mixtures thereof. The quaternary compounds are such as AgInGaS2 and CuInGaS2.

[0099] III-V compounds may be selected from the group consisting of binary compounds, ternary compounds, and quaternary compounds. Among them, the binary compounds are selected from the group consisting of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb, and mixtures thereof; the ternary compounds are selected from the group consisting of GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InAlP, InNP, InNAs, InNSb, InPAs, InPSb, and mixtures thereof; the quaternary compounds are selected from the group consisting of GaAlNP, GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb, and mixtures thereof. The III-V compounds may also include Group II metals. For example, InZnP, etc. may be selected as III-II-V compounds.

[0100] IV-VI compounds may be selected from the group consisting of binary compounds, ternary compounds, and quaternary compounds. Among them, the binary compounds are selected from the group consisting of SnS, SnSe, SnTe, PbS, PbSe, PbTe, and mixtures thereof; the ternary compounds are selected from the group consisting of SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe, and mixtures thereof; the quaternary compounds are selected from the group consisting of SnPbSSe, SnPbSeTe, SnPbSTe, and mixtures thereof.

[0101] The II-IV-V compounds can be ternary compounds selected from the group consisting of ZnSnP, ZnSnP2, ZnSnAs2, ZnGeP2, ZnGeAs2, CdSnP2, CdGeP2, and mixtures thereof.

[0102] The Group-IV element can be selected from the group consisting of Si, Ge, and mixtures thereof. The Group-IV compound can be a binary compound selected from the group consisting of SiC, SiGe, and mixtures thereof.

[0103] Each element included in a multi-component compound (such as a binary compound, a ternary compound, and a quaternary compound) can be present in the particles at a uniform or non-uniform concentration. For example, the above chemical formula can refer to the types of elements included in the compound, and the ratios of the elements in the compound can be different from each other. For example, AgInGaS2 can refer to AgIn x Ga 1-x S2 (where x is a real number between 0 and 1).

[0104] In this case, the binary compound, the ternary compound, or the quaternary compound can be present in the particles at a uniform concentration, or they can be present in the same particles after being divided into states where their concentration distributions are partially different from each other. The quantum dots can have a core / shell structure in which one quantum dot surrounds another quantum dot. The core / shell structure can have a concentration gradient in which the concentration of the element present in the shell gradually decreases toward the core.

[0105] In some embodiments of the present disclosure, the quantum dots can have a core-shell structure, the core-shell structure including a core containing the above-described nanocrystals and a shell surrounding the core. The shell of the quantum dots can serve as a protective layer for maintaining semiconductor properties by preventing chemical modification of the core and / or as a charging layer for imparting electrophoretic properties to the quantum dots. The shell can be single-layer or multi-layer. Examples of the shell of the quantum dots can include metal or non-metal oxides, semiconductor compounds, or combinations thereof.

[0106] For example, the metal or non-metal oxides can include binary compounds such as SiO2, Al2O3, TiO2, ZnO, MnO, Mn2O3, Mn3O4, CuO, FeO, Fe2O3, Fe3O4, CoO, Co3O4, and NiO, or ternary compounds such as MgAl2O4, CoFe2O4, NiFe2O4, and CoMn2O4, but the embodiments of the present disclosure are not limited thereto.

[0107] In addition, examples of semiconductor compounds may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, AlSb, etc., but embodiments of the present disclosure are not limited thereto.

[0108] The quantum dots may have a full width at half maximum (FWHM) of the emission wavelength spectrum of about 45 nm or less (e.g., about 40 nm or less, or as another example, about 30 nm or less), and within those ranges, color purity or color reproducibility can be improved. Since the light emitted by the quantum dots is emitted in all directions, a wide viewing angle can be improved.

[0109] The shape of the quantum dots is not particularly limited to those commonly used in the art, but more specifically, shapes such as spherical, pyramidal, or multi-arm shapes or shapes of cubic nanoparticles, nanotubes, nanowires, nanofibers, and nanoplates can be used.

[0110] Since the bandgap can be controlled by adjusting the size of the quantum dots or the ratio of elements in the quantum dot compound, light of various wavelengths can be obtained from the quantum dot light-emitting layer. Therefore, by using the above-described quantum dots (using quantum dots of different sizes or different element ratios in the quantum dot compound), a light-emitting element configured to emit light of various wavelengths can be realized. Specifically, the control of the size of the quantum dots or the ratio of elements in the quantum dot compound can be selected to emit red, green, and / or blue light. The quantum dots can be configured to emit white light by combining light of various colors.

[0111] In an embodiment of the present disclosure, the quantum dots included in the first light control pattern CCP-R overlapping with the first pixel region PXA-R may have a red emission color. In the case where the particle size of the quantum dots is small, light in a shorter wavelength range can be emitted. For example, among quantum dots having the same core, the quantum dots emitting green light may have a smaller particle size than the quantum dots emitting red light. Among quantum dots having the same core, the quantum dots emitting blue light may have a smaller particle size than the quantum dots emitting green light. However, embodiments of the present disclosure are not limited thereto, and even among quantum dots having the same core, their particle size can be adjusted according to the shell-forming material, shell thickness, etc.

[0112] In the case where the quantum dots have various emission colors such as blue, red, and green, the quantum dots having different emission colors may respectively have different core materials.

[0113] The first light control pattern CCP-R may further include a scatterer. The first light control pattern CCP-R may include a first quantum dot that converts blue light into red light and a scatterer that scatters light.

[0114] The scatterer may be an inorganic particle. For example, the scatterer may include at least one of TiO2, ZnO, Al2O3, SiO2, and hollow silica. The scatterer may include at least one of TiO2, ZnO, Al2O3, SiO2, and hollow silica, or may be a mixture of two or more materials selected from TiO2, ZnO, Al2O3, SiO2, and hollow silica.

[0115] The first light control pattern CCP-R may include a base resin that disperses the first quantum dot and the scatterer. The base resin may be a medium in which the first quantum dot and the scatterer are dispersed, and may be made of various resin compositions that can generally be referred to as binders. For example, the base resin may be an acrylic-based resin, a urethane-based resin, a silicone-based resin, an epoxy-based resin, etc. The base resin may be a transparent resin.

[0116] In this embodiment, the first light control pattern CCP-R may be formed by an inkjet process. The liquid composition may be disposed in the bank opening BOH. The volume of the composition polymerized by a thermal curing process or a photo-curing process may decrease after curing.

[0117] The light control layer CCL may include a first barrier layer CAP1 disposed on one surface of the first light control pattern CCP-R. The first barrier layer CAP1 may be used to prevent the penetration of moisture and / or oxygen (referred to as "moisture / oxygen" herein), and improve the optical properties of the optical structure layer OSL by adjusting the refractive index. The first barrier layer CAP1 may be disposed on the upper surface or the lower surface of the first light control pattern CCP-R so as to be able to block the first light control pattern CCP-R from being exposed to moisture / oxygen, and specifically, may block the quantum dot included in the first light control pattern CCP-R from being exposed to moisture / oxygen. The first barrier layer CAP1 may also protect the first light control pattern CCP-R from external impacts.

[0118] In an embodiment of the present disclosure, the first barrier layer CAP1 may be disposed to be spaced apart from the display element layer DP-LED, and the first light control pattern CCP-R may be interposed therebetween. For example, the first barrier layer CAP1 may be disposed on the upper surface of the first light control pattern CCP-R. In an embodiment of the present disclosure, the light control layer CCL may include a second barrier layer CAP2 disposed between the first light control pattern CCP-R and the display element layer DP-LED. The first barrier layer CAP1 may cover the upper surface of the first light control pattern CCP-R adjacent to the color filter layer CFL, and the second barrier layer CAP2 may cover the lower surface of the first light control pattern CCP-R adjacent to the display element layer DP-LED. In this specification, the "upper surface" may be the surface located at the top based on the third direction DR3, and the "lower surface" may be the surface located at the bottom based on the third direction DR3.

[0119] The first barrier layer CAP1 and the second barrier layer CAP2 may cover the bank BMP and the surface of the first light control pattern CCP-R.

[0120] The first barrier layer CAP1 may cover the bank BMP and the surface of the first light control pattern CCP-R adjacent to the color filter layer CFL. The first barrier layer CAP1 may be directly disposed under the filling layer FML. The second barrier layer CAP2 may be directly disposed on the thin film encapsulation layer TFE. The light control layer CCL may be disposed on the thin film encapsulation layer TFE of the display element layer DP-LED, and the second barrier layer CAP2 may be interposed between the light control layer CCL and the thin film encapsulation layer TFE. The light control patterns CCP-R, CCP-G, and CCP-B of the light control layer CCL may be formed in a continuous process on the second barrier layer CAP2 disposed on the thin film encapsulation layer TFE.

[0121] The first barrier layer CAP1 and the second barrier layer CAP2 may include an inorganic material. In the display panel DP according to an embodiment of the present disclosure, the first barrier layer CAP1 may include silicon oxynitride (SiON). The first barrier layer CAP1 and the second barrier layer CAP2 may include silicon oxynitride. For example, however, and not limited thereto, each of the first barrier layer CAP1 and the second barrier layer CAP2 may include silicon oxide (SiO x ) or silicon nitride (SiN x ). In an embodiment of the present disclosure, the first barrier layer CAP1 disposed on the first light control pattern CCP-R may include silicon oxynitride, and the second barrier layer CAP2 disposed under the first light control pattern CCP-R may include silicon oxide.

[0122] The color filter layer CFL may be disposed on the light control layer CCL. The color filter layer CFL may include at least one color filter. The color filter may transmit light in a specific wavelength range and block light outside of that wavelength range. The first color filter CF1 corresponding to the first pixel region PXA-R may transmit red light and block green and blue light.

[0123] The first color filter CF1 may include a base resin and dyes and / or pigments dispersed in the base resin. The base resin may be a medium in which the dyes and / or pigments are dispersed and may be made of various resin compositions that can generally be referred to as binders.

[0124] The first color filter CF1 may have a uniform thickness in the first pixel region PXA-R. The light converted from blue light as the source light to red light by the first light control pattern CCP-R may be provided to the outside with uniform brightness in the first pixel region PXA-R.

[0125] The optical structure layer OSL may further include a filling layer FML disposed between the light control layer CCL and the color filter layer CFL. In an embodiment of the present disclosure, the filling layer FML may fill the space between the light control layer CCL and the color filter layer CFL. The filling layer FML may be directly disposed on the first barrier layer CAP1, and the color filter layer CFL may be directly disposed on the filling layer FML. The lower surface of the filling layer FML may contact the upper surface of the first barrier layer CAP1, and the upper surface of the filling layer FML may contact the lower surfaces of the color filters CF1, CF2, and CF3 of the color filter layer CFL.

[0126] The filling layer FML may serve as a buffer between the light control layer CCL and the color filter layer CFL. In an embodiment of the present disclosure, the filling layer FML may serve as a shock absorber or the like and increase the strength of the display panel DP. The filling layer FML may be formed of a filling resin including a polymer resin. For example, the filling layer FML may be formed of a filling resin including an acrylic-based resin, an epoxy-based resin, or the like.

[0127] By being disposed between the light control layer CCL and the color filter layer CFL, the filling layer FML may serve as an optical functional layer to increase the light extraction efficiency or prevent reflected light from entering the light control layer CCL. The filling layer FML may have a lower refractive index than the adjacent layers.

[0128] In an embodiment of the present disclosure, the display panel DP may further include a base layer BL disposed on the color filter layer CFL. The base layer BL may be a member that provides a reference surface on which the color filter layer CFL and the light control layer CCL are disposed. The base layer BL may be a glass substrate, a metal substrate, or a plastic substrate. However, the embodiments of the present disclosure are not limited thereto, and the base layer BL may be an inorganic layer, an organic layer, or a composite material layer. Different from what is shown, in an embodiment of the present disclosure, the base layer BL may be omitted.

[0129] Although not shown, an antireflection layer may be disposed on the base layer BL. The antireflection layer may reduce the reflectance of external light incident from the outside. The antireflection layer may selectively transmit light emitted from the display panel DP. In an embodiment of the present disclosure, the antireflection layer may be a single layer including dyes and / or pigments dispersed in a base resin. The antireflection layer may be provided as a single continuous layer that completely overlaps the entire first pixel region PXA-R, second pixel region PXA-G, and third pixel region PXA-B (see Figure 4A ).

[0130] The antireflection layer may not include a polarization layer. Therefore, the light guided to the display element layer DP-LED through the antireflection layer may not be polarized. The display element layer DP-LED may receive unpolarized light from above the antireflection layer.

[0131] Reference Figure 4A , the display panel DP may include a base substrate BS and a circuit element layer DP-CL disposed on the base substrate BS. The circuit element layer DP-CL may be disposed on the base substrate BS. The circuit element layer DP-CL may include an insulating layer, a semiconductor pattern, a conductive pattern, and signal lines. The insulating layer, semiconductor layer, and conductive layer may be formed on the base substrate BS by coating, deposition, etc., and the insulating layer, semiconductor layer, and conductive layer may be selectively patterned by a photolithography process. Thereafter, the semiconductor pattern, conductive pattern, and signal lines included in the circuit element layer DP-CL may be formed. In an embodiment of the present disclosure, the circuit element layer DP-CL may include a transistor, a buffer layer, and an insulating layer.

[0132] The light-emitting element LED according to an embodiment of the present disclosure may include a first electrode EL1, a second electrode EL2 configured to face the first electrode EL1, and a light-emitting layer EML disposed between the first electrode EL1 and the second electrode EL2. The light-emitting layer EML included in the light-emitting element LED may include an organic light-emitting material or a quantum dot as a light-emitting material. The light-emitting element LED may further include a hole control layer HTR and an electron control layer ETR. Although not shown, the light-emitting element LED may further include a capping layer (not shown) disposed on the second electrode EL2.

[0133] The pixel defining layer PDL can be disposed on the circuit element layer DP-CL and cover a part of the first electrode EL1. The light-emitting opening OH can be defined in the pixel defining layer PDL. The light-emitting opening OH of the pixel defining layer PDL can expose at least a part of the first electrode EL1. In this embodiment, the light-emitting regions EA1, EA2, and EA3 can be defined to correspond to the regions of the first electrode EL1 exposed by the light-emitting opening OH.

[0134] The display element layer DP-LED can include a first light-emitting region EA1, a second light-emitting region EA2, and a third light-emitting region EA3. The first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 can be partitioned by the pixel defining layer PDL. The first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 can correspond to a first pixel region PXA-R, a second pixel region PXA-G, and a third pixel region PXA-B, respectively.

[0135] The light-emitting regions EA1, EA2, and EA3 can overlap with the pixel regions PXA-R, PXA-G, and PXA-B. When viewed in a plane, the areas of the pixel regions PXA-R, PXA-G, and PXA-B divided by the color filters CF1, CF2, and CF3 can be substantially equal to the areas of the light-emitting regions EA1, EA2, and EA3.

[0136] In the light-emitting element LED, the first electrode EL1 can be disposed on the circuit element layer DP-CL. The first electrode EL1 can be an anode or a cathode. The first electrode EL1 can be a pixel electrode. The first electrode EL1 can be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode.

[0137] The hole control layer HTR can be disposed between the first electrode EL1 and the light-emitting layer EML. The hole control layer HTR can include at least one of a hole injection layer, a hole transport layer, and an electron blocking layer. The hole control layer HTR can be disposed as a common layer to overlap with the light-emitting regions EA1, EA2, and EA3 and the entire pixel defining layer PDL that separates the light-emitting regions EA1, EA2, and EA3 from each other. However, the embodiments of the present disclosure are not limited thereto, and the hole control layer HTR can be patterned and disposed to be separately disposed corresponding to each of the light-emitting regions EA1, EA2, and EA3.

[0138] The light-emitting layer EML may be disposed on the hole control layer HTR. In an embodiment of the present disclosure, the light-emitting layer EML may be provided as a common layer to overlap with the light-emitting regions EA1, EA2, and EA3 and the entire pixel defining film PDL that separates the light-emitting regions EA1, EA2, and EA3 from each other. In an embodiment of the present disclosure, the light-emitting layer EML may emit blue light. The light-emitting layer EML may completely overlap with the hole control layer HTR and the electron control layer ETR.

[0139] However, the embodiments of the present disclosure are not limited thereto, and in an embodiment of the present disclosure, the light-emitting layer EML may be disposed in the light-emitting opening OH. For example, the light-emitting layer EML may be formed separately to correspond to the light-emitting regions EA1, EA2, and EA3 divided by the pixel defining film PDL. The light-emitting layer EML formed separately to correspond to the light-emitting regions EA1, EA2, and EA3 may all emit blue light or may emit light in different wavelength ranges.

[0140] The light-emitting layer EML may have a single-layer structure composed of a single material, a single-layer structure composed of different materials, or a multi-layer structure having layers composed of different materials. The light-emitting layer EML may include a fluorescent material or a phosphorescent material. In the light-emitting element LED according to an embodiment of the present disclosure, the light-emitting layer EML may include a light-emitting material such as an organic light-emitting material, a metal-organic complex, or a quantum dot. As an example, Figure 3 and Figure 4A shows a light-emitting element LED including one light-emitting layer EML, but in an embodiment of the present disclosure, the light-emitting element LED may include a light-emitting stack each including at least one light-emitting layer.

[0141] Figure 5 is a schematic cross-sectional view of a light-emitting element according to an embodiment of the present disclosure. Different from the light-emitting element according to an embodiment of the present disclosure shown in Figure 3 and Figure 4A as an example, Figure 5 shows a light-emitting element LED including light-emitting stacks ST1, ST2, ST3, and ST4.

[0142] Referring to Figure 5 , the light-emitting element LED according to an embodiment of the present disclosure may include a first electrode EL1, a second electrode EL2 configured to face the first electrode EL1, and a first light-emitting stack ST1, a second light-emitting stack ST2, a third light-emitting stack ST3, and a fourth light-emitting stack ST4 disposed between the first electrode EL1 and the second electrode EL2. As an example, Figure 5 shows that the light-emitting element LED includes four light-emitting stacks, but the number of light-emitting stacks included in the light-emitting element LED may be less than or greater than four.

[0143] The light-emitting element LED may include a first charge generation layer CGL1, a second charge generation layer CGL2, and a third charge generation layer CGL3 disposed between a first light-emitting stack ST1, a second light-emitting stack ST2, a third light-emitting stack ST3, and a fourth light-emitting stack ST4.

[0144] When a voltage is applied, each of the first charge generation layer CGL1, the second charge generation layer CGL2, and the third charge generation layer CGL3 may generate charges (electrons and holes) by forming a complex through an oxidation-reduction reaction. Thereafter, the first charge generation layer CGL1, the second charge generation layer CGL2, and the third charge generation layer CGL3 may supply the generated charges to the adjacent light-emitting stacks ST1, ST2, ST3, and ST4. The first charge generation layer CGL1, the second charge generation layer CGL2, and the third charge generation layer CGL3 may double the efficiency of the current generated in the adjacent light-emitting stacks ST1, ST2, ST3, and ST4 and may play a role in controlling the charge balance between the adjacent light-emitting stacks ST1, ST2, ST3, and ST4.

[0145] Each of the first charge generation layer CGL1, the second charge generation layer CGL2, and the third charge generation layer CGL3 may include an n-type layer and a p-type layer. The first charge generation layer CGL1, the second charge generation layer CGL2, and the third charge generation layer CGL3 may have a structure in which the n-type layer and the p-type layer are combined with each other. However, without being limited thereto, the first charge generation layer CGL1, the second charge generation layer CGL2, and the third charge generation layer CGL3 may include at least one of an n-type layer and a p-type layer only. The n-type layer may be a charge generation layer that supplies electrons to an adjacent light-emitting stack. The n-type layer may be a layer in which an n-dopant is doped in a base material. The p-type layer may be a charge generation layer that supplies holes to an adjacent light-emitting stack.

[0146] In an embodiment of the present disclosure, the thickness of each of the first charge generation layer CGL1, the second charge generation layer CGL2, and the third charge generation layer CGL3 may be in the range of about 1 angstrom to about 150 angstroms The concentration of the n-dopant doped in the first charge generation layer CGL1, the second charge generation layer CGL2, and the third charge generation layer CGL3 may be in the range of about 0.1% to about 3%, for example, about 0.1% to about 1%. When the concentration is less than about 0.1%, the effects of the first charge generation layer CGL1, the second charge generation layer CGL2, and the third charge generation layer CGL3 that control the charge balance may be difficult to manifest. When the concentration is greater than about 3%, the light efficiency of the light-emitting element LED may be reduced.

[0147] Each of the first charge generation layer CGL1, the second charge generation layer CGL2, and the third charge generation layer CGL3 may include a charge generation compound composed of an arylamine-based organic compound, a metal, a metal oxide, a metal carbide, a metal fluoride, or a mixture thereof. For example, the arylamine-based organic compound may include α-NPD, 2-TNATA, TDATA, MTDATA, spiro-TAD, or spiro-NPB. The metal may include cesium (Cs), molybdenum (Mo), vanadium (V), titanium (Ti), tungsten (W), barium (Ba), or lithium (Li). The metal oxide, metal carbide, and metal fluoride may include Re2O7, MoO3, V2O5, WO3, TiO2, Cs2CO3, BaF2, LiF, or CsF. However, the materials of the first charge generation layer CGL1, the second charge generation layer CGL2, and the third charge generation layer CGL3 are not limited to the above examples.

[0148] Each of the first light-emitting stack ST1, the second light-emitting stack ST2, the third light-emitting stack ST3, and the fourth light-emitting stack ST4 may include a light-emitting layer. The first light-emitting stack ST1 may include a first light-emitting layer BEML1, the second light-emitting stack ST2 may include a second light-emitting layer BEML2, the third light-emitting stack ST3 may include a third light-emitting layer BEML3, and the fourth light-emitting stack ST4 may include a fourth light-emitting layer GEML. Some of the light-emitting layers BEML1, BEML2, BEML3, and GEML included in the first light-emitting stack ST1, the second light-emitting stack ST2, the third light-emitting stack ST3, and the fourth light-emitting stack ST4 may emit light of substantially the same color, and some of them may emit light of different colors.

[0149] In an embodiment of the present disclosure, the first light-emitting layer BEML1, the second light-emitting layer BEML2, and the third light-emitting layer BEML3 of the first light-emitting stack ST1, the second light-emitting stack ST2, and the third light-emitting stack ST3 may emit light of substantially the same first color. For example, the first color light may be blue light as the above source light. The wavelength range of the light emitted from the first light-emitting layer BEML1, the second light-emitting layer BEML2, and the third light-emitting layer BEML3 may be from about 420 nm to about 480 nm.

[0150] The fourth light-emitting layer GEML of the fourth light-emitting stack ST4 may emit a second color light different from the first color light. For example, the second color light may be green light. The wavelength range of the light emitted from the fourth light-emitting layer GEML may be from about 520 nm to about 600 nm.

[0151] The light-emitting element LED can emit light in the direction from the first electrode EL1 to the second electrode EL2. In the light-emitting element LED according to an embodiment of the present disclosure, the light-emitting stacks ST1, ST2, ST3, and ST4 may include hole transport regions HTR1, HTR2, HTR3, and HTR4 and electron transport regions ETR1, ETR2, ETR3, and ETR4, respectively. The hole transport regions HTR1, HTR2, HTR3, and HTR4 may transport holes provided from the first electrode EL1 or the charge generation layers CGL1, CGL2, and CGL3 to the light-emitting layers BEML1, BEML2, BEML3, and GEML. The electron transport regions ETR1, ETR2, ETR3, and ETR4 may transport electrons provided from the second electrode EL2 or the charge generation layers CGL1, CGL2, and CGL3 to the light-emitting layers BEML1, BEML2, BEML3, and GEML.

[0152] As an example, it is shown that, based on the direction of light emission, the light-emitting element LED according to an embodiment of the present disclosure has a structure in which the hole transport regions HTR1, HTR2, HTR3, and HTR4 are provided below the light-emitting layers BEML1, BEML2, BEML3, and GEML included in the light-emitting stacks ST1, ST2, ST3, and ST4 and the electron transport regions ETR1, ETR2, ETR3, and ETR4 are provided above the light-emitting layers BEML1, BEML2, BEML3, and GEML included in the light-emitting stacks ST1, ST2, ST3, and ST4. For example, the light-emitting element LED according to an embodiment of the present disclosure may have a forward element structure. However, not limited thereto, based on the direction of light emission, the light-emitting element LED according to an embodiment of the present disclosure may have a reverse element structure in which the electron transport regions ETR1, ETR2, ETR3, and ETR4 are provided below the light-emitting layers BEML1, BEML2, BEML3, and GEML included in the light-emitting stacks ST1, ST2, ST3, and ST4 and the hole transport regions HTR1, HTR2, HTR3, and HTR4 are provided above the light-emitting layers BEML1, BEML2, BEML3, and GEML included in the light-emitting stacks ST1, ST2, ST3, and ST4.

[0153] The hole transport regions HTR1, HTR2, HTR3, and HTR4 may respectively include hole injection layers HIL1, HIL2, HIL3, and HIL4 and hole transport layers HTL1, HTL2, HTL3, and HTL4 disposed on the hole injection layers HIL1, HIL2, HIL3, and HIL4. The hole transport layers HTL1, HTL2, HTL3, and HTL4 may contact the lower surfaces of the light emitting layers BEML1, BEML2, BEML3, and GEML. However, not limited thereto, the hole transport regions HTR1, HTR2, HTR3, and HTR4 may further include hole side additional layers disposed on the hole transport layers HTL1, HTL2, HTL3, and HTL4. The hole side additional layers may include at least one of a hole buffer layer, a light emission assisting layer, and an electron blocking layer. The hole buffer layer may improve the light emission efficiency by compensating for the resonance distance according to the wavelength of the light emitted from the light emitting layers BEML1, BEML2, BEML3, and GEML. The electron blocking layer may be used to prevent electrons from being injected from the electron transport regions ETR1, ETR2, ETR3, and ETR4 into the hole transport regions HTR1, HTR2, HTR3, and HTR4.

[0154] The electron transport regions ETR1, ETR2, ETR3, and ETR4 may include electron transport layers. The electron transport regions ETR1, ETR2, ETR3, and ETR4 may further include electron injection layers disposed on the electron transport layers. For example, the fourth electron transport region ETR4 included in the fourth light emitting stack ST4 may further include a fourth electron injection layer EIL4 disposed on the fourth electron transport layer ETL4. The electron transport regions ETR1, ETR2, ETR3, and ETR4 may further include electron side additional layers disposed between the electron transport layers and the light emitting layers BEML1, BEML2, BEML3, and GEML. The electron side additional layers may include at least one of an electron buffer layer and a hole blocking layer.

[0155] In a light-emitting element LED according to an embodiment of the present disclosure, the first electrode EL1 may be a reflective electrode. For example, the first electrode EL1 may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, F, Mo, Ti, W, In, Zn, Sn, or a compound or mixture thereof (e.g., a mixture of Ag and Mg) that exhibits a high reflectivity, or a material having a multilayer structure such as LiF / Ca or LiF / Al. As another example, the first electrode EL1 may have a multilayer structure including a reflective film formed of the above materials and a transparent conductive film formed of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc. For example, the first electrode EL1 may have a two-layer structure of ITO / Ag and a three-layer structure of ITO / Ag / ITO, but the embodiments of the present disclosure are not limited thereto. Without being limited thereto, the first electrode EL1 may include the above metal materials, a combination of two or more metal materials selected from the above metal materials, oxides of the above metal materials, etc. The thickness of the first electrode EL1 may be in the range of about 70 nm to about 1000 nm. For example, the thickness of the first electrode EL1 may be in the range of about 100 nm to about 300 nm.

[0156] In a light-emitting element LED according to an embodiment of the present disclosure, each of the hole transport regions HTR1, HTR2, HTR3, and HTR4 may have a single-layer structure made of a single material, a single-layer structure made of different materials, or a multilayer structure having layers made of different materials.

[0157] The hole transport regions HTR1, HTR2, HTR3, and HTR4 may be formed by using various methods such as a vacuum deposition method, a spin coating method, a casting method, a Langmuir-Blodgett (LB) method, an inkjet printing method, a laser printing method, and a laser-induced thermal imaging (LITI) method.

[0158] Each of the hole transport regions HTR1, HTR2, HTR3, and HTR4 may contain a phthalocyanine compound such as copper phthalocyanine, DNTPD (N1,N1'-([1,1'-biphenyl]-4,4'-diyl)bis(N1-phenyl-N4,N4-dim-tolyl-1,4-diamine)), m-MTDATA (4,4',4”-[tris(3-methylphenyl)phenylamino]triphenylamine), TDATA (4,4',4”-tris(N,N-diphenylamino)triphenylamine), 2-TNATA (4,4',4”-tris[N(2-naphthyl)-N-phenylamino]-triphenylamine), PEDOT / PSS (poly(3,4-ethylenedioxythiophene) / poly(4-styrenesulfonate)), PANI / DBSA (polyaniline / dodecylbenzenesulfonic acid), PANI / CSA (polyaniline / camphorsulfonic acid), PANI / PSS (polyaniline / poly(4-styrenesulfonate)), NPB (N,N'-di(naphthalen-1-yl)-N,N'-diphenyl-benzidine), polyether ketone containing triphenylamine (TPAPEK), 4-isopropyl-4'-methyldiphenyliodonium [tetrakis(pentafluorophenyl)borate], HATCN (dipyrazino[2,3-f:2',3'-h]quinoxaline-2,3,6,7,10,11-hexacarbonitrile), etc.

[0159] Each of the hole transport regions HTR1, HTR2, HTR3, and HTR4 may contain a carbazolyl derivative (such as N-phenylcarbazole and polyvinylcarbazole), a fluorenyl derivative, TPD (N,N'-bis(3-methylphenyl)-N,N'-diphenyl-[1,1'-biphenyl]-4,4'-diamine), a triphenylamino derivative (such as TCTA (4,4',4”-tris(carbazol-9-yl)triphenylamine)), NPB (N,N'-di(naphthalen-1-yl)-N,N'-diphenylene-benzidine), TAPC (4,4'-cyclohexylidenebis[N,N-bis(4-methylphenyl)aniline]), HMTPD (4,4'-bis[N,N'-(3-tolyl)amino]-3,3'-dimethylbiphenyl), mCP (1,3-bis(carbazol-9-yl)benzene), etc.

[0160] Each of the hole transport regions HTR1, HTR2, HTR3, and HTR4 may contain CzSi (9-(4-tert-butylphenyl)-3,6-bis(triphenylsilyl)-9H-carbazole), CCP (9-phenyl-9H-3,9'-bicarbazole), mDCP (1,3-bis(1,8-dimethyl-9H-carbazol-9-yl)benzene), etc.

[0161] In the hole transport regions HTR1, HTR2, HTR3, and HTR4, the compound in the hole transport region may be included in at least one of the hole injection layers HIL1, HIL2, HIL3, and HIL4, the hole transport layers HTL1, HTL2, HTL3, and HTL4, and the hole-side additional layer.

[0162] The thickness of each of the hole transport regions HTR1, HTR2, HTR3, and HTR4 may be in the range of about 10 nm to about 1000 nm, for example, about 10 nm to about 500 nm. The thickness of each of the hole injection layers HIL1, HIL2, HIL3, and HIL4 may be, for example, in the range of about 5 nm to about 100 nm. The thickness of each of the hole transport layers HTL1, HTL2, HTL3, and HTL4 may be in the range of about 5 nm to about 100 nm. In the case where the hole transport regions HTR1, HTR2, HTR3, and HTR4 include a hole-side additional layer, the thickness of the hole-side additional layer may be in the range of about 1 nm to about 100 nm. When the thickness of the hole transport regions HTR1, HTR2, HTR3, and HTR4 and the thickness of each layer included therein satisfy the above ranges, satisfactory hole transport characteristics can be obtained without significantly increasing the driving voltage.

[0163] In addition to the above materials, each of the hole transport regions HTR1, HTR2, HTR3, and HTR4 may further include a charge generation material to improve conductivity. The charge generation material may be uniformly or non-uniformly dispersed within the hole transport regions HTR1, HTR2, HTR3, and HTR4. The charge generation material may be, for example, a p-type dopant. The p-type dopant may include at least one of a metal halide compound, a quinone derivative, a metal oxide, and a compound containing a cyano group, but the embodiments of the present disclosure are not limited thereto. For example, the p-dopant may include metal halide compounds such as CuI and RbI, quinone derivatives such as TCNQ (tetracyanoquinodimethane) and F4-TCNQ (2,3,5,6-tetrafluoro-7,7',8,8'-tetracyanoquinodimethane), metal oxides such as tungsten oxide and molybdenum oxide, etc., but the embodiments of the present disclosure are not limited thereto.

[0164] Each of the blue emission layers BEML1, BEML2, and BEML3 and the green emission layer GEML may include a host material and a dopant material. Each of the blue emission layers BEML1, BEML2, and BEML3 and the green emission layer GEML may include a material containing a carbazole derivative moiety or an amine derivative moiety as a hole-transporting host material. Each of the blue emission layers BEML1, BEML2, and BEML3 and the green emission layer GEML may include a material having a nitrogen-containing aromatic ring structure (such as a pyridine derivative moiety, a pyridazine derivative moiety, a pyrimidine derivative moiety, a pyrazine derivative moiety, and a triazine derivative moiety) as an electron-transporting host material.

[0165] Each of the blue emission layers BEML1, BEML2, and BEML3 and the green emission layer GEML may include an anthracene derivative, a pyrene derivative, a fluoranthene derivative, a derivative, a dihydrobenzanthracene derivative, or a benzophenanthrene derivative as a host material. Each of the blue emission layers BEML1, BEML2, and BEML3 and the green emission layer GEML may also include a conventional material known in the art as a host material. For example, as a host material, each of the blue emission layers BEML1, BEML2, and BEML3 and the green emission layer GEML may include at least one of DPEPO (bis[2-(diphenylphosphino)phenyl]ether oxide), CBP (4,4'-bis(carbazol-9-yl)biphenyl), mCP (1,3-bis(carbazol-9-yl)benzene), PPF (2,8-bis(diphenylphosphoryl)dibenzofuran), TCTA (4,4',4”-tris(carbazol-9-yl)-triphenylamine), and TPBi (1,3,5-tris(1-phenyl-1H-benzo[d]imidazol-2-yl)benzene). However, embodiments of the present disclosure are not limited thereto, and for example, Alq3 (tris(8-hydroxyquinolinato)aluminum), PVK (poly(N-vinylcarbazole)), ADN (9,10-di(naphthalen-2-yl)anthracene), TBADN (2-tert-butyl-9,10-di(naphthalen-2-yl)anthracene), DSA (stilbenylarylide), CDBP (4,4'-bis(9-carbazolyl)-2,2'-dimethyl-biphenyl), MADN (2-methyl-9,10-bis(naphthalen-2-yl)anthracene), CP1 (hexaphenylcyclotriphosphazene), UGH2 (1,4-bis(triphenylsilyl)benzene), DPSiO3 (hexaphenylcyclotrisiloxane), DPSiO4 (octaphenylcyclotetrasiloxane), etc. may be used as a host material.

[0166] In embodiments of the present disclosure, as known fluorescent dopant materials, the blue light-emitting layers BEML1, BEML2, and BEML3 may include styryl derivatives (e.g., 1,4-bis[2-(3-N-ethylcarbazolyl)vinyl]benzene (BCzVB), 4-(di-p-tolylamino)-4'-[(di-p-tolylamino)styryl]stilbene (DPAVB), N-(4-((E)-2-(6-((E)-4-(diphenylamino)styryl)naphthalen-2-yl)vinyl)phenyl)-N-phenylaniline (N-BDAVBi), 4,4'-bis[2-(4-(N,N-diphenylamino)phenyl)vinyl]biphenyl (DPAVBi)), perylene and its derivatives (e.g., 2,5,8,11-tetra-tert-butylperylene (TBP)), pyrene and its derivatives (e.g., 1,1-dipyrene, 1,4-dipyrenylbenzene, 1,4-bis(N,N-diphenylamino)pyrene), etc.).

[0167] The green light-emitting layer GEML may include known phosphorescent dopant materials. For example, metal complexes containing iridium (Ir), platinum (Pt), osmium (Os), gold (Au), titanium (Ti), zirconium (Zr), hafnium (Hf), europium (Eu), terbium (Tb), or thulium (Tm) may be used as phosphorescent dopants. Specifically, FIrpic (iridium(III) bis(4,6-difluorophenylpyridinato-N,C2') picolinate), Fir6 (iridium(III) bis(2,4-difluorophenylpyridinato)-tetrakis(1-pyrazolyl)borate), or PtOEP (platinum octaethylporphyrin) may be used as phosphorescent dopants.

[0168] Each of the electron transport regions ETR1, ETR2, ETR3, and ETR4 may have a single-layer structure made of a single material, a single-layer structure made of different materials, or a multilayer structure having layers made of different materials. For example, at least some of the electron transport regions ETR1, ETR2, ETR3, and ETR4 may include a fourth electron transport layer ETL4 and a fourth electron injection layer EIL4.

[0169] Each of the electron transport regions ETR1, ETR2, ETR3, and ETR4 may be formed by using various methods such as a vacuum deposition method, a spin coating method, a casting method, a Langmuir-Blodgett (LB) method, an inkjet printing method, a laser printing method, and a laser-induced thermal imaging (LITI) method.

[0170] The electron transport regions ETR1, ETR2, ETR3, and ETR4 may include anthracene-based compounds. However, not limited thereto, each of the electron transport regions ETR1, ETR2, ETR3, and ETR4 may include, for example, Alq3 (tris(8-hydroxyquinolinato)aluminum), 1,3,5-tris[(3-pyridinyl)-benzene-3-yl]benzene, T2T (2,4,6-tris(3'-(pyridin-3-yl)biphenyl-3-yl)-1,3,5-triazine), 2-(4-(N-phenylbenzimidazol-1-yl)phenyl)-9,10-dinaphthylanthracene, TPBi (1,3,5-tris(1-phenyl-1H-benzo[d]imidazol-2-yl)benzene), BCP (2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline), Bphen (4,7-diphenyl-1,10-phenanthroline), TAZ (3-(4-biphenylyl)-4-phenyl-5-tert-butylphenyl-1,2,4-triazole), NTAZ (4-(naphthalen-1-yl)-3,5-diphenyl-4H-1,2,4-triazole), tBu-PBD (2-(4-biphenylyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole), BAlq (bis(2-methyl-8-quinolinato-N1,O8)-(1,1'-biphenyl-4-yl)aluminum), BeBq2 (beryllium bis(benzoquinolin-10-yl)), ADN (9,10-di(naphthalen-2-yl)anthracene), BmPyPhB (1,3-bis[3,5-bis(pyridin-3-yl)phenyl]benzene), and mixtures thereof.

[0171] Each of the electron transport regions ETR1, ETR2, ETR3, and ETR4 may include a metal halide such as LiF, NaCl, CsF, RbCl, RbI, CuI, and KI, a lanthanide metal such as Yb, and a co-deposited material of a metal halide and a lanthanide metal. For example, the electron transport regions ETR1, ETR2, ETR3, and ETR4 may include KI:Yb, RbI:Yb, etc. as co-deposited materials. The electron transport regions ETR1, ETR2, ETR3, and ETR4 may include two or more materials selected from Mg, Ag, Yb, and Al. For example, the electron transport regions ETR1, ETR2, ETR3, and ETR4 may include Mg and Yb.

[0172] The electron transport regions ETR1, ETR2, ETR3, and ETR4 can be made of metal oxides such as Li2O and BaO, Liq (lithium 8-hydroxyquinoline), etc., but the embodiments of the present disclosure are not limited thereto. Each of the electron transport regions ETR1, ETR2, ETR3, and ETR4 can also be made of a mixture of an electron transport material and an insulating organic metal salt. The organic metal salt can be a material having a band gap of about 4 eV or higher. Specifically, for example, the organic metal salt can include metal acetates, metal benzoates, metal acetoacetates, metal acetylacetonates, or metal stearates.

[0173] In addition to the above materials, each of the electron transport regions ETR1, ETR2, ETR3, and ETR4 can also include at least one of BCP (2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline) and Bphen (4,7-diphenyl-1,10-phenanthroline), but the embodiments of the present disclosure are not limited thereto.

[0174] The electron transport regions ETR1, ETR2, ETR3, and ETR4 can include the compounds of the above electron transport regions ETR1, ETR2, ETR3, and ETR4 in the electron injection layer or the electron transport layer. In the case where the electron transport regions ETR1, ETR2, ETR3, and ETR4 include an electron-side additional layer, the electron-side additional layer can include the above materials. In the embodiments of the present disclosure, the fourth electron injection layer EIL4 can be composed of two or more materials selected from Mg, Ag, Yb, and Al. The fourth electron injection layer EIL4 can be composed of a mixture of, for example, Mg and Yb.

[0175] The thickness of each of the electron transport regions ETR1, ETR2, ETR3, and ETR4 can be, for example, in the range of about 10 nm to about 150 nm. The thickness of the electron transport layer can be in the range of about 0.1 nm to about 100 nm, for example, in the range of about 0.3 nm to about 50 nm. When the thickness of the electron transport layer satisfies the above range, satisfactory electron transport characteristics can be obtained without significantly increasing the driving voltage.

[0176] The second electrode EL2 can be disposed on the light-emitting stacks ST1, ST2, ST3, and ST4. The second electrode EL2 can be a common electrode. The second electrode EL2 can be a cathode or an anode, but the embodiments of the present disclosure are not limited thereto. For example, when the first electrode EL1 is an anode, the second electrode EL2 can be a cathode, and when the first electrode EL1 is a cathode, the second electrode EL2 can be an anode.

[0177] The second electrode EL2 can be a semi-transmissive electrode or a transmissive electrode. When the second electrode EL2 is a transmissive electrode, the second electrode EL2 is made of a transparent metal oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium tin zinc oxide (ITZO).

[0178] When the second electrode EL2 is a semi-transmissive electrode or a reflective electrode, the second electrode EL2 can include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, F, Mo, Ti, Yb, W, In, Zn, Sn, or a compound or mixture containing them (e.g., AgMg, AgYb, or MgAg), or a material having a multi-layer structure such as LiF / Ca or LiF / Al. As another example, the second electrode EL2 can have a multi-layer structure, the multi-layer structure including a reflective or semi-transmissive film formed of the above materials and a transparent conductive film formed of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc. For example, the second electrode EL2 can include one of the aforementioned metal materials, a combination of two or more metal materials selected from the aforementioned metal materials, oxides of the aforementioned metal materials, etc.

[0179] Although not shown, the second electrode EL2 can be connected to an auxiliary electrode. When the second electrode EL2 is connected to the auxiliary electrode, the resistance of the second electrode EL2 can be reduced.

[0180] According to an embodiment of the present disclosure, a capping layer CPL can be further provided on the second electrode EL2 of the light-emitting element LED. The capping layer CPL can include multiple layers or a single layer.

[0181] In an embodiment of the present disclosure, the capping layer CPL can be an organic layer or an inorganic layer. For example, when the capping layer CPL includes an inorganic material, the inorganic material can include an alkali metal compound such as LiF, an alkaline earth metal compound such as MgF2, SiON, SiN X , SiO y , etc.

[0182] For example, when the capping layer CPL includes an organic material, the organic material can include α-NPD, NPB, TPD, m-MTDATA, Alq3, CuPc, TPD15 (N4, N4, N4', N4'-tetrakis(biphenyl-4-yl)biphenyl-4,4'-diamine), TCTA (4,4',4”-tris(carbazol-9-yl)triphenylamine), etc., or include an epoxy resin or an acrylate such as a methacrylate.

[0183] The refractive index of the capping layer CPL can be about 1.6 or greater. Specifically, with respect to light having a wavelength range of about 550 nm to about 660 nm, the refractive index of the capping layer CPL can be about 1.6 or greater.

[0184] Referring again to Figure 4A , in the light-emitting element LED according to an embodiment of the present disclosure, the electron control layer ETR can be disposed between the light-emitting layer EML and the second electrode EL2. The electron control layer ETR can include at least one of an electron injection layer, an electron transport layer, and a hole blocking layer. Referring to Figure 4A , the electron control layer ETR can be provided as a common layer so as to completely overlap with the light-emitting regions EA1, EA2, and EA3 and the pixel defining film PDL that separates the light-emitting regions EA1, EA2, and EA3. However, the embodiments of the present disclosure are not limited thereto, and the electron control layer ETR can be patterned and disposed so as to be separately provided corresponding to each of the light-emitting regions EA1, EA2, and EA3.

[0185] The second electrode EL2 can be disposed on the electron control layer ETR. The second electrode EL2 can be a common electrode. The second electrode EL2 can be a cathode or an anode, but the embodiments of the present disclosure are not limited thereto. For example, when the first electrode EL1 is an anode, the second electrode EL2 can be a cathode, and when the first electrode EL1 is a cathode, the second electrode EL2 can be an anode. The second electrode EL2 can be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode.

[0186] The thin film encapsulation layer TFE can be disposed on the light-emitting element LED. For example, in an embodiment of the present disclosure, the thin film encapsulation layer TFE can be disposed on the second electrode EL2. In the case where the light-emitting element LED includes a capping layer (not shown), the thin film encapsulation layer TFE can be disposed on the capping layer (not shown). As described above, the thin film encapsulation layer TFE can include at least one organic layer and at least one inorganic layer, and the inorganic layer and the organic layer can be alternately disposed.

[0187] The display panel DP according to an embodiment of the present disclosure can include an optical structure layer OSL disposed on the display element layer DP-LED. The optical structure layer OSL can include a light control layer CCL, a color filter layer CFL, and a base layer BL.

[0188] The light control layer CCL can include a light converter. The light converter can be a quantum dot, a phosphor, etc. The light converter can convert the wavelength of the received light and emit the converted light. For example, the light control layer CCL can be a layer that at least partially includes quantum dots or phosphors.

[0189] The light control layer CCL may include light control patterns CCP-R, CCP-G, and CCP-B. The light control patterns CCP-R, CCP-G, and CCP-B may be spaced apart from each other. The light control patterns CCP-R, CCP-G, and CCP-B may be arranged to be spaced apart from each other by the dam BMP. The light control patterns CCP-R, CCP-G, and CCP-B may be disposed in dam openings BOH1, BOH2, and BOH3 defined in the dam BMP. However, embodiments of the present disclosure are not limited thereto. In Figure 4A , the dam BMP is shown as having a rectangular shape and not overlapping with the light control patterns CCP-R, CCP-G, and CCP-B in cross-section, but the edges of some of the light control patterns CCP-R, CCP-G, and CCP-B may at least partially overlap with the dam BMP. For example, the edge of the third light control pattern CCP-B may be arranged to overlap with the dam BMP in a plane. The dam BMP may have a trapezoidal shape in cross-section. The dam BMP may have a shape in which the cross-sectional width of the dam BMP increases as it approaches the display element layer DP-LED.

[0190] The light control patterns CCP-R, CCP-G, and CCP-B may convert the wavelength of the light provided from the display element layer DP-LED or transmit the provided light.

[0191] The light control layer CCL may include a first light control pattern CCP-R that provides red light as the first light, a second light control pattern CCP-G that provides green light as the second light, and a third light control pattern CCP-B that provides blue light as the third light. The light control layer CCL may include a first light control pattern CCP-R that converts the source light provided from the light-emitting element LED into the first light, a second light control pattern CCP-G that converts the source light into the second light, and a third light control pattern CCP-B that transmits the source light. At least some of the light control patterns CCP-R, CCP-G, and CCP-B may include quantum dots that convert the source light into light of a specific wavelength.

[0192] Some of the light control patterns CCP-R, CCP-G, and CCP-B can be formed by an inkjet process. In an embodiment of the present disclosure, the first light control pattern CCP-R and the second light control pattern CCP-G can be formed by an inkjet process. A liquid ink composition can be provided within each of the first dam opening BOH1 and the second dam opening BOH2, and the provided ink composition can be polymerized by a thermal curing process or a photo-curing process to form the first light control pattern CCP-R and the second light control pattern CCP-G. Other light control patterns among the light control patterns CCP-R, CCP-G, and CCP-B can be formed by a photoresist process. In an embodiment of the present disclosure, the third light control pattern CCP-B can be formed by a photoresist process. After the photoresist composition is at least provided in the third dam opening BOH3, the third light control pattern CCP-B can be formed by curing the provided photoresist composition.

[0193] The light control layer CCL may further include a scatterer. The first light control pattern CCP-R may include a first quantum dot and a scatterer, the second light control pattern CCP-G may include a second quantum dot and a scatterer, and the third light control pattern CCP-B may not include a quantum dot but may include a scatterer. Each of the first light control pattern CCP-R, the second light control pattern CCP-G, and the third light control pattern CCP-B may further include a base resin that disperses the quantum dots and the scatterer. Since the third light control pattern CCP-B is formed by the photoresist process described below, the third light control pattern CCP-B may include a photosensitive resin.

[0194] The light control layer CCL may include a first barrier layer CAP1 disposed on one side of the first light control pattern CCP-R. The light control layer CCL may include the first barrier layer CAP1 spaced apart from the display element layer DP-LED with the light control patterns CCP-R, CCP-G, and CCP-B interposed therebetween and a second barrier layer CAP2 adjacent to the display element layer DP-LED.

[0195] In the display panel DP, the optical structure layer OSL may include a color filter layer CFL disposed on the light control layer CCL. The color filter layer CFL may include color filters CF1, CF2, and CF3. The color filter layer CFL may include a first color filter CF1 configured to transmit a first light, a second color filter CF2 configured to transmit a second light, and a third color filter CF3 configured to transmit source light. In an embodiment of the present disclosure, the first color filter CF1 may be a red color filter, the second color filter CF2 may be a green color filter, and the third color filter CF3 may be a blue color filter.

[0196] Each of the color filters CF1, CF2, and CF3 may include a polymer photosensitive resin and a colorant. The first color filter CF1 may include a red colorant, the second color filter CF2 may include a green colorant, and the third color filter CF3 may include a blue colorant. The first color filter CF1 may include a red pigment or a red dye, the second color filter CF2 may include a green pigment or a green dye, and the third color filter CF3 may include a blue pigment or a blue dye.

[0197] The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be respectively disposed corresponding to the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be respectively disposed corresponding to the first light control pattern CCP-R, the second light control pattern CCP-R, and the third light control pattern CCP-B.

[0198] In the peripheral region NPXA disposed between the pixel regions PXA-R, PXA-G, and PXA-B, the color filters CF1, CF2, and CF3 configured to transmit different lights may be set to overlap each other. The color filters CF1, CF2, and CF3 may be set to overlap each other in the third direction DR3 as the thickness direction to define a boundary between adjacent pixel regions PXA-R, PXA-G, and PXA-B. Different from what is shown, the color filter layer CFL may include a light-blocking portion (not shown) to define a boundary between adjacent color filters CF1, CF2, and CF3. The light-blocking portion (not shown) may be formed of a blue color filter or may be formed by including an inorganic light-blocking material or an organic light-blocking material including a black pigment or a black dye.

[0199] The optical structure layer OSL may include a filling layer FML disposed between the light control layer CCL and the color filter layer CFL. The filling layer FML may be disposed between the light control patterns CCP-R, CCP-G, and CCP-B and the color filters CF1, CF2, and CF3. The filling layer FML may be disposed on the light control layer CCL to prevent the light control patterns CCP-R, CCP-G, and CCP-B from being exposed to moisture or oxygen. By being disposed between the light control patterns CCP-R, CCP-G, and CCP-B and the color filters CF1, CF2, and CF3, the filling layer FML may serve as an optical functional layer to improve the light extraction efficiency or prevent reflected light from being incident on the light control layer CCL. The filling layer FML may have a lower refractive index than other adjacent layers.

[0200] In an embodiment of the present disclosure, the optical structure layer OSL may further include a base layer BL disposed on the color filter layer CFL. The base layer BL may be a member that provides a base surface on which the color filter layer CFL and the light control layer CCL are disposed. For example, the base layer BL may be a glass substrate, a metal substrate, or a plastic substrate. However, the embodiments of the present disclosure are not limited thereto, and the base layer BL may be an inorganic layer, an organic layer, or a composite material layer. Different from what is shown, in an embodiment of the present disclosure, the base layer BL may be omitted.

[0201] Figures 4B to 4D Display panels DP-1, DP-2, and DP-3 according to embodiments of the present disclosure are respectively shown, which are different from the display panel DP according to the embodiments of the present disclosure shown in Figure 4A the present disclosure.

[0202] Referring to Figure 4B , a display panel DP-1 according to an embodiment of the present disclosure may include a lower panel and an optical structure layer OSL disposed on the lower panel. The lower panel includes a base substrate BS, a circuit element layer DP-CL disposed on the base substrate BS, and a display element layer DP-LED disposed on the circuit element layer DP-CL. The optical structure layer OSL may include a light control layer CCL, a color filter layer CFL, and a base layer BL.

[0203] A display panel DP-1 according to an embodiment of the present disclosure may include a lower panel and an upper panel. The lower panel includes a display element layer DP-LED, and the upper panel (optical structure layer OSL) includes a light control layer CCL and a color filter layer CFL. And in an embodiment of the present disclosure, a filling layer FML may be disposed between the lower panel and the upper panel.

[0204] In an embodiment of the present disclosure, the filling layer FML may fill the space between the display element layer DP-LED and the light control layer CCL. The filling layer FML may be directly disposed on the thin film encapsulation layer TFE, and a second barrier layer CAP2 may be directly disposed on the filling layer FML. The lower surface of the filling layer FML may contact the upper surface of the thin film encapsulation layer TFE, and the upper surface of the filling layer FML may contact the lower surface of the second barrier layer CAP2.

[0205] The filling layer FML may be used as a buffer between the display element layer DP-LED and the light control layer CCL. In an embodiment of the present disclosure, the filling layer FML may perform functions such as shock absorption, and increase the strength of the display panel DP-1. In an embodiment, the filling layer FML may be formed of a filling resin including a polymer resin. For example, the filling layer FML may be formed of a filling resin including an acrylic-based resin, an epoxy-based resin, etc.

[0206] Compared with Figure 4ACompared with the display panel DP shown in Figure 4B The display panel DP-1 according to an embodiment of the present disclosure shown in Figure 4B is an embodiment in which the filling layer FML is provided between the display element layer DP-LED and the light control layer CCL. For example, in Figure 4B In the display panel DP-1 of Figure 4B , the circuit element layer DP-CL and the display element layer DP-LED as the lower panel can be provided on the upper surface of the base substrate BS serving as the base surface, and the color filter layer CFL and the light control layer CCL as the upper panel (optical structure layer OSL) can be provided on the upper surface of the base layer BL serving as the base surface, and the display panel DP-1 can be formed by joining the lower panel and the upper panel to each other with the filling layer FML interposed therebetween.

[0207] In the display panel DP-1 according to an embodiment of the present disclosure, a step difference or height difference may occur between the lower surface of the bank BMP and the lower surfaces of the light control patterns CCP-R, CCP-G, and CCP-B. For example, the lower surface of the bank BMP may be defined as being higher than the lower surfaces of the light control patterns CCP-R, CCP-G, and CCP-B. The height difference between the lower surface of the bank BMP and the lower surfaces of the light control patterns CCP-R, CCP-G, and CCP-B may be, for example, in the range of about 2 μm to about 3 μm.

[0208] The second barrier layer CAP2 may be provided to follow the step difference between the bank BMP and the light control patterns CCP-R, CCP-G, and CCP-B. The second barrier layer CAP2 may be directly provided on the filling layer FML.

[0209] The display panel DP-1 according to an embodiment of the present disclosure may include a low refractive index layer LR. The low refractive index layer LR may be provided between the light control layer CCL and the color filter layer CFL. The low refractive index layer LR may be provided above the light control layer CCL to prevent the light control patterns CCP-R, CCP-G, and CCP-B from being exposed to moisture / oxygen. By being provided between the light control patterns CCP-R, CCP-G, and CCP-B and the color filters CF1, CF2, and CF3, the low refractive index layer LR can also serve as an optical function layer to improve the light extraction efficiency or prevent reflected light from entering the light control layer CCL. The low refractive index layer LR may have a lower refractive index than the adjacent layers.

[0210] The low refractive index layer LR may include at least one inorganic layer. For example, the low refractive index layer LR may include silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, silicon oxynitride, a metal thin film, etc. having a fixed light transmittance. However, the embodiments of the present disclosure are not limited thereto, and the low refractive index layer LR may include an organic layer. For example, the low refractive index layer LR may have a structure in which hollow particles are dispersed in an organic polymer resin. The low refractive index layer LR may be composed of a single layer or multiple layers.

[0211] Reference Figure 4C According to an embodiment of the present disclosure, the display panel DP-2 may include a lower panel and an optical structure layer OSL-1 disposed on the lower panel. The lower panel includes a base substrate BS, a circuit element layer DP-CL disposed on the base substrate BS, and a display element layer DP-LED disposed on the circuit element layer DP-CL. In the display panel DP-2 according to an embodiment of the present disclosure, the optical structure layer OSL-1 may include a light control layer CCL-1, a low refractive index layer LR-1, a color filter layer CFL-1, and a base layer BL-1 sequentially stacked on the thin film encapsulation layer TFE. The optical structure layer OSL-1 may include a first barrier layer CAP1 and a second barrier layer CAP2 disposed on the upper surface and the lower surface of the light control layer CCL-1.

[0212] The light control layer CCL-1 may be disposed above the display element layer DP-LED and the thin film encapsulation layer TFE, and the second barrier layer CAP2 may be interposed therebetween. The light control layer CCL-1 may include dams BMP and light control patterns CCP-R, CCP-G, and CCP-B disposed between the dams BMP. The low refractive index layer LR-1 may be disposed on the light control layer CCL-1.

[0213] The color filter layer CFL-1 may include color filters CF1, CF2, and CF3 and a light blocking portion BM.

[0214] Compared with Figure 4B the display panel DP-1 shown in Figure 4CThe display panel DP-2 according to an embodiment of the present disclosure shown in [Figure] is an embodiment in which a light control layer CCL-1, a low refractive index layer LR-1, and a color filter layer CFL-1 are provided on the upper surface of a thin film encapsulation layer TFE serving as a base surface. For example, the light control patterns CCP-R, CCP-G, and CCP-B of the light control layer CCL-1 can be formed on the thin film encapsulation layer TFE by a continuous process, and the color filters CF1, CF2, and CF3 of the color filter layer CFL-1 can be sequentially formed on the light control layer CCL-1 by a continuous process. The light control layer CCL-1 can be formed on the upper surface of a second barrier layer CAP2 provided on the thin film encapsulation layer TFE and serving as a base surface, and can have a shape that is vertically reversed compared to the shape of the light control layer CCL shown in Figure 4A Specifically, each of the dams BMP and the light control patterns CCP-R, CCP-G, and CCP-B can have a shape that is vertically reversed compared to the shape shown in Figure 4A . The color filter layer CFL-1 can be formed on the upper surface of the light control layer CCL-1 serving as a base surface, and can have a shape different from the shape shown in Figure 4A .

[0215] In the color filter layer CFL-1 according to an embodiment of the present disclosure, the light blocking portion BM can be a black matrix. The light blocking portion BM can be formed of an inorganic light blocking material or an organic light blocking material including a black pigment or a black dye. The light blocking portion BM can prevent light leakage between adjacent color filters CF1, CF2, and CF3 and define a boundary.

[0216] Referring to Figure 4D , the display element layer DP-LED1 included in the display panel DP-3 according to an embodiment of the present disclosure can include a light emitting element LED-1, and the light emitting element LED-1 can be a micro LED element or a nano LED element. The light emitting element LED-1 can be disposed between portions of a pixel defining film PDL, and can be electrically connected to a contact portion S-C, and the length and width of the light emitting element LED-1 can be about several hundred nanometers to about several hundred micrometers. The light emitting element LED-1 can be an LED element including an active layer and at least one semiconductor material layer. The light emitting element LED-1 can further include an insulating layer covering the surfaces of the active layer and the semiconductor material layer. The light emitting element LED-1 can be patterned and disposed to overlap each of the pixel regions PXA-R, PXA-G, and PXA-B. The display panel DP-3 can include a buffer layer BFL provided on the light emitting element LED-1. The buffer layer BFL can be provided on the light emitting element LED-1 and cover the light emitting element LED-1. In the display panel DP-3 according to an embodiment of the present disclosure shown in Figure 4D , the buffer layer BFL can be omitted.

[0217] Figure 6A is a schematic enlarged plan view of a part of a display panel according to an embodiment of the present disclosure. Figure 6B is a schematic enlarged plan view of a part of a display panel according to an embodiment of the present disclosure. Figure 7 is a schematic cross-sectional view of a part of a display panel according to an embodiment of the present disclosure. In Figure 2 the display area DA shown, Figure 6A the arrangement shapes of the filter regions FA1, FA2, and FA3 and the bank openings BOH1, BOH2, and BOH3 on a plane corresponding to the first filter region FA1, the second filter region FA2, and the third filter region FA3 are shown. Figure 6B shows on a plane corresponding to Figure 6A the light-emitting openings OH formed in the pixel defining film PDL and the planar shapes of the light-emitting regions EA1, EA2, and EA3 defined by the light-emitting openings OH. Figure 7 shows a cross-section corresponding to the line III-III' shown in Figure 2 .

[0218] Referring to Figure 2 , Figure 3 , Figure 4A and Figure 6A , the first filter region FA1, the second filter region FA2, and the third filter region FA3 may respectively correspond to the above-mentioned first pixel region PXA-R, second pixel region PXA-G, and third pixel region PXA-B, and may be defined by the color filters CF1, CF2, and CF3. The first filter region FA1 may be defined by the first color filter CF1, the second filter region FA2 may be defined by the second color filter CF2, and the third filter region FA3 may be defined by the third color filter CF3. The first filter region FA1 may overlap with the first color filter CF1 and may not overlap with the second color filter CF2 and the third color filter CF3. The second filter region FA2 may overlap with the second color filter CF2 and may not overlap with the first color filter CF1 and the third color filter CF3. The third filter region FA3 may overlap with the third color filter CF3 and may not overlap with the first color filter CF1 and the second color filter CF2.

[0219] Each of the first filter region FA1, the second filter region FA2, and the third filter region FA3 may have a rectangular shape. Each of the first filter region FA1, the second filter region FA2, and the third filter region FA3 may have a rectangular shape having a short side extending in a first direction DR1 and a long side extending in a second direction DR2. The areas of the first filter region FA1, the second filter region FA2, and the third filter region FA3 may be set according to the color of the emitted light. The area of the first filter region FA1 that emits red light may be the largest, and the area of the third filter region FA3 that emits blue light may be the smallest.

[0220] The bank openings BOH defined in the bank BMP may include a first bank opening BOH1, a second bank opening BOH2, and a third bank opening BOH3. The first light control pattern CCP-R may be disposed in the first bank opening BOH1, the second light control pattern CCP-G may be disposed in the second bank opening BOH2, and the third light control pattern CCP-B may be disposed in the third bank opening BOH3. In the present specification, the region defined by the first bank opening BOH1 may be described as the first bank region BA1, the region defined by the second bank opening BOH2 may be described as the second bank region BA2, and the region defined by the third bank opening BOH3 may be described as the third bank region BA3.

[0221] In an embodiment of the present disclosure, the first bank region BA1 may include a first sub-region BSA1 and a second sub-region BSA2. The first sub-region BSA1 and the second sub-region BSA2 may have an integral shape and may be connected to each other. The first light control pattern CCP-R may be disposed in the first bank opening BOH1 that defines each of the first sub-region BSA1 and the second sub-region BSA2. For example, the first light control pattern CCP-R may be disposed to overlap the first sub-region BSA1 and the second sub-region BSA2.

[0222] The first sub-region BSA1 may have a first width W1 in the first direction DR1, and the second sub-region BSA2 may have a second width W2 greater than the first width W1 in the first direction DR1. For example, the second sub-region BSA2 may have a width larger than that of the first sub-region BSA1 in the first direction DR1. The length of the second sub-region BSA2 in the second direction DR2 may be less than the length of the first sub-region BSA1 in the second direction DR2. In other words, the second sub-region BSA2 may have a length shorter than that of the first sub-region BSA1 in the second direction DR2. The first width W1 may be in the range of about 25 micrometers to about 30 micrometers, and the second width W2 may be in the range of about 35 micrometers to about 50 micrometers.

[0223] The first filter region FA1 may overlap with a part of the first sub-region BSA1 and the second sub-region BSA2. The first filter region FA1 may have a first filter width W-F1 in the first direction DR1, and the first filter width W-F1 may be less than the first width W1. The first sub-region BSA1 may have a first length L1 in the second direction DR2, the first filter region FA1 may have a first filter length L-F1 in the second direction DR2, and the first filter length L-F1 may be greater than the first length L1. For example, the first filter region FA1 may be arranged to overlap with the first sub-region BSA1 except for a part of the outer region of the first sub-region BSA1, and the length of the first filter region FA1 in the second direction DR2 may be greater than the length of the first sub-region BSA1 in the second direction DR2. Therefore, a part of the first filter region FA1 may be arranged to extend into the second sub-region BSA2.

[0224] A part of the second sub-region BSA2 may include a part that does not overlap with the first filter region FA1. The connection region CNA described below may overlap with the part of the second sub-region BSA2 that does not overlap with the first filter region FA1.

[0225] The first sub-region BSA1 may include a (1-1) side S1-1 and a (1-2) side S1-2 that are spaced apart from each other in the first direction DR1. The second sub-region BSA2 may include a (2-1) side S2-1 and a (2-2) side S2-2 that are spaced apart from each other in the first direction DR1. The above-mentioned first width W1 may be the spacing distance between the (1-1) side S1-1 and the (1-2) side S1-2, and the above-mentioned second width W2 may be the spacing distance between the (2-1) side S2-1 and the (2-2) side S2-2.

[0226] Based on the second direction DR2, the (1-2) side S1-2 and the (2-2) side S2-2 may be parallel to each other. For example, the (1-2) side S1-2 and the (2-2) side S2-2 may define one side extending in the second direction DR2. Since the spacing distance between the (1-2) side S1-2 and the (1-1) side S1-1 and the spacing distance between the (2-2) side S2-2 and the (2-1) side S2-1 are different from each other, the first sub-region BSA1 and the second sub-region BSA2 may have different widths, and the (1-2) side S1-2 and the (2-2) side S2-2 may extend on the same straight line.

[0227] In an embodiment of the present disclosure, the second bank region BA2 may include a third sub-region BSA3 and a fourth sub-region BSA4. The third sub-region BSA3 and the fourth sub-region BSA4 may have an integral shape and may be connected to each other. The second light control pattern CCP-G may be disposed in the second bank opening BOH2 that defines each of the third sub-region BSA3 and the fourth sub-region BSA4. For example, the second light control pattern CCP-G may be disposed to overlap with the third sub-region BSA3 and the fourth sub-region BSA4.

[0228] The third sub-region BSA3 may have a third width W3 in a first direction DR1, and the fourth sub-region BSA4 may have a fourth width W4 greater than the third width W3 in the first direction DR1. For example, the fourth sub-region BSA4 may have a greater width than the third sub-region BSA3 in the first direction DR1. The length of the fourth sub-region BSA4 in a second direction DR2 may be less than the length of the third sub-region BSA3 in the second direction DR2. In other words, the fourth sub-region BSA4 may have a shorter length than the third sub-region BSA3 in the second direction DR2. The third width W3 may be in the range of about 25 micrometers to about 30 micrometers, and the fourth width W4 may be in the range of about 35 micrometers to about 50 micrometers. The third width W3 may be substantially equal to the first width W1 described above. The fourth width W4 may be substantially equal to the second width W2 described above.

[0229] The second filter region FA2 may overlap with a part of the third sub-region BSA3 and the fourth sub-region BSA4. The second filter region FA2 may have a second filter width W-F2 in the first direction DR1, and the second filter width W-F2 may be less than the third width W3. The third sub-region BSA3 may have a second length L2 in the second direction DR2, the second filter region FA2 may have a second filter length L-F2 in the second direction DR2, and the second filter length L-F2 may be greater than the second length L2. For example, the second filter region FA2 may be disposed to overlap with the third sub-region BSA3 except for a part of the outer region of the third sub-region BSA3, and the length of the second filter region FA2 in the second direction DR2 may be greater than the length of the third sub-region BSA3 in the second direction DR2. Accordingly, a part of the second filter region FA2 may be disposed to extend into the fourth sub-region BSA4.

[0230] The fourth sub-region BSA4 may include a part that does not overlap with the second filter region FA2. A connection region CNA, which will be described below, may overlap with the part of the fourth sub-region BSA4 that does not overlap with the second filter region FA2.

[0231] The third sub-region BSA3 may include a (3-1) side S3-1 and a (3-2) side S3-2 spaced apart from each other in the first direction DR1. The fourth sub-region BSA4 may include a (4-1) side S4-1 and a (4-2) side S4-2 spaced apart from each other in the first direction DR1. The above-mentioned third width W3 may be the spacing distance between the (3-1) side S3-1 and the (3-2) side S3-2, and the above-mentioned fourth width W4 may be the spacing distance between the (4-1) side S4-1 and the (4-2) side S4-2.

[0232] Based on the second direction DR2, the (3-2) side S3-2 and the (3-1) side S3-1 may be parallel to each other. For example, the (3-2) side S3-2 and the (3-1) side S3-1 may define a side extending in the second direction DR2. Since the spacing distance between the (3-2) side S3-2 and the (3-1) side S3-1 and the spacing distance between the (4-2) side S4-2 and the (4-1) side S4-1 are different from each other, the third sub-region BSA3 and the fourth sub-region BSA4 may have different widths, and the (3-2) side S3-2 and the (4-2) side S4-2 may extend on the same straight line.

[0233] In an embodiment of the present disclosure, the third embankment region BA3 may have a fifth width W5 in the first direction DR1 and a third length L3 in the second direction DR2. The third filter region FA3 may overlap with the third embankment region BA3. The third embankment region BA3 may have a rectangular shape on the plane.

[0234] The fifth width W5 may be substantially equal to the first width W1 of the first sub-region BSA1. The fifth width W5 may be substantially equal to the third width W3 of the third sub-region BSA3. For example, the width in the first direction DR1 of each of the first sub-region BSA1, the third sub-region BSA3, and the third embankment region BA3 may be constant. In this specification, "substantially equal" includes not only the case where lengths, widths, areas, etc. are physically the same as each other, but also the case where there are differences equal to the process errors that occur even though the designs are the same.

[0235] The third length L3 may be shorter than the first length L1 and the second length L2. The first length L1 and the second length L2 may be substantially equal to each other.

[0236] The third filter area FA3 may have a third filter width W-F3 in the first direction DR1, and the third filter width W-F3 may be smaller than the fifth width W5. The third bank area BA3 may have a third length L3 in the second direction DR2, and the third filter area FA3 may have a length shorter than the third length L3 in the second direction DR2.

[0237] In an embodiment of the present disclosure, the first bank area BA1, the second bank area BA2, and the third bank area BA3 may be sequentially arranged in the first direction DR1. The spacing distances in the first direction DR1 between the first sub-area BSA1, the third sub-area BSA3, and the third bank area BA3 may be constant. In an embodiment of the present disclosure, the first spacing distance d1 between the first sub-area BSA1 and the third sub-area BSA3 adjacent to each other, the second spacing distance d2 between the third sub-area BSA3 and the third bank area BA3 adjacent to each other, and the third spacing distance d3 between the third bank area BA3 and the first sub-area BSA1 adjacent to each other may be substantially equal to each other. Each of the first spacing distance d1, the second spacing distance d2, and the third spacing distance d3 may be in the range of about 8 micrometers to about 13 micrometers.

[0238] In a display panel according to an embodiment of the present disclosure, a first bank area defined by a first bank opening in which a first light control pattern is disposed may include a first sub-area having a first width and a second sub-area having a second width greater than the first width. A second bank area defined by a second bank opening in which a second light control pattern is disposed may include a third sub-area having a third width and a fourth sub-area having a fourth width greater than the third width. Since a display panel according to an embodiment of the present disclosure has a structure of a first filter area and a second filter area respectively overlapping with a first sub-area and a second sub-area having a relatively narrow width, the size of the pixel area can be reduced, thereby achieving high resolution. Since the inkjet process landing area (or area for the inkjet process) for respectively forming the first light control pattern and the second light control pattern can be ensured by the second sub-area and the fourth sub-area having a wide width, the process efficiency for forming the first light control pattern and the second light control pattern can be improved.

[0239] refer to Figure 2 , Figure 6B and Figure 7 , in the display panel according to the embodiment of the present disclosure, the display area DA may further include a connection area CNA.

[0240] The connection region CNA may overlap with a part of each of the first bank region BA1 and the second bank region BA2. The connection region CNA may overlap with a part of each of the second sub-region BSA2 and the fourth sub-region BSA4.

[0241] As Figure 6B shown, the light-emitting openings OH may be defined in the pixel-defining film PDL, and the light-emitting openings OH may include a first light-emitting opening OH1, a second light-emitting opening OH2, and a third light-emitting opening OH3. In this embodiment, the above-mentioned light-emitting region EA may be defined by the light-emitting openings OH. The first light-emitting region EA1 may be defined by the first light-emitting opening OH1, the second light-emitting region EA2 may be defined by the second light-emitting opening OH2, and the third light-emitting region EA3 may be defined by the third light-emitting opening OH3. The first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may respectively correspond to the first filter region FA1, the second filter region FA2, and the third filter region FA3 described above in Figure 6A The connection region CNA may not overlap with each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3. The connection region CNA may not overlap with each of the above-mentioned first filter region FA1, the second filter region FA2, and the third filter region FA3.

[0242] Referring to Figure 2 , Figure 6B and Figure 7 , the connection region CNA may be a region where the auxiliary electrode SE and the second electrode EL2 are connected to each other. The auxiliary electrode SE may be disposed on the circuit element layer DP-CL. The auxiliary electrode SE and the above-mentioned first electrode EL1 (see Figure 3 ) may include the same material and may be formed on the circuit element layer DP-CL by the same process. The connection region CNA may be a part where the second electrode EL2 is connected to the auxiliary electrode SE by removing organic layers such as the hole control layer HTR, the light-emitting layer EML, and the electron control layer ETR included in the light-emitting element through a laser drilling process. The auxiliary electrode SE may be a conductive pattern to which a power voltage is applied.

[0243] The connection region CNA may overlap with the bank BMP and may also overlap with a part of the first bank opening BOH1 and a part of the second bank opening BOH2. As described above, since the connection region CNA does not overlap with each of the first filter region FA1, the second filter region FA2, and the third filter region FA3 described above, the color filters CF1, CF2, and CF3 (see Figure 4A)It may not overlap with the connection region CNA. In the display panel according to an embodiment of the present disclosure, since the connection region CNA overlaps with each of the first bank opening BOH1 and the second bank opening BOH2 and does not overlap with the first filter region FA1, the second filter region FA2, and the third filter region FA3, a wide inkjet process landing region can be ensured while ensuring the aperture ratio of the pixel region, thereby improving the process efficiency of manufacturing the display panel.

[0244] Figures 8A to 8D Each of them is a schematic enlarged plan view of a part of the display panel according to an embodiment of the present disclosure. Figures 8A to 8D Each of them shows the relationship between the filter regions FA (FA1, FA2, and FA3) and the bank regions BA (BA1, BA2, and BA3) in another display region DA-1, DA-2, DA-3, or DA-4 according to another embodiment of the present disclosure, which is different from the display region DA shown in Figure 2 the present disclosure.

[0245] Reference Figure 8A , the display region DA-1 according to an embodiment of the present disclosure may have such a shape that the filter regions FA1, FA2, FA3 and the bank regions BA1, BA2, BA3 are vertically reversed compared to the display region DA of Figure 2 . For example, in the display region DA of Figure 2 , the first sub-region BSA1 of the first bank region BA1 may be disposed in the lower region in the second direction DR2, and its second sub-region BSA2 may be disposed in the upper region in the second direction DR2. However, in the display region DA-1 according to an embodiment of the present disclosure, the first sub-region BSA1 may be disposed in the upper region in the second direction DR2, and the second sub-region BSA2 may be disposed in the lower region in the second direction DR2. In the display region DA-1 according to an embodiment of the present disclosure, the third sub-region BSA3 may be disposed in the upper region in the second direction DR2, and the fourth sub-region BSA4 may be disposed in the lower region in the second direction DR2. Corresponding to the shapes of the vertically reversed bank regions BA1, BA2, and BA3, the filter regions FA1, FA2, and FA3 and the connection region CNA may also be vertically reversed compared to the embodiment of Figure 2 .

[0246] Reference Figure 8B, in the display area DA-2 according to an embodiment of the present disclosure, each of the first bank region BA1 and the second bank region BA2 may include a chamfered portion. In the first bank region BA1, the second sub-region BSA2 may include a first chamfered portion CP1. In the second bank region BA2, the fourth sub-region BSA4 may include a second chamfered portion CP2. The first chamfered portion CP1 may have a shape that is recessed from the (2-1) side S2-1 toward the inside of the second sub-region BSA2. The second chamfered portion CP2 may have a shape that is recessed from the (4-1) side S4-1 toward the inside of the fourth sub-region BSA4.

[0247] Reference Figure 8C , in the display area DA-3 according to an embodiment of the present disclosure, compared with Figure 2 the display area DA, the length of the second bank region BA2 in the second direction DR2 may be shorter than the length of the first bank region BA1 in the second direction DR2. In an embodiment of the present disclosure, the second length L2' of the third sub-region BSA3 in the second direction DR2 may be shorter than the first length L1' of the first sub-region BSA1 in the second direction DR2.

[0248] In the display area DA-3 according to an embodiment of the present disclosure, the first bank region BA1, the second bank region BA2, and the third bank region BA3 may respectively have lengths corresponding to the lengths of the corresponding filter regions FA1, FA2, and FA3 in the second direction DR2. For example, the first bank region BA1 may have a length corresponding to the length of the first filter region FA1, the second bank region BA2 may have a length corresponding to the length of the second filter region FA2, and the third bank region BA3 may have a length corresponding to the length of the third filter region FA3.

[0249] In the display area DA-3, the length of the first filter region FA1 in the second direction DR2 may be greater than the length of the second filter region FA2 in the second direction DR2. The length of the second filter region FA2 in the second direction DR2 may be greater than the length of the third filter region FA3 in the second direction DR2. Therefore, the length of the first bank region BA1 in the second direction DR2 may be greater than the length of the second bank region BA2 in the second direction DR2, and the length of the second bank region BA2 in the second direction DR2 may be greater than the length of the third bank region BA3 in the second direction DR2.

[0250] Reference Figure 8D, in the display area DA-4 according to an embodiment of the present disclosure, the first filter area FA1 and the second filter area FA2 among the filter areas FA1, FA2, and FA3 may have a shape in which a part of their widths is widened to correspond to the first bank area BA1 and the second bank area BA2, respectively. In an embodiment of the present disclosure, the first filter area FA1 may include a first sub-filter area SFA1 overlapping with the first sub-area BSA1 and a second sub-filter area SFA2 overlapping with the second sub-area BSA2. The width of the second sub-filter area SFA2 in the first direction DR1 may be greater than the width of the first sub-filter area SFA1 in the first direction DR1. The second filter area FA2 may include a third sub-filter area SFA3 overlapping with the third sub-area BSA3 and a fourth sub-filter area SFA4 overlapping with the fourth sub-area BSA4. The width of the fourth sub-filter area SFA4 in the first direction DR1 may be greater than the width of the third sub-filter area SFA3 in the first direction DR1.

[0251] Although the second sub-filter area SFA2 and the fourth sub-filter area SFA4 of the first filter area FA1 and the second filter area FA2 have been widened, the connection area CNA may be arranged not to overlap with each of the filter areas FA1, FA2, and FA3.

[0252] Figure 9 is a schematic enlarged plan view of a part of a display panel according to an embodiment of the present disclosure. Figure 9 Shows the arrangement relationship between the filter areas FA1, FA2, and FA3 and the bank areas BA1, BA2, and BA3 in a part of each of the display area DA and the non-display area NDA.

[0253] Reference Figure 9 , each of the bank areas BA1, BA2, and BA3 may be provided not only in the display area DA but also in at least a part of the non-display area NDA. The first bank area BA1 may include a (1-1) bank area BA1-1 provided in the display area DA and a (1-2) bank area BA1-2 provided in the non-display area NDA. The above-mentioned first light control pattern CCP-R (see Figure 4A ) may be provided in each of the (1-1) bank area BA1-1 and the (1-2) bank area BA1-2. The second bank area BA2 may include a (2-1) bank area BA2-1 provided in the display area DA and a (2-2) bank area BA2-2 provided in the non-display area NDA. The above-mentioned second light control pattern CCP-G (see Figure 4A) can be provided in each of the (2-1)st bank region BA2-1 and the (2-2)nd bank region BA2-2. The third bank region BA3 can include the (3-1)st bank region BA3-1 provided in the display region DA and the (3-2)nd bank region BA3-2 provided in the non-display region NDA. The above-mentioned third light control pattern CCP-B (see Figure 4A ) can be provided in each of the (3-1)st bank region BA3-1 and the (3-2)nd bank region BA3-2.

[0254] Different from the bank regions BA1, BA2, and BA3, the filter regions FA1, FA2, and FA3 can be provided in the display region DA and may not be provided in the non-display region NDA. The first filter region FA1 can overlap with the (1-1)st bank region BA1-1 and may not overlap with the (1-2)nd bank region BA1-2. The second filter region FA2 can overlap with the (2-1)st bank region BA2-1 and may not overlap with the (2-2)nd bank region BA2-2. The third filter region FA3 can overlap with the (3-1)st bank region BA3-1 and may not overlap with the (3-2)nd bank region BA3-2.

[0255] Hereinafter, a method of manufacturing a display panel according to an embodiment of the present disclosure will be described.

[0256] A method of manufacturing a display panel according to an embodiment of the present disclosure may include preparing a display element layer including a light-emitting element that outputs source light and forming an optical structure layer on the light-emitting element. Forming the optical structure layer may include forming a bank in which a first bank opening to a third bank opening are formed on the light-emitting element, patterning a photoresist material in the third bank opening to form a third light control pattern, and forming a first light control pattern and a second light control pattern in the first bank opening and the second bank opening respectively by an inkjet process. The content of the first bank opening, the second bank opening, the third bank opening, and the bank regions defined by them described above can be equally applied to the same content to be described hereinafter. Figures 1A to 9 The content of the first bank opening, the second bank opening, the third bank opening, and the bank regions defined by them described above can be equally applied to the same content to be described hereinafter.

[0257] Figures 10A to 10D is a schematic cross-sectional view showing some steps of a method of manufacturing a display panel according to an embodiment of the present disclosure. Figures 10A to 10D Some steps of forming an optical structure layer in a method of manufacturing a display panel according to an embodiment of the present disclosure are briefly shown.

[0258] Refer to Figure 10A, A method of manufacturing a display panel according to an embodiment of the present disclosure may include forming a bank BMP in which a first bank opening BOH1, a second bank opening BOH2, and a third bank opening BOH3 are formed. The bank BMP may be formed on a base member BLL. The base member BLL may provide a base surface on which the bank BMP and light control patterns CCP-R, CCP-G, and CCP-B (see Figure 10D ) are formed. For example, in the case of manufacturing the display panel DP shown in Figure 4A , the base member BLL may be a second barrier layer CAP2, and in the case of manufacturing the display panel DP-1 shown in Figure 4B , the base member BLL may be a first barrier layer CAP1.

[0259] Referring to Figure 10B and Figure 10C , a method of manufacturing a display panel according to an embodiment of the present disclosure may include applying a photoresist material PRL at least inside the third bank opening BOH3 and patterning the photoresist material PRL to form a third light control pattern CCP-B. As shown in Figure 10B , the photoresist material PRL may be provided not only inside the third bank opening BOH3 but also inside the first bank opening BOH1 and the second bank opening BOH2, and may also be provided on the bank BMP. For example, the photoresist material PRL may be disposed on the entire base member BLL, and after an exposure process for providing light L, uncured portions may be removed to form a third light control pattern CCP-B. In patterning the photoresist material PRL, a separate photomask may be provided to perform an exposure process only on a part of the photoresist material PRL. As an example, Figure 10B shows a negative photoresist cured by irradiating light L onto the photoresist material PRL corresponding to the third bank opening BOH3, but embodiments of the present disclosure are not limited thereto, and the photoresist material PRL may be a positive photoresist, and light may be irradiated onto portions of the photoresist material PRL other than the third bank opening BOH3.

[0260] Referring to Figure 10C and Figure 10D, a method of manufacturing a display panel according to an embodiment of the present disclosure may include forming a first light control pattern CCP-R and a second light control pattern CCP-G in a first bank opening BOH1 and a second bank opening BOH2, respectively, by an inkjet process. The first light control pattern CCP-R may be formed by providing a first ink INK1 within the first bank opening BOH1 through a first nozzle NZ1. The second light control pattern CCP-G may be formed by providing a second ink INK2 within the second bank opening BOH2 through a second nozzle NZ2. The first ink INK1 and the second ink INK2 for forming the first light control pattern CCP-R and the second light control pattern CCP-G, respectively, may include quantum dots.

[0261] The inkjet landing point where the first ink INK1 lands (or is provided) through the first nozzle NZ1 may be the second sub-region BSA2 or the like described above. Figure 6A The inkjet landing point where the second ink INK2 lands through the second nozzle NZ2 may be the fourth sub-region BSA4 or the like described above. In the method of manufacturing a display panel according to an embodiment of the present disclosure, since the inkjet process of the first ink INK1 and the second ink INK2 is performed through each of the second sub-region BSA2 and the fourth sub-region BSA4 having a wide width, the process efficiency of forming the first light control pattern CCP-R and the second light control pattern CCP-G may be improved. Figure 6A

[0262] According to an embodiment of the present disclosure, since the bank opening region provided in the light control layer includes sub-regions respectively corresponding to pixel regions having a small width, high resolution may be achieved, and since other sub-regions of the bank opening region are formed to have a large width for the inkjet process, an inkjet process landing region may be ensured, thereby improving the process efficiency of manufacturing a display panel.

[0263] The above description is an example of the technical features of the present disclosure, and those skilled in the art to which the present disclosure pertains will be able to make various modifications and changes. Therefore, the above-described embodiments of the present disclosure may be implemented individually or in combination with each other.

[0264] Therefore, the embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, but to describe the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. The protection scope of the present disclosure should be interpreted by the appended claims, and it should be interpreted that all technical spirits within the equivalent scope are included within the scope of the present disclosure.​

Claims

1. Display panel, comprising: A display element layer, including light-emitting elements that output source light; And An optical structure layer, disposed on the light-emitting elements and transmitting the source light or converting the source light into light of different wavelengths, wherein, The optical structure layer includes: A light control layer, disposed above the light-emitting elements, and including a bank having a first bank opening and a first light control pattern disposed in the first bank opening; and A color filter layer, disposed above the light control layer and including a first color filter disposed in a first color filter region, The first bank region defined by the first bank opening includes: A first sub-region, having a first width in a first direction and a first length in a second direction intersecting the first direction; and A second sub-region, having a second width in the first direction, The second width is greater than the first width, The first color filter region overlaps with the first sub-region and a part of the second sub-region, The width of the first color filter region in the first direction is less than or equal to the first width, and The length of the first color filter region in the second direction is greater than or equal to the first length.

2. The display panel according to claim 1, wherein, The bank further includes a second bank opening spaced apart from the first bank opening and a third bank opening spaced apart from each of the first bank opening and the second bank opening, and The light control layer further includes a second light control pattern disposed in the second bank opening and a third light control pattern disposed in the third bank opening.

3. The display panel according to claim 2, wherein, The second bank region defined by the second bank opening includes: A third sub-region, having a third width in the first direction and a second length in the second direction; and A fourth sub-region, having a fourth width in the first direction, The fourth width is greater than the third width.

4. The display panel according to claim 3, wherein, The third bank region is defined by the third bank opening, and The widths of the first sub-region, the third sub-region, and the third bank region in the first direction are equal to each other.

5. The display panel according to claim 4, wherein, The first bank region, the second bank region, and the third bank region are arranged in sequence in the first direction, The first sub-region and the third sub-region are spaced apart from each other by a first interval distance in the first direction, The third sub-region and the third bank region are spaced apart from each other by a second interval distance in the first direction, and The first interval distance and the second interval distance are equal to each other.

6. The display panel according to claim 3, wherein, The color filter layer further includes: A second color filter, disposed in a second color filter region spaced apart from the first color filter region; and A third color filter, disposed in a third color filter region spaced apart from the first color filter region and the second color filter region.

7. The display panel according to claim 6, wherein, The second color filter region overlaps with the third sub-region and a part of the fourth sub-region, The width of the second filter region in the first direction is less than or equal to the third width, and the length of the second filter region in the second direction is greater than or equal to the second length.

8. The display panel according to claim 6, wherein, the widths of the first filter region, the second filter region, and the third filter region in the first direction are equal to each other, the length of the first filter region in the second direction is greater than the length of the second filter region in the second direction, and the length of the second filter region in the second direction is greater than the length of the third filter region in the second direction.

9. The display panel according to claim 3, wherein, The second length is shorter than the first length.

10. The display panel according to claim 2, wherein, the third bank region is defined by the third bank opening, and the third bank region has a rectangular shape in a plane.

11. The display panel according to claim 10, wherein, the second bank region is defined by the second bank opening, and the length of the third bank region in the second direction is shorter than the length of each of the first bank region and the second bank region in the second direction.

12. The display panel according to claim 2, wherein, the first light control pattern includes first quantum dots that convert the source light into light of a first wavelength, and the second light control pattern includes second quantum dots that convert the source light into light of a second wavelength.

13. The display panel according to claim 2, wherein, The third light control pattern includes a photosensitive resin.

14. The display panel according to claim 1, further comprising: a circuit element layer including a pixel circuit electrically connected to the light-emitting element, wherein, the light-emitting element includes: a first electrode disposed on the circuit element layer; an intermediate layer disposed on the first electrode and including a light-emitting layer; and a second electrode disposed on the intermediate layer, the display element layer further includes an auxiliary electrode disposed on the circuit element layer and electrically connected to the second electrode, and at least a part of the connection region where the auxiliary electrode is disposed overlaps with the second sub-region in a plane.

15. The display panel according to claim 1, wherein, the first sub-region includes a (1-1) side and a (1-2) side that extend in the second direction and are spaced apart from each other in the first direction, the second sub-region includes a (2-1) side and a (2-2) side that extend in the second direction and are spaced apart from each other in the first direction, and the (1-2) side and the (2-2) side are aligned with each other on the same straight line in the second direction.

16. The display panel according to claim 15, wherein, The second sub-region includes a first chamfered portion that is recessed from the (2-1) side of the second sub-region toward the inside of the second sub-region.

17. The display panel according to claim 1, wherein, the first filter region includes: a first sub-filter region that overlaps with the first sub-region; and a second sub-filter region that overlaps with the second sub-region, and The width of the second sub-filter region in the first direction is greater than the width of the first sub-filter region in the first direction.

18. The display panel according to claim 1, wherein, The display element layer is divided into a display region in which the light-emitting elements are provided and a non-display region surrounding at least a part of the display region; And The first bank region includes: The (1-1) bank region, provided in the display region; And The (1-2) bank region, provided in the non-display region.

19. A display panel, comprising: A light-emitting element that outputs source light; And An optical structure layer provided on the light-emitting element and transmitting the source light or converting the source light into light of a different wavelength, wherein, The optical structure layer includes: A light control layer including a bank provided on the light-emitting element and having a first bank opening, a second bank opening, and a third bank opening, a first light control pattern provided in the first bank opening, a second light control pattern provided in the second bank opening, and a third light control pattern provided in the third bank opening; and A color filter layer provided on the light control layer and including a first color filter overlapping with the first light control pattern, a second color filter overlapping with the second light control pattern, and a third color filter overlapping with the third light control pattern, The first bank region defined by the first bank opening includes a first sub-region and a second sub-region, the first sub-region having a first width in a first direction, and the second sub-region having a second width in the first direction; and The second bank region defined by the second bank opening includes a third sub-region and a fourth sub-region, the third sub-region having a third width in the first direction, and the fourth sub-region having a fourth width in the first direction, The second width is greater than the first width; The fourth width is greater than the third width; A third bank region is defined by the third bank opening; and The widths of the first sub-region, the third sub-region, and the third bank region in the first direction are equal to each other.

20. A method of manufacturing a display panel, the method comprising: Preparing a display element layer including a light-emitting element that outputs source light; And Forming an optical structure layer on the light-emitting element, wherein, Forming the optical structure layer includes: Forming a bank having a first bank opening, a second bank opening, and a third bank opening above the light-emitting element; Patterning a photoresist material in the third bank opening to form a third light control pattern; and Forming a first light control pattern and a second light control pattern in the first bank opening and the second bank opening respectively by an inkjet process; The first bank region defined by the first bank opening includes a first sub-region and a second sub-region, the first sub-region having a first width in a first direction, and the second sub-region having a second width in the first direction, The second bank region defined by the second bank opening includes a third sub-region and a fourth sub-region, the third sub-region having a third width in the first direction, and the fourth sub-region having a fourth width in the first direction, The second width is greater than the first width, and the fourth width is greater than the third width.

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