Multi-core memory controller

Abstract

The present disclosure provides systems, methods, and apparatuses of a memory system for operating at least a portion of a memory core at a frequency lower than a memory clock to reduce power consumption and cost. In a first aspect, a memory controller includes a first core to schedule a first memory operation for a first portion of a clock cycle of a memory clock, and includes a second core to schedule a second memory operation for a second portion of the clock cycle of the memory clock. Other aspects and features are also claimed and described.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims the benefit of U.S. Patent Application No. 18 / 059,937, entitled “MULTIPLE-CORE MEMORY CONTROLLER,” filed November 29, 2022, the entire content of which is expressly incorporated by reference herein. TECHNICAL FIELD

[0003] Generally, aspects of the present disclosure relate to computer information systems, and more specifically, to memory systems for storing data. Some features can implement and provide improved memory capabilities for interfacing host devices to memory. BACKGROUND

[0004] Computing devices (e.g., laptop computers, mobile phones, etc.) can include one or more processors to perform various computing functions, such as telephony, wireless data access, and camera / video functions, among others. Memory is an important component of a computing device. The processor can be coupled to the memory to perform the computing functions described above. For example, the processor can fetch instructions from the memory to perform the computing functions, and / or store temporary data within the memory for processing these computing functions, among others. SUMMARY

[0005] The following summary of some aspects of the present disclosure is intended to provide an overview of the discussed technology and is not intended to be exhaustive or to narrow the scope of the present disclosure. The summary is not intended to be a generic description of the entire disclosure, nor is it intended to narrow the scope of the disclosure to only the aspects explicitly described in the summary. Rather, the sole purpose of the summary is to present some concepts of one or more aspects of the present disclosure in a general way as a prelude to the more detailed description presented later.

[0006] An apparatus according to at least one embodiment includes a memory controller configured to communicate with a host device to a memory. The memory includes a memory array configured to store data. The memory is configured to provide data stored in the memory array to the host upon request of the memory controller in performing a computing function. The memory controller can include a plurality of cores configured to schedule memory operations to the memory. In some aspects, the memory controller can be interfaced with the memory at a first speed (e.g., a memory clock frequency). The cores of the memory controller can operate at a second speed (e.g., a memory controller clock frequency) that is slower than the memory speed (e.g., the memory clock frequency). Bandwidth or speed of transferring data to and / or from the memory is proportional to the memory clock. Configuration of the memory controller according to aspects described herein provides for operating a plurality of cores at a slower speed than the memory with a slight or no reduction in utilization of bandwidth available from the memory based on the memory clock. An apparatus according to at least one embodiment includes a host device having a memory controller configured with a plurality of cores to communicate with a memory according to aspects described herein.

[0007] In one aspect of the disclosure, a method for scheduling memory operations based on memory requests received from components of a host device includes scheduling, by a first core of a plurality of cores of a memory controller, a first memory operation for a first portion of a clock cycle of a memory clock; scheduling, by a second, different core of the plurality of cores of the memory controller, a second memory operation for a second portion of the clock cycle of the memory clock; and transmitting, by a memory physical (PHY) interface of the memory controller, during the clock cycle of the memory clock, a first signal corresponding to the first memory operation and a second signal corresponding to the second memory operation.

[0008] In further aspects of the disclosure, an apparatus includes at least one processor and a memory coupled to the at least one processor. The at least one processor is configured to perform operations including scheduling, by a first core of a plurality of cores of a memory controller, a first memory operation for a first portion of a clock cycle of a memory clock; scheduling, by a second, different core of the plurality of cores of the memory controller, a second memory operation for a second portion of the clock cycle of the memory clock; and transmitting, by a memory physical (PHY) interface of the memory controller, during the clock cycle of the memory clock, a first signal corresponding to the first memory operation and a second signal corresponding to the second memory operation. The processor can be a processor, controller, or other logic circuitry in a host. The processor can alternatively be a controller embedded in a memory device.

[0009] In further aspects of the disclosure, an apparatus can include a memory controller operating at a memory controller clock frequency based on a first clock, wherein the memory controller includes a memory physical (PHY) interface operating at a memory clock frequency based on a memory clock, and a plurality of cores each operating at the memory controller clock frequency that is less than the memory clock frequency, coupled to a memory through a channel by the memory physical (PHY) interface, configured to access data stored in the memory through the channel and the memory physical (PHY) interface, and configured to perform operations including scheduling, by a first core of the plurality of cores of the memory controller, a first memory operation for a first portion of a clock cycle of the memory clock, scheduling, by a second, different core of the plurality of cores of the memory controller, a second memory operation for a second portion of the clock cycle of the memory clock, and transmitting, by a memory physical (PHY) interface of the memory controller, during the clock cycle of the memory clock, a first signal corresponding to the first memory operation and a second signal corresponding to the second memory operation.

[0010] In further aspects of the disclosure, an apparatus can include a memory controller operating at a memory controller clock frequency based on a first clock, wherein the memory controller includes a memory physical (PHY) interface operating at a memory clock frequency based on a memory clock, and a plurality of cores each operating at the memory controller clock frequency that is less than the memory clock frequency, coupled to a memory through a channel by the memory physical (PHY) interface, configured to access data stored in the memory through the channel and the memory physical (PHY) interface, and configured to perform operations including scheduling, by a first core of the plurality of cores of the memory controller, a first memory operation for a first portion of a clock cycle of the memory clock, scheduling, by a second, different core of the plurality of cores of the memory controller, a second memory operation for a second portion of the clock cycle of the memory clock, and transmitting, by a memory physical (PHY) interface of the memory controller, during the clock cycle of the memory clock, a first signal corresponding to the first memory operation and a second signal corresponding to the second memory operation.

[0011] In another aspect of the disclosure, an apparatus can include a memory controller as part of a host device configured to communicate with a memory through a channel in accordance with aspects of the disclosure herein. The host device can include components configured to share content of the memory and access the memory through the channel and the memory controller. For example, the host device can include components such as a processor, a graphics processor, a neural processor including one or more neural network processing cores, and / or a digital signal processor (DSP). In some embodiments, the host device is integrated in a single semiconductor package with the memory controller and / or the memory.

[0012] In further aspects of the disclosure, an apparatus, such as a wireless device, includes at least one processor and memory coupled to the at least one processor. The at least one processor is configured to communicate with the memory through a memory controller coupled to a channel that couples the processor to the memory. The processor can be a processor in a host, a controller, or other logic circuit.

[0013] In further aspects of the disclosure, a non-transitory computer-readable medium storing instructions that, when executed by a processor, cause the processor to perform operations described herein with respect to aspects of the disclosure.

[0014] The memory in the present disclosure can be embedded within a processor on a semiconductor die or be part of a different semiconductor die. The memory can be of various types. For example, the memory can be static random access memory (SRAM), dynamic random access memory (DRAM), magnetic random access memory (MRAM), NAND flash, or NOR flash, etc.

[0015] Methods and apparatuses are presented in the present disclosure through the non-limiting example of low power double data rate (LPDDR) synchronous dynamic random access memory (SDRAM). For example, LPDDR memory operates according to LPDDR specifications published by the Joint Electron Device Engineering Council (JEDEC). One such LPDDR specification can be LPDDR5. Another such LPDDR specification can be LPDDR6.

[0016] Other aspects, features, and implementations will become apparent to those of ordinary skill in the art, upon reviewing the following description in conjunction with the accompanying drawings. While features can be discussed relative to certain example aspects and figures below, one or more aspects can include one or more of the advantageous features discussed herein. In other words, while one or more aspects can be discussed with respect to certain advantageous features, one or more of such features can also be used in accordance with a corresponding aspect. In similar fashion, while example aspects can be discussed below as device, system or method aspects it should be understood that each aspect can be implemented in a device, system and method context. Reference to thus can be understood to reference each of the aspects individually as well as in any combination.

[0017] The method can be embedded in a computer readable medium as computer program code comprising instructions which cause a processor to perform the steps of the method. In some embodiments, the processor can be part of a mobile device that includes a first network adapter configured to send data (such as images or video in a recording or as streaming data) over a first network connection of a plurality of network connections. The processor can be coupled to the first network adapter and to a memory for storing data to support processing and communication operations performed by the processor. The network adapter can support communication over a wireless communication network such as a 5G NR communication network. The processor can cause transmission of data stored in the memory over the wireless communication network.

[0018] The foregoing has outlined rather broadly the features and technical advantages of examples according to the disclosure in order that the detailed description that follows can be better understood. Additional features and advantages will be described hereinafter. The disclosed concepts and specific examples can be readily utilized as bases or starting points for modifying or designing other structures for carrying out the same purposes of the disclosure. Such equivalent constructions are not to be

[0019] While aspects and implementations are described in this application by illustration to some examples, those skilled in the art will understand that additional implementations and use cases can be implemented in many different arrangements and scenarios. The innovations described herein can be implemented across many differing platform types, devices, systems, shapes, sizes, and packaging arrangements. For example, aspects and / or uses can occur in a chip-level implementation or in other non-module-component based devices (e.g., end-user devices, vehicles, communication devices, computing devices, industrial equipment, retail / purchasing devices, medical devices, artificial intelligence (Al)-enabled devices, etc.). While some examples can be specifically directed to use cases or applications, or can not be specifically directed to a use case or application, various adaptable applicability of described innovations can occur. Implementations can range from complete chip-level implementations to non-module, non-chip-level implementations, and further to aggregate, distributed, or original equipment manufacturer (OEM) devices or systems incorporating one or more aspects of the described innovations. In some practical settings, devices incorporating described aspects and features can also necessarily include additional components and features that can not be explicitly described or shown in order to implement and practice aspects claimed and described. For example, transmission and reception of wireless signals necessarily includes a number of components for analog and digital purposes (e.g., hardware components including antennas, radio frequency (RF) chains, power amplifiers, modulators, buffers, processors, interleavers, adders / summers, etc.). Innovations described herein are intended to be applicable in various devices, chip-level components, systems, distributed arrangements, or end-user apparatuses having different sizes, shapes, and constitution. BRIEF DESCRIPTION OF DRAWINGS

[0020] Further understanding of the nature and advantages of the disclosure can be realized by reference to the following drawings. In the drawings, like components or features can have the same reference label. Furthermore, various components of the same type can be distinguished by following the reference labels by dashes and a second label that distinguishes among the groups of components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.

[0021] Figure 1 A block diagram illustrating an example computing system including a host, a memory, and a channel coupling the host with the memory, in accordance with one or more aspects of the present disclosure is shown.

[0022] Figure 2 A block diagram illustrating an example computing system including a host, a memory, and a channel coupling the host with the memory, in accordance with one or more aspects of the present disclosure is shown.

[0023] Figure 3A is an example timing diagram for sending commands from different cores on different clock edges according to some aspects of the disclosure.

[0024] Figure 3B is an example timing diagram for sending commands with timestamps from different cores on different clock edges according to some aspects of the disclosure.

[0025] Figure 4 is a block diagram illustrating a memory controller with asymmetric cores according to one aspect of the disclosure.

[0026] Figure 5 is a flowchart of an example method of operation for a memory controller with multiple cores according to some aspects of the disclosure.

[0027] Figure 6A and Figure 6B illustrates a waveform for transferring data through an example channel in a write operation according to certain aspects of the disclosure.

[0028] Figure 7A and Figure 7B illustrates a waveform for transferring data through an example channel in a read operation according to certain aspects of the disclosure.

[0029] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION

[0030] The detailed description set forth below, in connection with the appended drawings and embodiments described herinin, is intended as a description of various configurations and is not intended to limit the scope of the disclosure. Rather, the detailed description includes specific details for the purpose of providing a thorough understanding of the inventive subject matter. It will be apparent to those skilled in the art, from this disclosure and with no further effort, that the inventive subject matter can be practiced without such specific details. In some instances, well-known structures and components are shown in block diagram form, rather than in detail, for the purpose of clarity.

[0031] The present disclosure provides systems, apparatuses, methods, and computer readable media that support data processing, including techniques for interfacing a memory controller to a memory in an electronic device, such as a wireless communication device. The memory controller can be interfaced to the memory at a first speed (e.g., a memory clock frequency). Cores of the memory controller can operate at a second speed (e.g., a clock rate) that is lower than the memory speed (e.g., the memory clock). Bandwidth or speed of transferring data to and / or from the memory is proportional to the memory clock. Configurations for the memory controller according to aspects described herein provide for operating multiple cores at a slower speed than the memory, with little or no reduction in utilization of bandwidth available to the memory based on the memory clock.

[0032] Particular implementations of the subject matter described in this disclosure can be implemented to realize one or more of the following potential advantages or benefits. In some aspects, the disclosure provides reduced cost by allowing portions of the memory controller to operate at a slower speed, which can reduce the complexity of circuit design and manufacturing. In some aspects, the disclosure provides reduced power consumption, as power consumption can scale with clock frequency, and the lower frequency at each of the cores reduces power consumption in the memory controller to a large extent.

[0033] Figure 1 A device 100 is shown that includes a host 110, a memory 150, and a channel 190 coupling the host 110 and the memory 150. The device 100 can be, for example, a device in a computing system (e.g., a server, a data center, a desktop computer), a mobile computing device (e.g., a laptop computer, a cellular phone, a vehicle, etc.), an Internet of Things device, a virtual reality (VR) system, an augmented reality (AR) system, an automotive system (e.g., a driver assistance system, an autonomous driving system), an image capture device (e.g., a standalone digital camera or digital video recorder, a wireless communication device handset equipped with a camera, such as a mobile telephone, cellular or satellite wireless telephone, personal digital assistant (PDA), panel or tablet computer, gaming device, computing device such as a webcam, video surveillance camera, or other device with digital imaging or video capability), and / or a multimedia system (e.g., a television, a compact disc player, a streaming media device).

[0034] The host 110 can include at least one processor, such as a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a multimedia engine, and / or a neural processing unit (NPU). The host 110 can be configured to, while performing a computing function (such as one of data processing, data communication, graphics display, camera, AR or VR rendering, image processing, neural processing, etc.), be coupled to and communicate with the memory 150 (e.g., memories 150-1 to 150-4) via the channel 190 (e.g., channels 190-1 to 190-4). For example, the memories 150-1 to 150-4 can store instructions or data for the host to perform the computing function.

[0035] The host 110 can include a memory controller 130, which can include controller PHY modules 134-1 through 134-4. Each of the controller PHY modules 134-1 through 134-4 can be coupled to a respective one of the memories 150-1 through 150-4 via a respective one of the channels 190-1 through 190-4. For ease of reference, reads and writes are referenced from the perspective of the host 110. For example, in a read operation, the host 110 can receive stored data from one or more of the memories 150-1 through 150-4 via one or more of the channels 190-1 through 190-4. In a write operation, the host 110 can provide data to be written into one or more of the memories 150-1 through 150-4 for storage via one or more of the channels 190-1 through 190-4. The memory controller 130 can be configured to control various aspects of communications to and from the memories 150-1 through 150-4, such as a logical layer. The controller PHY modules 134-1 through 134-4 can be configured to control electrical characteristics (e.g., voltage levels, phase, latency, frequency, etc.) of signals provided or received on the channels 190-1 through 190-4, respectively.

[0036] In some examples, the memories 150-1 through 150-4 can be LPDDR DRAMs (e.g., LPDDR5, LPDDR6). In some examples, the memories 150-1 through 150-4 can be different kinds of memories (such as one LPDDR5, one LPDDR6, one flash memory, and one SRAM), respectively. The host 110, the memories 150-1 through 150-4, and / or the channels 190-1 through 190-4 can operate according to LPDDR (e.g., LPDDR5, LPDDR6) specifications. In some examples, each of the channels 190-1 through 190-4 can include 16 bits of data (e.g., 16 DQs). In some examples, each of the channels 190-1 through 190-4 can operate on 32 bits of data (e.g., 32 DQs). In some examples, each of the channels 190-1 through 190-4 can operate on 64 bits of data (e.g., 64 DQs). Figure 1 In some examples, the host 110 can include more or fewer channels, such as 8 or 16 channels.

[0037] Figure 2 A configuration of the host 110, the memories 150, and the channels 190 according to some aspects of the disclosure is shown in more detail. Figure 2 A host 110 is illustrated having Figure 1of the apparatus 100. The channel 190 between the host 110 and the memory 150 can include multiple connections, some of which carry data (e.g., user data or application data) and some of which carry non-data (e.g., addresses and other signaling information). For example, the non-data connections in the channel 190 can include a data clock (e.g., WCK) for providing data to the respective memory 150 on a byte-by-byte basis, and a read data strobe (e.g., RDQS) for receiving data from the respective memory 150 on a byte-by-byte basis. The channel 190 can further include data mask (e.g., DM, sometimes referred to as data mask inversion DMI, to indicate multiple functions performed by the signal connections) signaling for masking certain portions of data in write operations. The channel 190 can further include command and address (e.g., CA[0:n]) and associated CA clock to provide commands (e.g., read or write commands) to the memory 150.

[0038] The host 110 can include at least one processor 120, which can include a CPU 122, a GPU 123, and / or a NPU 124. The host 110 can further include a memory controller 130 having a controller PHY module 134 and a logic circuit 132. The memory controller 130 can be coupled to the at least one processor 120 via a bus system 115 in performing various computing functions. The term “bus system” can provide that elements coupled to the “bus system” can exchange information directly or indirectly with one another. In different embodiments, the “bus system” can include multiple physical connections and intermediate stages such as buffers, latches, registers, etc. Modules can be implemented in hardware, software, or a combination of hardware and software. The logic circuit 132 can coordinate execution of memory requests received on the bus system 115, such as by scheduling transmission of signals on connections of the channel 190 via the control controller PHY module 134.

[0039] The memory controller 130 can send and / or receive data blocks to other modules such as the at least one processor 120 and / or the memory 150. The memory 150 can include a memory I / O module 160 (e.g., a PHY layer) configured to control electrical characteristics (e.g., voltage levels, phases, latencies, frequencies, etc.) to provide or receive signals on connections of the channel 190. For example, the memory I / O module 160 can be configured to capture (e.g., sample) data, commands, and addresses from the host 110 via the channel 190 and output data to the host 110 via the channel 190. Example techniques for communicating on the channel 190 between the memory I / O module 160 and the memory controller 130 are described in U.S. Patent Application No. 16 / 209, 1 13, filed December 3, 2018, entitled “MEMORY CONTROLLER,” which is incorporated by reference herein in its entirety. Figures 6A-6Band shown in the examples of FIGS. 7A-7B. The memory 150 can further include a memory array 175, which can include a plurality of memory cells that store values (e.g., DRAM memory cells, MRAM memory cells, SRAM memory cells, flash memory cells). The host 110 can read data stored in the memory array 175 and write data into the memory array 175 via the channel 190 and the memory I / O module 160. The memory array 175 can be divided into a plurality of memory banks, where each memory bank is organized as a plurality of pages accessed by a column.

[0040] Application or user data can be processed by the processor 120 and the memory controller 130 that are instructed to store and / or retrieve such data from the memory 150. For example, data can be generated during execution of an application, such as a spreadsheet program that calculates values based on other data. As another example, data can be generated during execution of an application by receiving user input to, for example, a spreadsheet program. As another example, data can be generated during execution of a game application that generates information about a representation of a scene rendered by a three-dimensional (3-D) application.

[0041] The host 110 is coupled to the memory 150 via the channel 190, which is shown for data bytes DQ[0:7]. The channel 190 and signaling between the host 110 and the memory 150 can be implemented according to JEDEC DRAM specifications (e.g., LPDDR5, LPDDR6). As shown, the channel 190 includes signal connections for DQ, read data strobe (RDQS), data mask (DM), data clock (WCK), command and address (CA[0:n]), and command and address clock (CK). The host 110 can use the read data strobe RDQS to strobe (e.g., provide a clock for) data in a read operation to receive data on DQ. The memory 150 can use the data mask DM to mask certain portions of data from being written in a write operation. The memory 150 can use the data clock WCK to sample data on DQ for a write operation. The memory 150 can use the command and address clock CK to provide a clock (e.g., receive) for CA. The signal connections for each signaling can include a pin at the host 110, a pin at the memory 150, and one or more conductive traces that electrically connect the pins. The one or more conductive traces can be part of a single integrated circuit (IC) on a silicon chip that includes the processor 120 and the memory 150, can be part of a package on package (PoP) that includes the processor 120 and the memory 150, or can be part of a printed circuit board (PCB) that is coupled to both the processor 120 and the memory 150.

[0042] Memory 150 can include a memory I / O module 160 (e.g., a PHY layer) configured to control electrical characteristics (e.g., voltage levels, phases, latencies, frequencies, etc.) to provide or receive signals on channel 190. For example, memory I / O module 160 can be configured to capture (e.g., sample) data, commands, and addresses from host 110 via channel 190 and output data to host 110 via channel 190. Information sent across channel 190 can be stored in registers (as temporary or short-term storage locations) in memory I / O module 160 of memory 150 prior to long-term storage in memory array 175.

[0043] Memory 150 can further include a memory array 175, which can include a plurality of memory cells (e.g., DRAM memory cells) that store information. Host 110 can read data stored in memory array 175 and write data into memory array 175 via channel 190.

[0044] Memory controller 130 can operate at a memory controller clock frequency based on a clock signal supplied to memory controller 130 or generated within memory controller 130 from an external clock signal provided to memory controller 130. The memory controller clock frequency is typically the same as the memory clock of memory 150. Operating memory controller 130 and memory 150 at the same clock frequency maintains high efficiency, latency, and bandwidth. As memory device frequencies increase, the design and manufacturing of memory controllers operating at increased clock frequencies can be challenging. Reducing the memory controller clock frequency from the memory clock frequency can reduce the challenge, but the reduced operating rate of the memory controller can reduce the bandwidth utilization of the memory (e.g., the maximum bandwidth that can be provided by the memory), thus reducing the performance of the device.

[0045] According to aspects of the present disclosure, memory controller 130 can include a plurality of cores, each core including logic circuitry to schedule operations at memory 150 to fulfill memory requests. In some embodiments, the cores are symmetric such that each core is capable of generating the same set of commands for output to the memory. In some embodiments, the cores are asymmetric such that each core is capable of generating different (overlapping or non-overlapping) sets of commands for output to the memory. Each processing core 132A-N can operate at a memory clock frequency that is lower than the memory clock frequency. Although each core can not be able to fully utilize memory 150 due to the lower operating frequency of each core, the plurality of cores operating together can improve the utilization of memory 150 and achieve the efficiency and bandwidth that a single core operating at the memory clock frequency is capable of. Using multiple cores can improve the balance between high performance, low power, and low cost.

[0046] The multiple cores 132A-N can be configured to schedule commands that can be sent to the memory 150 together. In Figures 3A-3B Two examples are shown in FIG. 3.

[0047] Figure 3A is an example timing diagram for sending commands from different cores on different clock edges according to some aspects of the disclosure. The memory controller clock signal is shown with edges 302A, 302B, 304A, and 304B. When there are two or more cores in the memory controller, the memory controller clock signal can have a longer period time (e.g., a lower frequency than the clock to the memory device) than the clock to the memory device. In some embodiments, the memory clock controller frequency is a ratio of 1 / N of the memory clock, where N corresponds to the number of cores in the memory controller. As further described with respect to Figure 3A In a dual core embodiment, one memory controller core sends commands on the positive edge at half the memory clock frequency and the other memory controller core sends commands on the negative edge at half the memory clock frequency. The memory clock, which is twice the frequency (or some other ratio) of the memory controller clock, receives a command on each of the memory clock cycles. For example, the memory device receives command 312A on the first clock of the memory and then receives command 312B on the second clock of the memory and then receives command 314A and then receives command 314B. The result is that the memory device receives commands faster than either memory controller core sends commands. In an embodiment with two memory controller cores operating at half the memory clock frequency, the memory device can receive a command for each clock of the memory.

[0048] Edges 302A and 304A are rising clock edges, where the clock transitions from low to high. Edges 302B and 304B are falling clock edges, where the clock transitions from high to low. One clock cycle starts with a rising clock edge at edge 302A and continues to the rising clock edge at edge 304A.

[0049] Commands 312A, 312B, 314A, and 314B can be sent from the memory controller 130 to the memory 150 over the memory PHY interface 134. The first core can schedule commands 312A and 314A, and the second core can schedule commands 312B and 314B. Although the two cores can not be able to produce commands separately for each memory clock cycle, the commands from the cores can be interleaved to increase the utilization of the memory. For example, the first core can signal commands on the rising clock edges of edges 302A and 304A, and the second core can signal commands on the falling clock edges of edges 302B and 304B. In some embodiments, two or more cores can be assigned specific clock edges for scheduling commands, and these assignments can be static or dynamic. For example, in some embodiments, two cores are each assigned to a rising edge and a falling edge, respectively. In other embodiments, each core can be dynamically assigned a specific edge by a high-level scheduler. For example, the cores can be configured to generate different (overlapping or non-overlapping) commands, and the cores are dynamically assigned to certain clock edges by a high-level scheduler based on upcoming operation schedules in the command queues.

[0050] The example signals can include column addresses for commands 312A and 314A and an activate signal for commands 312B and 314B. The cores can schedule commands 312A-B and 314A-B and signal the memory controller PHY interface 134 to generate signals on the channel 190 to communicate the commands to the memory 150. Although the example illustrates two cores scheduling commands for opposite clock edges, other configurations can be used. For example, four cores can schedule commands, each core scheduling for every second rising or falling edge. In this configuration, each of the four cores can operate at a clock frequency that is one fourth of the memory clock frequency. Other multiples of cores and clock edges can be used, such as eight cores dividing the memory clock cycle. Additionally, the configuration can not require each core to operate at only certain clock edges, but can allow cores to operate at different clock edges in the memory clock cycle. Figure 3A The example of FIG. 3 illustrates two cores scheduling commands for opposite clock edges, but other configurations can be used. For example, four cores can schedule commands, each core scheduling for every second rising or falling edge. In this configuration, each of the four cores can operate at a clock frequency that is one fourth of the memory clock frequency. Other multiples of cores and clock edges can be used, such as eight cores dividing the memory clock cycle. Additionally, the configuration can not require each core to operate at only certain clock edges, but can allow cores to operate at different clock edges in the memory clock cycle.

[0051] Figure 3A Commands of FIG. 3 can be queued by the cores at certain clock edges to facilitate the timing and ordering of the commands. In some aspects of the disclosure, the commands can have an associated timestamp to indicate the timing and / or ordering of the commands.

[0052] Figure 3Bis an example timing diagram for sending commands with timestamps from different cores on different clock edges according to some aspects of the present disclosure. Each of the commands 322A, 322B, 324A, and 324B can have an associated timestamp. The timestamp can be an arbitrary counter used to indicate the intended sequence of the commands 322A-B and 324A-B. Alternatively, the timestamp can be an identifying value that matches a memory clock cycle to which the command should be attached. Yet another timestamp example is an offset value used to indicate the relative position of the command with respect to a certain memory clock cycle. When the timestamp is sent with the command, the command can be sent to the memory PHY interface 134 on the same clock edge or a different clock edge. Figure 3B The example of shows command 322A provided at clock edge 302A along with command 322B. The memory PHY interface 134 can use the accompanying timestamp to first send command 322A on channel 190 and then send command 322B at the next clock edge on channel 190.

[0053] In some aspects, the logic circuits or cores of the memory controller can be similarly configured in a symmetric fashion such that each core is capable of scheduling the same commands. In other aspects, the logic circuits or cores of the memory controller can be configured asymmetrically such that each core has different capabilities or responsibilities, but the capabilities or responsibilities can be overlapping between the cores. The asymmetric configuration can have less flexibility, but uses less circuitry, resulting in a smaller die area and a lower cost controller.

[0054] Figure 4 One example implementation of a memory controller to accommodate asymmetric cores is shown in. Figure 4 is a block diagram illustrating a memory controller with asymmetric cores according to one aspect of the present disclosure. The memory controller 130 includes logic circuits 132, which include a command queue 140. The command queue 140 can receive and temporarily store memory requests received on the bus system 115 from system components. A scheduler 170 processes the requests in the command queue 140 and controls the memory PHY interface 134 to control signaling to the memory 150. The scheduler 170 can include two logic circuits (e.g., cores) 152 and 154. The core 152 can include a column scheduler 152A that handles the prioritization and scheduling of column commands present in the command queue 140. The core 154 can include a precharge and activation scheduler.

[0055] The memory PHY interface 134 of the memory controller 130 can include a plurality of buffers 162 and 164. In some embodiments, the number of buffers can correspond to the number of cores in the scheduler 170, although different configurations can be used. The PHY interface 134 can select outputs from the cores 152 and 154 to output to the memory 150 through a switch 166. In some aspects, the decision logic 168 can be used to time stamp match between the outputs of the buffers 162 and 164 to order the commands in the desired order. The cores 152 and 154 can be synchronized through communication between the cores such that consistency is obtained between the two cores 152 and 154. For example, when the first core 152 sends a command, the second core 154 knows of the command sent by the first core 152 and then sends a command accordingly such that the expectations of the memory device are met. In some embodiments, a standard document or other specification document for the memory can specify a required sequence of commands that the cores 152 and 154 must collectively follow to obtain valid output from the memory. In some aspects, the PHY interface 134 can alternate between the buffers 162 and 164 for sending the command signals. In some aspects, the PHY interface 134 can use the time stamps of the commands in the buffers 162 and 164 to order the signals to the memory 150.

[0056] Figure 5 A method of operating a memory from a memory controller according to some aspects described is shown in FIG. 6. Figure 5 is a flowchart of an example method of operation for a memory controller having a plurality of cores according to some aspects of the disclosure.

[0057] The method 500 includes, at block 502, scheduling a first memory operation by scheduling, in a first core of a memory controller, a first portion of a clock cycle of a memory clock for the first memory operation. The first core can execute based on a clock signal having a clock frequency that is lower than a memory clock frequency at which the memory or a memory PHY interface operates. Although the lower clock frequency can result in the first core being unable to determine memory operations for the memory that utilize all available memory bandwidth at the memory clock frequency, a plurality of cores operating at the lower clock frequency can improve utilization of the memory bandwidth. In some embodiments, the plurality of cores can be configured to fully utilize the memory bandwidth. In some aspects, the first core can determine memory operations for a particular portion of a clock cycle of the memory. For example, the first core can always schedule memory operations for a rising edge of the memory clock. As another example, the first core can schedule operations without regard to the portion of the clock cycle in which the memory operation can execute if determined by the memory PHY interface.

[0058] At block 504, the method 500 includes scheduling a second memory operation by scheduling, in a second core of the memory controller, a second portion of a clock cycle for a memory clock. The second core can execute based on a clock signal having a clock frequency that is lower than a memory clock frequency at which the memory or the memory PHY interface operates. The second core can have the same or a different clock frequency than the first core. In some aspects, the second core can schedule memory operations for a particular portion of a clock cycle of the memory. For example, the second core can always schedule memory operations for a falling edge of the memory clock. As another example, the first core can schedule operations without regard to the portion of the clock cycle in which the memory operation can execute given the portion of the clock cycle determined by the memory PHY interface.

[0059] In one example operation, retrieving a memory request from the command queue can cause the first core to determine a column command and the second core to determine an activate command. In another example operation, retrieving a memory request from the command queue can cause the first core to determine a column address and the second core to determine another column address.

[0060] At block 506, the method 500 includes sending a first signal corresponding to the first operation to the memory during the first portion of the clock cycle and sending a second signal corresponding to the second operation during the second portion of the clock cycle. The sending can be performed by the memory PHY interface that receives outputs from the first core and the second core. The sending can include receiving the first memory operation in a first buffer (e.g., a first first-in-first-out (FIFO) buffer) and the second memory operation in a second buffer (e.g., a second first-in-first-out (FIFO) buffer).

[0061] In some aspects, as part of the scheduling of memory operations by the first core at block 502 and the second core at block 504, a timestamp is determined. For example, the first memory operation can have an associated first timestamp and the second memory operation can have an associated second timestamp. The memory PHY interface can use the timestamps to determine which memory operation to transmit next on the channel.

[0062] Although two cores are described in many examples, the memory controller can be configured with additional cores, such as three cores, four cores, five cores, six cores, or more. The additional cores can be provided a clock at a similar or different clock frequency from each other. In some embodiments, N cores are each provided a clock at a frequency of (1 / N)*(memory clock), such that the combined memory operations from each of the N cores can fully utilize the memory bandwidth.

[0063] Example read and write operations that can be performed by the determination of a command by the first core and the second core are illustrated in Figures 6A-6B a read operation and Figures 7A-7B a write operation.

[0064] Figure 6A and Figure 6B illustrate waveforms of transmitting data through example channels in a write operation according to certain aspects of the present disclosure. The command and address clock (CK) can be a differential signal with CK_t and CK_c signal connections. The data clock WCK can be a differential signal with WCK0_t and WCK0_c signal connections. The read data strobe RDQS can be a differential signal with RDQS_t and RDQS_c signal connections. The data mask is labeled DM0 to indicate that DM0 corresponds to the lower byte of DQ (DQ[0:7]). At TO (rising edge of CK_c and falling edge of CK_t), a CAS command can be provided by the host 110 for a write operation to the memory 150. At Tl, the host 110 can provide a write command to the memory 150.

[0065] After a period of write latency (WL), the host 110 can toggle the data clock WCK0_t and WCK0_c to provide clocking to the memory 150 for receiving data for a write on the DQ signal connections. At Tc0-Tc2, the memory 150 can serially receive 16 bytes of data on each of the DQ[0:7] signal connections, clocked by the data clock WCK0_t and WCK0_c. The memory 150 can serially receive a 16-bit data mask DM0 (e.g., based on the data clock WCK0_t and WCK0_c) to mask certain portions of the received data to avoid the write operation. In some examples, the 16 bytes of data and the 16-bit data mask DM0 can be received by the memory 150, with each bit of the data mask DM0 masking a corresponding byte of the received data. At Tc0-Tc2, the RDQS_t signal connection can be a Hi-Z state. In a read operation, the RDQS_t signal connection can be configured to provide a read data strobe (RDQS) from the memory 150 to the host 110.

[0066] Figure 7A and Figure 7BA waveform for transferring data through an example channel in a read operation is illustrated in accordance with certain aspects of the present disclosure. A command and address clock (CK) can be a differential signal with CK_t and CK_c signal connections. A data clock WCK can be a differential signal with WCK0_t and WCK0_c signal connections. A read data strobe RDQS can be a differential signal with RDQS_t and RDQS_c signal connections. A data mask is labeled DM0 to indicate that DM0 corresponds to the lower byte of DQ (DQ[0:7]). At TO (a rising edge of CK_c and a falling edge of CK_t), a CAS command can be provided by the host 110 for a read operation to the memory 150. At Tl, a read command can be provided by the host 110 to the memory 150.

[0067] After a period of read latency (RL), the memory 150 can toggle the read data strobe RDQS to provide a clock to the host 110 to receive data for the read operation on the DQ signal connections. At Tc0-Tc2, the host 110 can serially receive 16 bytes of data on each of the DQ[0:7] signal connections, clocked by the read data strobe RDQS_t and RDQS_c. Thus, in this example, the host 110 receives 16 bytes of data.

[0068] At Tc0-Tc2, the data mask DM0 signal connections can be in a Hi-Z state. In a write operation, the DM signal connections can be configured to provide a data mask from the host 110 to the memory 150, clocked by WCK0_t and WCK0_c.

[0069] A wireless communication device can include a memory configured to transfer data to the memory as illustrated in at least Figure 1 and 2 may be provided in or integrated into any processor-based device in accordance with any of the aspects disclosed herein. Examples include, without limitation, a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics, a drone, and a multicopter.

[0070] In one or more aspects, techniques for memory storage and retrieval can include additional aspects, such as any single aspect or any combination of aspects described in connection with one or more other processes or devices described elsewhere herein. In a first aspect, supporting data operations can include an apparatus configured for: scheduling, by a first core of a plurality of cores, a first memory operation for a first portion of a clock cycle of a memory clock; scheduling, by a second core of the plurality of cores, a second memory operation for a second portion of the clock cycle of the memory clock; and transmitting, over a memory physical (PHY) interface, during the clock cycle of the memory clock, a first signal corresponding to the first memory operation and a second signal corresponding to the second memory operation.

[0071] Additionally, the apparatus can perform or operate according to one or more aspects as described below. In some implementations, the apparatus includes a wireless device, such as a UE. In some implementations, the apparatus includes a remote server, such as a cloud-based computing solution, that receives image data for processing to determine an output image frame. In some implementations, the apparatus can include at least one processor, and a memory coupled to the processor. The processor can be configured to perform the operations described herein with respect to the apparatus. In some other implementations, the apparatus can include a non-transitory computer-readable medium having program code recorded thereon, and the program code can be executable by a computer to cause the computer to perform the operations described herein with reference to the apparatus. In some implementations, the apparatus can include one or more means configured to perform the operations described herein. In some implementations, a method of wireless communication can include one or more operations described herein with reference to the apparatus.

[0072] In a second aspect, in combination with the first aspect, the apparatus is further configured to schedule the first memory operation as a column address; and schedule the second memory operation as an activate command.

[0073] In a third aspect, in combination with one or more of the first aspect or the second aspect, the first portion of the clock cycle of the memory clock includes a portion that starts at a rising clock edge of the memory clock; and the second portion of the clock cycle of the memory clock includes a portion that starts at a falling clock edge of the memory clock.

[0074] In a fourth aspect, in combination with one or more of the first through third aspects, scheduling the first memory operation includes determining a first timestamp corresponding to the first memory operation, determining the second memory operation includes scheduling a second timestamp corresponding to the second memory operation, and transmitting the first signal and the second signal is based on the first timestamp and the second timestamp.

[0075] In a fifth aspect, in combination with one or more of the first through fourth aspects, the first timestamp corresponds to a rising clock edge of a memory clock and the second timestamp corresponds to a falling clock edge of the memory clock.

[0076] In a sixth aspect, in combination with one or more of the first through fifth aspects, the memory physical (PHY) interface includes a first buffer configured to store first memory operations from the first core and a second buffer configured to store second memory operations from the second core.

[0077] In a seventh aspect, in combination with one or more of the first through sixth aspects, the first core includes a first logic circuit configured to schedule at least a first type of memory operation, wherein the first logic circuit is coupled to the first buffer; and the second core includes a second logic circuit configured to schedule at least a second type of memory operation, wherein at least one of the second type is different from the first type, wherein the second logic circuit is coupled to the second buffer.

[0078] In an eighth aspect, in combination with one or more of the first through seventh aspects, the first logic circuit is configured to schedule at least a column address operation; and the second logic circuit is configured to schedule at least a precharge operation or an activate operation.

[0079] In a ninth aspect, in combination with one or more of the first through eighth aspects, the memory controller is configured to output back-to-back column addresses on a rising clock edge and a falling clock edge of a memory clock.

[0080] In a tenth aspect, in combination with one or more of the first through ninth aspects, the memory physical (PHY) interface is configured to operate at a memory clock frequency.

[0081] In an eleventh aspect, in combination with one or more of the first through tenth aspects, an apparatus can include a host device including a memory controller in accordance with one or more of the aspects, wherein the apparatus includes a memory and the host device is configured to communicate with the memory over a channel.

[0082] In a twelfth aspect, in combination with the eleventh aspect, the host device can include a processor coupled to the memory controller.

[0083] In a thirteenth aspect, in combination with one or more of the eleventh through twelfth aspects, the host device further includes a graphics processor coupled to the memory controller; and a neural processor coupled to the memory controller, wherein the memory controller includes a command queue configured to receive memory requests from the processor, the graphics processor, and the neural processor.

[0084] In a fourteenth aspect, in combination with one or more of the first aspect through the thirteenth aspect, the graphics processor, neural processor, processor, and memory are integrated in a single semiconductor package.

[0085] In the description of the embodiments of the present disclosure, a large number of specific details are set forth (such as examples of specific components, circuits, and processes) in order to provide a thorough understanding of the present disclosure. As used herein, the term "coupled" means connected, either directly or through one or more intermediate components or circuits. Also, in the description of embodiments herein, and for purposes of explanation and non limitation, specific nomenclature is set forth to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the teachings of this disclosure can be practiced without these specific details. In other instances, well-known circuits and devices are shown in block diagram form in order to avoid obscuring the present disclosure.

[0086] Some portions of the following detailed description are presented in terms of procedures, logic blocks, processing and other symbolic representations of operations on data bits within a computer memory. In the present disclosure, procedures, logic blocks, processing and the like are conceived to be self consistent sequences of steps or instructions leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared and otherwise manipulated in a computer system.

[0087] In the drawings, a single block can be described as performing one or more functions. The one or more functions performed by the block can be performed in a single component or across multiple components, and / or can be performed using hardware, software, or a combination of hardware and software. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans can implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure. Also, the example devices can include components other than those shown, including well-known components such as processors, memory, etc.

[0088] Unless otherwise stated, it will be apparent from the following discussion that throughout this application, the use of terms such as “access,” “receive,” “send,” “use,” “select,” “determine,” “normalize,” “multiply,” “average,” “monitor,” “compare,” “apply,” “update,” “measure,” “derive,” “set,” “generate,” “schedule,” etc., refers to the actions and processing of a computer system or similar electronic computing device that manipulates and converts data represented as physical (electronic) quantities in the registers and memories of the computer system into other data that are similarly represented as physical quantities in the registers, memories, or other such information storage, transmission, or display devices of the computer system.

[0089] The terms "device" and "apparatus" are not limited to one or a specific number of physical objects (such as a smartphone, a camera controller, a processing system, etc.). As used herein, a device can be any electronic device having one or more parts that can implement at least some of the contents of this disclosure. Although the term "device" is used in the description and examples herein to describe various aspects of this disclosure, the term "device" is not limited to a particular configuration, type, or number of objects. As used herein, an apparatus can include a device or part of a device for performing the described operations.

[0090] Certain components in a device or apparatus described as “unit for access,” “unit for receiving,” “unit for transmitting,” “unit for using,” “unit for selecting,” “unit for determining,” “unit for normalizing,” “unit for multiplying,” or other similarly named terms referring to one or more operations on data (such as image data), may refer to processing circuitry (e.g., application-specific integrated circuit (ASIC), digital signal processor (DSP), graphics processing unit (GPU), central processing unit (CPU)) configured to perform the functions by means of hardware, software, or a combination of hardware configured by software.

[0091] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0092] This article is about Figures 1-2The described components, blocks and modules can include processors, electronic devices, hardware devices, electronic components, logical circuits, memories, software codes, firmware codes, and others or any combination thereof. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, and / or functions, among other examples, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. In addition, the features discussed herein can be implemented via special-purpose processor circuitry, via executable instructions, or a combination thereof.

[0093] Those skilled in the art will appreciate that, for Figure 1 , Figure 2 or Figure 4 one or more blocks (or operations) described in one figure can be combined with those of another figure. For example, Figures 3A-3B one or more blocks (or operations) of Figure 1 or Figure 2 may be combined with one or more blocks (or operations) of Figure 5 , 6A -6B or 7A-7B. As another example, one or more blocks associated with Figure 1 , 2 or 4 can be combined with one or more blocks (or operations) associated with

[0094] Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein can be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans can implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure. Skilled artisans will also readily recognize that the order or combination of components, methods, or interactions that are described herein are merely examples and that the components, methods, or interactions of the various aspects of the present disclosure can be combined or performed in ways other than those illustrated and described herein.

[0095] The various illustrative logics, logical blocks, modules, circuits and algorithm processes described in connection with the implementations disclosed herein can be implemented as electronic hardware, computer software, or combinations of both. The interchangeability of hardware and software has been described generally, in terms of

[0096] The hardware and data processing apparatus used to implement the various illustrative logics, logical blocks, modules and circuits described in connection with the aspects disclosed herein can be implemented or performed with a general purpose single- or multi-chip processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor can be a microprocessor, or any conventional processor, controller, microcontroller, or state machine. In some implementations, a processor can be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. In some implementations, particular processes and methods can be performed by an electric circuitry specifically created for the given function.

[0097] In one or more aspects, the functions described can be implemented in hardware, digital electronic circuitry, computer software, firmware, including the structures disclosed in this specification and their structural equivalents, or any combination thereof. Implementations of the subject matter described in this specification also can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, encoded on a computer storage medium for execution by, or to control the operation of, data processing apparatus.

[0098] If implemented in software, the functions can be stored or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media include both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage medium can be any available medium that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. Additionally, the operations of methods according to the implementations of the disclosure can be embodied in a computer-readable medium and a computer-readable medium can include one or any combination of the above components or a combination of the above components with other components.

[0099] Various modifications to the implementations described in this disclosure can be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to some other implementations without departing from the spirit or scope of this disclosure. Thus, the claims are not intended to be limited to the implementations shown herein, but are to be accorded the widest scope consistent with this disclosure, the principles and the novel features disclosed herein.

[0100] Additionally, those of ordinary skill in the art will readily understand that the terms "upper" and "lower" or "front" and "back" or "top" and "bottom" or "forward" and "rearward" are sometimes used for ease of description of the figures, and indicate relative positions corresponding to the orientation of the figures on the properly oriented page, and can not reflect the proper orientation of any device that is implemented.

[0101] As used herein, the term "coupled to" in the various tense of the verb "couple" can mean that element A is directly connected to element B, or that other elements can be connected between element A and element B (i.e., element A is indirectly connected to element B) to operate some intended function. In the case of electrical components, the term "coupled to" can also be used herein to mean that element A and element B are electrically connected (as well as any combination electrically connected to each other) using wires, traces, or other conductive materials. In some examples, the term "coupled to" means that electrical energy is transferred between element A and element B to operate some intended function.

[0102] In some examples, the term "electrically connected" means having a current or being configurable to have a current flowing between element A and element B. For example, in addition to wires, traces, or other conductive materials and components, element A and element B can be connected via a resistor, a transistor, or an inductor. Also, for radio frequency functions, element A and element B can be "electrically connected" via a capacitor.

[0103] The terms "first," "second," "third," etc. are employed in this specification for ease of reference only and can not carry substantive meanings. Likewise, the names of components / modules can be employed for ease of reference and can not limit the components / modules.

[0104] Certain features described in this specification in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation can also be implemented separately or in any appropriate sub-combination. Moreover, although features can be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination and the claimed combination can be directed to a sub-combination or variation of a sub-combination.

[0105] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring such an order, nor that all illustrated operations be performed, to accomplish desirable results. Further, the drawings can schematically depict one more example processes in the form of a flowchart. However, other operations that are not depicted can be incorporated in the example processes that are schematically depicted. For example, one or more additional operations can be performed before, after, simultaneously with, or between any of the illustrated operations. In certain circumstances, multitasking and parallel processing can be advantageous. Moreover, the separation of various system components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated in a single software product or packaged into multiple software products. Additionally, some other implementations are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results.

[0106] As used herein, including in the claims “or” as used in a list of items prefaced by “at least one of’ indicates a disjunctive list such that, for example, a list stating “at least one of A, B, or C” means: A or B or C or AB or AC or BC or ABC (i.e., A and B and C).

[0107] As understood by one of ordinary skill in the art, the term “substantially” is defined as largely but not necessarily wholly the object specified (and includes the specified object; for example, substantially 90 degrees includes 90 degrees, and substantially parallel includes parallel). In any disclosed implementation, the term “substantially” can be replaced with “[percentage] of” the specified content, where the percentage includes 0.1%, 1%, 5%, or 10%.

[0108] The foregoing description of the present disclosure has been presented for the purposes of concurrency and illustration so that others skilled in the art can construct and use the disclosure. Modifications to embodiments of the present disclosure will be obvious to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the spirit or scope of the disclosure. Therefore, the present disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus for scheduling memory operations, comprising: A memory controller that operates at the memory controller clock frequency based on a first clock, wherein the memory controller: It includes a memory physical (PHY) interface based on a memory clock, operating at the memory clock frequency, and multiple cores, each of which operates at a memory controller clock frequency lower than the memory clock frequency. The memory is coupled to the memory via a channel through the memory physical (PHY) interface. Configured to access data stored in the memory via the channel and the memory physical (PHY) interface, and Configured to perform operations including the following: A first memory operation is scheduled by a first core among the plurality of cores for a first portion of the clock cycle of the memory clock, wherein the first core includes a first logic circuit configured to schedule at least a first type of memory operation, wherein the first logic circuit is coupled to a first buffer. A second memory operation is scheduled by a second core among the plurality of cores for a second portion of the clock cycle of the memory clock, wherein the second core includes a second logic circuit configured to schedule at least a second type of memory operation, wherein at least one of the at least second types is different from the first type, and wherein the second logic circuit is coupled to a second buffer; and During the clock cycle of the memory clock, a first signal corresponding to the first memory operation and a second signal corresponding to the second memory operation are sent through the memory physical (PHY) interface, wherein the memory physical (PHY) interface includes: a first buffer configured to store the first memory operation from the first core, and a second buffer configured to store the second memory operation from the second core.

2. The apparatus according to claim 1, wherein: Scheduling the first memory operation includes scheduling column addresses; and Scheduling the second memory operation includes scheduling activation commands.

3. The apparatus according to claim 2, wherein: The first portion of the clock cycle of the memory clock includes a portion that begins at the rising clock edge of the memory clock; as well as The second portion of the clock cycle of the memory clock includes a portion that begins at the falling clock edge of the memory clock.

4. The apparatus according to claim 3, wherein: Scheduling the first memory operation includes determining a first timestamp corresponding to the first memory operation. Scheduling the second memory operation includes determining a second timestamp corresponding to the second memory operation, and The transmission of the first signal and the second signal is based on the first timestamp and the second timestamp.

5. The apparatus according to claim 4, wherein, The first timestamp corresponds to the rising clock edge of the memory clock, and the second timestamp corresponds to the falling clock edge of the memory clock.

6. The apparatus according to claim 1, wherein: The first logic circuit is configured to at least schedule column address operations; and The second logic circuit is configured to schedule at least a precharge operation or an activation operation.

7. The apparatus according to claim 6, wherein, The memory controller is configured to output back-to-back column addresses on the rising and falling edges of the memory clock.

8. The apparatus according to claim 1, wherein, The memory physical (PHY) interface is configured to operate at the memory clock frequency.

9. The apparatus according to claim 1, wherein, The memory controller is configured to communicate with a memory that includes a low-power double data rate (LPDDR6) memory module.

10. A method for scheduling memory operations, comprising: A first memory operation is scheduled in a first core of a memory controller for a first portion of a clock cycle of a memory clock via a first core of a plurality of cores, wherein scheduling the first memory operation for the first portion includes: scheduling a first type of memory operation in the first core; The first memory operation from the first core is stored in the first buffer of the memory physical (PHY) interface of the memory controller via the memory physical (PHY) interface; The second core of the memory controller schedules a second memory operation for a second portion of the clock cycle of the memory clock through a second core of the plurality of cores, wherein scheduling the second memory operation for the second portion includes: scheduling a second type of memory operation that is different from the first type of memory operation in the second core; The second memory operation from the second core is stored in the second buffer of the memory controller's memory physical (PHY) interface via the memory physical (PHY) interface; and During the first portion of the clock cycle, a first signal corresponding to the first memory operation is sent to the memory via the memory physical (PHY) interface, and during the second portion of the clock cycle, a second signal corresponding to the second memory operation is sent to the memory, wherein the memory clock has a memory clock frequency higher than the memory controller frequency of the memory controller, and wherein sending the first signal and the second signal includes receiving the first memory operation from the first buffer and receiving the second memory operation from the second buffer.

11. The method of claim 10, wherein: Scheduling the first memory operation includes scheduling column addresses; and Scheduling the second memory operation includes scheduling activation commands.

12. The method according to claim 11, wherein: The first portion of the clock cycle of the memory clock includes a portion that begins at the rising clock edge of the memory clock; as well as The second portion of the clock cycle of the memory clock includes a portion that begins at the falling clock edge of the memory clock.

13. The method according to claim 12, wherein: Scheduling the first memory operation includes determining a first timestamp corresponding to the first memory operation. Scheduling the second memory operation includes determining a second timestamp corresponding to the second memory operation, and The transmission of the first signal and the second signal is based on the first timestamp and the second timestamp.

14. The method according to claim 13, wherein, The first timestamp corresponds to the rising clock edge of the memory clock, and the second timestamp corresponds to the falling clock edge of the memory clock.

15. The method of claim 10, wherein: The scheduling of the first memory operation for the first part includes scheduling column address operations, and The scheduling of the second memory operation for the second part includes scheduling at least one of a precharge operation or an activation operation.

16. The method of claim 10, wherein: Scheduling the first memory operation for the first part includes scheduling the first column address operation. Scheduling the second memory operation for the second part includes scheduling the second column address operation, and Sending the first signal and the second signal includes sending the back-to-back column address on the rising clock edge and the falling clock edge of the memory clock.

17. The method according to claim 10, wherein, The memory physical (PHY) interface is configured to operate at the memory clock frequency.

18. The method according to claim 10, wherein, The memory controller is configured to communicate with a memory that includes a low-power double data rate (LPDDR6) memory module.

19. An apparatus for scheduling memory operations, comprising: Memory; The host device is configured to communicate with the memory via a channel. The host device includes a memory controller coupled to the channel, wherein the memory controller: This includes a memory physical (PHY) interface based on a memory clock, operating at the memory clock frequency, and multiple cores, each of which operates at a memory controller clock frequency lower than the memory clock frequency. The memory is coupled to the memory via a channel through the memory physical (PHY) interface. Configured to access data stored in the memory via the channel and the memory physical (PHY) interface, and Configured to perform operations including the following: A first memory operation is scheduled by a first core among the plurality of cores for a first portion of the clock cycle of the memory clock, wherein the first core includes a first logic circuit configured to schedule at least a first type of memory operation, wherein the first logic circuit is coupled to a first buffer. A second memory operation is scheduled by a second core among the plurality of cores for a second portion of the clock cycle of the memory clock, wherein the second core includes a second logic circuit configured to schedule at least a second type of memory operation, wherein at least one of the at least second types is different from the first type, and wherein the second logic circuit is coupled to a second buffer; and During the clock cycle of the memory clock, a first signal corresponding to the first memory operation and a second signal corresponding to the second memory operation are sent through the memory physical (PHY) interface, wherein the memory physical (PHY) interface includes: a first buffer configured to store the first memory operation from the first core, and a second buffer configured to store the second memory operation from the second core.

20. The apparatus according to claim 19, wherein: Scheduling the first memory operation includes scheduling column addresses; and Scheduling the second memory operation includes scheduling activation commands.

21. The apparatus according to claim 20, wherein: The first portion of the clock cycle of the memory clock includes a portion that begins at the rising clock edge of the memory clock; as well as The second portion of the clock cycle of the memory clock includes a portion that begins at the falling clock edge of the memory clock.

22. The apparatus according to claim 21, wherein: Scheduling the first memory operation includes determining a first timestamp corresponding to the first memory operation. Scheduling the second memory operation includes determining a second timestamp corresponding to the second memory operation, and The transmission of the first signal and the second signal is based on the first timestamp and the second timestamp.

23. The apparatus according to claim 19, wherein, The host device includes a processor coupled to the memory controller.

24. The apparatus according to claim 23, wherein, The host device further includes: A graphics processor coupled to the memory controller; and The neural processor, coupled to the memory controller, The memory controller includes a command queue configured to receive memory requests from the processor, the graphics processor, and the neural processor.

25. The apparatus according to claim 24, wherein, The graphics processor, the neural processor, the processor, and the memory are integrated in a single semiconductor package.

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