Voltage identification signal decoder with pre-charging

Abstract

In an example, an apparatus includes a first decoder circuit (112) having a first voltage identification (VID) analog input and a first digital output. The apparatus also includes a pre-charge circuit (115) having a digital input and a first analog output, the digital input coupled to the first digital output. The apparatus also includes a second decoder circuit (114) having a second VID analog input, a pre-charge analog input, and a second digital output, the pre-charge analog input coupled to the first digital output. The apparatus also includes a multiplexer (216) having a multiplexer output, and a first multiplexer input and a second multiplexer input, the first multiplexer input coupled to the first digital output, and the second multiplexer input coupled to the second digital output.

Description

Background Art

[0001] A power supply circuit can be implemented to provide a direct current (DC) voltage to a device such as a computer. The power supply circuit can be disposed in a voltage regulator circuit that provides an output voltage (VOUT) to other components in a computer system, such as a central processing unit (CPU). Some CPUs implement dynamic voltage transitions such that the CPU can determine the amount of output voltage. At higher performance levels that consume more computing resources, the CPU can request a higher output voltage. Conversely, at lower performance levels and thus lower computing resource consumption, the CPU can request a smaller output voltage, thereby saving power. The CPU can transmit such power requests to a power controller associated with the voltage regulator. Summary of the Invention

[0002] In one example, a device includes a first decoder circuit having a first voltage identification (VID) analog input and a first digital output. The device further includes a precharge circuit having a digital input and a first analog output, the digital input coupled to the first digital output. The device further includes a second decoder circuit having a second VID analog input, a precharge analog input, and a second digital output, the precharge analog input coupled to the first digital output. The device further includes a multiplexer having a multiplexer output and a first multiplexer input and a second multiplexer input, the first multiplexer input coupled to the first digital output, and the second multiplexer input coupled to the second digital output.

[0003] In one example, a device includes a first decoder circuit, a precharge circuit, a second decoder circuit, and a multiplexer. The first decoder circuit has a first VID analog input and a first digital output, and is configured to provide a first digital code at the first digital output based on a VID signal from the first VID analog input. The precharge circuit has a digital input and a first analog output, the digital input being coupled to the first digital output, and the precharge circuit is configured to receive the first digital code at the digital input and provide a precharge signal at the first analog output based on the first digital code. The second decoder circuit has a second VID analog input, a precharge analog input, and a second digital output, the precharge analog input being coupled to the first digital output, and the second decoder circuit is configured to provide a second digital code at the second digital output based on the precharge signal and the VID signal received via the second VID analog input, wherein the resolution of the first decoder circuit is less than the resolution of the second decoder circuit. The multiplexer has a multiplexer output, a first multiplexer input, a second multiplexer input, and a select input, the first multiplexer input being coupled to the first digital output and the second multiplexer input being coupled to the second digital output, and the multiplexer is configured to provide the first digital code at the multiplexer output in response to a first state of a select signal at the select input and provide the second digital code at the multiplexer output in response to a second state of the select signal.

[0004] In one example, a voltage regulator includes a power stage and a power controller. The power stage is configured to provide a corresponding output voltage. The power controller is configured to receive an analog VID signal representing a target voltage and selectively activate one or more of the power stage to reduce a difference between the target voltage and a sum of the corresponding output voltage. The power controller includes a VID signal decoder circuit for decoding the VID signal. The VID signal decoder circuit includes a first decoder circuit, a precharge circuit, a second decoder circuit, and a multiplexer. The first decoder circuit has a first VID analog input and a first digital output. The first decoder circuit is configured to provide a first digital code at the first digital output based on the VID signal from the first VID analog input. The precharge circuit has a digital input and a first analog output. The digital input is coupled to the first digital output. The precharge circuit is configured to receive the first digital code at the digital input and provide a precharge signal at the first analog output based on the first digital code. The second decoder circuit has a second VID analog input, a precharge analog input, and a second digital output. The precharge analog input is coupled to the first digital output. The second decoder circuit is configured to provide a second digital code at the second digital output based on the precharge signal and the VID signal received via the second VID analog input, wherein a resolution of the first decoder circuit is less than a resolution of the second decoder circuit. The multiplexer has a multiplexer output, a first multiplexer input, a second multiplexer input, and a select input. The first multiplexer input is coupled to the first digital output, and the second multiplexer input is coupled to the second digital output. The multiplexer is configured to provide the first digital code at the multiplexer output in response to a first state of a select signal at the select input and provide the second digital code at the multiplexer output in response to a second state of the select signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a block diagram of a computer system in various examples.

[0006] Figure 2 is a block diagram of a voltage identification signal decoder in various examples.

[0007] Figure 3 is a schematic diagram of an analog filter in various examples.

[0008] Figure 4 is a timing diagram in various examples.

[0009] Figure 5A flowchart of a method for providing an output voltage in various examples. DETAILED DESCRIPTION

[0010] As described above, a CPU or other device may provide a request to a power supply circuit to supply an output voltage having a specific value or within a specific value range. The value or value range may be for any suitable one or more parameters, such as voltage, current, etc. A voltage identification (VID) signal decoder may decode a signal (e.g., a VID signal) containing the request to determine the specific value or range. The VID signal decoder may be implemented in a power controller of a voltage regulator circuit that is capable of providing an adaptive or changeable output voltage to a system. For example, the system may include a CPU capable of implementing a dynamic voltage transition as described above, such that the CPU may provide a VID signal to request the amplitude of the output voltage, which is supplied as the power supply voltage of the CPU from the voltage regulator circuit to the CPU. In one example, the VID signal is provided as a pulse width modulation (PWM) signal having a duty cycle corresponding to the amplitude of the requested power supply voltage. In some examples, the amplitude is encoded according to any suitable coding scheme. For example, the VID signal may have an eight-digit code encoded therein to indicate the amplitude of the power supply voltage requested by the CPU.

[0011] In some examples, the VID signal decoder is configured to receive and decode a VID signal to determine the amplitude of the output voltage supplied as the power supply voltage from the voltage regulator circuit to the CPU. Some implementations of the VID signal decoder include a coarse resolution decoder circuit and a fine resolution decoder circuit. The coarse resolution decoder circuit provides a first digital code that is a coarse duty cycle code corresponding to the decoded VID signal. The fine resolution decoder circuit provides a second digital code that is a fine duty cycle code corresponding to the decoded VID signal. In one example, the output voltage provided according to the first digital code has an error tolerance with respect to the value of the power supply voltage requested by the CPU that is greater than the value of the output voltage provided according to the second digital code. However, a greater amount of time may be spent in determining the second digital code compared to determining the first digital code, thus increasing the delay when supplying the output voltage to the CPU.

[0012] For example, a coarse resolution decoder circuit may provide a faster decoding of the VID signal, thereby providing a first digital code with lower accuracy than a fine resolution decoder circuit. Conversely, a fine resolution decoder circuit may provide a slower decoding of the VID signal, thereby providing a second digital code with higher accuracy than a coarse resolution decoder circuit. In one example, the coarse resolution decoder circuit includes a counter configured to determine the on-time and off-time of each cycle of the VID signal, and may include a PWM decoder configured to provide the first digital code based on the relative difference between the on-time and off-time of the VID signal. In one example, the fine resolution decoder circuit may include an analog filter and an analog-to-digital converter (ADC), the analog filter being configured to filter the VID signal to provide an analog value associated with the duty cycle of the VID signal, the ADC being configured to provide a digital representation of the analog value associated with the duty cycle of the VID signal as the second digital code.

[0013] As described above, the time taken for the fine resolution decoder circuit to provide the second digital code may be greater than the time taken for the coarse resolution decoder circuit to provide the first digital code. However, the second digital code may produce an output voltage with greater accuracy relative to the value of the supply voltage requested by the CPU. To reduce the time taken for the fine resolution decoder circuit to provide the second digital code (e.g., increase the speed of the fine resolution decoder circuit), the fine resolution decoder circuit may be biased according to the first digital code. For example, the capacitor of the analog filter of the fine resolution decoder circuit may be pre-charged or biased based on the first digital code. Since the operation of the coarse resolution decoder circuit is faster than the operation of the fine resolution decoder circuit, biasing the fine resolution decoder circuit based on the output of the coarse resolution decoder circuit (e.g., the first digital code) increases the speed of the fine resolution decoder circuit when providing the second digital code.

[0014] In one example, the VID signal decoder further includes a multiplexer that receives a first digital code and a second digital code provided by a corresponding coarse-resolution decoder circuit and a fine-resolution decoder circuit. The multiplexer is configured to provide either the first digital code or the second digital code as an output based on a select signal. Thus, the output signal provided by the multiplexer corresponds to the decoded VID signal provided by either the coarse-resolution decoder circuit or the fine-resolution decoder circuit. In one example, the select signal is provided based on a relative amplitude difference between the first digital code and the second digital code such that it is within a predetermined number of least significant bits (LSBs) (e.g., two LSBs). For example, the select signal may initially be provided in a first state such that the multiplexer provides the first digital code as an output to provide a fast decoding of the VID signal via the coarse-resolution decoder circuit. Thus, the output voltage provided by the first digital code may begin to quickly converge on the amplitude requested by the VID signal. In response to the second digital code being close in amplitude to the first digital code (e.g., within two LSBs), the select signal may switch to a second state such that the multiplexer provides the second digital code as an output to provide a more accurate decoding of the VID signal via the fine-resolution decoder circuit. Thus, the VID signal decoder can provide both a fast (e.g., approximately 10 microseconds (μs) or less) but less accurate decoding and an accurate but slower (e.g., approximately 25 - 30 μs or less) decoding of the VID signal.

[0015] Figure 1 is a block diagram of a computer system 100 in various examples. The computer system 100 may be implemented as part of any of a variety of computing devices, such as a computer, a mobile device, a wearable device, a server, or any other computing device. The computer system 100 includes a CPU 102 that is configured to implement any of a variety of processing functions, such as being programmed according to software, firmware, or a combination thereof. As described herein, the CPU 102 is capable of implementing dynamic voltage transitions such that the CPU 102 can request the value of the supply voltage it receives from a power source to perform certain computing functions. For example, at a higher performance where a larger amount of computing resources are consumed, the CPU 102 may request a higher value supply voltage. Conversely, during times when the operation of the CPU 102 does not consume a large amount of computing resources, the CPU 102 may request a small supply voltage, thereby saving power. To request the value of the supply voltage, the CPU 102 provides a VID signal, shown as VID in Figure 1 the example of.

[0016] In Figure 1In an example, computer system 100 includes a voltage regulator 104 configured to provide VOUT, for example, to CPU 102 such that VOUT is the supply voltage for CPU 102. The voltage regulator 104 includes a number N of power stages 106, where N is a positive integer. Each of the power stages 106 provides a respective voltage V1 to VN at respective inductors L1 to LN such that the voltages V1 to VN collectively correspond to (e.g., are summed to form or provide) VOUT based on the selective activation of the power stages 106. The voltage regulator 104 includes a power controller 108 configured to selectively activate the power stages 106 based on a VID signal such that the voltages V1 to VN provided respectively via some or all of the power stages 106 are combined to form VOUT at an amplitude defined by the VID signal. In Figure 1 an example, the selective activation is shown as PWM signals PWM1 to PWMN provided to respective power stages 106 to control the provision and / or amplitude of respective voltages V1 to VN.

[0017] In Figure 1In an example, the power controller 108 includes a VID signal decoder 110 that is configured to decode a VID signal to determine the supply voltage amplitude requested by the CPU 102. In one example, the VID signal decoder 110 includes a coarse resolution decoder circuit 112 and a fine resolution decoder circuit 114. For example, the coarse resolution decoder circuit 112 may operate in the digital domain, and the fine resolution decoder circuit 114 may operate in the analog domain. The coarse resolution decoder circuit 112 provides a first digital code corresponding to the decoded VID signal, for example, based on a faster decoding scheme of the VID signal compared to the fine resolution decoder circuit 114. In contrast, the fine resolution decoder circuit 114 provides a second digital code corresponding to the decoded VID signal, for example, based on a more accurate decoding scheme of the VID signal compared to the coarse resolution decoder circuit 112. In one example, the fine resolution decoder circuit 114 is coupled to the coarse resolution decoder circuit 112 via a digital-to-analog converter (DAC) 115. The DAC 115 can convert the first digital code into an analog representation and provide the analog representation to the fine resolution decoder circuit 114 to bias or pre-charge the fine resolution decoder circuit 114. Based on the biasing, the amount of time used by the fine resolution decoder circuit 114 to determine and provide the second digital code can be reduced. For example, as described above, the VID signal may be encoded with several digital bits (e.g., 8 bits) to represent the value of the requested supply voltage. The coarse resolution decoder circuit 112 may determine the first 6 bits of the 8 bits encoded in the VID signal and provide these 6 bits as the first digital code. In this way, rather than determining all 8 bits of the VID signal, the fine resolution decoder circuit 114 is biased based on the first 6 bits of the encoded VID signal, leaving the remaining 2 bits to be determined by the fine resolution decoder circuit. In one example, this described biasing reduces the time used by the fine resolution decoder circuit 114 to provide the second digital code from approximately 9*ln(2)*T to approximately 2*ln(2)*T, where T is the time constant of the fine resolution decoder circuit 114. As described in more detail below, the VID signal decoder 110 can be configured to decode the VID signal based on a combination of the first digital code and the second digital code and thus in a fast and accurate manner to provide a fast and accurate response to the following operation: providing VOUT to the amplitude requested by the CPU 102 via the VID signal.

[0018] Figure 2 is a block diagram of the VID signal decoder 110 in various examples. Thus, in the following description of the example of Figure 2 reference is made to the example of Figure 1 In various examples, the VID signal decoder 110 may be implemented as a combination of hardware, firmware, and / or software to decode the VID signal.

[0019] The VID signal decoder 110 includes a coarse resolution decoder circuit 112, a fine resolution decoder circuit 114, and a DAC 115. The coarse resolution decoder circuit 112 and the fine resolution decoder circuit 114 are each configured to receive the VID signal and separately decode the VID signal. In one example, as described herein, decoding by the fine resolution decoder circuit 114 is biased based on the output of the coarse resolution decoder circuit 112 (e.g., a first digital code). For example, the VID signal may be provided as a PWM signal having a duty cycle corresponding to the encoded amplitude of VOUT, the amplitude corresponding to the supply voltage requested by the CPU 102. For example, the VID signal may have an eight-bit signal encoded therein to specify the requested VOUT amplitude. Thus, each of the 1 / 256 steps and thus a change of approximately 0.4% in the duty cycle of the VID signal may correspond to a single discrete voltage amplitude step in VOUT (e.g., approximately 5 millivolts (mV)). As described in more detail herein, the coarse resolution decoder circuit 112 operates in the digital domain to decode the VID signal, while the fine resolution decoder circuit 114 operates in the analog domain to decode the VID signal.

[0020] In one example, the coarse resolution decoder circuit 112 includes a counter 206 and a decoder 208. The counter 206 is configured to sample each period of the VID signal to determine the logical high portion of the period relative to the logical low period of the period, and thereby determine an approximate duty cycle of the VID signal for a given period of the VID signal. The counter 206 can thus determine the amount of high count (HC) and the amount of low count (LC) within a given period of the VID signal. The high count corresponds to the on-time of the duty cycle, and the low count corresponds to the off-time of the duty cycle. The high count and the low count are each provided to the decoder 208 such that the decoder 208 can determine the approximate PWM duty cycle of the VID signal. For example, the decoder 208 can implement a decoding scheme to provide a first digital code based on the relative difference between the on-time and the off-time of the VID signal, shown as CRS in the Figure 2 example.

[0021] In one example, the decoding scheme can be implemented by the decoder 208 as a binary search, which is configured to iteratively compare the duty cycle with a target code that changes a binary value at each most significant bit at each iteration to determine the first digital code. The binary search can correspond to a successive approximation register (SAR) algorithm or can operate similar to a successive approximation register (SAR) algorithm. Thus, in order to determine the duty cycle of the VID signal, a binary search can be implemented in place of a division operation, thereby saving processing power and time.

[0022] For example, a binary search can convert the determined ON time (TON) of the duty cycle of the VID signal relative to the OFF time (TOFF) into a first digital code corresponding to an eight-bit CRS. The CRS can be represented according to the following equations 1 and 2.

[0023] CRS = TON / (TON + TOFF) * 256 (1)

[0024] CRS * (TON + TOFF) = TON * 256 (2)

[0025] Initially, the target code can be set to the eight-bit code 10000000, whose value corresponds to one half of the maximum value that can be represented as an eight-bit code, and thus is the numerical value 128 (corresponding to a 50% duty cycle). Therefore, the decoder 208 can compare the TON * 256 term with the initial target code * (TON + TOFF) term to determine whether the duty cycle of the VID signal is greater than or less than 50%. The binary search can thus set the most significant bit (MSB) of the target code to logic 1 or logic 0, respectively, depending on whether the duty cycle of the VID signal is greater than or less than 50%. Then, the binary search can iteratively step down to the next highest MSB, set the value to logic -1, and iteratively compare the TON * 256 term with the (TON + TOFF) * updated target code term.

[0026] As a first example, the first iterative comparison determines that the TON * 256 term is greater than the initial target code 10000000 * (TON + TOFF) term, and thus the duty cycle of the VID signal is greater than 50%. Therefore, the binary search sets the MSB of the target code to logic -1. Then, the binary search iteratively steps down to the next highest MSB and sets the value to logic -1 to iteratively compare the TON * 256 term with the updated target code 11000000 * (TON + TOFF) term. Therefore, the binary search can determine whether the duty cycle of the VID signal is greater than or less than 75%.

[0027] As a second example, the first iterative comparison determines that the TON * 256 term is less than the initial target code 10000000 * (TON + TOFF) term, and thus the duty cycle of the VID signal is less than 50%. Therefore, the binary search sets the MSB of the target code to logic -0. Then, the binary search iteratively steps down to the next highest MSB and sets the value to logic -1 to iteratively compare the TON * 256 term with the updated target code 01000000 * (TON + TOFF) term. Therefore, the binary search can determine whether the duty cycle of the VID signal is greater than or less than 25%.

[0028] Binary search can thus iteratively provide each bit of the target code until a comparison at the least significant bit (LSB) of the target code. Thus, binary search can provide an eight-bit CRS corresponding to the duty cycle of the VID signal in eight system clock cycles. Binary search can thus be implemented quickly (e.g., in microseconds) to provide the CRS. However, due to the sampling error associated with counter 206, the CRS may be accurate only to about the six most significant bits (MSBs). Thus, the coarse resolution decoder circuit 112 can provide a fast but slightly inaccurate decoding of the VID signal. For example, decoder 208 can provide an eight-bit CRS as an output in response to the completion of the binary search, or can continuously provide an updated target code as an output until the updated target code is complete as an eight-bit CRS.

[0029] The fine resolution decoder circuit 114 includes an analog filter 210, an analog-to-digital converter (ADC) 212, and an averaging circuit 214. The analog filter 210 can be configured to filter the period of the VID signal to provide an analog voltage corresponding to the duty cycle of the VID signal. For example, the analog filter 210 can correspond to a low-pass filter with a time constant T of a time less than the period of the VID signal. In one example, the analog filter 210 is implemented as a fifth-order passive resistor-capacitor (RC) filter that provides about 54 dB of attenuation at about 400 kHz. Thus, the analog filter 210 can have a time constant of about 30 μs.

[0030] As described above, the analog filter 210 can be biased according to the first digital code provided by the coarse resolution decoder circuit 112. For example, an analog representation of the first digital code can be provided to the analog filter by DAC 115, determined by DAC 115 based on the first digital code received from the coarse resolution decoder circuit 112. The analog filter 210 can include a bias or precharge input to receive the analog representation to bias or precharge the analog filter 210 (e.g., a capacitor (not shown) of the analog filter 210) to the value of the analog representation to reduce the time it takes for the fine resolution decoder circuit 114 to provide an accurate analog value of the duty cycle of the VID signal. In one example, the analog filter 210 provides an analog value of the duty cycle of the VID signal to the ADC 212, which in turn provides a corresponding digital representation of the duty cycle of the VID signal to the averaging circuit 214. In one example, the averaging circuit 214 is a moving average filter of any suitable architecture that provides, for example, a moving average of the received digital representations over a programmed number of samples to provide a second digital code, in Figure 2Shown as FN in. Thus, the fine-resolution decoder circuit 114 can provide an accurate but slightly less fast decoding of the VID signal, where the time taken to determine the second digital decoding is reduced by biasing the fine-resolution decoder circuit 114 according to the output of the coarse-resolution decoder circuit 112.

[0031] The first digital code CRS and the second digital code FN from the coarse-resolution decoder circuit 112 and the fine-resolution decoder circuit 114 respectively are provided to the multiplexer 216. The multiplexer 216 is configured to provide one of CRS or FN as the output signal (VDEC) based on the logical state of the select signal (SEL). In one example, the logical state of SEL controls whether the multiplexer provides CRS or FN as VDEC. VDEC is in turn implemented by the power controller 108 (e.g., via a DAC (not shown)) to control the amplitude of VOUT based on the selective activation of the power stage 106 via the respective signals PWM1 to PWMN.

[0032] In Figure 2 the example of, SEL is provided by the resolution selector 218. The resolution selector 218 is configured to monitor CRS and FN to determine the logical state of SEL. For example, the resolution selector 218 can provide SEL in a first logical state to cause the multiplexer 216 to provide CRS as VDEC, or provide SEL in a second logical state to cause the multiplexer 216 to provide FN as VDEC. For example, the resolution selector 218 sets the logical state of SEL based on the difference between CRS and FN. For example, the resolution selector 218 sets SEL to the first logical state in response to the difference between CRS and FN being greater than a programmed threshold, and sets SEL to the second logical state in response to the difference between CRS and FN being less than the programmed threshold. In one example, the programmed threshold is 3 (e.g., the value of two asserted LSBs of CRS and FN).

[0033] In one example, in response to a change in the VID signal, both the coarse-resolution decoder circuit 112 and the fine-resolution decoder circuit 114 can operate to provide CRS and FN corresponding to the updated duty cycle of the VID signal. However, as described above, the coarse-resolution decoder circuit 112 can provide CRS more quickly than the fine-resolution decoder circuit 114 provides FN. Thus, the value of CRS can be greater than the value of FN by more than a predetermined threshold value. In such examples, the resolution selector 218 can provide SEL in a first logical state such that the multiplexer 216 provides CRS as VDEC. Thus, the power controller 108 can selectively activate the power stage 106 to change the amplitude of VOUT to the amplitude corresponding to VDEC as defined by CRS.

[0034] Continuing with the above example, when VOUT stabilizes to the amplitude corresponding to VDEC as determined by CRS, the fine-resolution decoder circuit 114, which is biased according to CRS, continues to decode the VID signal to provide FN. At a subsequent time point, the resolution selector 218 determines that the difference between CRS and FN is within a predetermined threshold (e.g., within two LSBs). As described above, the fine-resolution decoder circuit 114 can provide a more accurate decoding of the VID signal compared to the coarse-resolution decoder circuit 112, but is slower than the coarse-resolution decoder circuit 112. Therefore, in response to the difference between CRS and FN being determined to be within the predetermined threshold, the resolution selector 218 changes SEL from the first logic state to the second logic state, such that the multiplexer 216 provides FN as VDEC. Thus, the power controller 108 can then selectively activate the power stage 106 to change the amplitude of VOUT to the amplitude corresponding to VDEC as defined by FN. Thus, VOUT is adjusted to the more accurate amplitude defined by FN. As a result, the VID signal decoder 110 can provide a fast but less accurate response to the change in the duty cycle of the VID signal based on the coarse-resolution decoder circuit 112, where the change in the duty cycle of the VID signal corresponds to the supply voltage change requested by the CPU 102. The VID signal decoder 110 then provides a more accurate but less quickly provided amplitude of VOUT to the CPU 102 based on the fine-resolution decoder circuit 114 biased according to CRS provided by the coarse-resolution decoder circuit 112 to meet the supply voltage requested by the CPU 102.

[0035] Figure 3Is a schematic diagram of the analog filter 210 in various examples. The analog filter 210 includes a first input (e.g., an analog VID input), a second input (e.g., a precharged analog input), and an output. In some examples, the analog filter 210 is a fifth-order filter that includes five serially cascaded low-pass filters. For example, the analog filter 210 includes filters 302, 304, 306, 308, and 310. The filter 302 receives the VID signal such that the input of the filter 302 is the input of the first input of the analog filter 210. In one example, the analog filter 210 includes a number of switches equal to the number of filters included in the analog filter 210. For example, the analog filter 210 includes switches 312, 314, 316, 318, and 320. Each of the switches 312-320 can be coupled between the corresponding filter in the filters 302-310 and the node 322. For example, the switch 312 is coupled between the node 322 and the output of the filter 302, the switch 314 is coupled between the node 322 and the output of the filter 304, the switch 316 is coupled between the node 322 and the output of the filter 306, the switch 318 is coupled between the node 322 and the output of the filter 308, and the switch 320 is coupled between the node 322 and the output of the filter 310. In some examples, each of the switches 312-320 includes a control terminal (not shown) that receives a control signal. The control signal controls the on state of the switch. The control signal can be provided according to any suitable control scheme, the scope of which is not limited herein. In some examples, a control signal is provided that has an asserted value for a determined amount of time, e.g., the amount of time is approximately equal to the capacitance value of the filter including a capacitor multiplied by the sum of the output impedance of the DAC 115 and the corresponding switch coupled to the filter. In one example, the node 322 is also the second input of the analog filter 210, and the output of the filter 310 is the output of the analog filter 210. Although the analog filter 210 is shown as a fifth-order filter in Figure 2 In the figure, in various other examples, the analog filter 210 can be implemented with a larger or smaller order based on the trade-off between the available surface area to be consumed by the implementation of the analog filter 210, the attenuation of the analog filter 210, and the settling time of the analog filter 210.

[0036] In an example of operation, an analog representation is received at a second input (e.g., node 322) of analog filter 210. Switches 312 - 320 are controlled to be closed (e.g., conduct between their respective end terminals) for a determined amount of time to pre - charge filters 302 - 310 according to the analog representation. When the determined amount of time has expired, switches 312 - 320 are controlled to be open (e.g., not conduct between their respective end terminals). In this way, instead of providing a signal at the output of analog filter 210 based only on the VID signal as received by filter 302, the signal is biased or pre - charged based on the analog representation received at node 322 to provide the output signal of analog filter 210 at the output of filter 310.

[0037] Figure 4 is an example of a timing diagram in various examples. Timing diagram 400 includes FIGS. 402, 404, and 406. FIGS. 402, 404, and 406 are shown as being connected in time such that FIGS. 402, 404, and 406 are time - aligned. FIG. 402 is an example of the amplitude of the CRS provided as a dashed line over time by the coarse - resolution decoder circuit 112. FIG. 404 is an example of the amplitude of the FN provided as a dotted line over time by the fine - resolution decoder circuit 114. FIG. 406 is an example of the amplitude of the VDEC provided as a thick solid line over time by the multiplexer 216 and the CRS and FN superimposed therein. As Figure 4 shown in the example of, the CRS, FN, and VDEC are plotted to represent a time - based convergence to an amplitude and do not necessarily represent a time - based swing of a changing value. In one example, timing diagram 400 corresponds to the decoding of the VID signal by the VID signal decoder 110 over time. Thus, in Figure 4 the following description of the example of, reference will be made to Figure 2 the example of or other figures of this description.

[0038] Initially, at time T0, the VID signal has a first duty cycle corresponding to a first amplitude of VOUT. The first amplitude of VOUT may be relatively low, for example, based on lower processing requirements of the CPU 102. Thus, at time T0, the CRS may have an initial value CRS1, and the FN may have an initial value FN1. At time T1, the CPU 102 changes the duty cycle of the VID signal in order to request a greater amplitude of VOUT. Thus, at time T1, the coarse - resolution decoder circuit 112 operates to provide the CRS to the updated duty cycle of the VID signal. In FIG. 402, at time T1, the CRS begins to rapidly increase from CRS1 to CRS2.

[0039] For example, the decoder 208 continuously provides the updated target code as output until the updated target code is completed as an eight-bit CRS. Thus, shortly after time T1 (e.g., after the first iteration of the binary search), the CRS corresponding to the updated target code can be larger than FN by a predetermined threshold. Therefore, the resolution selector 218 can provide SEL in the first logic state such that the multiplexer 216 provides the CRS as the VDEC. As a result, in FIG. 406, the VDEC is provided as the CRS and thus starts to increase rapidly at T1. Also at T1, the fine-resolution decoder circuit 114 starts to charge components (e.g., the capacitors of the filters 302-310) according to the VID signal to increase the value of FN from FN1.

[0040] At time T2, the CRS converges to the value of the VID signal decoded by the coarse-resolution decoder circuit 112 at the value of CRS2. Therefore, the power controller 108 can selectively activate the power stage 106 to change the amplitude of VOUT to correspond to the amplitude of the VDEC bounded by the CRS with the value CRS2. After time T2, the CRS is provided to the fine-resolution decoder circuit 114 to bias the fine-resolution decoder circuit 114, thereby rapidly increasing the value of FN up to time T3. After the biasing, the fine-resolution decoder circuit 114 decodes the updated VID signal and thus converges to the value corresponding to the duty cycle of the VID signal.

[0041] At time T4, the operation of the analog filter 210 may have continued according to the VID signal such that the difference between the CRS and FN can be within a predetermined threshold (e.g., 2 LSBs). As a result, the resolution selector 218 switches the SEL from the first logic state to the second logic state. Therefore, the multiplexer 216 provides the FN as the VDEC. In Figure 4 the example of, at time T5, the FN converges to the value of the VID signal decoded by the fine-resolution decoder circuit 114 at the value of FN3 which is slightly larger than the value CRS2. Therefore, the VDEC slightly increases from the value CRS2 to the value FN3 corresponding to the more accurately decoded value of the duty cycle of the VID signal. As a result, the VID signal decoder 110 can provide a rapid response to the change in the duty cycle of the VID signal corresponding to the change in the supply voltage requested by the CPU 102 based on the coarse-resolution decoder circuit 112, and ultimately can provide a more accurate amplitude of VOUT to the CPU 102 to meet the demand of the supply voltage requested by the CPU 102.

[0042] Figure 5FIG. 500 is a flow diagram of a method 500 for providing an output voltage in various examples. In at least some examples, method 500 is implemented by a voltage regulator such as voltage regulator 104. At operation 502, a VID signal decoder circuit (e.g., VID signal decoder 110) receives a VID signal. The VID signal is encoded with a digital value corresponding to a requested output voltage to be provided by the voltage regulator. At operation 504, the VID signal is provided to a coarse resolution decoder circuit (e.g., coarse resolution decoder circuit 112) and a fine resolution decoder circuit (e.g., fine resolution decoder circuit 114) of the VID signal decoder. At operation 506, the VID signal is decoded via the coarse resolution decoder circuit to provide a first digital code (e.g., CRS). At operation 508, as described herein, the fine resolution decoder circuit is biased or precharged according to the CRS. At operation 510, the VID signal is decoded via the fine resolution decoder circuit that is biased according to the CRS provided herein to provide a second digital code (e.g., FN). At operation 512, the first digital code is initially provided as an output signal (e.g., VDEC). At operation 514, in response to a difference between relative amplitudes of the first digital code and the second digital code being less than a threshold, the output signal is switched from the first digital code to the second digital code. At operation 516, an output voltage is provided, for example, to a CPU at an amplitude defined by the output signal.

[0043] Although the operations of method 500 described herein have been described and labeled with digital reference numerals, in various examples, method 500 includes additional operations not recited herein. In some examples, any one or more of the operations recited herein include one or more sub-operations. In some examples, any one or more of the operations recited herein are omitted. In some examples, any one or more of the operations listed herein are performed in an order other than the order presented herein (e.g., in reverse order, substantially simultaneously, overlapping, etc.). Each of these alternatives is within the scope of this specification.

[0044] The term "coupled" is used throughout the specification. The term may cover a connection, communication, or signal path that implements a functional relationship consistent with this specification. For example, if device A provides a signal to control device B to perform an action, then in a first example, device A is coupled to device B, or in a second example, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not substantially change the functional relationship between device A and device B such that device B is controlled by device A via the control signal provided by device A.

[0045] A device “configured to” perform a task or function can be configured (e.g., programmed and / or hardwired) by the manufacturer at the time of manufacture to perform the function and / or can be configured (or reconfigured) by the user after manufacture to perform the function and / or other additional or alternative functions. The configuration can be performed by firmware and / or software programming of the device, by the construction and / or layout of hardware components, and the interconnection of the device, or a combination thereof.

[0046] A circuit or device described herein as including particular components can actually be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (such as a voltage source and / or a current source) can instead include semiconductor elements (e.g., semiconductor die and / or integrated circuit (IC) packages) within only a single physical device and can be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or by an end user and / or a third party after manufacture.

[0047] Although certain components may be described herein as belonging to a particular process technology, those components can be interchanged with components of other process technologies. The circuits described herein can be reconfigured to include replacement components to provide functionality that is at least partially similar to the functionality available prior to the component replacement. Unless otherwise stated, a component shown as a resistor generally represents any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component can instead be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component can instead be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0048] The use of the phrase “ground voltage potential” in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable to or suitable for the teachings of this specification. In this specification, unless otherwise indicated, “about,” “approximately,” or “substantially” in front of a parameter means within + / - 10% of the parameter. Modifications can be made in the described examples, and there may be other examples within the scope of the claims.

Claims

1. A device, comprising: A first decoder circuit having a first voltage identification (VID) analog input and a first digital output; A precharge circuit having a digital input and a first analog output, the digital input being coupled to the first digital output; A second decoder circuit having a second VID analog input, a precharge analog input and a second digital output, the precharge analog input being coupled to the first digital output; And A multiplexer having a multiplexer output and a first multiplexer input and a second multiplexer input, the first multiplexer input being coupled to the first digital output, and the second multiplexer input being coupled to the second digital output.

2. The device according to claim 1, wherein the first decoder circuit comprises: A counter having a counter input and a counter output, the counter input being coupled to the first VID analog input; and A decoder having a decoder input and a decoder output, wherein the decoder input is coupled to the counter output, and the decoder output is the first digital output.

3. The device according to claim 1, wherein the second decoder circuit comprises: An analog filter having a filter output, the second VID analog input and the precharge analog input; An analog-to-digital converter (ADC) having an ADC input and an ADC output, the ADC input being coupled to the filter output; and An averaging circuit having an averaging input and an averaging output, wherein the averaging input is coupled to the ADC output, and the averaging output is the second digital output.

4. The device according to claim 1, wherein the precharge circuit is a digital-to-analog converter (DAC).

5. A device, comprising: A first decoder circuit having a first voltage identification (VID) analog input and a first digital output, the first decoder circuit being configured to provide a first digital code at the first digital output based on a VID signal from the first VID analog input; A precharge circuit having a digital input and a first analog output, the digital input being coupled to the first digital output, the precharge circuit being configured to receive the first digital code at the digital input and provide a precharge signal at the first analog output based on the first digital code; A second decoder circuit having a second VID analog input, a precharge analog input and a second digital output, the precharge analog input being coupled to the first digital output, the second decoder circuit being configured to provide a second digital code at the second digital output based on the precharge signal and the VID signal received via the second VID analog input, wherein the resolution of the first decoder circuit is less than the resolution of the second decoder circuit; And A multiplexer having a multiplexer output, a first multiplexer input and a second multiplexer input and a selection input, the first multiplexer input being coupled to the first digital output, and the second The multiplexer input is coupled to the second digital output, and the multiplexer is configured to provide the first digital code at the multiplexer output in response to a first state of a select signal at the select input and to provide the second digital code at the multiplexer output in response to a second state of the select signal.

6. The apparatus of claim 5, further comprising a resolution circuit configured to monitor the first digital code and the second digital code to: provide the select signal in the first state in response to a difference between the first digital code and the second digital code being at least a threshold difference; and provide the select signal in the second state in response to the difference between the first digital code and the second digital code being less than the threshold difference.

7. The apparatus of claim 5, wherein the VID signal is a pulse width modulation (PWM) signal having a duty cycle representative of a target output voltage.

8. The apparatus of claim 7, wherein the first decoder circuit comprises: a counter having a counter input and a counter output, the counter input being coupled to the first VID analog input, the counter being configured to determine an on-time and an off-time of each period of the VID signal; and a PWM decoder having a decoder input and a decoder output, wherein the decoder input is coupled to the counter output and the decoder output is the first digital output, and wherein the PWM decoder is configured to provide the first digital code based on a relative difference between the on-time and the off-time of the VID signal.

9. The apparatus of claim 8, wherein the PWM decoder is configured to iteratively compare the duty cycle with a target code that changes at each iteration to provide the first digital code by decoding the VID signal.

10. The apparatus of claim 8, wherein the precharge circuit comprises a DAC having a digital-to-analog converter (DAC) input and a DAC output, wherein the DAC input is coupled to the output of the PWM decoder, the DAC output is coupled to the precharge analog input, and the DAC is configured to provide the precharge signal at the DAC output in response to the first digital code at the DAC input.

11. The apparatus of claim 7, wherein the second decoder circuit comprises: an analog filter having a filter output and first and second filter inputs, wherein the first filter input is the second VID analog input, the second filter input is the precharge analog input, and the analog filter is configured to provide an analog signal based on the duty cycle of the VID signal; an analog-to-digital converter (ADC) having an ADC input and an ADC output, the ADC input being coupled to the filter output, and the ADC being configured to provide a digital value representative of the analog signal; and An averaging circuit having an averaging input and an averaging output, where the averaging output is the second digital output, the averaging input is coupled to the ADC output, and the second digital code is an average value of the digital values over a period of time.

12. The apparatus of claim 11, wherein the precharge circuit is a digital-to-analog converter (DAC), the first analog output is coupled to the precharge analog input, the analog filter includes a capacitor coupled between the precharge analog input and a ground terminal, and the DAC is configured to charge the capacitor with the precharge signal.

13. The apparatus of claim 5, wherein the precharge circuit is a digital-to-analog converter (DAC).

14. A voltage regulator comprising: A power stage configured to provide a corresponding output voltage; And A power controller configured to: Receive an analog voltage identification (VID) signal representing a target voltage; and Selectively activate one or more of the power stages to reduce a difference between the target voltage and a sum of the corresponding output voltages, the power controller including a VID signal decoder circuit for decoding the VID signal, wherein the VID signal decoder circuit includes: A first decoder circuit having a first voltage identification (VID) analog input and a first digital output, the first decoder circuit being configured to provide a first digital code at the first digital output based on a VID signal from the first VID analog input; A precharge circuit having a digital input and a first analog output, the digital input being coupled to the first digital output, the precharge circuit being configured to receive the first digital code at the digital input and provide a precharge signal at the first analog output based on the first digital code; A second decoder circuit having a second VID analog input, a precharge analog input, and a second digital output, the precharge analog input being coupled to the first digital output, the second decoder circuit being configured to provide a second digital code at the second digital output based on the precharge signal and the VID signal received via the second VID analog input, wherein a resolution of the first decoder circuit is less than a resolution of the second decoder circuit; And A multiplexer having a multiplexer output, a first multiplexer input, a second multiplexer input, and a selection input, the first multiplexer input being coupled to the first digital output, and the second multiplexer input being coupled to the second digital output, the multiplexer being configured to provide the first digital code at the multiplexer output in response to a first state of a selection signal at the selection input and provide the second digital code at the multiplexer output in response to a second state of the selection signal.

15. The voltage regulator according to claim 14, wherein the pre-charge circuit includes a digital-to-analog converter (DAC), the DAC being configured to receive the first digital code and provide an analog representation of the first digital code as the pre-charge signal.

16. The voltage regulator according to claim 15, wherein the VID signal is a pulse width modulation (PWM) signal having a duty cycle representing the target voltage.

17. The voltage regulator according to claim 16, wherein the first decoder circuit includes: A counter having a counter input and a counter output, the counter input being coupled to the first VID analog input, the counter being configured to determine the on-time and off-time of each cycle of the VID signal; and A PWM decoder having a decoder input and a decoder output, wherein the decoder input is coupled to the counter output, and the decoder output is the first digital output, wherein the PWM decoder is configured to provide the first digital code based on a relative difference between the on-time and the off-time of the VID signal.

18. The voltage regulator according to claim 17, wherein the second decoder circuit includes: An analog filter having a filter output and a first filter input and a second filter input, wherein the first filter input is the second VID analog input, the second filter input is the pre-charge analog input, and the analog filter is configured to provide an analog signal based on the duty cycle of the VID signal; An analog-to-digital converter (ADC) having an ADC input and an ADC output, the ADC input being coupled to the filter output, and the ADC being configured to provide a digital value representing the analog signal; and An averaging circuit having an averaging input and an averaging output, wherein the averaging output is the second digital output, the averaging input is coupled to the ADC output, and the second digital code is an average value of the digital value over a period of time.

19. The voltage regulator according to claim 18, wherein the DAC is coupled between the PWM decoder and the analog filter to pre-charge the analog filter.

20. The voltage regulator according to claim 14, wherein the VID signal decoder circuit includes a resolution circuit, the resolution circuit being configured to monitor the first digital code and the second digital code to: Provide the selection signal in the first state in response to a difference between the first digital code and the second digital code being at least a threshold difference; and Provide the selection signal in the second state in response to the difference between the first digital code and the second digital code being less than the threshold difference.

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