Three-dimensional memory device including inverted steps and method of manufacturing same

Abstract

A device structure includes an alternating stack of insulating layers and composite layers over a source layer, where each of the composite layers includes a combination of a respective dielectric material layer and a respective conductive layer; a memory opening, the memory opening extending vertically through the alternating stack; memory opening filling structures in the memory opening, where each of the memory opening filling structures includes a respective vertical stack of memory elements and a respective vertical semiconductor channel; and a contact via structure extending vertically through respective subsets of the dielectric material layer and the insulating layer in the alternating stack and contacting a horizontal surface of a respective one of the conductive layers in the alternating stack.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of the entire contents of U.S. Non - provisional application Ser. No. 18 / 357,676, entitled “THREE - DIMENSIONAL MEMORY DEVICE CONTAINING INVERTED STAIRCASE AND METHOD OF MAKING THE SAME”, filed on Jul. 24, 2023, with the United States Patent and Trademark Office, and incorporates the entire contents thereof by reference for all purposes. This U.S. Non - provisional application claims the priority of U.S. Provisional application Ser. No. 63 / 482,105, filed on Jan. 30, 2023. Technical Field

[0003] The present disclosure generally relates to the field of semiconductor devices, and more particularly to three - dimensional memory devices including an inverted staircase and a contact via structure, and methods of forming the same. Background Art

[0004] A three - dimensional memory device is disclosed in the article by T. Endoh et al., entitled “Novel Ultra High Density Memory With A Stacked - Surrounding Gate Transistor (S - SGT) Structured Cell”, IEDM Proc. (2001) 33 - 36. The three - dimensional memory device includes three - dimensional vertical NAND strings having one bit per cell. Support circuits for performing write, read, and erase operations on the memory cells in the vertical NAND strings are typically provided by complementary metal - oxide - semiconductor (CMOS) devices formed on the same substrate as the three - dimensional memory device. Summary of the Invention

[0005] According to one aspect of the present disclosure, there is provided a device structure including: an alternating stack of insulating layers and composite layers located above a source layer, wherein each composite layer in the alternating stack includes a combination of a respective dielectric material layer and a respective conductive layer; a memory opening extending vertically through the alternating stack; a memory opening filling structure located in the memory opening, wherein each memory opening filling structure in the memory opening filling structure includes a respective vertical stack of memory elements and a respective vertical semiconductor channel; and a contact via structure extending vertically through respective subsets of the dielectric material layers and the insulating layers in the alternating stack and contacting a horizontal surface of a respective one of the conductive layers in the alternating stack.

[0006] According to another aspect of the present disclosure, a method of forming a device structure includes: forming an alternating stack of an insulating layer and a sacrificial material layer including a dielectric material above a carrier substrate; forming a memory opening through the alternating stack; forming a memory opening fill structure in the memory opening, wherein each memory opening fill structure in the memory opening fill structure includes a corresponding vertical stack of memory elements and a corresponding vertical semiconductor channel; forming a lateral isolation trench and a via through-hole cavity in the alternating stack, wherein each sacrificial material layer in the sacrificial material layer is exposed to each lateral isolation trench in the lateral isolation trench, and the via through-hole cavity has different depths; forming a lateral recess by isotropically recessing the sacrificial material layer around the lateral isolation trench and the via through-hole cavity, wherein the lateral extent of the lateral recess is different, and wherein the remaining portion of the sacrificial material layer includes a dielectric material layer; forming a conductive layer in the lateral recess; forming a lateral isolation trench fill structure and a via fill pillar structure in the lateral isolation trench and the via through-hole cavity, respectively; forming a contact via through-hole cavity through a corresponding subset of the dielectric material layer and through a corresponding subset of the insulating layer to a horizontal surface of a corresponding one of the conductive layers; and forming a contact via structure in the contact via through-hole cavity that contacts the conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic vertical cross-sectional view of an exemplary structure after forming a source-level insulating layer, a source layer, and an alternating stack of an insulating layer and a sacrificial material layer above a carrier substrate according to an embodiment of the present disclosure.

[0008] Figure 2A is a vertical cross-sectional view of an exemplary structure after forming a support pillar structure and a support wall structure according to an embodiment of the present disclosure.

[0009] Figure 2B is Figure 2A a top-down view of the exemplary structure of. The vertical plane A-A' is Figure 2A the plane of the vertical cross-section of.

[0010] Figure 2C is Figure 2A and Figure 2B an enlarged top-down view of the exemplary structure of. The vertical plane A-A' is Figure 2A the plane of the vertical cross-section of.

[0011] Figure 3A is a vertical cross-sectional view of an exemplary structure after forming a memory opening according to an embodiment of the present disclosure.

[0012] Figure 3B is Figure 3A a top-down view of the exemplary structure of. The vertical plane A-A' isFigure 3A The plane of the vertical section.

[0013] Figure 3C is Figure 3A and Figure 3B An enlarged top-down view of an exemplary structure of. The vertical plane A-A' is Figure 3A The plane of the vertical section.

[0014] Figures 4A to 4F A sequential schematic vertical sectional view of a memory opening within an exemplary structure during the formation of a memory opening fill structure according to an embodiment of the present disclosure.

[0015] Figure 5A A vertical sectional view of an exemplary structure after the formation of a memory opening fill structure according to an embodiment of the present disclosure.

[0016] Figure 5B is Figure 5A A top-down view of an exemplary structure of. The vertical plane A-A' is Figure 5A The plane of the vertical section.

[0017] Figure 5C is Figure 5A and Figure 5B An enlarged top-down view of an exemplary structure of. The vertical plane A-A' is Figure 5A The plane of the vertical section.

[0018] Figure 6A A vertical sectional view of an exemplary structure after the formation of a patterned hard mask according to an embodiment of the present disclosure.

[0019] Figure 6B is Figure 6A A top-down view of an exemplary structure of. The vertical plane A-A' is Figure 6A The plane of the vertical section.

[0020] Figure 6C is Figure 6A and Figure 6B An enlarged top-down view of an exemplary structure of. The vertical plane A-A' is Figure 6A The plane of the vertical section.

[0021] Figures 7A to 7E A sequential vertical sectional view of an exemplary structure during the formation of a lateral isolation trench and a via through hole trench according to an embodiment of the present disclosure.

[0022] Figure 8A A vertical sectional view of an exemplary structure after the formation of a lateral recess according to an embodiment of the present disclosure.

[0023] Figure 8B isFigure 8A Top-down view of an exemplary structure. The vertical plane A-A' is Figure 8A the plane of the vertical section of

[0024] Figure 8C is Figure 8A and Figure 8B An enlarged top-down view of an exemplary structure of Figure 8A the vertical section of

[0025] Figure 8D is along Figure 8B 、 Figure 8C 、 Figure 8F and Figure 8G Vertical sectional view of an exemplary structure along the vertical plane D-D' of

[0026] Figure 8E is along Figure 8A Another vertical sectional view of an exemplary structure along the vertical plane A-A', where the position of the omitted area in the view is shifted laterally with respect to the Figure 8A view.

[0027] Figure 8F is along Figure 8A 、 Figure 8D and Figure 8E Horizontal sectional view of an exemplary structure along the horizontal plane F-F' in

[0028] Figure 8G is along Figure 8A 、 Figure 8D and Figure 8E Horizontal sectional view of an exemplary structure along the horizontal plane G-G' in

[0029] Figure 9A Vertical sectional view of an exemplary structure after forming a conductive layer in a lateral recess according to an embodiment of the present disclosure.

[0030] Figure 9B is Figure 9A Top-down view of an exemplary structure of Figure 9A the vertical section of

[0031] Figure 9C is Figure 9A and Figure 9B An enlarged top-down view of an exemplary structure of Figure 9A the vertical section of

[0032] Figure 9D is along Figure 9B 、 Figure 9C 、 Figure 9F and Figure 9GVertical sectional view of an exemplary structure of the vertical plane D-D'.

[0033] Figure 9E is along Figure 9A Another vertical sectional view of an exemplary structure of the vertical plane A-A', where the position of the omitted area in the view is laterally shifted with respect to the Figure 9A view.

[0034] Figure 9F is along Figure 9A 、 Figure 9D and Figure 9E Horizontal sectional view of an exemplary structure of the horizontal plane F-F' in

[0035] Figure 9G is along Figure 9A 、 Figure 9D and Figure 9E Horizontal sectional view of an exemplary structure of the horizontal plane G-G' in

[0036] Figure 10A Vertical sectional view of an exemplary structure after forming a lateral isolation trench filling structure and a via filling pillar structure according to an embodiment of the present disclosure.

[0037] Figure 10B is Figure 10A Top-down view of an exemplary structure. The vertical plane A-A' is the plane of the vertical section of Figure 10A .

[0038] Figure 10C is Figure 10A and Figure 10B Enlarged top-down view of an exemplary structure. The vertical plane A-A' is the plane of the vertical section of Figure 10A .

[0039] Figure 10D is along Figure 10B and Figure 10C Vertical sectional view of an exemplary structure of the vertical plane D-D'.

[0040] Figure 11 Vertical sectional view of an exemplary structure after forming a metal interconnect structure and a memory side bonding pad according to an embodiment of the present disclosure.

[0041] Figure 12 Vertical sectional view of an exemplary structure after bonding a logic die to a memory die according to an embodiment of the present disclosure.

[0042] Figure 13 Vertical sectional view of an exemplary structure after removing a carrier substrate according to an embodiment of the present disclosure.

[0043] Figure 14A is a vertical cross-sectional view of an exemplary structure after forming a layer contact via structure and a source contact via structure according to an embodiment of the present disclosure.

[0044] Figure 14B is along Figure 14A a horizontal cross-sectional view of an exemplary structure of the horizontal plane B-B'. The vertical plane A-A' is Figure 14A the plane of the vertical cross-section of

[0045] Figure 15 is a vertical cross-sectional view of an exemplary structure after forming a backside metal interconnect structure and a backside bond pad according to an embodiment of the present disclosure.

[0046] Figure 16A , Figure 16B , Figure 16C , Figure 16D and Figure 16E is a sequential vertical cross-sectional view of steps during the fabrication of an alternative exemplary structure according to an alternative embodiment of the present disclosure. DETAILED DESCRIPTION

[0047] As discussed above, embodiments of the present disclosure are directed to three-dimensional memory devices including inverted steps and contact via structures and methods of forming the same, aspects of which are described below. Embodiments of the present disclosure can be used to form various structures including multi-level memory structures, non-limiting examples of which include semiconductor devices such as three-dimensional memory array devices including a plurality of NAND memory strings.

[0048] The drawings are not drawn to scale. In cases where a single instance of an element is illustrated, multiple instances of the element may be replicated unless otherwise explicitly described or clearly indicated that no replication of the element exists. Ordinal numbers such as "first", "second", and "third" are used only to identify similar elements, and different ordinal numbers may be used in the specification and claims of the present disclosure. The same reference numerals represent the same or similar elements. Unless otherwise stated, it is assumed that elements with the same reference numerals have the same composition. Unless otherwise indicated, "contact" between elements refers to direct contact between elements providing an edge or surface shared by the elements. As used herein, a first element located "on" a second element may be located on the outer side of the surface of the second element or on the inner side of the second element. As used herein, a first element is "directly located" "on" a second element if there is physical contact between the surface of the first element and the surface of the second element. As used herein, a "prototype" structure or a "structure in process" refers to an instantaneous structure in which the shape or composition of at least one component is subsequently modified. As used herein, a first electronic component is electrically connected to a second electronic component if there is an electrical conduction path between the first electronic component and the second electronic component.

[0049] As used herein, a "layer" refers to a portion of material that includes a region having a thickness. A layer can extend over an entire underlying or overlying structure, or can have a scope that is less than the scope of the underlying or overlying structure. Additionally, a layer can be a region of a uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer can be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, or can have one or more layers thereon, above, and / or below it.

[0050] As used herein, a "semiconductor material" refers to a material having a conductivity in the range of 1.0×10 -6 S / cm to 1.0×10 5 S / cm. As used herein, a "semiconductor material" refers to a material having a conductivity in the range of 1.0×10 -6 S / cm to 1.0×10 5 S / cm in the absence of an electrical dopant, and capable of producing a doped material having a conductivity in the range of 1.0 S / cm to 1.0×10 5 S / cm when appropriately doped with an electrical dopant. As used herein, an "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the band structure, or an n-type dopant that adds electrons to the conduction band within the band structure. As used herein, a "conductive material" refers to a material having a conductivity greater than 1.0×10 5 S / cm. As used herein, an "insulator material" or "dielectric material" refers to a material having a conductivity less than 1.0×10 -6 S / cm. As used herein, a "heavily doped semiconductor material" refers to a semiconductor material doped with an electrical dopant at a high enough atomic concentration to become a conductive material when formed as a crystalline material or when transformed into a crystalline material by an annealing process (e.g., from an initial amorphous state), i.e., having a conductivity greater than 1.0×10 5 S / cm. A "doped semiconductor material" can be a heavily doped semiconductor material, or can be a semiconductor material including a dopant providing a conductivity in the range of 1.0×10 -6 S / cm to 1.0×10 5A semiconductor material with an electrical dopant (i.e., a p-type dopant and / or an n-type dopant) having a concentration within the range of S / cm in conductivity. "Intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrical dopant. Thus, a semiconductor material can be semi-conductive or conductive, and can be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semi-conductive or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, "metal material" refers to a conductive material that includes at least one metal element. All conductivity measurements are performed under standard conditions.

[0051] Generally speaking, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board through a set of pins or solder balls. A semiconductor package may include a semiconductor chip (or "chip") or multiple semiconductor chips joined between semiconductor chips, for example, through flip-chip bonding or another chip-to-chip bonding. A package or chip may include a single semiconductor die (or "die") or multiple semiconductor dice. A die is the smallest unit that can independently execute external commands or report status. Generally, a package or chip with multiple dice can execute as many external commands simultaneously as the total number of dice therein. Each die includes one or more planes. The same simultaneous operations can be performed in each plane within the same die, but there may be some limitations. In the case where the die is a memory die (i.e., a die including memory elements), simultaneous read operations, simultaneous write operations, or simultaneous erase operations can be performed in each plane within the same memory die. Each plane contains multiple memory blocks (or "blocks"), which are the smallest units that can be erased in a single erase operation. Each memory block contains multiple pages, which are the smallest units that can be selected for programming.

[0052] Reference Figure 1 , illustrates an exemplary structure according to an embodiment of the present disclosure, which includes a carrier substrate 9, a source-level insulating layer 8, a source layer 10, and an alternating stack (32, 46) of an insulating layer 32 and a sacrificial material layer 42. The carrier substrate 9 may include any substrate that can be used to provide structural support during the formation of a memory die thereon. For example, the carrier substrate 9 may include a semiconductor substrate, an insulating substrate, a conductive substrate, or a combination thereof. In one embodiment, the carrier substrate 9 may include a commercially available single-crystalline silicon wafer. The source-level insulating layer 8 is composed of an insulating material. For example, the source-level insulating layer 8 may include silicon oxide and may have a thickness within the range of 50 nm to 1,000 nm, but smaller and larger thicknesses may also be employed.

[0053] The source layer 10 is formed in or on an upper portion of the source-level insulating layer 8. In one embodiment, the source-level insulating layer 8 may be embedded in the source layer 10. The source layer 10 includes a heavily doped semiconductor material (such as polysilicon, a silicon-germanium alloy, or a group III-V compound semiconductor material) that is doped with a conductivity type opposite to that of a subsequently formed vertical semiconductor channel. If the vertical semiconductor channel is doped with a first conductivity type, the source layer 10 may be doped with a second conductivity type opposite to the first conductivity type. If the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The atomic concentration of the dopant of the second conductivity type in the source layer 10 may be in the range of 5.0×10 18 / cm 3 to 2.0×10 21 / cm 3 such as 1.0×10 19 / cm 3 to 1.0×10 21 / cm 3 but smaller and larger atomic concentrations may also be employed. The thickness of the source layer 10 may be in the range of 100 nm to 500 nm, but smaller and larger thicknesses may also be employed. In one embodiment, the top surface of the source layer 10 is formed in a horizontal plane including the top surface of the source-level insulating layer 8.

[0054] An alternating stack of the insulating layer 32 and the sacrificial material layer 42 is formed on the source layer 10. The insulating layer 32 includes an insulating material, such as a silicon oxide-based insulating material. As used herein, a silicon oxide-based insulating material refers to an insulating material including undoped silicate glass, doped silicate glass, organosilicate glass, or silicon oxynitride with or without dopants therein. The bottommost layer of the insulating layer 32 is referred to herein as the bottommost insulating layer 32B. The topmost layer of the insulating layer 32 is referred to herein as the topmost insulating layer 32T.

[0055] The insulating layer 32 includes and / or consists essentially of an insulating material. Insulating materials that may be used for the insulating layer 32 include, but are not limited to, silicon oxide (including doped or undoped silicate glass), silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, etc. In one embodiment, the insulating layer 32 may consist essentially of silicon oxide, such as undoped silicate glass or doped silicate glass.

[0056] The sacrificial material layer 42 includes a sacrificial material that can be selectively removed relative to the insulating material of the insulating layer 32. As used herein, if a removal process removes a first material at a rate of at least twice the removal rate of a second material, then the removal of the first material is "selective" with respect to the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material with respect to the second material. Non-limiting examples of sacrificial materials include silicon nitride, borosilicate glass, organosilicate glass, and polymeric materials. In one embodiment, the sacrificial material layer 42 may include silicon nitride.

[0057] For example, the insulating layer 32 and the sacrificial material layer 42 may be deposited by chemical vapor deposition (CVD). The thicknesses of the insulating layer 32 and the sacrificial material layer 42 may be in the range of 20 nm to 50 nm, although smaller and larger thicknesses may be employed for each insulating layer 32 and each sacrificial material layer 42. The number of repetitions of the pairs of the insulating layer 32 and the sacrificial material layer 42 may be in the range of 2 to 1,024, and typically in the range of 8 to 256, although larger numbers of repetitions may also be employed.

[0058] An exemplary structure may include a memory array region 100 and at least one contact region 300, in which a memory stack structure will be subsequently formed in the memory array region and a contact via structure will be subsequently formed in the at least one contact region.

[0059] Reference Figures 2A to 2C , a photoresist material stack (not shown) including at least a photoresist layer may be formed over the topmost insulating layer 32T and may be lithographically patterned to form openings therein. The openings include discrete circular or oval openings formed in the contact region 300 and elongated openings formed adjacent to the boundary between the memory array region 100 and the contact region 300. In one embodiment, the elongated opening includes a trench-shaped opening having a respective pair of transverse opening segments extending laterally along a first horizontal direction (e.g., the word line direction) hd1 and a respective pair of longitudinal opening segments extending laterally along a second horizontal direction (e.g., the bit line direction) hd2. In another embodiment, the elongated opening includes a slit-shaped opening.

[0060] Patterns in the photoresist material stack can be transferred through at least one anisotropic etching by using the patterned photoresist material stack as an etch mask through the alternating stack (32, 42) and the source-level insulating layer 8. The portions of the alternating stack (32, 42) and the source-level insulating layer 8 located below the openings in the patterned photoresist material stack are etched to form support openings and support trenches. The carrier substrate 9 can be used as an etch stop structure. As used herein, a "support opening" refers to an opening in which a support structure (such as a support pillar structure) that mechanically supports other elements is subsequently formed. The support openings can include cylindrical or rectangular openings. As used herein, a "support trench" refers to a trench in which a trench-shaped support structure (such as a trench-shaped wall structure) that mechanically supports other elements is subsequently formed. The support trenches can include linear elongated trenches, curved elongated trenches, or moat-shaped trenches that surround a portion of the alternating stack (32, 42). The trench-shaped support structure can include a linear wall, a curved wall, or a moat-shaped wall that surrounds a portion of the alternating stack (32, 42).

[0061] A dielectric filling material such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass can be deposited in the support openings and support trenches by a conformal deposition process such as a low-pressure chemical vapor deposition process. An excess portion of the dielectric filling material can be removed from above a horizontal plane including the top surface of the topmost insulating layer 32T. For example, a recess etching process can be employed. The remaining portion of the dielectric filling material that fills the support openings constitutes the support pillar structure 20. The remaining portion of the dielectric filling material that fills the support moat trenches constitutes the support wall structure 120. Each of the support pillar structure 20 and the support wall structure 120 can be substantially composed of at least one dielectric filling material. Each support pillar structure in the support pillar structure 20 can have a corresponding horizontal cross-sectional shape that is circular, elliptical, or square, and the support wall structure 120 can have a corresponding shape of a linear wall, a curved wall, or a rectangular wall frame, which can optionally have rounded corners.

[0062] The support pillar structure 20 and the support wall structure 120 can be formed as a periodic structure having periodicity along a second horizontal direction hd2. In this case, a unit pattern including a set of support pillar structures 20 and a set of support wall structures 120 can be repeated along the second horizontal direction hd2. Each repeating unit pattern of the structure is referred to herein as a repeating unit RU. According to one aspect of the present disclosure, each support wall structure in the support wall structure 120 can have a length along the second horizontal direction hd2 that is less than the width of the repeating unit RU along the second horizontal direction hd2. In one embodiment, the support pillar structure 20 and the support wall structure 120 can contact the top surface of the carrier substrate 9. In one embodiment, the support pillar structure 20 and the support wall structure 120 can have a top surface coplanar with the top surface of the topmost insulating layer 32T.

[0063] ReferenceFigures 3A to 3C A photoresist material stack (not shown), including at least a photoresist layer, may be formed over the topmost insulating layer 32T and may be lithographically patterned to form openings therein. The openings include discrete openings that form a memory array region 100 within a region where the source layer 10 is present. In one embodiment, a cluster of openings may be formed as a two-dimensional periodic array of openings formed within corresponding repeating units RU.

[0064] By at least one anisotropic etching using the patterned photoresist material stack as an etch mask, the pattern in the photoresist material stack may be transferred through the alternating stack (32, 42) and at least to the top surface of the source layer 10. The portion of the alternating stack (32, 42) located below the openings in the patterned photoresist material stack is etched to form memory openings. As used herein, a "memory opening" refers to a structure in which a memory element (such as a memory stack structure) is subsequently formed.

[0065] The memory openings 49 extend through the entire alternating stack (32, 42). The chemistry of the anisotropic etching process used to etch through the materials of the alternating stack (32, 42) may be alternated to optimize the etching of the materials in the alternating stack (32, 42). The anisotropic etching may be, for example, a series of reactive ion etchings. The sidewalls of the memory openings 49 may be substantially vertical or may be tapered. Subsequently, the patterned photoresist material stack may be removed, for example, by ashing. In one embodiment, the memory openings 49 may extend from the top surface of the alternating stack (32, 42) to a horizontal plane including at least the topmost surface of the source layer 10. In one embodiment, after the top surface of the source layer 10 is physically exposed at the bottom of each memory opening 49, an over-etch into the source layer 10 may be optionally performed. The over-etch may be performed before or after removing the photoresist material stack. In other words, the recessed surface of the source layer 10 may be vertically offset from the non-recessed top surface of the source layer 10 by a recess depth. The recess depth may be, for example, in the range of 1 nm to 50 nm, where smaller and larger recess depths may also be employed. The over-etch is optional and may be omitted. If the over-etch is not performed, the bottom surface of the memory openings 49 may be coplanar with the topmost surface of the source layer 10.

[0066] A two-dimensional array of memory openings 49 may be formed in the memory array region 100. Multiple rows of memory openings 49 may be formed such that each row of memory openings 49 is arranged along a first horizontal direction hd1. The multiple rows of memory openings 49 may be laterally spaced apart along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1.

[0067] Figures 4A to 4F is a schematic vertical cross-sectional view of the order of memory openings 49 within an exemplary structure during the formation of a memory opening fill structure 58 according to an embodiment of the present disclosure.

[0068] Reference Figure 4A , which illustrates the memory opening 49 after the processing steps described in the reference Figures 3A to 3C .

[0069] Reference Figure 4B , a set of material layers can be conformally deposited, which may include an optional barrier dielectric layer 52, a memory material layer 54, and an optional dielectric liner 56. The barrier dielectric layer 52 may include at least one barrier dielectric material, such as silicon oxide and / or dielectric metal oxide. The memory material layer 54 may include any memory material in which memory bits can be stored. For example, the memory material layer 54 may include a charge storage layer, such as a silicon nitride layer. Alternatively, the memory material layer 54 may include a ferroelectric memory material, a resistive memory material, a phase change memory material, or any other memory material known in the art. In some embodiments, the memory material layer 54 may include a vertical stack of discrete memory material portions formed at the level of the sacrificial material layer 42. Generally speaking, the memory material layer 54 may include a vertical stack of memory elements formed at the level of the sacrificial material layer 42. In one embodiment, the vertical stack of memory elements includes the portion of the memory material layer 54 located at the level of the sacrificial material layer 42. The optional dielectric liner 56 (if present) may provide electrical isolation between the memory material layer 54 and the semiconductor channel to be formed subsequently. In the case where the memory material layer 54 includes a charge storage material, the optional dielectric liner 56 may include a tunneling dielectric layer.

[0070] Reference Figure 4C , an anisotropic etching process can be performed to remove the horizontal extensions of the optional barrier dielectric layer 52, the memory material layer 54, and the optional dielectric liner 56. The combination of the vertical extensions of the optional barrier dielectric layer 52, the memory material layer 54, and the optional dielectric liner 56 remaining in the respective memory openings 49 constitutes the memory film 50.

[0071] Reference Figure 4D, a semiconductor channel layer 60L can be deposited over the memory film 50. The semiconductor channel layer 60L includes a semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel layer 60L includes amorphous silicon or polycrystalline silicon. The semiconductor channel layer 60L can be formed by a conformal deposition method such as low-pressure chemical vapor deposition (LPCVD). In one embodiment, the semiconductor channel layer 60L can be deposited as an amorphous semiconductor material. The thickness of the semiconductor channel layer 60L can be in the range of 2 nm to 10 nm, but smaller and larger thicknesses can also be used. A memory cavity is formed in the volume of each memory opening 49 that is not filled with the deposited material layers (52, 54, 56, 60L).

[0072] Reference Figure 4E , a dielectric core layer can be deposited to fill any remaining portion of the memory cavity within each memory opening. The dielectric core layer includes a dielectric material, such as silicon oxide or organosilicate glass. The dielectric core layer can be deposited by a conformal deposition method (such as low-pressure chemical vapor deposition (LPCVD)) or by a self-planarizing deposition process (such as spin coating). The dielectric core layer can then be recessed selectively with respect to the material of the semiconductor channel layer 60L, for example, by recess etching. The material of the dielectric core layer is recessed vertically below the horizontal plane of the top surface including the topmost insulating layer 32T. Each remaining portion of the dielectric core layer constitutes a dielectric core 62.

[0073] Reference Figure 4F , a doped semiconductor material having a second conductivity type can be deposited in each recess cavity located above the dielectric core 62. The second conductivity type is opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. In one embodiment, the doped semiconductor material can be deposited as an amorphous semiconductor material. The dopant concentration in the doped semiconductor material having a second conductivity type can be in the range of 5.0×10 18 / cm 3 to 2.0×10 21 / cm 3 , but smaller and larger dopant concentrations can also be used.

[0074] An etch-back process may be performed to remove portions of the doped semiconductor material doped with the second conductivity type and the semiconductor channel layer 60L above the top surface of the topmost insulating layer 32T, e.g., by chemical mechanical polishing (CMP) or recess etching, to form the drain region 63. Each remaining portion of the doped semiconductor material doped with the second conductivity type constitutes the drain region 63. Each remaining portion of the semiconductor channel layer 60L constitutes the vertical semiconductor channel 60. When the vertical NAND device including the vertical semiconductor channel 60 is turned on, current may flow through each vertical semiconductor channel 60. Within each memory opening 49, the dielectric liner 56 is surrounded by the memory material layer 54 and laterally surrounds the vertical semiconductor channel 60. Each set of adjacent blocking dielectric layer 52, memory material layer 54, and dielectric liner 56 together constitutes the memory film 50, which may store charge for a macroscopic retention time. In some embodiments, at this step, the blocking dielectric layer 52 may be absent from the memory film 50 and may be formed later after the formation of the lateral recess. As used herein, the macroscopic retention time refers to the retention time suitable for the operation of the memory device as a permanent memory device, such as a retention time exceeding 24 hours. Each combination of the memory film 50 and the vertical semiconductor channel 60 constitutes a memory stack structure 55.

[0075] Each adjacent combination of the vertical semiconductor channel 60 and the memory film 50 constitutes a memory stack structure 55. Thus, each memory stack structure 55 may include the vertical semiconductor channel 60, the dielectric liner 56, a plurality of memory elements including portions of the memory material layer 54, and optionally the blocking dielectric layer 52. Each combination of the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 is referred to herein as a memory opening fill structure 58. Generally speaking, each memory opening fill structure in the memory opening fill structure 58 includes a corresponding vertical stack of memory elements (including portions of the memory material layer 54) and a corresponding vertical semiconductor channel 60. In one embodiment, each memory opening fill structure in the memory opening fill structure 58 includes a corresponding drain region 63 that contacts the top end of the corresponding vertical semiconductor channel 60.

[0076] Reference Figures 5A to 5C , an exemplary structure after the formation of the memory opening fill structure 58 within the memory opening 49 is illustrated. An example of the memory opening fill structure 58 may be formed in Figures 3A to 3C each memory opening 49 of the structure of

[0077] Reference Figures 6A to 6C, a patterned hard mask layer 38 may be formed over the topmost insulating layer 32T. The patterned hard mask layer may include a semiconductor material (such as amorphous silicon) and / or a metal material (such as TiN). The openings in the patterned hard mask layer 38 may have the pattern of all the subsequent laterally isolated trenches and via vias cavities to be formed. The openings in the patterned hard mask layer 38 include an elongated opening 77 that extends laterally from one end of the memory array region 100 to the other end of the memory array region 100 along a first horizontal direction hd1, such that each end of the elongated opening 77 has an area overlap with a corresponding underlying support wall structure in the support wall structure 120. In addition, the openings in the patterned hard mask layer 38 include a plurality of rows of discrete openings 27 formed in a contact region 300 within a respective one of the repeating units RU.

[0078] In one embodiment, each repeating unit RU may include two elongated openings 77 and one row of discrete openings 27 for each contact region 300. Thus, in the case where two contact regions 300 are adjacent to the memory array region 100, each repeating unit RU may include two elongated openings 77 and two rows of discrete openings 27, as Figure 6C shown. In one embodiment, each row of discrete openings 27 may be arranged at a uniform pitch p along the first horizontal direction hd1, as Figure 6A and Figure 6B shown. In one embodiment, the elongated openings 77 may have a uniform width in the range of 200 nm to 2 microns along a second horizontal direction hd2, but smaller and larger widths may also be employed. Each elongated opening 77 may have a corresponding horizontal cross-sectional shape that is rectangular or rounded rectangular. The discrete openings 27 may have a lateral dimension (such as length or width) in the range of 200 nm to 2 microns, but smaller or larger lateral dimensions may also be employed. In one embodiment, the discrete openings 27 may have a corresponding horizontal cross-sectional shape that is circular, elliptical, rectangular, rounded rectangular, or any other two-dimensional shape with a closed perimeter.

[0079] Referring to Figures 7A to 7D , a set of unit process steps may be iteratively performed by using a patterned photoresist layer (271, 272, 273) as the mask pattern changes. The set of process steps includes: a patterned photoresist formation step that forms a patterned photoresist layer (271, 272, 273) that covers a corresponding subset of the discrete openings 27 and does not cover the elongated openings 77; and an anisotropic etching step that etches portions of the alternating stack (32, 42) that are not masked by the patterned hard mask layer 38 or the corresponding patterned photoresist layer (271, 272, 273).

[0080] In one embodiment, multiple iterations of a combination of a corresponding masking process and a corresponding anisotropic etching process may be performed to etch through corresponding subsets of the sacrificial material layer 42 and corresponding subsets of the insulating layer 32 below each opening (79, 29) in the patterned hard mask layer 38. Each masking process may employ a corresponding patterned photoresist layer (271, 272, 273, etc.) that masks corresponding subsets of the openings (79, 29) in the patterned hard mask layer 38 and does not mask the corresponding complementary subsets of the openings. Each anisotropic etching process etches a corresponding number of the sacrificial material layers 42 and a corresponding number of the insulating layers 32 below each opening in the patterned hard mask layer 38 that is not masked by the corresponding patterned photoresist layer. In one embodiment, the etch depth of the anisotropic etching steps is different between the unit process steps within the set of unit process steps. The patterned photoresist layers (271, 272, 273, etc.) may be removed, for example, by ashing after the corresponding anisotropic etching process.

[0081] In one embodiment, the number of etched sacrificial material layers 42 and etched insulating layers 32 below the unmasked openings in the patterned hard mask layer 38 may be a non-negative integer power of 2, i.e., 1, 2, 4, 8, 16, 32, 64, etc. By using a combination of various mask patterns for the patterned photoresist layers, the total depth of the vias 29 can be varied such that the top surface of the sacrificial material layer 42 is physically exposed at each level of the conductive layer 46. The patterned hard mask layer 38 may then be removed. The lateral dimension (such as the diameter) of the vias 29 may be in the range of 30 nm to 300 nm, although smaller and larger lateral dimensions may also be employed. Generally, the vias 29 may extend vertically through an alternating stack of the insulating layer 32 and the sacrificial material layer 42.

[0082] According to one aspect of the present disclosure, the pattern of the patterned photoresist layer (271, 272, 273, etc.) is selected such that the area of the elongated opening 77 in the patterned hard mask layer 38 is not masked by any of the patterned photoresist layers in the patterned photoresist layer (271, 272, 273, etc.). Lateral isolation trenches 79 may be formed below each elongated opening 77 in the patterned hard mask layer 38. Generally, the pattern of the patterned photoresist layer (271, 272, 273, etc.) is selected such that the via through holes cavities 29 are formed with different depths below each row of discrete openings 27 in the patterned hard mask layer 38. In addition, the depth of the via through holes cavities 29 within each row of via through holes cavities 29 decreases with the lateral distance from the closest side boundary between the contact region 300 and the memory array region 100. In addition, the pattern of the patterned photoresist layer (271, 272, 273, etc.) may be selected such that each sacrificial material layer in the sacrificial material layer 42 is physically exposed to the corresponding via through holes cavity 29 within each row of via through holes cavities 29 located within the corresponding repeating unit RU and within the corresponding contact region 300. In one embodiment, for each row of via through holes cavities 29 located within the corresponding repeating unit RU and within the corresponding contact region 300, all of the insulating layers 32 except for the topmost insulating layer 32T may have corresponding top surfaces physically exposed to the corresponding via through holes cavity 29. Each sacrificial material layer in the sacrificial material layer 42 may be physically exposed to each lateral isolation trench 79. In one embodiment, each lateral isolation trench 79 may vertically extend through each sacrificial material layer 42. The lateral isolation trenches 79 may or may not vertically extend to the top surface of the source layer 10.

[0083] Reference Figure 7E , the patterned hard mask layer 38 may be removed, for example, by performing an isotropic etching process that selectively removes the material of the patterned hard mask layer 38 relative to the materials of the insulating layer 32 and the sacrificial material layer 42. For example, if the patterned hard mask layer 38 includes a semiconductor material, a wet etching process that selectively etches the semiconductor material relative to the materials of the insulating layer 32 and the sacrificial material layer 42 may be performed.

[0084] Generally, the lateral isolation trenches 79 and the via through holes cavities 29 may be formed in the alternating stack (32, 42). Each sacrificial material layer in the sacrificial material layer 42 is exposed to each lateral isolation trench 79. The via through holes cavities 29 within each row of via through holes cavities 29 may have different depths and may be arranged at a uniform pitch p along a first horizontal direction hd1. Each sacrificial material layer in the sacrificial material layer 42 may be physically exposed to the corresponding via through holes cavity 29 within each row of via through holes cavities 29, and the depth of the via through holes cavity 29 may decrease with the lateral distance from the closest side boundary between the memory array region 100 and the contact region 300 where the row of via through holes cavities 29 is located.

[0085] According to one aspect of the present disclosure, the pattern of the lateral isolation trenches 79 can be selected such that each patterned portion of the sacrificial material layer 42 can extend continuously into one of the contact regions 300 through a gap between a corresponding adjacent pair of support wall structures 120 that are laterally spaced apart along the second horizontal direction hd2. In one embodiment, each of the support wall structures 120 can be located between a corresponding one of the lateral isolation trenches 79 and a corresponding row of vias through holes 29. In one embodiment, each of the support wall structures 120 can include a section perpendicular to the longitudinal direction of the lateral isolation trench 79 (i.e., the first horizontal direction hd1).

[0086] In one embodiment, for each support wall structure 120, the lateral isolation trench 79 and the corresponding row of vias through holes 29 can be formed on opposite sides of the support wall structure 120. In one embodiment, each of the support wall structures 120 can intersect a corresponding pair of adjacent lateral isolation trenches 79. Each of the support wall structures 120 can be physically exposed to a corresponding subset of the lateral isolation trenches 79, such as a pair of lateral isolation trenches 79. In one embodiment, at least one of the lateral isolation trenches 79 can cut a corresponding one of the support wall structures 120. In one embodiment, at least one of the support wall structures 120 can be cut by a corresponding pair of lateral isolation trenches 79 and can be divided into a pair of dielectric material portions (i.e., support wall segments).

[0087] Reference Figures 8A to 8G, an isotropic etching process can be performed to selectively etch the material of the sacrificial material layer 42 relative to the material of the insulating layer 32 by providing an etch medium into the lateral isolation trenches 79 and the vias through holes 29. For example, if the sacrificial material layer 42 comprises silicon nitride, a wet etching process using hot phosphoric acid can be performed to remove the portion of the sacrificial material layer 42 proximal to the lateral isolation trenches 79 and the vias through holes 29 by providing phosphoric acid into the lateral isolation trenches 79 and the vias through holes 29. Each lateral recess 43 can be formed within a corresponding volume from which a portion of the corresponding sacrificial material layer 42 is etched. The duration of the isotropic etching process can be selected such that the lateral etch distance of the isotropic etching process is greater than half of the lateral pitch between adjacent pairs of lateral isolation trenches 79. In this case, the sacrificial material layer 42 can be completely removed from the memory array region 100. Additionally, the duration of the isotropic etching process can be selected such that each sacrificial material layer in the sacrificial material layer 42 includes a remaining portion in each contact region 300 after the isotropic etching process. Each remaining portion of the sacrificial material layer 42 is referred to herein as a dielectric material layer 41. The dielectric material layer 41 can be formed at each level where the sacrificial material layer 42 is provided.

[0088] Generally speaking, the lateral recesses 43 can be performed by isotropically indenting the sacrificial material layer 42 around the lateral isolation trenches 79 and the vias through holes 29. The lateral extent of the lateral recesses 43 can be different for different levels, i.e., as a function of the depth of the vias through holes 29 relative to the substrate 9. As discussed above, the depth of the vias through holes 29 can decrease with the lateral distance from the nearest lateral boundary between the memory array region 100 and the contact regions 300 (i.e., the farther from the boundary, the shallower the depth of the vias through holes 29, as Figure 8A and Figure 8E shown). In one embodiment, the depth of the vias through holes 29 can decrease with the lateral distance from the nearest support wall structure 120. In this case, for each pair of lateral recesses 43 located in the corresponding contact region 300, the overlying lateral recess 43 has a greater lateral extent than the underlying lateral recess 43. In one embodiment, the lateral extent of the lateral recesses 43 increases with the vertical distance from the top surface of the substrate 9. In one embodiment, the lateral extent of the dielectric material layer 41 decreases with the vertical distance from the top of the substrate 9.

[0089] According to one aspect of the present disclosure, an isotropic etching process etches the material of the sacrificial material layer 42 isotropically (i.e., at an etching rate independent of the etching direction). Accordingly, each dielectric material layer in the dielectric material layer 41 may include a sidewall segment equidistant from the periphery of the nearest side access via cavity in the access via cavity 29. In one embodiment, a pair of vertically adjacent boundaries between a corresponding lateral recess 43 and a corresponding dielectric material layer 41 in the same horizontal plane in the contact region 300 may be laterally offset from each other by a uniform pitch p. In Figure 8F In one embodiment shown, a subset of the boundaries between the corresponding lateral recesses 43 and the corresponding dielectric material layers 41 may include a corresponding pair of longitudinal boundary segments (43A, 43B) extending laterally along a first horizontal direction hd1 and separated along a second horizontal direction hd2, and a corresponding pair of vertically straight and horizontally concave segments 43C. Each lateral recess 43 may continuously extend along the first horizontal direction hd1 through the entire length of the memory array region 100, may laterally extend through the gap 120G between the corresponding pair of support wall structures 120, and may laterally extend along the first horizontal direction hd1 through a corresponding portion of the contact region 300, such that the lateral extent of the corresponding portion of the lateral recess 43 is less than the total lateral extent of the contact region 300 along the first horizontal direction hd1. In one embodiment, each lateral recess 43 in the lateral recesses 43 may laterally surround at least one access via cavity 29 within a corresponding row access via cavity 29. Each lateral recess 43 laterally surrounds a corresponding two-dimensional array of memory opening filling structures 58 and a corresponding subset of the support pillar structures 20.

[0090] Referring Figures 9A to 9G to, a backside blocking dielectric layer (not shown) may optionally be formed in the lateral recesses 43 by a conformal deposition process. At least one conductive material, such as at least one metal material, may be conformally deposited in the lateral recesses 43. The at least one conductive material may include, for example, a combination of a metal barrier material and a metal fill material. The metal barrier material may include, for example, TiN, TaN, WN, MoN, TiC, TaC, WC, or a combination thereof. The metal fill material may include, for example, Ti, Ta, Mo, Co, Ru, W, Cu, other transition metals, and / or their alloys or layer stacks. The at least one conductive metal material may be deposited in the lateral recesses 43 and at the peripheral portions of the lateral isolation trenches 79 and the access via cavities 29 by performing at least one conformal deposition process, such as at least one atomic layer deposition and / or at least one chemical vapor deposition. The lateral isolation trenches 79 and the access via cavities 29 may be used as conduits for delivering precursor materials for depositing the at least one conductive material. The duration of the at least one conformal deposition process may be selected such that the lateral recesses 43 are filled with the at least one conductive material, while each of the lateral isolation trenches 79 and the access via cavities 29 includes a corresponding central void that is not filled with the at least one conductive material.

[0091] An excess portion of at least one conductive material deposited in the lateral isolation trenches 79 and via via holes 29 or deposited above the topmost insulating layer 32T can be removed by performing an etch-back process, which may include an isotropic etching process and / or an anisotropic etching process. Each remaining portion of the conductive layer 46 and at least one dielectric material layer 41 that is in direct contact with the conductive layer 46 or is laterally spaced from the conductive layer 46 only by a vertical extension of a backside barrier dielectric layer (not shown) constitutes a composite layer (41, 46).

[0092] An alternating stack {32, (46, 41)} of the insulating layer 32 and the composite layer (46, 41) can be formed above the source layer 10 and above the substrate 9. Each composite layer in the composite layer (46, 41) includes at least a combination of a corresponding dielectric material layer 41 and a corresponding conductive layer 46. The lateral extent of the conductive layer 46 in the alternating stack {32, (46, 41)} increases with the vertical distance from the top surface of the substrate 9 (e.g., increases from a horizontal plane including the interface between the source layer 10 and the alternating stack {32, (46, 41)}).

[0093] Reference Figures 10A to 10D , at least one filling material can be deposited in the lateral isolation trenches 79 and via via holes 29. Via filling pillar structures (24, 26) can be formed in each via via hole in the via via holes 29, and lateral isolation trench filling structures (74, 76) can be formed in each lateral isolation trench in the lateral isolation trenches 79. Generally, the via filling pillar structures (24, 26) and the lateral isolation trench filling structures (74, 76) include dielectric surfaces that contact corresponding subsets of the layers of the respective alternating stack {32, (46, 41)} having the insulating layer 32 and the composite layer (46, 41).

[0094] In an illustrative example, an insulating fill material, such as undoped silicate glass or doped silicate glass, may be conformally deposited in the lateral isolation trenches 79 and the vias through holes cavities 29 by a conformal deposition process. An anisotropic etching process may be optionally performed. A conductive fill material and / or a heavily doped semiconductor fill material may be deposited in the remaining volume of the lateral isolation trenches 79 and the vias through holes cavities 29. The portions of the conductive fill material and / or the semiconductor fill material that cover a horizontal plane of the top surface including the topmost insulating layer 32T and any remaining portions (if any) of the insulating fill material that cover the horizontal plane of the top surface including the topmost insulating layer 32T may be removed by performing a planarization process. The planarization process may include a recess etching process and / or a chemical mechanical polishing (CMP) process. Each remaining portion of the insulating fill material, the conductive fill material, and / or the semiconductor fill material that fills the vias through holes cavities 29 constitutes a via fill pillar structure (24, 26). Each remaining portion of the insulating fill material, the conductive fill material, and / or the semiconductor fill material that fills the lateral isolation trenches 79 constitutes a lateral isolation trench fill structure (74, 76). Each via fill pillar structure (24, 26) includes an insulating via fill material portion 24 that includes the remaining portion of the insulating fill material and an optional internal via fill material portion 26 that includes the remaining portion of the conductive fill material or the heavily doped semiconductor fill material. Each lateral isolation trench fill structure (74, 76) includes an insulating trench fill material portion 74 that includes the remaining portion of the insulating fill material and may optionally include an internal trench fill material portion 76 that includes the remaining portion of the conductive fill material or the heavily doped semiconductor fill material.

[0095] Generally speaking, the lateral isolation trench fill structures (74, 76) and the via fill pillar structures (24, 26) may be formed in the lateral isolation trenches 79 and the vias through holes cavities 29, respectively. Each via fill pillar structure in the via fill pillar structures (24, 26) extends vertically through and contacts a corresponding subset of the conductive layers 46 and has a top surface that may include the top surface of the topmost insulating layer 32T in a first horizontal plane HP1 and a bottom surface at a different vertical distance from the first horizontal plane HP1.

[0096] The lateral isolation trench fill structures (74, 76) are located in respective ones of the lateral isolation trenches 79. The lateral isolation trenches 79 extend vertically through each of the composite layers (46, 41) in the composite layer stack {32, (46, 41)} and extend laterally in a first horizontal direction hd1. In one embodiment, each of the lateral isolation trench fill structures (74, 76) and the via fill pillar structures (24, 26) includes the same set of at least one fill material, and the at least one fill material includes an insulating fill material.

[0097] In one embodiment, the support wall structure 120 may contact a corresponding subset of the lateral isolation trench fill structures (74, 76) and may contact the interface between the corresponding insulating layer 32 and the conductive layer 46 in the composite layers (46, 41). The support wall structure 120 may extend vertically through each layer within the alternating stack {32, (46, 41)}.

[0098] Reference Figure 11 , a contact level dielectric layer 80 may be formed over the alternating stack {32, (46, 41)} by depositing a dielectric material such as silicon oxide. The thickness of the contact level dielectric layer 80 may be in the range of 100 nm to 600 nm, although smaller and larger thicknesses may also be employed.

[0099] A photoresist layer (not shown) may be applied over the contact level dielectric layer 80 and may be lithographically patterned to form an opening therethrough. An anisotropic etching process may be performed to transfer the pattern of the opening in the photoresist layer through the contact level dielectric layer 80 down to the top surface of a corresponding one of the drain regions in the drain region 63. A drain contact via cavity may be formed through the contact level dielectric layer 80. Subsequently, the photoresist layer may be removed, for example, by ashing.

[0100] At least one conductive material, such as a combination of a metal barrier material and a metal fill material, may be deposited in the drain contact via cavity. The excess portion of the at least one conductive material may be removed from above the horizontal plane including the top surface of the contact level dielectric layer 80 by a planarization process, which may employ a recess etching process and / or a chemical mechanical polishing process. The remaining portion of the at least one conductive material filling the drain contact via cavity constitutes the drain contact via structure 88.

[0101] A memory - side dielectric material layer 960 and a memory - side metal interconnect structure 980 may be formed over the contact - level dielectric layer 80. The memory - side dielectric material layer 960 may include at least one via - level dielectric layer, at least one additional wire - level dielectric layer, and / or at least one additional wire and via - level dielectric layer. The memory - side metal interconnect structure 980 may include a metal via structure, a metal wire structure, and / or an integrated metal wire and via structure. The metal wire structure may include a bit line 108 that electrically contacts a drain contact via structure (i.e., a drain electrode) 88 via one or more metal via structures (not shown for clarity). A metal bonding pad, herein referred to as a memory - side bonding pad 988, may be formed at the top - most level of the additional dielectric material layer 960. The memory - side bonding pad 988 may be electrically connected to the memory - side metal interconnect structure 980 and to respective nodes of a three - dimensional memory array including an alternating stack {32, (46, 41)} of an insulating layer 32 and a composite layer (46, 41) and a memory opening fill structure 58. Generally, the memory - side dielectric material layer 960 covers the alternating stack {32, (46, 41)}, and the memory - side metal interconnect structure 980 and the memory - side bonding pad 988 are embedded in the memory - side dielectric material layer 960. The above steps form a memory die 900.

[0102] Reference Figure 12 , a logic die 700 is provided. The logic die 700 includes a logic - side substrate 709, semiconductor devices 720 located on the logic - side substrate 709 and including logic - side semiconductor devices (such as field - effect transistors), a logic - side metal interconnect structure 780 embedded within a logic - side dielectric material layer 760, and a logic - side bonding pad 778. The semiconductor devices 720 may include peripheral circuits configured to control the operation of a memory array within the memory die 900. In one embodiment, the peripheral circuits may be configured to drive various electronic components within the memory array, including but not limited to the bit line 108 (i.e., the peripheral circuits may include bit - line driver circuits). In one embodiment, the peripheral circuits may be configured to control the operation of a vertical stack of memory elements within the memory array in the memory die 900.

[0103] The logic die 700 may be attached to the memory die 900, for example, by bonding the logic - side bonding pad 778 to the memory - side bonding pad 988 at a bonding interface 800. The bonding between the memory die 900 and the logic die 700 may be performed using a wafer - to - wafer bonding process, in which a two - dimensional array of memory dies 900 is bonded to a two - dimensional array of logic dies 700 either by a die - bonding process or by a die - to - die bonding process. The logic - side bonding pads 788 within each logic die 700 may be bonded to the memory - side bonding pads 988 within respective memory dies 900.

[0104] ReferenceFigure 13 , the carrier substrate 9 can be removed, for example, by grinding, polishing, cleaving, isotropic etching processes, and / or anisotropic etching processes. The distal side of the source-level insulating layer 8 can be physically exposed. As used herein, the distal side of an element in the bonding assembly refers to the side that is away from the horizontal plane including the bonding interface 800 of the bonding assembly.

[0105] Reference Figure 14A and Figure 14B , a photoresist layer (not shown) can be applied over the source-level insulating layer 8. The photoresist layer can be lithographically patterned to form discrete openings over the regions of the source layer 10 and over the portions of the conductive layer 46 that are not under any other conductive layer 46 (i.e., in the stepped portion of the contact region 300). An anisotropic etching process can be performed to selectively etch through the unmasked portions of the source-level insulating layer 8, the insulating layer 32, and the dielectric material layer 41 with respect to the materials of the conductive layer 46 and the source layer 10. At least one source contact cavity is formed on the back side (i.e., the distal side) of the source layer 10, and layer contact via cavities are formed through corresponding subsets of the source-level insulating layer 8 and the layers in the insulating layer 32 and the dielectric material layer 41. The conductive layer 46 in the stepped portion of the contact region 300 acts as an etch stop layer during the formation of the layer contact via cavities. Subsequently, the photoresist layer can be removed, for example, by ashing.

[0106] At least one conductive fill material can be deposited in the at least one source contact cavity and the layer contact via cavities. For example, the at least one conductive fill material can include a metal barrier liner material (such as TiN, TaN, WN, MoN, TiC, TaC, WC, etc.) and a metal fill material (such as W, Ti, Ta, Co, Ru, Mo, Cu, etc.). The excess portion of the at least one conductive fill material that is above the horizontal plane including the back side surface of the source-level insulating layer 8 (i.e., the distal surface from the bonding interface 800) can be removed by a planarization process. The planarization process can include a chemical mechanical polishing (CMP) process and / or a recess etching process. Each remaining portion of the at least one conductive fill material that fills the corresponding source contact cavity constitutes a source contact via structure 82. Each remaining portion of the at least one conductive fill material that fills the corresponding layer contact via cavity constitutes a layer contact via structure 86. Each conductive layer in the conductive layer 46 can be contacted by a corresponding layer contact via structure 86. Since the sidewalls of the conductive layer contact via structures 86 only contact dielectric materials (i.e., the insulating layer 32 and the dielectric material layer 41), the insulating sidewall spacers surrounding the structures 86 can be omitted.

[0107] Generally, contact via cavities (such as layer contact via cavities) can be formed from the bottom (i.e., from the side away from the bonding interface 800) of an alternating stack {32, (46, 41)} through corresponding subsets of the dielectric material layer 41 and through corresponding subsets of the insulating layer 32 to the bottom (i.e., distal) surface of a corresponding one of the conductive layers 46. The contact via cavities can be arranged as multiple rows of contact via cavities formed within corresponding repeating units RU in the corresponding contact regions 300. In one embodiment, the via fill pillar structures (24, 26) can be arranged at a uniform pitch p along a first horizontal direction hd1, and the contact via cavities can be arranged at a uniform pitch p along the first horizontal direction hd1 and can be laterally offset from a row of via fill pillar structures (24, 26) (located within a row of via vias cavities 29) along a second horizontal direction hd2. Thus, the layer contact via structure 86 can be arranged at a uniform pitch p along the first horizontal direction hd1 and can be laterally offset from the via fill pillar structures (24, 26) along the second horizontal direction hd2.

[0108] In one embodiment, the source level insulating layer 8 is embedded in the source layer 10. The layer contact via structure 86 extends vertically through the source level insulating layer 8. In one embodiment, the bottom surface (i.e., the distal surface) of the layer contact via structure 86 lies in a horizontal plane (herein referred to as the second horizontal plane HP2) including the bottom surface (i.e., the distal surface) of the source level insulating layer 8. It should be understood that depending on the orientation of the exemplary structure, the exemplary structure can be flipped upside down, and the top surface can become the bottom surface, and the bottom surface can become the top surface.

[0109] The layer contact via structure 86 extends vertically through corresponding subsets of the dielectric material layer 41 in the alternating stack {32, (46, 41)} and contacts the bottom surface (i.e., the distal surface) of a corresponding one of the conductive layers 46 in the alternating stack {32, (46, 41)}. In one embodiment, the layer contact via structure 86 is arranged at a uniform pitch p along the first horizontal direction hd1; the via fill pillar structures (24, 26) are arranged at a uniform pitch p along the first horizontal direction hd1 and are laterally offset from the contact via structure 86 along the second horizontal direction hd2; and each contact via structure in the contact via structure 86 is laterally offset from a corresponding one of the via fill pillar structures (24, 26) by a lateral offset distance lod.

[0110] Reference Figure 15, a dorsal dielectric material layer 360 may be formed on the distal surface (i.e., the dorsal surface) of the source-level insulating layer 8. A dorsal metal interconnect structure 380 is formed in the dorsal dielectric material layer 360. The dorsal metal interconnect structure 380 may be electrically connected to a corresponding one of the conductive layers in the conductive layer 46, the source layer 10, and various additional conductive via structures (not shown) that vertically extend through the insulating layer 32 and the dielectric material layer 41. For example, a first subset of the dorsal metal interconnect structure 380 may be electrically connected to a corresponding one of the layer contact via structures in the layer contact via structure 86, and a second subset of the dorsal metal interconnect structure 380 may be electrically connected to the source layer 10. The dorsal metal interconnect structure 380 may include a dorsal metal wire structure and a dorsal metal via structure. A dorsal bonding pad 388 may be formed on the dorsal (i.e., distal) side of the dorsal dielectric material layer 360.

[0111] A second logic die 750 may be bonded to the dorsal bonding pad 388. The second logic die 750 includes a second peripheral circuit 722 that is configured to control the operation of a memory array within the memory die 900. For example, the second peripheral circuit 722 may include a word line driver circuit for driving the word lines 46 via the contact via structure 86, and a source bias circuit for biasing the source layer 10. The second logic die 750 includes a second logic side bonding pad 798 that is electrically bonded to the dorsal bonding pad 389.

[0112] Figure 16A , Figure 16B , Figure 16C , Figure 16D and Figure 16E are sequential vertical cross-sectional views of steps during the fabrication of alternative exemplary structures according to an alternative embodiment of the present disclosure.

[0113] By omitting the formation of the source layer 10 in the steps shown in Figure 1 and by omitting the steps shown in Figure 4E and Figure 4F to omit the recessing of the dielectric core 62 and the formation of the drain region 63, an alternative exemplary structure of Figure 10D can be derived from the exemplary structure of Figure 16A .

[0114] Refer to Figure 16B, the source layer 10 is formed over the alternating stack {(32),(41,46)} and contacts the top of the vertical semiconductor channel region 60 located in the memory opening fill structure 58. The source layer 10 can be formed by depositing at least one conductive layer (such as a heavily doped semiconductor (e.g., polysilicon or amorphous silicon) layer and an optional metal or metal alloy capping layer) and optionally patterning the at least one conductive layer such that the source layer 10 remains at least in the memory array region 100. A capping dielectric layer 90, such as a silicon oxide or silicon nitride layer, can be formed over the source layer 10.

[0115] Reference Figure 16C , the carrier substrate 9 and the insulating layer 8 are removed as described above with respect to Figure 13 . During the removal of the carrier substrate 9 and the insulating layer 8, the temporarily processed substrate can be attached to the capping dielectric layer 90 for support.

[0116] Reference Figure 16D , the steps described above with respect to Figure 4E and Figure 4F are used to form a drain region 63 that contacts the vertical semiconductor channel 60 in the memory opening fill structure 58. The drain region 63 is formed to contact the bottom end of the vertical semiconductor channel 60 exposed after the removal of the carrier substrate 9 and the insulating layer 8. Thus, in an alternative embodiment, the source layer 10 and the drain region 63 are formed at opposite ends of the memory opening fill structure 58 relative to the positions of the source layer and the drain region in the exemplary structure of the embodiment shown in Figures 13 to 15 .

[0117] Reference Figure 16E , a drain contact via structure 88 is formed to contact the drain region 63 as described above with respect to Figure 11 . Subsequently, a memory side dielectric layer 960, a memory side interconnect structure 980 (including bit line 108), and a bond pad 988 are formed over the drain region 63 and the drain contact via structure 88 as described above with respect to Figure 11 . Then the logic die 700 is bonded to the bond pad 988 as described above with respect to Figure 12 .

[0118] In this alternative embodiment, the second logic die 750 can be omitted. In this case, the logic die includes a bit line driver circuit and a word line driver circuit that are electrically connected to the word line 46 and the bit line 108, respectively. In an alternative exemplary structure of the embodiment of Figure 16E , the conductive layer 46 having the longest lateral length is positioned further away from the bonding interface 800 with the logic die 700 than the conductive layer 46 having the shortest lateral length. Conversely, in Figure 15In the exemplary structure of the illustrated embodiment, the conductive layer 46 having the longest lateral length is positioned closer to the bonding interface 800 with the logic die 700 than the conductive layer 46 having the shortest lateral length.

[0119] In Figure 16E an alternative exemplary structure of the embodiment, the lateral extent of the conductive layers 46 in the alternating stack {32, (46, 41)} decreases with the vertical distance from a horizontal plane including the interface between the source layer 10 and the alternating stack {32, (46, 41)}. Conversely, in Figure 15 the exemplary structure of the illustrated embodiment, the lateral extent of the conductive layers 46 in the alternating stack {32, (46, 41)} increases with the vertical distance from a horizontal plane including the interface between the source layer 10 and the alternating stack {32, (46, 41)}.

[0120] Referring generally to all embodiments of the present disclosure, a device structure includes: an alternating stack {32, (46, 41)} of an insulating layer 32 and a composite layer (46, 41), the alternating stack being located above a source layer 10, wherein each composite layer in the composite layer (46, 41) includes a combination of a respective dielectric material layer 41 and a respective conductive layer 46; a memory opening 49 that extends vertically through the alternating stack {32, (46, 41)}; a memory opening fill structure 58 that is located in the memory opening 49, wherein each memory opening fill structure in the memory opening fill structure 58 includes a respective vertical stack of memory elements (e.g., portions of a memory film 50) and a respective vertical semiconductor channel 60; and a contact via structure 86 that extends vertically through respective subsets of the dielectric material layers 41 and the insulating layer 32 in the alternating stack {32, (46, 41)} and contacts a horizontal surface of a respective one of the conductive layers 46 in the alternating stack {32, (46, 41)}.

[0121] In Figure 15 the exemplary structure of the illustrated embodiment, the lateral extent of the conductive layers 46 in the alternating stack {32, (46, 41)} increases with the vertical distance from a horizontal plane including the interface between the source layer 10 and the alternating stack {32, (46, 41)}. Conversely, in Figure 16E an alternative exemplary structure of the embodiment, the lateral extent of the conductive layers 46 in the alternating stack {32, (46, 41)} decreases with the vertical distance from a horizontal plane including the interface between the source layer 10 and the alternating stack {32, (46, 41)}.

[0122] In Figure 15In an embodiment, the lateral extent of the dielectric material layer 41 decreases with the vertical distance from a horizontal plane including the interface between the source electrode layer 10 and the alternating stack {32, (46, 41)}. Conversely, in Figure 16E an alternative embodiment, the lateral extent of the dielectric material layer 41 increases with the vertical distance from a horizontal plane including the interface between the source electrode layer 10 and the alternating stack {32, (46, 41)}.

[0123] In one embodiment, the device structure includes via fill pillar structures (24, 26) that extend vertically through respective subsets of the conductive layer 46, have top surfaces in a first horizontal plane HP1, and have bottom surfaces at different vertical distances from the first horizontal plane HP1. In one embodiment, the contact via structures 86 are arranged in a uniform pitch p along a first horizontal direction hd1; the via fill pillar structures (24, 26) are arranged in a uniform pitch p along the first horizontal direction hd1 and are laterally offset from the contact via structures 86 along a second horizontal direction hd2; and each contact via structure in the contact via structures 86 is laterally offset from a respective one of the via fill pillar structures (24, 26) by a lateral offset distance lod. In one embodiment, each dielectric material layer in the dielectric material layer 41 includes sidewall segments that are equidistant from the periphery of a respective one of the via fill pillar structures (24, 26).

[0124] In one embodiment, the device structure includes: a lateral isolation trench 79 that extends vertically through each of the composite layers (46, 41) within the alternating stack {32, (46, 41)} and extends laterally along a first horizontal direction hd1; and a lateral isolation trench fill structure (74, 76) that is located in a respective one of the lateral isolation trenches 79, wherein each of the lateral isolation trench fill structures (74, 76) and the via fill pillar structures (24, 26) includes the same set of at least one fill material, and the at least one fill material includes an insulating fill material. In one embodiment, the device structure includes a support wall structure 120 that contacts a respective subset of the lateral isolation trench fill structures (74, 76) and contacts the interface between a respective insulating layer 32 and the conductive layer 46 in the composite layer (46, 41), and extends vertically through each layer within the alternating stack {32, (46, 41)}.

[0125] In one embodiment, the device structure further includes: a memory-side dielectric material layer 960 that covers the alternating stack {32, (46, 41)}; and a memory-side metal interconnect structure 980 that includes bit lines 108 and memory-side bond pads 988 embedded in the memory-side dielectric material layer 960. In one embodiment, the device structure further includes: a first logic die 700 that includes a first logic-side bond pad 788 electrically bonded to the memory-side bond pad 988.

[0126] In Figure 15 an embodiment, a back-side dielectric material layer 380 is located under the source layer 10 and embeds a back-side metal interconnect structure 380 and back-side bond pads 388. A first subset of the back-side metal interconnect structure 380 is electrically connected to a corresponding one of the contact via structures 86 in the contact via structure 86, and a second subset of the back-side metal interconnect structure 380 is electrically connected to the source layer 10. In Figure 15 an embodiment, the device structure further includes: a second logic die 750 that includes a second logic-side bond pad 798 electrically bonded to the back-side bond pad 388. The first logic die includes a bit line driver circuit 720 electrically connected to the bit lines 108; and the second logic die 750 includes a word line driver circuit 722 electrically connected to the conductive layer 46 through the contact via structure 86.

[0127] In Figure 16E an alternative embodiment, the first logic die 700 includes a bit line driver circuit 720 electrically connected to the bit lines 108 and a word line driver circuit 720 electrically connected to the conductive layer 46 through the contact via structure 86.

[0128] Various embodiments of the present disclosure provide a layer contact via structure 86 to an inverted step in the conductive layer 46. The layer contact via structure 86 extends through the alternating stack of the insulating layer 32 and the dielectric material layer 41. Thus, it is not necessary to form a large inverse-step dielectric layer (e.g., a silicon oxide layer) above the step of the stepped portion of the contact region 300. By omitting the inverse-step dielectric layer, the sinking of the device layer is reduced, the high-cost large-area planarization of the inverse-step dielectric layer is omitted, and a low-temperature reactive ion etching can be used to form support openings and memory openings through the alternating stack. In contrast, it is relatively difficult to use a low-temperature reactive ion etching to form an opening through the inverse-step dielectric layer. In addition, the bending of the back-side trench 79 results in an undesired contact between the support pillar structure 20 and the back-side trench, and the opportunity for lateral deflection and vertical sinking of the conductive layer 46 is reduced with the inverted step.

[0129] Notwithstanding the foregoing description of specific preferred embodiments, it is to be understood that the claims are not so limited. Those of ordinary skill in the art will recognize that various modifications can be made to the disclosed embodiments, and such modifications are intended to be within the scope of the claims. Compatibility is assumed between all embodiments that are not mutually alternative. The words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of" or "consisting of" replace the words "comprising" or "including", unless expressly stated otherwise. Where embodiments using a specific structure and / or configuration are shown in the present disclosure, it is to be understood that the claims can be practiced with any other compatible structure and / or configuration that is functionally equivalent, provided that such substitution is not expressly prohibited or otherwise known to be impossible to those of ordinary skill in the art. All publications, patent applications, and patents cited herein are hereby incorporated by reference in their entirety.

Claims

1. A device structure, the device structure comprising: An alternating stack of an insulating layer and a composite layer, the alternating stack being located above a source layer, wherein each composite layer in the composite layer comprises a combination of a corresponding dielectric material layer and a corresponding conductive layer; A memory opening, the memory opening extending vertically through the alternating stack; A memory opening filling structure, the memory opening filling structure being located in the memory opening, wherein each memory opening filling structure in the memory opening filling structure comprises a corresponding vertical stack of memory elements and a corresponding vertical semiconductor channel; And A contact via structure, the contact via structure extending vertically through a corresponding subset of the dielectric material layer and the insulating layer in the alternating stack and contacting a horizontal surface of a corresponding one of the conductive layers in the alternating stack.

2. The device structure according to claim 1, wherein: The lateral extent of the conductive layer in the alternating stack increases with the vertical distance from a horizontal plane including an interface between the source layer and the alternating stack; and The lateral extent of the dielectric material layer decreases with the vertical distance from the horizontal plane including the interface between the source layer and the alternating stack.

3. The device structure according to claim 1, wherein: The lateral extent of the conductive layer in the alternating stack decreases with the vertical distance from a horizontal plane including an interface between the source layer and the alternating stack; and The lateral extent of the dielectric material layer increases with the vertical distance from the horizontal plane including the interface between the source layer and the alternating stack.

4. The device structure according to claim 1, the device structure further comprising a via filling column structure, the via filling column structure extending vertically through a corresponding subset of the conductive layers, having a top surface in a first horizontal plane, and having a bottom surface at a different vertical distance from the first horizontal plane.

5. The device structure according to claim 4, wherein: The contact via structures are arranged at a uniform pitch in a first horizontal direction; The via filling column structures are arranged at the uniform pitch in the first horizontal direction and are laterally offset from the contact via structures in a second horizontal direction perpendicular to the first horizontal direction; and Each contact via structure in the contact via structures is laterally offset from a corresponding one of the via filling column structures in the via filling column structures by a lateral offset distance.

6. The device structure according to claim 4, wherein each dielectric material layer in the dielectric material layer comprises sidewall segments equidistant from the periphery of a corresponding one of the via filling column structures.

7. The device structure according to claim 5, the device structure further comprising: A lateral isolation trench, the lateral isolation trench extending vertically through each composite layer in the alternating stack and extending laterally in a first horizontal direction; And A lateral isolation trench fill structure, the lateral isolation trench fill structure being located in a respective one of the lateral isolation trenches, wherein each of the lateral isolation trench fill structure and the via fill pillar structure includes the same set of at least one fill material, and the at least one fill material includes an insulating fill material.

8. The device structure according to claim 7, the device structure further comprising a support wall structure that contacts a respective subset of the lateral isolation trench fill structures and contacts an interface between a respective insulating layer and a respective conductive layer in the composite layer, and extends vertically through each layer within the alternating stack.

9. The device structure according to claim 1, the device structure further comprising: A memory-side dielectric material layer that covers the alternating stack; And A memory-side metal interconnect structure that includes bit lines and memory-side bond pads embedded within the memory-side dielectric material layer.

10. The device structure according to claim 9, the device structure further comprising a first logic die that includes a first logic-side bond pad electrically bonded to the memory-side bond pad.

11. The device structure according to claim 10, the device structure further comprising a back-side dielectric material layer that is located beneath the source layer and embeds a back-side metal interconnect structure and back-side bond pads, wherein a first subset of the back-side metal interconnect structure is electrically connected to a respective one of the contact via structures, and a second subset of the back-side metal interconnect structure is electrically connected to the source layer.

12. The device structure according to claim 11, the device structure further comprising a second logic die that includes a second logic-side bond pad electrically bonded to the back-side bond pad.

13. The device structure according to claim 12, wherein: The first logic die includes a bit line driver circuit electrically connected to the bit lines; and The second logic die includes a word line driver circuit electrically connected to the conductive layer through the contact via structures.

14. The device structure according to claim 10, wherein the first logic die includes a bit line driver circuit electrically connected to the bit lines and a word line driver circuit electrically connected to the conductive layer through the contact via structures.

15. A method of forming a device structure, the method comprising: Forming an alternating stack of an insulating layer and a sacrificial material layer including a dielectric material above a carrier substrate; Forming a memory opening through the alternating stack; Forming a memory opening fill structure in the memory opening, wherein each memory opening fill structure in the memory opening fill structure includes a respective vertical stack of memory elements and a respective vertical semiconductor channel; Forming lateral isolation trenches and via through holes cavities in the alternating stack, wherein each sacrificial material layer in the sacrificial material layer is exposed to each of the lateral isolation trenches, and the via through holes cavities have different depths; A lateral recess is formed by isotropically recessing the sacrificial material layer around the lateral isolation trench and the via through-hole cavity, wherein the lateral extent of the lateral recess is different, and wherein the remaining portion of the sacrificial material layer comprises a dielectric material layer; A conductive layer is formed in the lateral recess; A lateral isolation trench filling structure and a via filling pillar structure are respectively formed in the lateral isolation trench and the via through-hole cavity; Contact via cavities are formed through corresponding subsets of the dielectric material layer and through corresponding subsets of the insulating layer to the horizontal surface of a corresponding one of the conductive layers; And Contact via structures in contact with the conductive layer are formed in the contact via cavities.

16. The method according to claim 15, the method further comprising forming a source layer in contact with the memory opening filling structure.

17. The method according to claim 16, wherein: The source layer is formed on or above the carrier substrate; and The method further comprises removing the carrier substrate, wherein the contact via cavities are formed after removing the carrier substrate.

18. The method according to claim 16, wherein: The alternating stack is formed above a carrier substrate; The source layer is formed on the alternating stack; and The method further comprises removing the carrier substrate after forming the source layer.

19. The method according to claim 15, wherein: The via through-hole cavities are arranged at a uniform pitch along a first horizontal direction; and The contact via cavities are arranged at the uniform pitch along the first horizontal direction and are laterally offset from the via through-hole cavities along a second horizontal direction perpendicular to the first horizontal direction.

20. The method according to claim 15, the method further comprising forming a support wall structure comprising an insulating material through the alternating stack, wherein: The lateral isolation trench and the via through-hole cavity are formed on opposite sides of the support wall structure; Each of the support wall structures in the support wall structure comprises a section perpendicular to the longitudinal direction of the lateral isolation trench; Each of the support wall structures in the support wall structure intersects a corresponding pair of the lateral isolation trenches; And The lateral recess is formed by performing an isotropic etching process that isotropically recesses the sacrificial material layer selectively with respect to the insulating material of the support wall structure.

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