Solid-state imaging device

Abstract

[Problem] To provide a solid-state imaging device in which pixel transistors can be appropriately arranged. [Solution] A solid-state imaging device according to the present disclosure includes a first substrate, a floating diffusion disposed in the first substrate, a first transistor disposed on the first substrate, a first insulating film disposed on the first substrate and the first transistor, and a second insulating film disposed on the first insulating film. A first wiring disposed in the first insulating film and electrically connected to the floating diffusion and the first transistor, a second substrate disposed on the first insulating film, a second transistor disposed on the second substrate, and a second insulating film disposed on the second substrate and the second transistor.

Description

Technical Field

[0001] The present disclosure relates to a solid-state imaging device. Background Art

[0002] Some solid-state imaging devices are formed by bonding a first substrate on which a photoelectric converter and a floating diffusion section are disposed and a second substrate to each other. The solid-state imaging device thus formed may impose restrictions on the layout of pixel transistors at each pixel.

[0003] For example, when a pixel transistor is placed on the first substrate, parasitic capacitance is likely to be generated between the wiring belonging to the pixel transistor and the second substrate. In addition, when a through-plug is placed in the second substrate, it may be difficult to place the pixel transistor on the second substrate, and the parasitic capacitance acting on the wiring may increase. Therefore, the degree of freedom in arranging the first and second substrates is likely to be reduced. Citation List Patent Documents

[0004] Patent Document 1: International Application Publication No. WO2019 / 130702 Patent Document 2: Japanese Unexamined Patent Application Publication No. 2019-84191A Summary of the Invention Technical Problem

[0005] The present disclosure provides a solid-state imaging device capable of appropriately arranging pixel transistors. Solution to Problem

[0006] A solid-state imaging device according to one aspect of the present disclosure includes: a first substrate; a floating diffusion section disposed in the first substrate; a first transistor disposed on the first substrate; a first insulating film disposed on the first substrate and the first transistor; a first wiring disposed in the first insulating film and electrically connected to the floating diffusion section and the first transistor; a second substrate disposed on the first insulating film; a second transistor disposed on the second substrate; and a second insulating film disposed on the second substrate and the second transistor. With this arrangement, for example, by placing the first transistor on the first substrate instead of the second substrate, the first transistor can be appropriately arranged.

[0007] In addition, according to the first aspect, the first transistor may be an amplifying transistor for converting the charge stored in the floating diffusion section into a voltage signal. With this arrangement, for example, the first transistor as an amplifying transistor can be appropriately arranged.

[0008] In addition, the solid-state imaging device according to the first aspect may further include: a third transistor disposed on the first substrate; a second wiring disposed in the first insulating film and electrically connected to the third transistor; a third insulating film disposed in the second substrate between the first insulating film and the second insulating film and extending through the second substrate; and one or more first plugs disposed in the third insulating film, wherein the one or more first plugs include a first plug disposed on the second wiring and not disposed on the first wiring. For example, in such an arrangement, even if there is a first plug (through-plug), the parasitic capacitance acting on the first wiring can be reduced.

[0009] In addition, according to the first aspect, the third transistor may be a transfer transistor for transferring charges generated by a photoelectric converter disposed in the first substrate. In such an arrangement, for example, a first plug (through-plug) can be disposed on the wiring of the transfer transistor.

[0010] In addition, the solid-state imaging device according to the first aspect may further include: a fourth transistor disposed on the first substrate; and a third wiring disposed in the first insulating film and electrically connected to the fourth transistor, wherein the one or more first plugs are not disposed on the third wiring. For example, in such an arrangement, even if there is a first plug (through-plug), the parasitic capacitance acting on the third wiring can be reduced.

[0011] Further, according to the first aspect, the fourth transistor may be a reset transistor for resetting the potential of the floating diffusion portion. In such an arrangement, for example, the fourth transistor serving as a reset transistor can be appropriately disposed.

[0012] In addition, according to the first aspect, at least a part of the first insulating film may be an insulating film having a dielectric constant lower than that of silicon oxide. In such an arrangement, for example, the parasitic capacitance acting on the first wiring with a lower dielectric constant can be reduced.

[0013] In addition, the solid-state imaging device according to the first aspect may further include: a fourth insulating film disposed in the second substrate between the first insulating film and the second insulating film and extending through the second substrate, wherein in a plan view, the first wiring is disposed at a position overlapping with the fourth insulating film. In such an arrangement, for example, the parasitic capacitance between the first wiring and the second substrate can be suppressed.

[0014] In addition, according to the first aspect, at least a part of the fourth insulating film may be an insulating film having a dielectric constant lower than that of silicon oxide. In such an arrangement, for example, the parasitic capacitance acting on the first wiring with a lower dielectric constant can be reduced.

[0015] In addition, according to the first aspect, in a plan view, the first wiring is disposed at a position overlapping with a hollow region extending through the second substrate. With this arrangement, for example, the parasitic capacitance acting on the first wiring line with a lower dielectric constant can be reduced.

[0016] Furthermore, according to the first aspect, the first wiring may be in contact with the hollow region. With this arrangement, for example, the volume of the hollow region can be increased.

[0017] In addition, the solid-state imaging device according to the first aspect may further include: a fourth insulating film disposed between the first insulating film and the second insulating film in the second substrate and extending through the second substrate, wherein, in a plan view, the third wiring is disposed at a position overlapping with the fourth insulating film. For example, with this arrangement, the parasitic capacitance acting on the third wiring with a lower dielectric constant can be reduced.

[0018] Moreover, the solid-state imaging device according to the first aspect may further include: a fifth insulating film disposed between the first insulating film and the second insulating film in the second substrate and extending through the second substrate, wherein the first substrate includes a first portion annularly surrounded by the fifth insulating film. With this arrangement, for example, the first portion of the second substrate can be separated from another portion of the second substrate.

[0019] In addition, according to the first aspect, in a plan view, the first wiring is disposed at a position overlapping with the first portion. With this arrangement, for example, the parasitic capacitance between the first wiring and the second substrate can be suppressed.

[0020] Furthermore, the solid-state imaging device according to the first aspect may further include: a second plug disposed on the first portion for controlling the potential of the first portion. With this arrangement, for example, the parasitic capacitance between the first wiring and the second substrate can be suppressed by controlling the potential of the first portion.

[0021] Moreover, the solid-state imaging device according to the first aspect may further include: a reset transistor for resetting the potential of the floating diffusion portion; and a conversion efficiency switching transistor disposed between the floating diffusion portion and the reset transistor for switching the conversion efficiency of a photoelectric converter disposed in the first substrate. For example, with this arrangement, the reset transistor can be electrically connected to the floating diffusion portion through the conversion efficiency switching transistor.

[0022] In addition, according to the first aspect, the reset transistor may be disposed on the first substrate. With this arrangement, for example, the reset transistor can be electrically connected to the conversion efficiency switching transistor without passing through the first plug.

[0023] In addition, according to the first aspect, the reset transistor may be disposed on the second substrate. With such an arrangement, for example, the reset transistor can be electrically connected to the conversion efficiency switching transistor through a first plug.

[0024] In addition, the solid-state imaging device according to the first aspect may further include: a circuit disposed on the second substrate and including a transistor and a capacitor. With such an arrangement, for example, the functions of the solid-state imaging device can be enhanced.

[0025] In addition, according to the first aspect, the circuit may be a sample-and-hold circuit. With such an arrangement, for example, a global shutter function can be added to the solid-state imaging device. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a block diagram showing the configuration of the solid-state imaging device according to the first embodiment. Figure 2 is a cross-sectional view showing the structure of the solid-state imaging device according to the first embodiment. Figure 3 is a circuit diagram showing the configuration of the solid-state imaging device according to the first embodiment. Figure 4 is a plan view showing the structure of the solid-state imaging device according to the first embodiment. Figure 5 is a cross-sectional view showing the structure of the solid-state imaging device according to the first modification of the first embodiment. Figure 6 is a plan view showing the structure of the solid-state imaging device according to the first modification of the first embodiment. Figure 7 is a cross-sectional view showing the structure of the solid-state imaging device according to the second modification of the first embodiment. Figure 8 is a cross-sectional view showing the structure of the solid-state imaging device according to the third modification of the first embodiment. Figure 9 is a cross-sectional view showing the structure of the solid-state imaging device according to the second embodiment. Figure 10 is a plan view showing the structure of the solid-state imaging device according to the second embodiment. Figure 11 is a cross-sectional view showing the structure of the solid-state imaging device according to the third embodiment. Figure 12 is a plan view showing the structure of the solid-state imaging device according to the third embodiment. Figure 13 is a circuit diagram showing the configuration of the solid-state imaging device according to the fourth embodiment. Figure 14This is a circuit diagram showing the configuration of a solid-state imaging device according to the fifth embodiment. Figure 15 This is a circuit diagram showing the configuration of a solid-state imaging device according to the sixth embodiment. Figure 16 This is a circuit diagram showing the configuration of a solid-state imaging device according to the seventh embodiment. Figure 17 This is a circuit diagram showing the configuration of a solid-state imaging device according to the eighth embodiment. Figure 18 This is a circuit diagram showing the configuration of a solid-state imaging device according to the ninth embodiment. Figure 19 This is a circuit diagram showing the configuration of a solid-state imaging device according to the tenth embodiment. Figure 20 This is a cross-sectional view showing the configuration of a solid-state imaging device according to the eleventh embodiment. Figure 21 This is a block diagram showing an example of the configuration of an electronic device. Figure 22 This is a block diagram showing an example of the configuration of a mobile body control system. Figure 23 This shows Figure 22 This is a plan view showing a specific example of the installation position of the imaging unit shown. Figure 24 This is a diagram showing a general configuration example of an endoscopic surgical system. Figure 25 This is a block diagram showing an example of the functional configuration of a camera and a CCU. Detailed Description of the Embodiments

[0027] Embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0028] (First Embodiment) Figure 1 This is a block diagram showing the configuration of a solid-state imaging device according to the first embodiment.

[0029] Figure 1 The solid-state imaging device shown includes a CMOS (Complementary Metal Oxide Semiconductor) type image sensor (CIS), and includes a pixel array region 2 having a plurality of pixels 1, a control circuit 3, a vertical drive circuit 4, a plurality of column signal processing circuits 5, a horizontal drive circuit 6, an output circuit 7, a plurality of vertical signal lines (VSL) 8, and a horizontal signal line (HSL) 9.

[0030] Each pixel 1 includes a photodiode serving as a photoelectric converter and a MOS transistor serving as a pixel transistor. Examples of the pixel transistor include, for example, a transfer transistor, a reset transistor, an amplification transistor, a selection transistor, and a switching transistor. These pixel transistors can be shared by some pixels 1.

[0031] In the pixel array region 2, a plurality of pixels 1 are arranged in a two-dimensional array. The pixel array region 2 includes an effective pixel region for detecting light, performing photoelectric conversion on the light, and outputting signal charges generated by the photoelectric conversion, and a black reference pixel region for outputting an optical black as a black level reference. Generally, the black reference pixel region is arranged in the peripheral portion of the effective pixel region.

[0032] Based on a vertical synchronization signal, a horizontal synchronization signal, a main clock, etc., the control circuit 3 generates various signals that provide a reference for the operations of the vertical drive circuit 4, the column signal processing circuit 5, and the horizontal drive circuit 6. Examples of the signals generated by the control circuit 3 include clock signals and control signals input to the vertical drive circuit 4, the column signal processing circuit 5, and the horizontal drive circuit 6.

[0033] The vertical drive circuit 4 includes, for example, a shift register, and performs a vertical scan of the rows of the pixels 1 in the pixel array region 2. The vertical drive circuit 4 also supplies a pixel signal based on the signal charges generated by the pixels 1 to the column signal processing circuit 5 through a vertical signal line 8.

[0034] The column signal processing circuit 5 is arranged, for example, in a manner aligned with each pixel column in the pixel array region 2, and performs signal processing on the signals output from the rows of the pixels 1 for each column based on the signals from the black reference pixel region. Examples of the signal processing include noise cancellation and signal amplification.

[0035] The horizontal drive circuit 6 includes, for example, a shift register, and supplies the pixel signals from the respective column signal processing circuits 5 to a horizontal signal line 9.

[0036] The output circuit 7 performs signal processing on the signals supplied from the respective column signal processing circuits 5 through the horizontal signal line 9, and outputs the processed signals.

[0037] Note that the pixel array region 2 according to the present embodiment may include only pixels 1 for detecting visible light or pixels 1 for detecting light other than visible light, or may include both pixels 1 for detecting visible light and pixels 1 for detecting light other than visible light. The light other than visible light can be, for example, infrared light.

[0038] Figure 2 is a cross-sectional view showing the structure of the solid-state imaging device according to the first embodiment. Figure 2Shows one pixel 1 in the solid-state imaging device according to the present embodiment.

[0039] Figure 2 The X-axis, Y-axis, and Z-axis perpendicular to each other are shown. The X-direction and Y-direction correspond to the lateral direction (horizontal direction), and the Z-direction corresponds to the upright direction (vertical direction). In addition, the +Z direction corresponds to the upward direction, and the -Z direction corresponds to the downward direction. In addition, the -Z direction may or may not be strictly consistent with the direction of gravity.

[0040] Figure 2 The solid-state imaging device shown according to the present embodiment includes a substrate 11, an element isolation insulating film 12, pixel transistors 13, pixel transistors 14, an interlayer insulating film 15, a plurality of contact plugs 16, a wiring layer 17, a substrate 21, an insulating film 22, an element isolation insulating film 23, pixel transistors 24, pixel transistors 25, an interlayer insulating film 26, a plurality of contact plugs 27, and a through-plug 31. The substrate 11, pixel transistors 13, pixel transistors 14, and interlayer insulating film 15 respectively represent examples of the first substrate, third transistor, first transistor, and first insulating film according to the present disclosure. The substrate 21, insulating film 22, pixel transistors 24 and 25, and interlayer insulating film 26 respectively represent examples of the second substrate, third insulating film, second transistor, and second insulating film according to the present disclosure. The through-plug 31 represents an example of the first plug according to the present disclosure.

[0041] For example, the substrate 11 includes a semiconductor substrate such as a Si (silicon) substrate. In Figure 2 the X-direction and Y-direction are parallel to the upper surface of the substrate 11, and the Z-direction is perpendicular to the upper surface of the substrate 11. In Figure 2 the upper surface of the substrate 11 represents the front side of the substrate 11, and the lower surface of the substrate 11 represents the back side of the substrate 11. The substrate 11 includes a well region 11a, diffusion regions 11b and 11c. Figure 2 The photodiode PD and the floating diffusion portion FD formed in the substrate 11 are also shown. The photodiode PD is formed by the PN junction between the well region 11a and the diffusion region 11b. The floating diffusion portion FD is formed by the diffusion region 11c. The well region 11a includes, for example, a P-type semiconductor region. The diffusion regions 11b and 11c include, for example, N-type semiconductor regions. The diffusion regions 11b and 11c are also referred to as active regions.

[0042] The element isolation insulating film 12 is formed in the substrate 11. The element isolation insulating film 12 includes, for example, a SiO2 (silicon oxide) film. In Figure 2 the element isolation insulating film 12 is disposed between the pixel transistor 13 and the pixel transistor 14.

[0043] The pixel transistor 13 includes a gate insulating film 13a and a gate electrode 13b formed in sequence on a substrate 11, and sidewall insulating films 13c formed on both sides of the gate electrode 13b. The gate insulating film 13a includes, for example, a SiO2 film. The gate electrode 13b includes, for example, an N-type semiconductor layer (e.g., a polysilicon layer). As Figure 2 shown, the gate electrode 13b is arranged near the diffusion regions 11b and 11c. The sidewall insulating films 13c include, for example, a SiO2 film and / or a SiN (silicon nitride) film. The pixel transistor 13 includes, for example, a transfer transistor TG.

[0044] The pixel transistor 14 includes a gate insulating film 14a and a gate electrode 14b formed in sequence on the substrate 11, and sidewall insulating films 14c formed on both sides of the gate electrode 14b. The gate insulating film 14a includes, for example, a SiO2 film. The gate electrode 14b includes, for example, an N-type semiconductor layer (e.g., a polysilicon layer). As Figure 2 shown, the gate electrode 14b is electrically connected to the diffusion region 11c (floating diffusion portion FD). The sidewall insulating films 14c include, for example, a SiO2 film and / or a SiN film. The pixel transistor 14 includes, for example, an amplifying transistor AMP (SF1).

[0045] The interlayer insulating film 15 is formed on the substrate 11, the element isolation insulating film 12, and the pixel transistors 13 and 14 so as to cover the pixel transistors 13 and 14. The interlayer insulating film 15 includes, for example, a stacked insulating film including a SiO2 film and other films.

[0046] The contact plug 16 is formed in the interlayer insulating film 15 and is arranged on the gate electrode 13b or the gate electrode 14b. Figure 2 The plugs 16a, 16b, and 16c are shown as examples of the contact plug 16. The plug 16a is arranged on the gate electrode 13b. The plug 16b is arranged on the diffusion region 11c. The plug 16c is arranged on the gate electrode 14b. The plugs 16a to 16c include, for example, an N-type semiconductor layer (e.g., a polysilicon layer).

[0047] The wiring layer 17 is formed in the interlayer insulating film 15 and is arranged on the contact plug 16. At Figure 2In [the structure], the wiring layer 17 includes wirings 17a and 17b separated from each other. The wiring 17a is disposed on the plug 16a. The wiring 17b is disposed on the plugs 16b and 16c, thereby electrically connecting the plugs 16b and 16c to each other. Accordingly, the pixel transistor 14 (gate electrode 14b) and the diffusion region 11c (floating diffusion portion FD) are electrically connected to each other through the wiring 17b. The wirings 17a and 17b include, for example, an N-type semiconductor layer (e.g., a polysilicon layer). The wirings 17a and 17b are also referred to as local wirings. In addition, the wiring 17b is also referred to as an FD wiring. The wiring 17b and the wiring 17a represent examples of a first wiring and a second wiring according to the present disclosure, respectively.

[0048] The substrate 21 is disposed on the interlayer insulating film 15. The solid-state imaging device according to the present embodiment includes substrates 11 and 21 bonded to each other. The substrate 21 is bonded to the substrate 11 through the interlayer insulating film 15. For example, the substrate 21 includes a semiconductor substrate such as an Si substrate. In Figure 2 [the structure], the X direction and the Y direction are parallel to the upper surface of the substrate 21, and the Z direction is perpendicular to the upper surface of the substrate 21. In Figure 2 [the structure], the upper surface of the substrate 21 represents the front surface of the substrate 21, and the lower surface of the substrate 21 represents the back surface of the substrate 21. The substrate 21 includes a well region 21a, diffusion regions 21b, 21c, and 21d. The well region 21a includes, for example, a P-type semiconductor region. The diffusion regions 21b to 21d include, for example, N-type semiconductor regions. The diffusion regions 21b to 21d are also referred to as active regions.

[0049] The insulating film 22 is embedded in an opening defined in the substrate 21. The opening extends through the substrate 21. Accordingly, the insulating film 22 extends through the substrate 21 and is disposed on the interlayer insulating film 15. The insulating film 22 includes, for example, an SiO2 film.

[0050] The element isolation insulating film 23 is formed in the substrate 21. The element isolation insulating film 23 includes, for example, an SiO2 film. In Figure 2 [the structure], the element isolation insulating film 23 is disposed between the pixel transistor 24 and the pixel transistor 25. In addition, in Figure 2 [the structure], in a plan view, the element isolation insulating film 23 is disposed at a position overlapping with the wiring 17b, that is, at a position overlapping with the wiring 17b in the Z direction.

[0051] The pixel transistor 24 includes a gate insulating film 24a and a gate electrode 24b formed in sequence on the substrate 21, and sidewall insulating films 24c formed on both sides of the gate electrode 24b. The gate insulating film 24a includes, for example, a SiO2 film. The gate electrode 24b includes, for example, an N-type semiconductor layer (e.g., a polysilicon layer). The sidewall insulating films 24c include, for example, a SiO2 film and / or a SiN film. The pixel transistor 24 includes, for example, a selection transistor SEL. Note that the diffusion region 21b serves as one of the source region and the drain region of the pixel transistor 24, and the diffusion region 21c serves as the other of the source region and the drain region of the pixel transistor 24.

[0052] The pixel transistor 25 includes a gate insulating film 25a and a gate electrode 25b formed in sequence on the substrate 21, and sidewall insulating films 25c formed on both sides of the gate electrode 25b (one sidewall insulating film 25c is omitted in the figure). The gate insulating film 25a includes, for example, a SiO2 film. The gate electrode 25b includes, for example, an N-type semiconductor layer (e.g., a polysilicon layer). The sidewall insulating films 25c include, for example, a SiO2 film and / or a SiN film. The pixel transistor 25 includes, for example, an amplifier transistor (post-stage amplifier transistor) SF2 different from the amplifier transistor AMP (SF1). Note that the diffusion region 21d serves as one of the source region and the drain region of the pixel transistor 25, and another diffusion region in the substrate 21 serves as the other of the source region and the drain region of the pixel transistor 25.

[0053] The interlayer insulating film 26 is formed on the substrate 21, the insulating film 22, the element isolation insulating film 23, and the pixel transistors 24 and 25 so as to cover the pixel transistors 24 and 25. The interlayer insulating film 26 includes, for example, a stacked insulating film including a SiO2 film and other films.

[0054] The contact plug 27 is formed in the interlayer insulating film 26 and is disposed on the substrate 21, the gate electrode 24b, or the gate electrode 25b. Figure 2 The plugs 27a, 27b, 27c, and 27d are shown as examples of the contact plug 27. The plug 27a is disposed on the gate electrode 24b. The plug 27b is disposed on the diffusion region 21b. The plug 27c is disposed on the diffusion region 21c. The plug 27d is disposed on the diffusion region 21d. The plugs 27a to 27d include, for example, an N-type semiconductor layer (e.g., a polysilicon layer). The solid-state imaging device according to the present embodiment further includes a plug (not shown) disposed on the gate electrode 25b as an example of the contact plug 27.

[0055] The via plug 31 is formed in the interlayer insulating film 15, the insulating film 22, and the interlayer insulating film 26 and extends through the substrate 21. The insulating film 22 is interposed between the substrate 21 and the via plug 31 and electrically isolates the substrate 21 and the via plug 31 from each other. The via plug 31 has, for example, a columnar shape extending in the Z direction, with its lower end positioned in the interlayer insulating film 15 and its upper end positioned in the interlayer insulating film 26. The via plug 31 includes, for example, a metal layer. The via plug 31 includes, for example, an Al (aluminum) layer, a W (tungsten) layer, or a Cu (copper) layer. The via plug 31 may also include a barrier metal layer. The via plug 31 is also referred to as TCS.

[0056] Each pixel 1 according to the present embodiment includes a plurality of via plugs 31 as described below. Figure 2 The plug 31a is shown as an example of the via plug 31. The plug 31a is arranged on the wiring 17a and is electrically connected to the wiring 17a. Therefore, the plug 31a is electrically connected to the pixel transistor 13 (gate electrode 13b) through the wiring 16b and the plug 16a. Note that, for example, each via plug 31 is arranged below a wiring (not shown) provided in the interlayer insulating film 26 and is electrically connected to the wiring.

[0057] The solid-state imaging device according to the present embodiment has a double-layer structure including a substrate 11 (first layer) and a substrate 21 (second layer). The regions in the substrate 11 and the interlayer insulating film 15 are referred to as the "first level", and the regions in the substrate 21 and the interlayer insulating film 26 are referred to as the "second level". For example, the photodiode PD, the floating diffusion portion FD, and the pixel transistors 13 and 14 are arranged in the first level, and the pixel transistors 24 and 25 are arranged in the second level. In addition, the via plug 31 extends through and straddles the first level and the second level. In Figure 2 which, the first level is denoted by F1 and the second level is denoted by F2.

[0058] Note that each of the pixel transistors 13, 14, 24, and 25 may include transistors other than the transfer transistor TG, the amplification transistor AMP (SF1), the selection transistor SEL, and the post-stage amplification transistor SF2. For example, any one of the pixel transistors 13, 14, 24, and 25 may include a reset transistor or a switching transistor.

[0059] As described above, the solid-state imaging device according to the present embodiment has a plug 31a (through-plug 31) extending through the substrate 21. The presence of the plug 31a disposed in the substrate 21 tends to be an obstacle, making it difficult to place the pixel transistors 23 on the substrate 21. However, according to the present embodiment, the plug 31a disposed on the wiring 16a can be placed in the substrate 21, enabling the pixel transistors 24 and 25 to be easily arranged on the substrate 21. The reason is that the wiring 16a can be arranged at an appropriate position such that the plug 31a no longer obstructs the arrangement of the pixel transistors 24 and 25 on the substrate 21.

[0060] In addition, the solid-state imaging device according to the present embodiment has a pixel transistor 14 (amplification transistor AMP) electrically connected to the floating diffusion portion FD in the first layer. If the pixel transistor 14 is arranged in the second layer, the entire length of the wiring and the plug for electrically connecting the floating diffusion portion FD and the pixel transistor 14 will increase, thereby increasing the parasitic capacitance caused by the wiring and the plug. According to the present embodiment, since the pixel transistor 14 is arranged in the first layer, the entire length of the wiring 17b and the plugs 16c and 16c for electrically connecting the floating diffusion portion FD and the pixel transistor 14 is reduced, so that the above-mentioned parasitic capacitance can be reduced. In addition, according to the present embodiment, since the entire length of the wiring 17b and the plugs 16c and 16c is reduced, the process variations in the entire length of the wiring 17b and the plugs 16c and 16c can be suppressed, and the differences in parasitic capacitance can be suppressed. Therefore, the differences in conversion efficiency between the pixels 1 can be suppressed.

[0061] The wiring 17b according to the present embodiment electrically connects the floating diffusion portion FD in the first layer to the pixel transistor 14 in the first layer. Therefore, the through-plug 31 according to the present embodiment is not arranged on the wiring 17b. Thereby, it is possible to prevent the parasitic capacitance caused by the through-plug 31 from acting on the wiring 17b. In addition, the through-plug 31 according to the present embodiment includes a plug 31a arranged on the wiring 17a. The plug 31a can electrically connect the pixel transistor 13 to the circuit in the second layer.

[0062] Note that the wiring layer 17 including the wirings 17a and 17b should preferably include a high heat-resistant material because a heat load is applied to the wiring layer 17 in the process after the formation of the wiring layer 17. Examples of the high heat-resistant material include polysilicon, tungsten (W), and copper (Cu).

[0063] Figure 3 It is a circuit diagram showing the configuration of the solid-state imaging device according to the first embodiment.

[0064] As Figure 3As shown, each pixel 1 includes a photodiode PD, a floating diffusion FD, a transfer transistor TG, a reset transistor RST, and an amplification transistor AMP in a first layer (F1). At least some of these transistors may be shared by a plurality of pixels 1.

[0065] The photodiode PD performs photoelectric conversion on incident light. The photodiode PD has an anode electrically connected to ground and a cathode electrically connected to the transfer transistor TG. The light applied to the photodiode PD is referred to as the exposure of the photodiode PD.

[0066] The transfer transistor TG transfers the charge generated by photoelectric conversion to the floating diffusion FD. One of the source and drain of the transfer transistor TG is electrically connected to the photodiode PD, and the other of the source and drain of the transfer transistor TG is electrically connected to the floating diffusion FD.

[0067] The floating diffusion FD stores the charge transferred by the transfer transistor TG. The floating diffusion FD is electrically connected to the transfer transistor TG, the reset transistor RST, and the amplification transistor AMP.

[0068] Before the photodiode PD starts exposure, the reset transistor RST releases the charge from the floating diffusion FD to reset the potential of the floating diffusion FD to the power supply voltage (VDD). One of the source and drain of the reset transistor RST is electrically connected to the power supply voltage, and the other of the source and drain of the reset transistor RST is electrically connected to the floating diffusion FD.

[0069] The amplification transistor AMP receives the charge transferred to the floating diffusion FD at its gate and outputs the charge to a switch transistor SW ( Figure 3 not shown in the figure) through a source follower. The gate of the amplification transistor AMP is electrically connected to the floating diffusion FD. One of the source and drain of the amplification transistor AMP is electrically connected to the power supply voltage, and the other of the source and drain of the amplification transistor AMP is electrically connected to the switch transistor SW. The amplification transistor AMP converts the charge stored in the floating diffusion FD into a voltage signal and outputs the voltage signal to the switch transistor SW.

[0070] Figure 4 is a plan view showing the structure of the solid-state imaging device according to the first embodiment. Figure 4 A and B of show the structure in the first layer and the structure in the second layer of the pixel 1 in the solid-state imaging device according to the present embodiment in a simplified manner.

[0071] Figure 4FIG. A shows a substrate 11, a diffusion region 11b (floating diffusion portion FD), an element isolation insulating film 12, a gate electrode 13b in a pixel transistor 13 (transfer transistor TG), a gate electrode 14b in a pixel transistor 14 (amplification transistor AMP), and a wiring 17b (FD wiring) in a wiring layer 17, etc. Figure 4 FIG. B shows a substrate 21 and an insulating film 22, etc. Note that the pixel transistors 13 and 14 are not located in the same XZ plane in Figure 4 FIG. A, but are shown in the same cross-section for ease of explanation. This also applies to other components in the solid-state imaging device according to the present embodiment.

[0072] Figure 4 FIGS. A and B also show a plurality of through-plugs 31 extending through the substrate 21. Figure 4 The ten through-plugs 31 shown in FIG. A are the same as Figure 4 the ten through-plugs 31 shown in FIG. B. One of these through-plugs 31 is a plug 31a.

[0073] (1) First modification Figure 5 is a cross-sectional view showing the structure of a solid-state imaging device according to a first modification of the first embodiment.

[0074] The solid-state imaging device according to the present modification ( Figure 5 ) includes components similar to those of the solid-state imaging device ( Figure 2 ) according to the first embodiment. However, like the insulating film 22, the element isolation insulating film 23 according to the present modification extends through the substrate 21 and is disposed on the interlayer insulating film 15. According to the present modification, the insulating film 22 and the element isolation insulating film 23 are disposed between the interlayer insulating film 15 and the interlayer insulating film 26 and are in contact with the lower surface of the interlayer insulating film 15 and the upper surface of the interlayer insulating film 26. The element isolation insulating film 23 according to the present modification represents an example of the fourth insulating film according to the present disclosure.

[0075] Similar to the wiring 17b according to the first embodiment, in a plan view, the wiring 17b according to the present modification is disposed at a position overlapping the element isolation insulating film 23. According to the first embodiment, since the element isolation insulating film 23 does not extend through the substrate 21, a parasitic capacitance is generated between the wiring 17b and the substrate 21. On the other hand, according to the present modification, since the element isolation insulating film 23 extends through the substrate 21, the parasitic capacitance between the wiring 17b and the substrate 21 can be suppressed. In other words, according to the present modification, the parasitic capacitance acting on the wiring 17b can be suppressed.

[0076] Incidentally, according to this modification example, in a plan view, a part of the wiring 17b overlaps with the element isolation insulating film 23. However, according to this modification example, in a plan view, the entire wiring 17b may overlap with the element isolation insulating film 23. The latter arrangement can further suppress the parasitic capacitance acting on the wiring 17b.

[0077] Figure 6 FIG. is a plan view showing the structure of the solid-state imaging device according to the first modification example of the first embodiment. Figure 6 A and B of FIG. schematically show the structure in the first layer and the structure in the second layer of the pixel 1 in the solid-state imaging device according to this modification example.

[0078] Figure 6 A and B of FIG. respectively correspond to Figure 4 A and B of FIG. However, Figure 6 B of FIG. shows Figure 4 the element isolation insulating film 23 that is not shown in A of FIG. for convenience. As Figure 6 shown in A and B of FIG., in a plan view, the wiring 17b according to this modification example is arranged at a position overlapping with the element isolation insulating film 23.

[0079] (2) Second modification example Figure 7 FIG. is a cross-sectional view showing the structure of the solid-state imaging device according to the second modification example of the first embodiment.

[0080] The solid-state imaging device according to this modification example ( Figure 7 ) includes components similar to those of the solid-state imaging device according to the first modification example ( Figure 5 ). However, the solid-state imaging device according to this modification example includes an interlayer insulating film 15' instead of the interlayer insulating film 15 and an element isolation insulating film 23' instead of the element isolation insulating film 23.

[0081] The interlayer insulating film 15' includes, for example, an insulating film having a dielectric constant lower than that of SiO2. Similarly, the element isolation insulating film 23' includes, for example, an insulating film having a dielectric constant lower than that of SiO2. Examples of these insulating films are SiOC (silicon oxycarbide). Note that the relative dielectric constant of SiO2 is about 4.1, while the relative dielectric constant of SiOC is about 2.9. According to this modification example, the dielectric constant of the insulating film near the wiring 17b is reduced, thereby further suppressing the parasitic capacitance acting on the wiring 17b.

[0082] Incidentally, according to this modification example, instead of using the SiOC film as the entire interlayer insulating film 15', the SiOC film can be used as a part of the interlayer insulating film 15'. Similarly, according to this modification example, instead of using the SiOC film as the entire element isolation insulating film 23', the SiOC film can be used as a part of the element isolation insulating film 23'. For example, a part of the interlayer insulating film 15' located below the wiring 17 may include a SiO2 film, and a part of the interlayer insulating film 15' located above the wiring 17 may include a SiOC film. In addition, the interlayer insulating film 15' and the element isolation insulating film 23' can be applied to the solid-state imaging device according to the first embodiment.

[0083] (3) Third Modification Example Figure 8 It is a cross-sectional view showing the structure of the solid-state imaging device according to the third modification example of the first embodiment.

[0084] The solid-state imaging device according to this modification example ( Figure 8 ) includes components similar to those of the solid-state imaging device ( Figure 5 ) according to the first modification example. However, the solid-state imaging device according to this modification example includes a hollow region 41 instead of the element isolation insulating film 23. The hollow region 41 according to this modification example is filled with air and remains in contact with the upper surface of the wiring 16b.

[0085] In a plan view, the wiring 17b according to this modification example is arranged at a position overlapping the hollow region 41. Therefore, according to this modification example, the parasitic capacitance between the wiring 17b and the substrate 21 can be suppressed. The role of the hollow region 41 is similar to that of an insulating film with a relative dielectric constant of 1. Therefore, similar to the second modification example, according to this modification example, the parasitic capacitance acting on the wiring 17b can be further suppressed.

[0086] As described above, the solid-state imaging device according to this embodiment includes a pixel transistor 14 (amplifying transistor AMP) electrically connected to the floating diffusion portion FD in the first layer. Therefore, according to this embodiment, for example, the pixel transistor 14 can be appropriately arranged to reduce the parasitic capacitance acting on the wiring 17b for the pixel transistor 14.

[0087] (Second Embodiment) Figure 9 It is a cross-sectional view showing the structure of the solid-state imaging device according to the second embodiment.

[0088] The solid-state imaging device according to this embodiment ( Figure 9 ) includes the solid-state imaging device ( Figure 5) The components are similar to those of the solid-state imaging device according to the first embodiment. However, in addition to including the components of the solid-state imaging device according to the first embodiment, the solid-state imaging device according to the present embodiment further includes a plug 16d included in the contact plug 16, a wiring 17c included in the wiring layer 17, and a pixel transistor 18. The wiring 17c and the pixel transistor 18 respectively represent examples of the third wiring and the fourth transistor according to the present disclosure.

[0089] The pixel transistor 18 includes a gate insulating film 18a and a gate electrode 18b sequentially formed on the substrate 11, and sidewall insulating films 18c formed on both sides of the gate electrode 13b. The gate insulating film 18a includes, for example, a SiO2 film. The gate electrode 18b includes, for example, an N-type semiconductor layer (e.g., a polysilicon layer). The sidewall insulating films 18c include, for example, a SiO2 film and / or a SiN (silicon nitride) film. The pixel transistor 18 includes, for example, a reset transistor RST.

[0090] The plug 16d is disposed on the gate electrode 18b. The plug 16d includes, for example, an N-type semiconductor layer (e.g., a polysilicon layer). The wiring 17c is disposed on the plug 16d. The wiring 17c includes, for example, an N-type semiconductor layer (e.g., a polysilicon layer).

[0091] The through-plug 31 according to the present embodiment is not disposed on the wiring 17c. Therefore, in this configuration, the parasitic capacitance caused by the through-plug 31 acting on the wiring 17c can be suppressed. In this way, like the pixel transistor 14 and the wiring 17b of the first embodiment, the pixel transistor 18 and the wiring 17c according to the present embodiment are arranged to be able to suppress the parasitic capacitance.

[0092] Like the wiring 17b according to the first embodiment, the wiring 17c according to the present embodiment is disposed in a position overlapping the element isolation insulating film 23 in a plan view. In addition, like the element isolation insulating film 23 in the first modification according to the first embodiment, the element isolation insulating film 23 according to the present embodiment extends through the substrate 21. Therefore, according to the present embodiment, the parasitic capacitance acting on the wiring 17c can be suppressed.

[0093] Figure 10 is a plan view showing the structure of the solid-state imaging device according to the second embodiment. Figure 10 A and B of show the structure in the first layer and the structure in the second layer of the pixel 1 in the solid-state imaging device according to the present embodiment in a simplified manner.

[0094] Figure 10 A and B of respectively correspond to Figure 4 A and B of. However, Figure 10 B of shows Figure 4 the element isolation insulating film 23 not shown for convenience in A of. As Figure 10As shown in A and B, in a plan view, the wiring 17c according to the present embodiment is arranged at a position overlapping with the element isolation insulating film 23.

[0095] Similar to the first embodiment, for example, the pixel transistor 18 can be appropriately arranged according to the present embodiment to reduce the parasitic capacitance acting on the wiring 17c for the pixel transistor 18. Note that the pixel transistor 18 may include transistors other than the reset transistor RST, such as the transfer transistor TG.

[0096] (Third Embodiment) Figure 11 is a cross-sectional view showing the structure of the solid-state imaging device according to the third embodiment.

[0097] The solid-state imaging device according to the present embodiment ( Figure 11 ) includes components similar to those of the solid-state imaging device ( Figure 5 ) according to the first modification of the first embodiment. However, the substrate 21 according to the present embodiment includes substrate portions 51 and 52 separated from each other. In addition, the contact plug 27 according to the present embodiment includes a plug 27e formed on the diffusion region 21e in the substrate portion 51 and a plug 27f formed on the diffusion region 21f in the substrate portion 52. The substrate portion 52 and the plug 27f represent examples of the first part and the second plug according to the present disclosure, respectively.

[0098] According to the present embodiment, the substrate portion 51 occupies most of the substrate 21, and the substrate portion 52 is smaller than the substrate portion 51. As will be described later, the substrate portion 52 is annularly surrounded by the insulating film 22 and the element isolation insulating film 23 ( Figure 12 B). The insulating film 22 and the element isolation insulating film 23 according to the present embodiment represent examples of the fifth insulating film according to the present disclosure. As Figure 11 schematically indicated by the arrow in, the plug 27f is used to control the potential of the substrate portion 52.

[0099] The wiring 17c according to the present embodiment is arranged at a position overlapping with the substrate portion 52 in a plan view. According to the present embodiment, the parasitic capacitance acting on the wiring 17c can be controlled by controlling the potential of the substrate portion 52 using the plug 27f. For example, the parasitic capacitance acting on the wiring 17c can be reduced by controlling the desired potential applied to the substrate portion 52 using the plug 27f.

[0100] Figure 12 is a plan view showing the structure of the solid-state imaging device according to the third embodiment. Figure 12 A and B of show the structure in the first layer and the structure in the second layer of the pixel 1 in the solid-state imaging device according to the present embodiment in a simplified manner.

[0101] Figure 12 A and B of Figure 4 correspond to A and B of Figure 12 However, B of Figure 4 shows the element isolation insulating film 23 that is not shown in A of Figure 12 for convenience. As shown in B of Figure 12 the substrate portion 52 is surrounded by the insulating film 22 and the element isolation insulating film 23 in a ring shape. Further, as shown in A and B of

[0102] Similar to the first and second embodiments, according to this embodiment, the pixel transistors 14 can be appropriately arranged, for example, to reduce the parasitic capacitance acting on the wiring 17b for the pixel transistors 14.

[0103] (Fourth Embodiment) Figure 13 is a circuit diagram showing the configuration of a solid-state imaging device according to the fourth embodiment. Figure 13 A and B of

[0104] According to Figure 13 the example shown in A of

[0105] each pixel 1 includes a photodiode PD, a floating diffusion portion FD, a transfer transistor TG, a reset transistor RST, an amplification transistor AMP, and a conversion efficiency switching transistor FDG in the first layer.

[0106] According to Figure 13 the example shown in B of Figure 13 each pixel 1 also includes a photodiode PD, a floating diffusion portion FD, a transfer transistor TG, a reset transistor RST, an amplification transistor AMP, and a conversion efficiency switching transistor FDG. However,

[0107] the reset transistor RST shown in B of

[0108] (Fifth Embodiment) Figure 14 This is a circuit diagram showing the configuration of the solid-state imaging device according to the fifth embodiment.

[0109] Similar to the fourth embodiment, each pixel 1 according to this embodiment includes a photodiode PD, a floating diffusion section FD, a transfer transistor TG, a reset transistor RST, an amplification transistor SF1 (AMP), and a conversion efficiency switching transistor FDG in the first layer. Each pixel 1 according to this embodiment further includes a switching transistor SW in the first layer. In addition, each pixel 1 according to this embodiment includes a current source transistor PC, a post-stage current source transistor VB, capacitors C1 and C2, switching transistors S1 and S2, and a VREG voltage transistor RB in the second layer, which constitute a sample-and-hold circuit 61. Each pixel 1 according to this embodiment further includes a post-stage amplification transistor SF2 and a selection transistor SEL. The solid-state imaging device according to this embodiment serves as a voltage-domain CIS (VD-GS) to perform a global shutter function by simultaneously converting the charge generated by the photodiode PD into a voltage at all pixels 1 and holding the voltage until the voltage reading is completed.

[0110] The switching transistor SW can electrically connect the amplification transistor SF1 to the capacitors C1 and C2 to each other. When the switching transistor SW is turned on, the amplification transistor SF1 is electrically connected to the capacitors C1 and C2 to each other. When the switching transistor SW is turned off, the amplification transistor SF1 is electrically isolated from the capacitors C1 and C2 to each other. One of the source and drain of the switching transistor SW is electrically connected to the amplification transistor SF1, and the other of the source and drain of the switching transistor SW is electrically connected to the current source transistor PC and the capacitors C1 and C2.

[0111] The capacitors C1 and C2 are electrically connected to the node V1 between the switching transistor SW and the current source transistor PC. One electrode of the capacitor C1 is electrically connected to the node V1, and the other electrode is electrically connected to the switching transistor S1. One electrode of the capacitor C2 is electrically connected to the node V1, and the other electrode is electrically connected to the switching transistor S2. The capacitors C1 and C2 are connected in parallel.

[0112] The switching transistor S1 can electrically connect the capacitor C1 to the post-stage amplification transistor SF2 to each other. When the switching transistor S1 is turned on, the capacitor C1 is electrically connected to the post-stage amplification transistor SF2 to each other. When the switching transistor S1 is turned off, the capacitor C1 is electrically isolated from the post-stage amplification transistor SF2 to each other. One of the source and drain of the switching transistor S1 is electrically connected to the capacitor C1, and the other of the source and drain of the switching transistor S1 is electrically connected to the VREG voltage transistor RB and the post-stage amplification transistor SF2.

[0113] The switching transistor S2 can electrically connect the capacitor C2 and the subsequent-stage amplification transistor SF2 to each other. When the switching transistor S2 is turned on, the capacitor C2 and the subsequent-stage amplification transistor SF2 are electrically connected to each other. When the switching transistor S2 is turned off, the capacitor C2 and the subsequent-stage amplification transistor SF2 are electrically isolated from each other. One of the source and drain of the switching transistor S2 is electrically connected to the capacitor C2, and the other of the source and drain of the switching transistor S2 is electrically connected to the VREG voltage transistor RB and the subsequent-stage amplification transistor SF2.

[0114] The VREG voltage transistor RB is electrically connected to the node V2 between the switching transistors S1, S2 and the subsequent-stage amplification transistor SF2. When turned on, the VREG voltage transistor RB applies the VREG voltage to the node V2.

[0115] The subsequent-stage amplification transistor SF2 receives the charges output from the capacitors C1 and C2 at its gate, and outputs these charges to the vertical signal line 8 (VSL) through a source follower. The gate of the subsequent-stage amplification transistor SF2 is electrically connected to the capacitors C1, C2 and the VREG voltage transistor RB. One of the source and drain of the subsequent-stage amplification transistor SF2 is electrically connected to the power supply voltage, and the other of the source and drain of the subsequent-stage amplification transistor SF2 is electrically connected to the selection transistor SEL.

[0116] The selection transistor SEL can keep the subsequent-stage amplification transistor SF2 and the vertical signal line 8 electrically connected. When the selection transistor SEL is turned on, the subsequent-stage amplification transistor SF2 and the vertical signal line 8 are electrically connected to each other. When the selection transistor SEL is turned off, the subsequent-stage amplification transistor SF2 and the vertical signal line 8 are electrically isolated from each other. One of the source and drain of the selection transistor SEL is electrically connected to the subsequent-stage amplification transistor SF2, and the other of the source and drain of the selection transistor SEL is electrically connected to the vertical signal line 8.

[0117] The current source transistor PC and the subsequent-stage current source transistor VB act as current sources. One of the source and drain of the current source transistor PC is electrically connected to the switching transistor SW, and the other of the source and drain of the current source transistor PC is electrically connected to the subsequent-stage current source transistor VB. One of the source and drain of the subsequent-stage current source transistor VB is electrically connected to the current source transistor PC.

[0118] According to this embodiment, the sample-and-hold circuit 61 provided in the second layer can perform, for example, a global shutter function.

[0119] (Sixth to Tenth Embodiments) Figure 15 is a circuit diagram showing the configuration of a solid-state imaging device according to the sixth embodiment.

[0120] Figure 15The pixel 1 shown has the same structure as Figure 14 the pixel 1 shown, but is different in that it does not include the conversion efficiency switching transistor FDG and the switching transistor SW. Therefore, this structure can effectively reduce the number of transistors in each pixel 1.

[0121] Figure 16 is a circuit diagram showing the structure of a solid-state imaging device according to the seventh embodiment.

[0122] Figure 16 The pixel 1 shown has the same structure as Figure 15 the pixel 1 shown, but is different in that it includes another post-stage amplification transistor SF2 and another selection transistor SEL, and does not include the post-stage current source transistors VB and the VREG voltage transistor RB. Figure 16 The pixel 1 shown includes, in the post-stage after the amplification transistor AMP, a circuit portion including the switching transistor S1, the capacitor C1, the post-stage amplification transistor SF2, and the selection transistor SEL, and a circuit portion including the switching transistor S2, the capacitor C2, the post-stage amplification transistor SF2, and the selection transistor SEL.

[0123] Figure 17 is a circuit diagram showing the structure of a solid-state imaging device according to the eighth embodiment.

[0124] Figure 17 The pixel 1 shown has the same structure as Figure 15 the pixel 1 shown, but is different in that it does not include the post-stage current source transistors VB and the VREG voltage transistor RB. Further, in Figure 17 the switching transistor S1 is arranged in the post-stage after the amplification transistor AMP, and the capacitor C2 is arranged between the amplification transistor AMP and the post-stage amplification transistor SF2. Further, in Figure 17 the capacitor C1 is electrically connected to the node between the switching transistor S1 and the capacitor C2, and the switching transistor S2 is electrically connected to the node between the capacitor C2 and the post-stage amplification transistor SF2.

[0125] Figure 18 is a circuit diagram showing the structure of a solid-state imaging device according to the ninth embodiment.

[0126] Figure 18 The pixel shown has the same structure as Figure 15 the pixel 1 shown, but is different in that it includes the switching transistor SH and does not include the VREG voltage transistor RB. The switching transistor SH is arranged in the post-stage after the amplification transistor AMP. Further, in Figure 18In [the figure], switching transistors S1 and S2 are electrically connected to corresponding nodes (connected in parallel) between switching transistor SH and subsequent-stage amplifying transistor SF2. Capacitors C1 and C2 are respectively arranged in the subsequent stage after switching transistors S1 and S2.

[0127] Figure 19 is a circuit diagram showing the configuration of a solid-state imaging device according to the tenth embodiment.

[0128] Figure 19 The pixel 1 shown has a structure similar to that of Figure 15 the pixel 1 shown, except that it includes capacitors Ca and Cb and switching transistors Sa and Sb, and does not include capacitors C1 and C2, switching transistor S2, and VREG voltage transistor RB. Switching transistor S1 is arranged between amplifying transistor AMP and subsequent-stage amplifying transistor SF2. Capacitor Ca and switching transistor Sa are arranged in series with each other in the subsequent stage after the node between switching transistor S1 and subsequent-stage amplifying transistor SF2. Similarly, capacitor Cb and switching transistor Sb are arranged in series with each other in the subsequent stage after the node between switching transistor S1 and subsequent-stage amplifying transistor SF2.

[0129] According to the sixth to tenth embodiments, pixel 1 can be provided in a solid-state imaging device in various configurations. The configurations according to the sixth to tenth embodiments can be applied to pixel 1 according to any one of the first to fourth embodiments.

[0130] (Eleventh Embodiment) Figure 20 is a cross-sectional view showing the structure of a solid-state imaging device according to the eleventh embodiment. As with Figure 2 and other drawings, Figure 20 shows one pixel 1 in the solid-state imaging device according to the present embodiment.

[0131] In addition to Figure 2 the components shown, the solid-state imaging device according to the present embodiment further includes an on-chip filter 81, an on-chip lens 82, a substrate 71, a transistor 62, and an interlayer insulating film 73.

[0132] In Figure 20 the upper surface of substrate 11 represents the front side of substrate 11, and the lower surface of substrate 11 represents the back side of substrate 11. The solid-state imaging device according to the present embodiment is a back-illuminated type, in which the lower surface (back side) of substrate 11 serves as the light incident surface (light detection surface).

[0133] In Figure 20Among them, pixel transistors 13 and 14 are formed on the upper surface of substrate 11, while on-chip filter 81 and on-chip lens 82 are formed on the lower surface of substrate 11. Specifically, on-chip filter 81 and on-chip lens 82 are sequentially formed below substrate 11.

[0134] On-chip filter 81 is used to transmit light of a predetermined wavelength and is formed on the upper surface of substrate 11 in each pixel 1. For example, red (R), green (G), and blue (B) on-chip filters 81 are arranged below the corresponding photodiodes PD of red, green, and blue pixels 1. In addition, an infrared light on-chip filter 81 can be arranged below the photodiode PD of the infrared light pixel 1.

[0135] On-chip lens 82 is used to focus the incident light and is formed below on-chip filter 81 in each pixel 1. According to this embodiment, the light incident on on-chip lens 82 is focused, passes through on-chip filter 81, and is applied to photodiode PD. Photodiode PD converts the light into charge through photoelectric conversion, thereby generating signal charge.

[0136] Substrate 71 is arranged above substrate 21. Substrate 71 includes, for example, a semiconductor substrate such as an Si substrate. In Figure 20 , the X direction and the Y direction are parallel to the lower surface of substrate 71, and the Z direction is perpendicular to the lower surface of substrate 71.

[0137] Transistor 72 includes a gate insulating film 62a and a gate electrode 62b sequentially formed below substrate 71, and sidewall insulating films 62c formed on both sides of gate electrode 62b. Gate insulating film 62a includes, for example, an SiO2 film. Gate electrode 62b includes, for example, an N-type semiconductor layer (e.g., a polysilicon layer). Sidewall insulating film 62c includes, for example, an SiO2 film and / or an SiN film. Transistor 72 constitutes, for example, the logic circuit of the solid-state imaging device according to this embodiment.

[0138] Interlayer insulating film 73 is formed below substrate 71 and transistor 72 so as to cover transistor 72. Interlayer insulating film 73 includes, for example, a stacked insulating film including an SiO2 film and other insulating films. According to this embodiment, interlayer insulating film 73 is formed on interlayer insulating film 26, and its lower surface is in contact with the upper surface of interlayer insulating film 24. Substrate 71 and substrate 21 are bonded together with interlayer insulating films 73 and 26 interposed therebetween.

[0139] As described above, the solid-state imaging device according to the present embodiment has a three-layer structure including a substrate 11 (first layer), a substrate 21 (second layer), and a substrate 71 (third layer). Given that the regions in the substrate 11 and the interlayer insulating film 14 are referred to as the "first level", and the regions in the substrate 21 and the interlayer insulating film 24 are referred to as the "second level", and the regions in the substrate 71 and the interlayer insulating film 73 are referred to as the "third level". For example, the photodiode PD, the floating diffusion section FD, and the pixel transistors 13 and 14 are arranged in the first level, the pixel transistors 24 and 25 are arranged in the second level, and the transistor 72 is arranged in the third level. Further, the via plug 31 extends through and straddles the first level and the second level. In Figure 20 it, the first level, the second level, and the third level are F1, F2, and F3, respectively.

[0140] According to the present embodiment, for example, by applying the three-layer structure to the solid-state imaging device, the number of transistors arranged in the first level and the second level can be reduced. Therefore, the planar area of each pixel 1 can be reduced, and the planar size (area) of the solid-state imaging device can be reduced.

[0141] Note that the structures of the first level, the second level, and the third level according to the present embodiment may be different from Figure 20 the structure shown. For example, Figure 20 some components in the first level shown may be relocated to the second level or the third level. This also applies to Figure 20 the components in the second level shown and Figure 20 the components in the third level shown.

[0142] (Application) Figure 21 is a block diagram showing a configuration example of an electronic device. Figure 21 The electronic device shown is a camera 100.

[0143] The camera 100 includes: an optical system 101 including a lens group; an imaging device 102 including a solid-state imaging device according to any one of the first to fourteenth embodiments; a digital signal processor (DSP) circuit 103 as a camera signal processing circuit; a frame memory 104; a display unit 105; a recording unit 106; an operation unit 107; and a power supply unit 108. Further, the DSP circuit 103, the frame memory 104, the display unit 105, the recording unit 106, the operation unit 107, and the power supply unit 108 are interconnected via a bus 109.

[0144] The optical system 101 acquires incident light (image light) from a subject and focuses the incident light onto the imaging surface of the imaging device 102. The imaging device 102 converts the amount of incident light focused onto the imaging surface by the optical system 101 into an electrical signal for each pixel and outputs the electrical signal as a pixel signal.

[0145] The DSP circuit 103 performs signal processing on the pixel signals output from the imaging device 102. The frame memory 104 includes a memory for storing a moving image or a still image captured by the imaging device 102 for one frame.

[0146] The display unit 105 includes, for example, a panel-type display device such as a liquid crystal panel or an organic EL panel, and displays a moving image or a still image captured by the imaging device 102. The recording unit 106 records, for example, a moving image or a still image captured by the imaging device 102 onto a recording medium such as a hard disk or a semiconductor memory.

[0147] When operated by a user, the operation unit 107 issues operation instructions related to various functions of the camera 100. The power supply unit 108 appropriately supplies various power supplies to the DSP circuit 103, the frame memory 104, the display unit 105, the recording unit 106, and the operation unit 107 as the operation power supplies for these supply targets.

[0148] By using any one of the solid-state imaging devices according to the first to fourteenth embodiments as the imaging device 102, it is expected that the imaging device 102 can acquire a satisfactory image.

[0149] The solid-state imaging device can be applied to various other products. For example, the solid-state imaging device can be installed in various moving bodies such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0150] Figure 22 is a block diagram showing a configuration example of a moving body control system. Figure 22 The shown moving body control system includes a vehicle control system 200.

[0151] The vehicle control system 200 includes a plurality of electronic control units interconnected via a communication network 201. According to Figure 22 the shown example, the vehicle control system 200 includes a drive system control unit 210, a body system control unit 220, an outside vehicle information detection unit 230, an inside vehicle information detection unit 240, and an integrated control unit 250. Figure 22 A microcomputer 251, a sound / image output unit 252, and a vehicle-mounted network I / F (interface) 253 are also shown as components of the integrated control unit 250.

[0152] The drive system control unit 210 controls the operation of devices related to the vehicle drive system. For example, the drive system control unit 210 serves as a control device for controlling a driving force generation device (e.g., an internal combustion engine or a drive motor) for generating a driving force for the vehicle, a driving force transmission mechanism for transmitting the driving force to the wheels, a steering mechanism for adjusting the vehicle steering angle, and a braking device for generating a braking force for the vehicle.

[0153] The body system control unit 220 controls the operation of various devices installed in the vehicle body according to various programs. For example, the body system control unit 220 serves as a controller for an intelligent key system, a keyless entry system, an electric window device, and various vehicle lights (e.g., headlights, taillights, brake lights, turn signals, and fog lights). In this case, the body system control unit 220 can be provided with radio waves transmitted from a portable device that replaces a key and signals from various switches. In response to such radio waves or signals, the body system control unit 220 controls, for example, a door lock device, an electric window device, and vehicle lights.

[0154] The outboard information detection unit 230 detects information related to the outside of the vehicle including the vehicle control system 200. For example, an imaging unit 231 is connected to the outboard information detection unit 230. The outboard information detection unit 230 controls the imaging unit 231 to capture an image of the outside of the vehicle and receives the captured image from the imaging unit 231. The outboard information detection unit 230 can perform an object detection process for detecting objects such as people, vehicles, obstacles, signs, and characters on the road, or perform a distance detection process based on the received image.

[0155] The imaging unit 231 includes an optical sensor that detects light and outputs an electrical signal representing the detected light amount. The imaging unit 231 can output the electrical signal as an image or output the electrical signal as measurement distance information. The light detected by the imaging unit 231 can be visible light or invisible light such as infrared radiation. The imaging unit 231 includes a solid-state imaging device according to any one of the first to fourteenth embodiments.

[0156] The inboard information detection unit 240 detects information related to the inside of the vehicle including the vehicle control system 200. For example, a driver state detection unit 241 for detecting the driver's state is connected to the inboard information detection unit 240. The driver state detection unit 241 includes, for example, a camera for capturing an image of the driver. The inboard information detection unit 240 can calculate the driver's fatigue level or the driver's attention level, or can determine whether the driver is dozing off based on the detection information input from the driver state detection unit 241. For example, the camera can include a solid-state imaging device according to any one of the first to fourteenth embodiments or Figure 21 the camera 100 shown.

[0157] The microcomputer 251 can calculate the control target values of the driving force generating device, the steering mechanism, or the braking device based on the vehicle external or internal information acquired by the vehicle external information detection unit 230 or the vehicle internal information detection unit 240, and output a control command to the drive system control unit 210. For example, the microcomputer 251 performs cooperative control to implement the functions of an Advanced Driver Assistance System (ADAS) including vehicle collision avoidance, impact mitigation, cruise control driving based on the inter-vehicle distance, constant speed driving, collision warning, and lane departure warning.

[0158] In addition, the microcomputer 251 can control the driving force generating device, the steering mechanism, or the braking device based on the information around the vehicle acquired by the vehicle external information detection unit 230 or the vehicle internal information detection unit 240, thereby performing cooperative control for the purpose of autonomous driving to achieve autonomous driving without driver intervention.

[0159] In addition, the microcomputer 251 can also output a control command to the body system control unit 220 based on the vehicle external information acquired by the vehicle external information detection unit 230. For example, the microcomputer 251 can control the headlights according to the positions of the vehicle ahead or the oncoming vehicle detected by the vehicle external information detection unit 230 to perform cooperative control such as taking an anti-glare action to switch from high beam to low beam.

[0160] The sound / image output unit 252 transmits an output signal representing at least one of sound and image to an output device capable of notifying visual or auditory information to vehicle occupants or the outside of the vehicle. According to Figure 22 the example shown, the output device includes an audio speaker 261, a display unit 262, and an instrument panel 263. The display unit 262 can include, for example, an in-vehicle display or a head-up display.

[0161] Figure 23 is a plan view showing Figure 22 a specific example of the set position of the imaging unit 231 shown.

[0162] Figure 23 The vehicle 300 shown includes imaging units 301, 302, 303, 304, and 305 as the imaging unit 231. The imaging units 301, 302, 303, 304, and 305 are provided at various positions on the front head of the vehicle, side mirrors, rear bumper or rear door, and the upper part of the front windshield inside the cab, for example.

[0163] The imaging unit 301 located at the front of the vehicle mainly acquires images of the front area of the vehicle 300. The imaging unit 302 located at the left rearview mirror and the imaging unit 303 located at the right rearview mirror mainly acquire images of the side areas of the vehicle 300. The imaging unit 304 located at the rear bumper or the rear door mainly acquires images of the rear area of the vehicle 300. The imaging unit 305 located at the upper part of the front windshield inside the cab mainly acquires images of the front area of the vehicle 300. The imaging unit 305 is used, for example, to detect the vehicle in front, pedestrians, obstacles, traffic signals, traffic signs, and lanes, etc.

[0164] Figure 23 An example of the imaging ranges of the imaging units 301, 302, 303, and 304 (hereinafter referred to as "imaging units 301 to 304") is shown. The imaging range 311 refers to the imaging range of the imaging unit 301 located at the front of the vehicle. The imaging range 312 refers to the imaging range of the imaging unit 302 located at the left rearview mirror. The imaging range 313 refers to the imaging range of the imaging unit 303 located at the right rearview mirror. The imaging range 314 refers to the imaging range of the imaging unit 304 located at the rear bumper or the rear door. The image data acquired by the imaging units 301 to 304 are superimposed together to obtain a bird's-eye view of the vehicle 300, that is, the view when looking at the vehicle 300 from a high place downward. Hereinafter, the imaging ranges 311, 312, 313, and 314 will be referred to as "imaging ranges 311 to 314".

[0165] At least one of the imaging units 301 to 304 may have the function of acquiring distance information. For example, at least one of the imaging units 301 to 304 may include a stereo camera having a plurality of imaging devices or an imaging device having pixels for detecting phase differences.

[0166] For example, the microcomputer 251 ( Figure 22 ) calculates the distance to the three-dimensional object within the imaging ranges 311 to 314 and the change in distance over time based on the distance information obtained from the imaging units 301 to 304. Based on the calculation results, the microcomputer 251 can extract the nearest three-dimensional object traveling in the same direction as the vehicle 300 at a predetermined speed (e.g., 0 km / h or more) on the driving path of the vehicle 300 as the vehicle in front. In addition, the microcomputer 251 can preset a safe following distance to the vehicle in front and can perform automatic braking control processing (including cruise control stop processing) and automatic acceleration control processing (including cruise control start processing), etc. Thus, according to this example, cooperative control for purposes such as autonomous driving can be performed to achieve autonomous driving without driver intervention.

[0167] For example, the microcomputer 251 can classify a three-dimensional object such as a motorcycle, a passenger vehicle, a large vehicle, a pedestrian, a utility pole, or others based on the distance information obtained from the imaging units 301 to 304, extract three-dimensional object data, and automatically avoid obstacles using the extracted three-dimensional object data. For example, the microcomputer 251 identifies obstacles around the vehicle 300 and classifies them into obstacles visible to the driver of the vehicle 300 and obstacles difficult for the driver to see. Then, the microcomputer 251 determines a collision risk indicating the degree of risk of collision with each obstacle, and if the collision risk is equal to or higher than a preset value (indicating that the vehicle 300 is in a situation where a collision is possible), outputs a warning to the driver via the audio speaker 261 and the display unit 262, and controls the drive system control unit 210 to force the vehicle 300 to decelerate or steer the vehicle 300 to avoid a possible collision, so that the microcomputer 251 can perform collision avoidance driving assistance.

[0168] At least one of the imaging units 301 to 304 may include an infrared camera for detecting infrared radiation. For example, the microcomputer 251 can identify a pedestrian by determining whether there is a pedestrian in the images captured by the imaging units 301 to 304. The microcomputer 251 can identify a pedestrian by performing a process of extracting feature points from the images captured by the imaging units 301 to 304, which are infrared cameras, and performing a pattern matching process on a series of feature points representing the object contour to determine whether the object is a pedestrian. If the microcomputer 251 determines that there is a pedestrian in the images captured by the imaging units 301 to 304 and thus identifies the pedestrian, the sound / image output unit 252 controls the display unit 262 to display a square contour line above the identified pedestrian for emphasis. In addition, the sound / image output unit 252 can control the display unit 262 to display an icon representing the pedestrian or the like at a desired position.

[0169] Figure 24 is a view showing a general construction example of an endoscopic surgical system to which the technology (this technology) according to the present disclosure can be applied.

[0170] Figure 24 shows the way in which a surgical operator (doctor) 531 is performing surgery on a patient 532 on a hospital bed 533 using an endoscopic surgical system 400. As Figure 24 shown, the endoscopic surgical system 400 includes an endoscope 500, other surgical tools 510 including a pneumoperitoneum tube 511 and an energy treatment tool 512, a support arm device 520 for supporting the endoscope 500, and a cart 600 for accommodating various devices for endoscopic surgery.

[0171] The endoscope 500 includes a barrel 501 that is inserted into the body cavity of a patient 532 from its distal end by a predetermined length, and a camera 502 connected to the proximal end of the barrel 501. Although the endoscope 500 is shown as a rigid endoscope having a rigid barrel as the barrel 501, the endoscope 500 can be configured as a flexible endoscope having a flexible barrel.

[0172] The distal end of the barrel 501 has an opening internally fitted with an objective lens. A light source device 603 is connected to the endoscope 500. The light generated by the light source device 603 is introduced into the distal end of the barrel 501 through an optical fiber extending in the barrel 501, and irradiates an observation target in the body cavity of the patient 532 through the objective lens. Note that the endoscope 500 can include a forward-view endoscope, a forward-view oblique endoscope, or a side-view endoscope.

[0173] The camera 502 internally houses an optical system and an imaging element. The reflected light (observation light) from the observation target is focused on the imaging element through the optical system. The imaging element photoelectrically converts the observation light into an electrical signal representing the observation light, that is, an image signal representing an observation image. The image signal is transmitted to a camera control unit (CCU) 601 as RAW data.

[0174] The CCU 601 includes, for example, a CPU (central processing unit) or a GPU (graphics processing unit), and overall controls the operations of the endoscope 500 and the display device 602. In addition, the CCU 601 receives the image signal from the camera 502, and performs various image processing processes on the image signal, such as an image development process (pixelization process), to display an image based on the image signal.

[0175] The display device 602 is controlled by the CCU 601 to display an image based on the image signal that has been subjected to the image processing process by the CCU 601.

[0176] The light source device 603 includes, for example, a light source such as an LED (light-emitting diode), and provides illumination light for photographing the surgical site to the endoscope 500.

[0177] The input device 604 represents an input interface for the endoscope surgical system 11000. A user can input various information and instructions to the endoscope surgical system 400 through the input device 604. For example, the user inputs an instruction for changing imaging conditions (type of illumination light, magnification, focal length, etc.) when the endoscope 500 captures an image.

[0178] The treatment tool control device 605 controls the energization of the energy treatment tool 512 for cauterization, tissue incision, vessel occlusion, etc. The pneumoperitoneum device 606 sends gas into the body cavity of the patient 532 through the pneumoperitoneum tube 511 to expand the body cavity, so as to ensure the field of view of the endoscope 500 and the space for the surgical operator to operate in the body cavity. The recorder 607 refers to a device for recording various information related to the surgery. The printer 608 refers to a device for printing various information related to the surgery in various formats (for example, including text, images or graphics).

[0179] Note that the light source device 603 that provides illumination light for photographing the image of the surgical site to the endoscope 500 may include, for example, an LED, a laser light source, or a white light source including a combination of an LED and a laser light source. In the case where the white light source includes a combination of RGB laser light sources, since the output intensity and output timing of each color (each wavelength) can be precisely controlled, the light source device 603 can adjust the white balance of the photographed image. In addition, in this case, it is also possible to irradiate the observation target with each laser beam from the RGB laser light sources in a time-division multiplexing manner and control the energization of the imaging element of the camera 502 in a manner synchronized with the illumination timing to photograph RGB images in a time-division multiplexing manner. According to this process, the endoscope 500 can obtain a color image without setting a color filter on the imaging element.

[0180] In addition, it is also possible to control the energization of the light source device 603 so that the intensity of the light output therefrom changes over a specified period of time. The energization of the imaging element of the camera 502 can be controlled in a manner synchronized with the timing of the change in the light intensity, so as to obtain images in a time-division multiplexing manner and combine the obtained images into a high-dynamic range image without the so-called crushed shadows and clipped whites.

[0181] In addition, the light source device 603 may be arranged to be capable of providing light within a predetermined wavelength band for special light observation. For example, special light observation includes a narrow-band imaging process that utilizes the wavelength dependence of light absorption by body tissues to capture high-contrast images of body tissues such as blood vessels in the mucosal surface layer by irradiating the body tissues with light within a band narrower than the illumination light (e.g., white light) in normal observation. Special light observation may also include fluorescence observation, which obtains an image through fluorescence generated by applying excitation light. For example, according to fluorescence observation, excitation light may be applied to the body tissues and fluorescence from the body tissues may be observed (autofluorescence observation), or a reagent such as indocyanine green (ICG) may be locally injected into the body tissues and excitation light at the fluorescence wavelength of the reagent may be applied to the body tissues to obtain a fluorescence image, etc. The light source device 603 may be configured to be capable of providing narrow-band light and / or excitation light for such special light observation.

[0182] Figure 25 is a block diagram showing an example of the functional configuration of the camera 502 and the CCU 601.

[0183] The camera 502 includes a lens unit 701, an imaging unit 702, a drive unit 703, a communication unit 704, and a camera control unit 705. The CCU 601 includes a communication unit 711, an image processing unit 712, and a control unit 713. The camera 502 and the CCU 601 are connected by a transmission cable 700 so as to communicate with each other.

[0184] The lens unit 701 is an optical system provided at the joint of the lens barrel 501. The observation light introduced into the lens barrel 501 from the distal end of the lens barrel 501 propagates to the camera 502 and is applied to the lens unit 701 at the camera 502. The lens unit 701 includes a combination of a plurality of lenses, which include a zoom lens and a focusing lens.

[0185] The imaging unit 702 includes more than one imaging element. The imaging unit 702 may include a single imaging element (commonly referred to as a single-panel type) or a plurality of imaging units (commonly referred to as a multi-panel type). In the case where the imaging unit 702 is of the multi-panel type, the imaging elements respectively generate RGB image signals, and for example, these image signals may be combined into a color image. Alternatively, the imaging unit 702 may have a pair of imaging elements for obtaining image signals for the left and right eyes respectively compatible with 3D (stereoscopic) display. 3D display may enable the surgical operator 531 to more accurately grasp the depth of the body tissues at the surgical site. Incidentally, in the case where the imaging unit 702 is of the multi-panel type, a plurality of lens units 701 may also be provided in combination with the respective imaging elements. The imaging unit 702 includes, for example, a solid-state imaging device according to any one of the first to fourteenth embodiments.

[0186] In addition, the imaging unit 702 does not necessarily have to be provided inside the camera 502. For example, the imaging unit 702 can be provided inside the lens barrel 501 directly behind the objective lens.

[0187] The drive unit 703 includes an actuator for moving the zoom lens and the focusing lens of the lens unit 701 a predetermined distance along the optical axis under the control of the camera control unit 705. The lens unit 701 driven in this way can appropriately adjust the magnification and focus of the image captured by the imaging unit 702.

[0188] The communication unit 704 includes a communication device for sending various information to the CCU 601 and receiving various information from the CCU 601. The communication unit 704 sends the image signal obtained from the imaging unit 702 to the CCU 601 as RAW data via the transmission cable 700.

[0189] In addition, the communication unit 704 receives a control signal for controlling the power-on of the camera 502 and provides the received control signal to the camera control unit 705. The control signal includes information related to imaging conditions, for example, information indicating the frame rate of the captured image, information indicating the exposure value when capturing the image, and / or information indicating the magnification and focus of the captured image.

[0190] Note that the imaging conditions including the frame rate, exposure value, magnification, and focus can be specified by the user or automatically set by the control unit 713 of the CCU 601 based on the acquired image signal. In the latter case, the so-called AE (Automatic Exposure) function, AF (Automatic Focus) function, and AWB (Automatic White Balance) function are included inside the endoscope 500.

[0191] The camera control unit 705 controls the power-on of the camera 502 based on the control signal received from the CCU 601 through the communication unit 704.

[0192] The communication unit 711 includes a communication device for sending / receiving various information to / from the camera 502. The communication unit 711 receives the image signal sent from the camera 502 via the transmission cable 700.

[0193] In addition, the communication unit 711 sends a control signal for controlling the power-on of the camera 502 to the camera 502. The image signal and the control signal can be sent, for example, through electrical communication or optical communication.

[0194] The image processing unit 712 performs various image processing operations on the image signal sent from the camera 502 in the form of RAW data.

[0195] The control unit 713 performs various control processes related to imaging of the surgical site and the like by the endoscope 500 and display of the captured images of the surgical site and the like. For example, the control unit 713 generates a control signal for controlling the energization of the camera 502.

[0196] In addition, the control unit 713 controls the display device 602 to display the captured image of the surgical site based on the image signal that has been processed by the image processing unit 712. At this time, the control unit 713 can use various image recognition techniques to recognize various objects in the captured image. For example, the control unit 713 can recognize surgical tools such as forceps, specific biological parts, bleeding, and the fog generated when using the energy treatment tool 512 by detecting the edge shape and color of the objects in the captured image. When the control unit 713 controls the display device 602 to display the captured image, the control unit 713 can also overlap and display various surgical assistance information with the surgical site image using the recognition result. When the displayed surgical assistance information is presented to the surgeon 531, the burden on the surgeon 531 can be reduced, and the surgeon 531 can perform the surgery reliably.

[0197] The transmission cable 700 that interconnects the camera 502 and the CCU 601 includes an electrical signal cable compatible with electrical signal communication, an optical fiber compatible with optical communication, or a composite cable including an electrical signal cable and an optical fiber.

[0198] Here, according to the illustrated example, the transmission cable 700 is used for wired communication. However, the communication between the camera 502 and the CCU 601 can be performed wirelessly.

[0199] The embodiments of the present disclosure have been described above. However, various changes and deformations can be made to the embodiments without departing from the scope of the present disclosure. For example, two or more embodiments can be combined and implemented.

[0200] Note that the present disclosure can also have the following configuration.

[0201] (1) A solid-state imaging device, comprising: A first substrate; A floating diffusion portion disposed in the first substrate; A first transistor disposed on the first substrate; A first insulating film disposed on the first substrate and the first transistor; A first wiring disposed in the first insulating film and electrically connected to the floating diffusion portion and the first transistor; A second substrate disposed on the first insulating film; A second transistor disposed on the second substrate; and A second insulating film, which is disposed on the second substrate and the second transistor.

[0202] (2) The solid-state imaging device according to (1), wherein the first transistor includes an amplifying transistor for converting the charge stored in the floating diffusion portion into a voltage signal.

[0203] (3) The solid-state imaging device according to (1), further comprising: A third transistor, which is disposed on the first substrate; A second wiring, which is disposed in the first insulating film and is electrically connected to the third transistor; A third insulating film, which is disposed in the second substrate between the first insulating film and the second insulating film and extends through the second substrate; and One or more first plugs, which are disposed in the third insulating film, wherein The one or more first plugs include a first plug disposed on the second wiring and not disposed on the first wiring.

[0204] (4) The solid-state imaging device according to (3), wherein the third transistor includes a transfer transistor for transferring the charge generated by the photoelectric converter disposed in the first substrate.

[0205] (5) The solid-state imaging device according to (3), further comprising: A fourth transistor, which is disposed on the first substrate; and A third wiring, which is disposed in the first insulating film and is electrically connected to the fourth transistor, wherein The one or more first plugs are not disposed on the third wiring.

[0206] (6) The solid-state imaging device according to (5), wherein the fourth transistor includes a reset transistor for resetting the potential of the floating diffusion portion.

[0207] (7) The solid-state imaging device according to (1), at least a part of the first insulating film includes an insulating film having a dielectric constant lower than that of silicon oxide.

[0208] (8) The solid-state imaging device according to (1), further comprising: A fourth insulating film, which is disposed in the second substrate between the first insulating film and the second insulating film and extends through the second substrate, wherein In a plan view, the first wiring is disposed at a position overlapping with the fourth insulating film.

[0209] (9) The solid-state imaging device according to (8), wherein at least a part of the fourth insulating film includes an insulating film having a dielectric constant lower than that of silicon oxide.

[0210] (10) The solid-state imaging device according to (1), wherein in a plan view, the first wiring is arranged at a position overlapping with a hollow region extending through the second substrate.

[0211] (11) The solid-state imaging device according to (10), wherein the first wiring remains in contact with the hollow region.

[0212] (12) The solid-state imaging device according to (5), further comprising: A fourth insulating film, which is arranged between the first insulating film and the second insulating film in the second substrate and extends through the second substrate, wherein in a plan view, the third wiring is arranged at a position overlapping with the fourth insulating film.

[0213] (13) The solid-state imaging device according to (1), further comprising: A fifth insulating film, which is arranged between the first insulating film and the second insulating film in the second substrate and extends through the second substrate, wherein the first substrate includes a first portion annularly surrounded by the fifth insulating film.

[0214] (14) The solid-state imaging device according to (13), wherein in a plan view, the first wiring is arranged at a position overlapping with the first portion.

[0215] (15) The solid-state imaging device according to (13), further comprising: A second plug, which is arranged on the first portion for controlling the potential of the first portion.

[0216] (16) The solid-state imaging device according to (1), further comprising: A reset transistor for resetting the potential of the floating diffusion part; and A conversion efficiency switching transistor, which is arranged between the floating diffusion part and the reset transistor for switching the conversion efficiency of a photoelectric converter arranged in the first substrate.

[0217] (17) The solid-state imaging device according to (16), wherein the reset transistor is arranged on the first substrate.

[0218] (18) The solid-state imaging device according to (16), wherein the reset transistor is arranged on the second substrate.

[0219] (19) The solid-state imaging device according to (1) further includes: A circuit disposed on the second substrate and including a transistor and a capacitor.

[0220] (20) The solid-state imaging device according to (19), wherein the circuit includes a sample-and-hold circuit. List of Reference Numerals

[0221] 1: Pixel, 2: Pixel array region, 3: Control circuit, 4: Vertical drive circuit, 5: Column signal processing circuit, 6: Horizontal drive circuit, 7: Output circuit, 8: Vertical signal line, 9: Horizontal signal line, 11: Substrate, 11a: Well region, 11b: Diffusion region, 11c: Diffusion region, 12: Element isolation insulating film, 13: Pixel transistor, 13a: Gate insulating film, 13b: Gate electrode, 13c: Sidewall insulating film, 14: Pixel transistor, 14a: Gate insulating film, 14b: Gate electrode, 14c: Sidewall insulating film, 15: Interlayer insulating film, 15': Interlayer insulating film, 16: Contact plug, 16a: Plug, 16b: Plug, 16c: Plug, 16d: Plug, 17: Wiring layer, 17a: Wiring, 17b: Wiring, 17c: Wiring, 18: Pixel transistor, 18a: Gate insulating film, 18b: Gate electrode, 18c: Sidewall insulating film, 21: Substrate, 21a: Well region, 21b: Diffusion region, 21c: Diffusion region, 21d: Diffusion region, 21e: Diffusion region, 21f: Diffusion region, 22: Insulating film, 23: Element isolation insulating film, 23': Element isolation insulating film, 24: Pixel transistor, 24a: Gate insulating film, 24b: Gate electrode, 24c: Sidewall insulating film, 25: Pixel transistor, 25a: Gate insulating film, 25b: Gate electrode, 25c: Sidewall insulating film, 26: Interlayer insulating film, 27: Contact plug, 27a: Plug, 27g: Plug, 27c: Plug, 27d: Plug, 27e: Plug, 27f: Plug, 31: Through-plug, 31a: Plug, 41: Hollow region, 51: Substrate portion, 52: Substrate portion, 61: Sample-and-hold circuit, 71: Substrate, 72: Transistor, 72a: Gate insulating film, 72b: Gate electrode, 72c: Sidewall insulating film, 73: Interlayer insulating film, 81: On-chip filter, 82: On-chip lens.

Claims

1. A solid-state imaging device, comprising: A first substrate; A floating diffusion portion disposed in the first substrate; A first transistor disposed on the first substrate; A first insulating film disposed on the first substrate and the first transistor; A first wiring disposed in the first insulating film and electrically connected to the floating diffusion portion and the first transistor; A second substrate disposed on the first insulating film; A second transistor disposed on the second substrate; And A second insulating film disposed on the second substrate and the second transistor.

2. The solid-state imaging device according to claim 1, wherein, The first transistor includes an amplifying transistor for converting the charge stored in the floating diffusion portion into a voltage signal.

3. The solid-state imaging device according to claim 1, further comprising: A third transistor disposed on the first substrate; A second wiring disposed in the first insulating film and electrically connected to the third transistor; A third insulating film disposed in the second substrate between the first insulating film and the second insulating film and extending through the second substrate; and One or more first plugs disposed in the third insulating film, wherein, The one or more first plugs include a first plug disposed on the second wiring and not disposed on the first wiring.

4. The solid-state imaging device according to claim 3, wherein, The third transistor includes a transfer transistor for transferring the charge generated by a photoelectric converter disposed in the first substrate.

5. The solid-state imaging device according to claim 3, further comprising: A fourth transistor disposed on the first substrate; And A third wiring disposed in the first insulating film and electrically connected to the fourth transistor, wherein, The one or more first plugs are not disposed on the third wiring.

6. The solid-state imaging device according to claim 5, wherein, The fourth transistor includes a reset transistor for resetting the potential of the floating diffusion portion.

7. The solid-state imaging device according to claim 1, wherein, At least a part of the first insulating film includes an insulating film having a dielectric constant lower than that of silicon oxide.

8. The solid-state imaging device according to claim 1, further comprising: A fourth insulating film disposed in the second substrate between the first insulating film and the second insulating film and extending through the second substrate, wherein, In a plan view, the first wiring is disposed at a position overlapping the fourth insulating film.

9. The solid-state imaging device according to claim 8, wherein, At least a part of the fourth insulating film includes an insulating film having a dielectric constant lower than that of silicon oxide.

10. The solid-state imaging device according to claim 1, wherein, In a plan view, the first wiring is disposed at a position overlapping a hollow region extending through the second substrate.

11. The solid-state imaging device according to claim 10, wherein, The first wiring remains in contact with the hollow region.

12. The solid-state imaging device according to claim 5, further comprising: A fourth insulating film disposed in the second substrate between the first insulating film and the second insulating film and extending through the second substrate, wherein, In a plan view, the third wiring is disposed at a position overlapping the fourth insulating film.

13. The solid-state imaging device according to claim 1, further comprising: A fifth insulating film, which is disposed between the first insulating film and the second insulating film in the second substrate and extends through the second substrate, wherein, the first substrate includes a first portion that is annularly surrounded by the fifth insulating film.

14. The solid-state imaging device according to claim 13, wherein, In a plan view, the first wiring is disposed at a position overlapping with the first portion.

15. The solid-state imaging device according to claim 13, further comprising: a second plug, which is disposed on the first portion for controlling the potential of the first portion.

16. The solid-state imaging device according to claim 1, further comprising: a reset transistor for resetting the potential of the floating diffusion portion; and a conversion efficiency switching transistor, which is disposed between the floating diffusion portion and the reset transistor for switching the conversion efficiency of the photoelectric converter disposed in the first substrate.

17. The solid-state imaging device according to claim 16, wherein, The reset transistor is disposed on the first substrate.

18. The solid-state imaging device according to claim 16, wherein, The reset transistor is disposed on the second substrate.

19. The solid-state imaging device according to claim 1, further comprising: a circuit, which is disposed on the second substrate and includes a transistor and a capacitor.

20. The solid-state imaging device according to claim 19, wherein, The circuit includes a sample-and-hold circuit.

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