A GaN-based power device dynamic on-resistance test circuit

Abstract

The application discloses a kind of GaN-based power device dynamic conduction resistance test circuit, comprising: power supply circuit provides voltage for the power device to be measured;Drive circuit provides gate drive for the power device to be measured;Transient suppression circuit prevents the gate overvoltage of the power device to be measured and provides static discharge channel;Clamp circuit captures the drain voltage variation of the power device to be measured from off to open, and the device conduction voltage test error is controlled in the required range;Power circuit controls the current size flowing through the power device to be measured;Free-wheeling loop provides the freewheeling channel for power circuit;Current sampling circuit samples the current flowing through the power device to be measured, and obtains conduction current.The technical scheme provided by the application can accurately measure the dynamic conduction resistance of GaN power device, and provide guidance for GaN power device design, preparation and application.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device testing, and in particular to a dynamic on-resistance testing circuit for GaN-based power devices. Background Technology

[0002] Gallium nitride (GaN), as a major representative of third-generation power semiconductors, has significant advantages in terms of structure and performance parameters. Compared with silicon (Si) MOSFETs, it has advantages such as a larger bandgap, higher thermal conductivity, stronger breakdown field strength, and faster electron saturation drift velocity, and has broad application prospects in fields such as high-frequency, high-efficiency, and high-power-density DC-DC conversion, data storage, and lidar systems.

[0003] GaN power devices exhibit superior performance with extremely low on-resistance. However, their unique physical structure leads to dynamic resistance degradation, known as current collapse. When a device switches to the conducting state after being subjected to high voltage bias, its on-resistance increases, resulting in increased power loss and reduced overall system efficiency. This limits the application of GaN power devices in applications with high reliability requirements. Accurately measuring the dynamic on-resistance of GaN power devices provides precise data for application design, reducing design complexity, mitigating failure risks, and ensuring product reliability and lifespan. Understanding the factors influencing changes in the dynamic on-resistance of GaN power devices is crucial for studying their dynamic resistance characteristics. Summary of the Invention

[0004] The technical problem solved by this invention is to overcome the shortcomings of the prior art and provide a dynamic on-resistance test circuit for GaN-based power devices, accurately measure the dynamic on-resistance of GaN power devices, and provide guidance for the design, fabrication and application of GaN power devices.

[0005] The technical solution of this invention is: a dynamic on-resistance testing circuit for GaN-based power devices, comprising:

[0006] The power supply circuit provides voltage to the power device under test.

[0007] The driving circuit provides gate drive for the power device under test;

[0008] Transient suppression circuitry prevents gate overvoltage of the power device under test and provides an electrostatic discharge path.

[0009] The clamping circuit captures the drain voltage change of the power device under test from off to on, and controls the test error of the device's on-voltage within the required range.

[0010] Power circuit, which controls the current flowing through the power device under test;

[0011] The freewheeling circuit provides a freewheeling path for the power circuit.

[0012] The current sampling circuit samples the current flowing through the power device under test to obtain the conduction current.

[0013] Furthermore, the driving circuit includes a driving chip U1, resistors R1, R2, and R3. One end of resistor R1 is connected to the high-side output of the driving chip U1, and the other end is connected to resistors R2 and R3, diode Z2 of the transient suppression circuit, and the gate of the power device under test M1. One end of resistor R2 is connected to the low-side output of the driving chip U1, and the other end is connected to resistors R1 and R3, diode Z2 of the transient suppression circuit, and the gate of the power device under test M1. Resistor R3 is connected in parallel with diode Z2 of the transient suppression circuit, and its two ends are respectively connected to the gate of the power device under test M1 and the ground terminal of the driving chip U1.

[0014] The transient suppression circuit includes a diode Z2, which is connected in parallel with a resistor R3 and is connected to the gate and source of the power device under test M1, respectively. The source is connected to the ground terminal of the driver chip U1.

[0015] The clamping circuit includes diodes D2 and D3, Zener diode Z1, capacitors C3 and C4, current-limiting resistor R5, and voltage-dividing resistor R6. Diodes D2 and D3 are connected in anti-parallel. The anode of diode D2 is connected to the anode of freewheeling diode D1, and the cathode of diode D2 is connected to one end of current-limiting resistor R5 and the cathode of Zener diode Z1. The anode of diode D3 is connected to one end of current-limiting resistor R5, and the cathode is connected to the anode of freewheeling diode D1. The cathode of Zener diode Z1 is connected to the anode of diode D3, and the anode of Zener diode Z1 is connected to the source of the power device under test M1. Capacitors C3 and C4 and resistor R6 are connected in parallel, with one end connected to R5 and the other end connected to the source of the power device under test M1.

[0016] The power circuit includes a current-limiting resistor R4 and an inductor L1. One end of the resistor R4 is connected in series with the inductor L1, and the other end is connected to the positive terminal of the power supply. One end of the inductor L1 is connected to the resistor R4, and the other end is connected to the drain of the device under test and the cathode of the diode D3.

[0017] The freewheeling circuit includes a freewheeling diode D1, the cathode of which is connected to the positive terminal of the power supply, and the anode of which is connected to the anode of diode D2, providing a freewheeling path for the inductor L1 current of the power circuit during the off-state of the power device under test.

[0018] The current sampling circuit includes a shunt Rs, which is connected between the output terminal of the power device under test M1 and the power supply circuit.

[0019] The voltage acquisition terminals are located at the two ends of the Zener diode Z1, which measures the sum of the forward voltage of the power device under test M1 and the voltage of the diode D3; the current acquisition terminals are located at the two ends of the shunt Rs, which measures the forward current flowing through the power device under test.

[0020] Furthermore, the driving circuit also includes a capacitor C2, the two ends of which are connected to the power supply terminal and the ground terminal of the driving chip U1, respectively, for filtering.

[0021] Furthermore, capacitor C1 is a liquid tantalum capacitor; diode D2 is a SiC diode, and diode D1 is a Schottky diode.

[0022] Furthermore, the power supply circuit includes a power supply V1 and a capacitor C1 connected in parallel.

[0023] This invention also provides a method for testing the dynamic on-resistance of GaN-based power devices, comprising:

[0024] Construct the dynamic on-resistance test circuit for the GaN-based power device;

[0025] The device under test (DUT) is set to the off state, and there is no current in the power circuit. An on signal is sent to the drive circuit, and the DUT is turned on. Inductor L1 is charged, and the current of the DUT gradually increases, while diode D2 is in the off state. An off signal is sent to the drive circuit, and the current of inductor L1 continues to flow through diode D1 in the freewheeling loop. An on signal is sent to the drive circuit again, and inductor L1 is charged. The current of the DUT continues to increase. The voltage at the voltage acquisition terminal and the current at the current acquisition terminal are captured. The current is the conduction current flowing through the DUT. The voltage at the voltage acquisition terminal minus the forward voltage drop of diode D2 is the conduction voltage of the DUT. The conduction voltage divided by the conduction current gives the dynamic on-resistance of the DUT.

[0026] Furthermore, by adjusting the inductance value of inductor L1, the current flowing through the power device under test is changed, thereby improving the dynamic on-resistance acquisition rate.

[0027] Furthermore, by controlling the turn-on and turn-off times of the power device under test, the dynamic on-resistance of the power device under test at different frequencies can be obtained.

[0028] Furthermore, the amplitude of the external voltage V1 was adjusted to test the effect of different drain-source voltages on the dynamic on-resistance of the power device under test.

[0029] The advantages of this invention compared to the prior art are:

[0030] (1) The GaN power device dynamic resistance test circuit of the present invention can accurately measure the dynamic resistance of GaN power devices in the switching state under different drain voltages, different conduction currents and different frequencies.

[0031] (2) This invention uses fewer components, has a simpler circuit, and is less expensive;

[0032] (3) The dynamic resistance test circuit of GaN power device of the present invention uses a shunt to sample the transient current of the switch, which has high bandwidth and effectively shields external noise;

[0033] (4) The present invention has electrostatic protection function to protect the device under test and avoid electrostatic damage. Attached Figure Description

[0034] Figure 1 This is a block diagram of the test circuit of the present invention;

[0035] Figure 2 This is a schematic diagram of the test circuit for this invention;

[0036] Figure 3 This is a schematic diagram of the test timing for the present invention. Detailed Implementation

[0037] To better understand the technical solution of the present invention, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0038] The core of the dynamic resistance test design for GaN power devices lies in accurately measuring the voltage across the device's drain and source terminals (DS) and the drain-source current flowing through the device. The technical solution provided by this invention is a dynamic on-resistance test circuit for GaN power devices, including a power supply circuit, a drive circuit, a transient suppression circuit, a clamping circuit, a power circuit, a freewheeling loop, and a current sampling circuit, such as... Figure 1 As shown:

[0039] The power supply circuit provides voltage to the device under test (DUT), which is the drain-source voltage when the device is off. The drive circuit provides gate drive to the DUT based on an external PWM pulse signal. The transient suppression circuit prevents gate overvoltage of the DUT and provides an electrostatic discharge channel. The clamping circuit is mainly used to resolve the voltage difference between the on-state and off-state voltage values ​​of the DUT, ensuring the accuracy of capturing the entire waveform of the drain voltage change of the DUT from off to on on in the oscilloscope, and controlling the device conduction voltage test error within a small range. The power circuit controls the current flowing through the DUT. The freewheeling circuit provides a freewheeling channel for the energy storage device in the power circuit. The current sampling circuit samples the current flowing through the DUT to obtain the conduction current.

[0040] In one possible implementation, such as Figure 2 As shown:

[0041] The power supply circuit includes a high-voltage power supply V1 and a liquid tantalum capacitor C1 connected in parallel.

[0042] The driving circuit includes a driving chip U1, resistors R1 to R3, and a capacitor C2. The two ends of capacitor C2 are connected to the power supply terminal and ground terminal of the driving chip U1, respectively, for filtering. One end of resistor R1 is connected to the high-side output of the driving chip U1, and the other end is connected to resistors R2 and R3, transient suppression diode Z2, and the gate of the power device under test M1. One end of resistor R2 is connected to the low-side output of the driving chip U1, and the other end is connected to resistors R1 and R3, transient suppression diode Z2, and the gate of the power device under test M1. Resistor R3 is connected in parallel with transient suppression diode Z2, and its two ends are connected to the gate of the power device under test M1 and the ground terminal of the driving chip U1, respectively.

[0043] The transient suppression circuit includes a TVS diode Z2, which is connected in parallel with a resistor R3 and is connected to the gate and source of the power device under test M1, respectively. The source is connected to the ground terminal of the driver chip U1. This ensures that the gate does not experience overvoltage and provides an electrostatic discharge path for the device.

[0044] The clamping circuit includes diodes D2 and D3, a Zener diode Z1, capacitors C3 and C4, a current-limiting resistor R5, and a voltage divider resistor R6. Diodes D2 and D3 are connected in anti-parallel. The anode of diode D2 is connected to the anode of freewheeling diode D1, and the cathode of diode D2 is connected to one end of the current-limiting resistor R5 and the cathode of Zener diode Z1. The anode of diode D3 is connected to one end of the current-limiting resistor R5, and its cathode is connected to the anode of freewheeling diode D1. The cathode of Zener diode Z1 is connected to the anode of diode D3, and the anode of Zener diode Z1 is connected to the source of the power device under test (DUT). Capacitors C3 and C4 and resistor R6 are connected in parallel, with one end connected to R5 and the other end connected to the source of the DUT. This ensures that the drain voltage amplitude of the DUT is clamped within a certain range when it is turned off. GaN power devices have a high drain voltage when turned off, but the drain voltage drops rapidly when turned on. Accurately capturing the change in the conduction voltage across the D and S terminals is a crucial aspect of the test. When using a high-precision oscilloscope to measure voltage, GaN power devices exhibit high voltage when turned off and low voltage when turned on. This requires the oscilloscope to have a large measurement range, and the internal amplifier of the oscilloscope may become distorted, resulting in inaccurate measurement of the on-state voltage. By designing a clamping circuit to clamp the drain voltage of the GaN power device to a range of a few volts when it is turned off, the voltage swing during device switching can be controlled within a smaller range.

[0045] The power circuit includes a current-limiting resistor R4 and an inductor L1. One end of the resistor R4 is connected in series with the inductor L1, and the other end is connected to the positive terminal of the power supply. One end of the inductor L1 is connected to the resistor R4, and the other end is connected to the drain of the device under test and the cathode of the diode D3. By controlling the energy storage time of the inductor L1, the conduction current flowing through the device under test is controlled.

[0046] The freewheeling circuit includes a fast recovery diode D1, whose cathode is connected to the positive terminal of the power supply and whose anode is connected to the anode of diode D2. It is used to provide a freewheeling path for the inductor current of the power circuit during the turn-off period of the device under test.

[0047] The current sampling circuit, including a shunt Rs, is connected between the output terminal of the power device under test and the power supply circuit for accurate measurement of the conduction current flowing through the device under test.

[0048] The two ends of the Zener diode Z1 are voltage acquisition terminals, used to measure the forward voltage of the power device under test;

[0049] The two ends of the shunt Rs are current acquisition terminals, used to measure the conduction current flowing through the power device under test.

[0050] Specifically, the dynamic on-resistance test method for GaN power devices is as follows:

[0051] At the beginning of the test, the GaN power device was in the off state, and there was no current in the power circuit. The GaN power device's DS terminals (i.e., Figure 2 The voltage at M1 is the power supply voltage V1. When a control signal is sent to the drive circuit, the GaN power device turns on, inductor L1 charges, the current in the GaN power device rises slowly, D2 is in the off state, and the voltage acquisition terminal is the regulated voltage of Zener diode Z1. When a turn-off signal is sent, the inductor current freewheels through Schottky diode D1 in the freewheeling circuit. When a turn-on signal is sent again, the inductor charges, and the current continues to rise. The voltage waveform at the voltage acquisition terminal and the current waveform at the current acquisition terminal are captured at this time. The current is the current flowing through the GaN power device. The voltage at the voltage acquisition terminal minus the forward voltage drop of SiC diode D2 is the turn-on voltage of the GaN power device. Dividing the voltage and current gives the dynamic on-resistance of the GaN power device. After the device under test is turned off, the current in the circuit decays to zero in the freewheeling circuit. Figure 3 The test timing diagram of the present invention is given.

[0052] The current flowing through the GaN power device can be changed by adjusting the inductance value of inductor L1. By controlling the turn-on and turn-off times of the device, the dynamic on-resistance of the GaN power device at different frequencies can be obtained. The amplitude of the external voltage V1 can be used to test the effect of different drain-source voltages on the dynamic resistance of the GaN power device.

[0053] It is understood that this invention has been described through embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of this invention. Furthermore, under the teachings of this invention, these features and embodiments can be modified to adapt to specific circumstances without departing from the spirit and scope of this invention. Therefore, this invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are protected by this invention.

[0054] The contents not described in detail in this specification are common knowledge to those skilled in the art.

Claims

1. A dynamic on-resistance testing circuit for GaN-based power devices, characterized in that, include: The power supply circuit provides voltage to the power device under test. The driving circuit provides gate drive for the power device under test; it includes a driving chip U1, resistors R1, R2, and R3. One end of resistor R1 is connected to the high-side output of driving chip U1, and the other end is connected to resistors R2 and R3, diode Z2 of the transient suppression circuit, and the gate of the power device under test M1. One end of resistor R2 is connected to the low-side output of driving chip U1, and the other end is connected to resistors R1 and R3, diode Z2 of the transient suppression circuit, and the gate of the power device under test M1. Resistor R3 is connected in parallel with diode Z2 of the transient suppression circuit, and its two ends are connected to the gate of the power device under test M1 and the ground terminal of driving chip U1, respectively. Transient suppression circuitry prevents gate overvoltage of the power device under test and provides an electrostatic discharge path. Includes diode Z2, which is connected in parallel with resistor R3 and is connected to the gate and source of the power device under test M1, respectively. The source is connected to the ground terminal of the driver chip U1. The clamping circuit captures the drain voltage change of the power device under test from off to on, controlling the test error of the device's conduction voltage within the required range. It includes diodes D2 and D3, Zener diode Z1, capacitors C3 and C4, current-limiting resistor R5, and voltage-dividing resistor R6. Diodes D2 and D3 are connected in anti-parallel. The anode of diode D2 is connected to the anode of freewheeling diode D1, and the cathode of diode D2 is connected to one end of current-limiting resistor R5 and the cathode of Zener diode Z1. The anode of diode D3 is connected to one end of current-limiting resistor R5, and the cathode is connected to the anode of freewheeling diode D1. The cathode of Zener diode Z1 is connected to the anode of diode D3, and the anode of Zener diode Z1 is connected to the source of power device under test M1. Capacitors C3 and C4 and voltage-dividing resistor R6 are connected in parallel, with one end connected to current-limiting resistor R5 and the other end connected to the source of power device under test M1. The power circuit controls the current flowing through the power device under test; it includes a current-limiting resistor R4 and an inductor L1. One end of the current-limiting resistor R4 is connected in series with the inductor L1, and the other end is connected to the positive terminal of the power supply. One end of the inductor L1 is connected to the current-limiting resistor R4, and the other end is connected to the drain of the device under test and the cathode of the diode D3. The freewheeling circuit provides a freewheeling path for the power circuit; it includes a freewheeling diode D1, whose cathode is connected to the positive terminal of the power supply and whose anode is connected to the anode of diode D2, providing a freewheeling path for the inductor L1 current of the power circuit during the off-state of the power device under test. The current sampling circuit samples the current flowing through the power device under test to obtain the conduction current; it includes a shunt Rs, which is connected between the output terminal of the power device under test M1 and the power supply circuit. The voltage acquisition terminals are located at the two ends of the Zener diode Z1, which measures the sum of the forward voltage of the power device under test M1 and the voltage of the diode D3; the current acquisition terminals are located at the two ends of the shunt Rs, which measures the forward current flowing through the power device under test.

2. The GaN-based power device dynamic on-resistance testing circuit according to claim 1, characterized in that: The driving circuit also includes capacitor C2, with its two ends connected to the power supply terminal and ground terminal of the driving chip U1, respectively, for filtering.

3. The GaN-based power device dynamic on-resistance testing circuit according to claim 1, characterized in that: The power supply circuit includes a power supply V1 and a capacitor C1 connected in parallel.

4. The GaN-based power device dynamic on-resistance testing circuit according to claim 3, characterized in that: The capacitor C1 is a liquid tantalum capacitor; the diode D2 is a SiC diode; and the freewheeling diode D1 is a Schottky diode.

5. A method for testing the dynamic on-resistance of GaN-based power devices, characterized in that: Construct the dynamic on-resistance test circuit for GaN-based power devices as described in claim 1; The device under test (DUT) is set to the off state, and there is no current in the power circuit. An on signal is sent to the drive circuit, and the DUT is turned on. Inductor L1 is charged, and the current of the DUT gradually increases, while diode D2 is in the off state. An off signal is sent to the drive circuit, and the current of inductor L1 continues to flow through diode D1 in the freewheeling loop. An on signal is sent to the drive circuit again, and inductor L1 is charged. The current of the DUT continues to increase. The voltage at the voltage acquisition terminal and the current at the current acquisition terminal are captured. The current is the conduction current flowing through the DUT. The voltage at the voltage acquisition terminal minus the forward voltage drop of diode D2 is the conduction voltage of the DUT. The conduction voltage divided by the conduction current gives the dynamic on-resistance of the DUT.

6. The method for testing the dynamic on-resistance of GaN-based power devices according to claim 5, characterized in that: Adjusting the inductance value of inductor L1 changes the current flowing through the power device under test, thereby improving the dynamic on-resistance acquisition rate.

7. The method for testing the dynamic on-resistance of GaN-based power devices according to claim 5, characterized in that: By controlling the turn-on and turn-off times of the power device under test, the dynamic on-resistance of the power device under test at different frequencies can be obtained.

8. The method for testing the dynamic on-resistance of GaN-based power devices according to claim 5, characterized in that: Adjust the amplitude of the external voltage V1 and test the effect of different drain-source voltages on the dynamic on-resistance of the power device under test.

Images