Circuit test method, platform, medium and terminal

Abstract

The invention provides a circuit test method and platform, a medium and an electronic terminal. The circuit test method comprises the following steps: automatically reading pad information of a superconducting integrated circuit to be tested; processing the pad information through a script generator to automatically generate a test script; calling a calculation engine and automatically connecting a test instrument; and performing a multi-thread test on the to-be-tested superconducting integrated circuit based on the test script and a preset test vector to obtain a test result. By automatically reading the pad information, automatically generating the test script and carrying out the multi-thread test on the to-be-tested superconducting integrated circuit, the requirements of manual operation can be reduced, and human errors in the test process are reduced, so that the efficiency and the accuracy of the test process are improved.

Description

Technical Field

[0001] The present disclosure belongs to the field of circuit testing, relates to circuit testing methods, and particularly relates to circuit testing methods, platforms, media, and terminals. Background Art

[0002] A superconducting integrated circuit refers to an integrated circuit based on Josephson junctions and superconducting materials, including applications such as single-flux-quantum (SFQ) circuits.

[0003] An SFQ circuit is a relatively special superconducting integrated circuit, which is mainly composed of Josephson junctions and represents digital logic "0" and "1" by the presence or absence of the magnetic flux quantum Ф0. Compared with traditional semiconductor CMOS (Complementary Metal Oxide Semiconductor) circuits, the tiny and quantized nature of the magnetic flux quantum significantly reduces the influence of crosstalk and power consumption, and the narrow voltage pulses generated in the junction when the magnetic flux quantum enters and exits the loop also enable it to obtain extremely high frequencies. This advantage of both ultra-high working speed and extremely low power consumption makes this circuit have significant prospects in applications such as ultra-wideband analog-to-digital converters (ADCs) and superconducting computers.

[0004] Compared with semiconductor circuits, due to the different manufacturing processes and working logics brought about by different components used, different fault types have emerged in superconducting circuits, and traditional ATPG (Automatic Test Pattern Generation) methods cannot achieve a high fault coverage rate in SFQ circuit testing. Since SFQ circuits operate in a low-temperature environment, room-temperature test equipment requires complex connection methods to connect the circuit under test. In addition, SFQ circuits have a natural gate-level pipelined architecture and have strict requirements for timing and delay, which also pose requirements for design for testability such as high-low speed conversion, testable pipelines, and sequential circuits. For the above reasons, the current testing of superconducting integrated circuits generally uses manual testing, which has the problem of low manual testing efficiency. Summary of the Invention

[0005] The purpose of the present disclosure is to provide circuit testing methods, platforms, media, and terminals for solving the problem of low manual testing efficiency of current superconducting integrated circuits.

[0006] In a first aspect, an embodiment of the present disclosure provides a circuit testing method, including: automatically reading the pad information of a superconducting integrated circuit to be tested; processing the pad information through a script generator to automatically generate a test script; calling a computing engine and automatically connecting a test instrument; and performing a multi-threaded test on the superconducting integrated circuit to be tested based on the test script and a preset test vector to obtain a test result.

[0007] By automatically reading the pad information, automatically generating the test script, and performing a multi-threaded test on the superconducting integrated circuit to be tested, the need for manual operation can be reduced, and human errors during the testing process can be minimized, thereby improving the efficiency and accuracy of the testing process.

[0008] In an embodiment of the present disclosure, the implementation method of performing a multi-threaded test on the superconducting integrated circuit to be tested based on the test script and a preset test vector to obtain a test result includes: based on the test script, the preset test vector, and a preset expected result, testing the superconducting integrated circuit to be tested through a first thread to obtain a correlation coefficient between the actual output result of the superconducting integrated circuit to be tested and the preset expected result; processing the correlation coefficient through a second thread to obtain a test result; and ending the test or performing a heating treatment on the superconducting integrated circuit to be tested according to the test result.

[0009] In an embodiment of the present disclosure, the implementation method of testing the superconducting integrated circuit to be tested through a first thread based on the test script, the preset test vector, and the preset expected result to obtain a correlation coefficient between the actual output result of the superconducting integrated circuit to be tested and the preset expected result includes: based on the test script, the preset test vector, the preset expected result, a bias setting script of the superconducting integrated circuit to be tested, and a read output waveform script, testing the superconducting integrated circuit to be tested through a first thread using a particle swarm optimization algorithm to obtain the correlation coefficient, where the preset expected result is an expected output waveform, and the correlation coefficient represents the coefficient when the actual output waveform of the superconducting integrated circuit to be tested has the highest similarity with the expected output waveform, and the position of each particle represents the bias of all dimensions of the superconducting integrated circuit to be tested.

[0010] In an embodiment of the present disclosure, the objective function of the particle swarm optimization algorithm is the absolute value of the correlation coefficient between the actual output waveform and the expected output waveform.

[0011] In an embodiment of the present disclosure, the implementation method of testing the superconducting integrated circuit to be tested through a first thread using a particle swarm optimization algorithm to obtain the correlation coefficient further includes: generating a random bias; if the particle is less than a preset mutation probability, mutating the position of the particle to the random bias; otherwise, the position of the particle remains unchanged.

[0012] In an embodiment of the present disclosure, the positions of the particles form a particle position matrix, the random biases form a random bias matrix, the particle position matrix and the random bias matrix are matrices of the same type, and the method for mutating the positions of the particles into the random biases includes: obtaining the index of the particle position mutation in the particle position matrix; obtaining the random bias in the random bias matrix based on the index; and mutating the position of the particle into the random bias.

[0013] In an embodiment of the present disclosure, the method for multi-threadedly testing the superconducting integrated circuit under test based on the test script and the preset test vector to obtain the test result includes: testing the superconducting integrated circuit under test through a plurality of threads based on the test script, the preset test vector, and the preset expected result to obtain a test result set; if all the test results in the test result set are test failures, ending the test; otherwise, testing the superconducting integrated circuit under test based on the next preset test vector in the Nth thread.

[0014] In a second aspect, the present disclosure provides a circuit test platform, including: a pad management tool for automatically reading the pad information of the superconducting integrated circuit under test, saving the loaded preset test vector, and displaying the pad information; a script generator for processing the pad information to automatically generate a test script; a test launcher for calling a computing engine and automatically connecting to a test instrument; and a circuit test module for multi-threadedly testing the superconducting integrated circuit under test based on the test script and the preset test vector to obtain a test result.

[0015] In a third aspect, the present disclosure provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the circuit test method according to any one of the first aspect is implemented.

[0016] In a fourth aspect, the present disclosure provides an electronic terminal, including a memory, a processor, and a computer program stored on the memory, and the processor executes the computer program to implement the circuit test method according to any one of the first aspect.

[0017] As described above, the circuit test method, platform, medium, and terminal of the present application have the following beneficial effects:

[0018] By automatically reading the pad information, automatically generating the test script, and multi-threadedly testing the superconducting integrated circuit under test, the need for manual operations can be reduced, and human errors during the testing process can be reduced, thereby improving the efficiency and accuracy of the testing process.

[0019] In addition, the circuit test platform standardizes test scripts and test steps, and can provide an experimental platform and support for a large amount of test data for the development of automated testing technology and intelligent testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It shows a schematic structural diagram of the circuit test platform according to an embodiment of the present disclosure.

[0021] Figure 2 It shows a flowchart of the circuit test method according to an embodiment of the present disclosure.

[0022] Figure 3 It shows a flowchart of an implementation method for multi-threaded testing of the superconducting integrated circuit under test based on the test script and a preset test vector to obtain a test result according to an embodiment of the present disclosure.

[0023] Figure 4 It shows a flowchart of an implementation method for testing the superconducting integrated circuit under test using a particle swarm optimization algorithm through a first thread to obtain the correlation coefficient according to an embodiment of the present disclosure.

[0024] Figure 5 It shows a flowchart of an implementation method for mutating the position of the particle into the random offset according to an embodiment of the present disclosure.

[0025] Figure 6 It shows a flowchart of an implementation method for multi-threaded testing of the superconducting integrated circuit under test based on the test script and a preset test vector to obtain a test result according to an embodiment of the present disclosure.

[0026] Figure 7 It shows a schematic structural diagram of the circuit test platform according to an embodiment of the present disclosure.

[0027] Figure 8 It shows a schematic diagram of the GUI of the circuit test platform according to an embodiment of the present disclosure.

[0028] Figure 9 It shows a schematic diagram of the multi-dimensional particle swarm algorithm test according to an embodiment of the present disclosure.

[0029] Figure 10 It shows a schematic block diagram of an electronic terminal according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] The following describes the embodiments of the present disclosure through specific examples. Those skilled in the art can easily understand other advantages and effects of the present disclosure from the content disclosed in this specification. The present disclosure can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0031] It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present disclosure schematically. Therefore, only the components related to the present disclosure are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0032] The technical solutions in the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings in the embodiments of the present disclosure.

[0033] Figure 1 It is a schematic structural diagram showing a circuit test platform according to an embodiment of the present disclosure. The circuit test platform includes a pad management tool, a script generator, and a test starter.

[0034] Optionally, the pad management tool has a graphical user interface (GUI) for displaying pad information, and is capable of allowing a user to manually modify and save specific pad information. The pad information can be saved into a python dictionary corresponding to the superconducting integrated circuit to be tested, so as to facilitate the generation of test scripts and the automatic test process. The superconducting integrated circuit to be tested may refer to the superconducting integrated circuit that needs to be tested.

[0035] Optionally, the script generator can be a Matlab (matrix factory) script generator. The responsibility of the Matlab script generator is to automatically generate all required test scripts. In existing circuit tests, this process requires manually inputting the pad planning information of the test chip and splicing it with most fixed content to generate a.m (Matlab format) file. Since the manual input method is not applicable to large circuits, the present disclosure optimizes this process so that it can directly obtain the pad information saved by the Pad Manager (pad management tool) and automatically generate test scripts.

[0036] Optionally, the test starter can use the matlab api interface to be capable of directly running Matlab using python, connecting to test instruments, and executing the test process. Matlab api is an interface provided by Matlab official, which allows python to call Matlab as a computing engine.

[0037] The principles and implementation manners of the circuit testing method and the circuit testing platform according to the embodiments of the present disclosure will be elaborated in detail below, so that those skilled in the art can understand the circuit testing method and the circuit testing platform according to the embodiments of the present disclosure without creative labor.

[0038] Figure 2 is a flowchart showing the circuit testing method according to the embodiments of the present disclosure. As Figure 2 shown, the present embodiment provides a circuit testing method, and the circuit testing method includes:

[0039] S11, automatically read the pad information of the superconducting integrated circuit to be tested.

[0040] Optionally, the pad information may be stored in an excel (spreadsheet) file storing chip information, and the excel file includes the pad information of the superconducting integrated circuit to be tested. The superconducting integrated circuit to be tested may be a chip to be tested.

[0041] S12, process the pad information through a script generator to automatically generate a test script.

[0042] Optionally, the script generator may be a matlab script generator. The script generator may include test logic associated with the pad information to automatically generate the test script in combination with the pad information to implement the functional test of the pad information.

[0043] S13, call a computing engine and automatically connect a test instrument.

[0044] Optionally, the computing engine may be a matlab computing engine, and the method for calling the computing engine and automatically connecting the test instrument includes: using python to start the computing engine through the engine startup function of matlab and connecting the test instrument. The test instrument is an instrument for testing the superconducting integrated circuit to be tested, and the computing engine is the computing engine for the circuit test. The engine startup function is not elaborated in this embodiment.

[0045] Optionally, in the actual test process, test logics such as the control of the tester and the running of the script can all be controlled by python.

[0046] S14, perform multi-threaded testing on the superconducting integrated circuit to be tested based on the test script and a preset test vector to obtain a test result.

[0047] Optionally, the multi-threaded testing may refer to testing the superconducting integrated circuit to be tested with two or more threads, and the test result is the result of the multi-threaded testing of the superconducting integrated circuit to be tested.

[0048] According to the above description, the circuit testing method includes: reading the pad information of the superconducting integrated circuit to be tested; processing the pad information through a script generator to generate a test script; calling a computing engine and automatically connecting test instruments; and performing multi-threaded testing on the superconducting integrated circuit to be tested based on the test script and a preset test vector to obtain a test result.

[0049] By automatically reading pad information, automatically generating a test script, and performing multi-threaded testing on the superconducting integrated circuit to be tested, the need for manual operations can be reduced, and human errors during the testing process can be minimized, thereby improving the efficiency and accuracy of the testing process.

[0050] Figure 3 This is a method for implementing multi-threaded testing on the superconducting integrated circuit to be tested based on the test script and a preset test vector to obtain a test result, including:

[0051] S21, based on the test script, the preset test vector, and the preset expected result, performing testing on the superconducting integrated circuit to be tested through a first thread to obtain the correlation coefficient between the actual output result of the superconducting integrated circuit to be tested and the preset expected result.

[0052] Optionally, the correlation coefficient can be between (-1, 1). Being close to 0 represents no correlation, and being close to ±1 indicates strong correlation. The correlation coefficient can be calculated using a function built into Matlab, correlation = corrcoef(expectedSignal, actualSignal), where correlation is the correlation coefficient, expectedSignal is the preset expected result, actualSignal is the actual output result, and corrcoef is the correlation coefficient calculation function built into Matlab. This embodiment will not elaborate further on this.

[0053] Optionally, the method for implementing performing testing on the superconducting integrated circuit to be tested through a first thread based on the test script, the preset test vector, and the preset expected result to obtain the correlation coefficient between the actual output result of the superconducting integrated circuit to be tested and the preset expected result includes: based on the test script, the preset test vector, the preset expected result, the bias setting script of the superconducting integrated circuit to be tested, and the read output waveform script, using a particle swarm optimization algorithm to perform testing on the superconducting integrated circuit to be tested through a first thread to obtain the correlation coefficient. The preset expected result is the expected output waveform, and the correlation coefficient represents the coefficient when the actual output waveform of the superconducting integrated circuit to be tested has the highest similarity to the expected output waveform. The position of each particle represents the bias of all dimensions of the superconducting integrated circuit to be tested.

[0054] Optionally, the biases in all dimensions of the superconducting integrated circuit to be tested can be the current bias values of all partitions of the superconducting integrated circuit to be tested.

[0055] Optionally, the objective function of the particle swarm optimization algorithm is the absolute value of the correlation coefficient between the actual output waveform and the expected output waveform.

[0056] Optionally, the bias setting script refers to the script for setting the bias of the superconducting integrated circuit to be tested, and the bias can be a current bias. The read output waveform script refers to the script for reading the waveform of the superconducting integrated circuit to be tested. The expected output waveform can be the expected output waveform of the superconducting integrated circuit to be tested, and the actual output waveform can be the actual output waveform of the superconducting integrated circuit to be tested.

[0057] Optionally, the first thread can be one of the multiple threads.

[0058] S22. Process the correlation coefficient through a second thread to obtain a test result.

[0059] Optionally, the second thread can be one of the multiple threads that is different from the first thread.

[0060] Optionally, the implementation method of processing the correlation coefficient through a second thread to obtain a test result includes: processing the correlation coefficient through a plurality of second threads to obtain the test results of each of the second threads.

[0061] Optionally, the test result can be judged according to the correlation coefficient described above. For example, when the correlation coefficient is greater than a certain preset correlation coefficient, it can be determined that the test is passed; when the correlation coefficient is not greater than the preset correlation coefficient, it can be determined that the test is not passed. The specific value of the preset correlation coefficient can be determined according to the actual situation, and this embodiment does not specifically limit it.

[0062] S23. End the test or perform a heating process on the superconducting integrated circuit to be tested according to the test result.

[0063] Optionally, the test result can be passed or not passed. The implementation method of ending the test or performing a heating process on the superconducting integrated circuit to be tested according to the test result includes: when the test result is not passed, end the test of the superconducting integrated circuit to be tested or perform a heating process on the superconducting integrated circuit.

[0064] Figure 4It shows an implementation method in an embodiment of the present disclosure for testing the superconducting integrated circuit to be measured by using a particle swarm optimization algorithm through a first thread to obtain the correlation coefficient, including:

[0065] S31, generate a random bias.

[0066] Optionally, the random bias can be generated by setting a random function for the bias, and this embodiment will not elaborate on the random function.

[0067] S32, if the particle is less than a preset mutation probability, mutate the position of the particle to the random bias, otherwise the position of the particle remains unchanged.

[0068] Optionally, the preset mutation probability can be flexibly set according to the actual situation, and this embodiment does not clearly limit it.

[0069] Optionally, mutating the position of the particle to the random bias may refer to updating the position of the particle to the random bias. The mutation of the position of the particle can be implemented through a random mutation function, and this embodiment will not elaborate on it.

[0070] Optionally, the particle can generate its corresponding mutation probability through a random number, and the particle being less than the preset mutation probability can refer to the mutation probability corresponding to the particle.

[0071] By setting the random bias and the mutation of the position of the particle, the coverage rate of the bias adjustment of the superconducting integrated circuit to be measured can be improved.

[0072] In an embodiment of the present disclosure, the positions of the particles form a particle position matrix, the random biases form a random bias matrix, and the particle position matrix and the random bias matrix are matrices of the same type. Figure 5 It shows an implementation method in an embodiment of the present disclosure for mutating the position of the particle to the random bias, including:

[0073] S41, obtain the index in the particle position matrix when the position of the particle mutates.

[0074] S42, obtain the random bias in the random bias matrix based on the index.

[0075] S43, mutate the position of the particle to the random bias.

[0076] Optionally, the index in the particle position matrix when the position of the particle mutates is (3, 4), that is, the element in the 3rd row and 4th column. The random bias is the element in the 3rd row and 4th column of the random bias matrix, and mutating the position of the particle to the random bias means updating the position of the particle to the random bias.

[0077] By adopting matrix operations, the operation speed can be improved. When scanning the same number of offsets, the speed is 4 times that of manually scanning the offsets, drawing pictures and judging whether they are correct.

[0078] In one embodiment of the present disclosure, Figure 6 It shows an implementation method for the multi-threaded testing of the superconducting integrated circuit under test based on the test script and the preset test vector to obtain the test results, including:

[0079] S51, based on the test script, the preset test vector and the preset expected result, test the superconducting integrated circuit under test through a plurality of threads to obtain a test result set.

[0080] S52, if all the test results in the test result set are test failures, end the test.

[0081] S53, otherwise, test the superconducting integrated circuit under test based on the next preset test vector in the Nth thread, where N is a positive integer.

[0082] Optionally, the specific value of N can be determined according to the actual situation, and this embodiment does not clearly limit it. By testing the same preset test vector multiple times through multiple threads, the stability of the test can be improved.

[0083] The protection scope of the circuit testing method described in the embodiments of the present disclosure is not limited to the order of the steps listed in this embodiment. Any solution achieved by adding or subtracting steps of the prior art and replacing steps according to the principles of the present disclosure is included in the protection scope of the present disclosure.

[0084] Figure 7 It shows a schematic structural diagram of the circuit testing platform 60 according to an embodiment of the present disclosure. As Figure 7 shown, this embodiment provides a circuit testing platform 60, including:

[0085] The pad management tool 610 is used to read the pad information of the superconducting integrated circuit under test, save the loaded preset test vector, and display the pad information.

[0086] The script generator 620 is used to process the pad information to generate a test script.

[0087] The test launcher 630 is used to call the computing engine and automatically connect to the test instrument.

[0088] Optionally, the computing engine can be a Matlab computing engine. The specific implementation steps of the test launcher are as follows: after setting the test parameters, start the Matlab engine through a specific function (Matlab engine startup function). During the actual test process, test logics such as the control of the tester and the running of scripts are all controlled by Python. The test launcher 630 can be integrated into a multi-threaded framework. The advantage of multi-threading is that it can publish tasks in parallel and execute automated tests serially in the background (considering that only one test rod can be used at a time).

[0089] A circuit test module 640 is used to perform multi-threaded tests on the superconducting integrated circuit under test based on the test script and the preset test vectors to obtain test results.

[0090] According to the above description, it can be seen that the circuit test platform can standardize test scripts and test steps, and provide an experimental platform and a large amount of test data support for the development of automated test technology and intelligent testing.

[0091] In an embodiment of the present disclosure, the circuit test platform includes a Pad Manager tool, a Matlab script generator, and a Matlab Test Runner program that is crucial for the platform to call Matlab API for multi-threaded automated testing.

[0092] The Pad Manager program mainly consists of three parts: the first part is responsible for reading the pad information of a specific circuit. Just select the excel file saving the chip information, and its content can be automatically read; the second module can load different preset test vectors. By setting the name of the test vector and modifying the specific values, and clicking save, it can be used during subsequent tests; the third part is a graphical user interface (GUI) that displays the pad information, allowing users to manually modify and save specific pad information. These information will be saved into the Python dictionary corresponding to this circuit for use in the generation of test scripts and the automated test process.

[0093] The responsibility of the Matlab script generator is to automatically generate all the required test scripts. In the early version of the present invention, this process required manually inputting the pad planning information of the test chip and splicing it with most fixed content to generate a.m file. However, practice has shown that the manual input method is not applicable to large circuits. Therefore, the present invention has optimized this process so that it can directly obtain the pad information saved by the Pad Manager and automatically generate test scripts.

[0094] After obtaining the input vector and test script, through the Matlab API interface, users can directly run Matlab using Python, connect to test instruments, and execute the test process. The Matlab API is an interface provided by Matlab official, which allows Python to call Matlab as a computing engine. The specific implementation steps are as follows: after setting the test parameters, start the Matlab engine through a specific function. During the actual test process, the test logic such as the control of the tester and the running of the script are all controlled by Python. The present invention also integrates this module into a multi-threaded framework. The advantage of multi-threading is that it can issue tasks in parallel and execute automatic tests serially in the background (considering that only one test rod can be used at the same time). Taking a certain CPU as an example, as Figure 3 shown, the current multi-threaded framework has been able to implement the following test process: First, thread 1 tests the first vector (reset) and obtains the correlation coefficient through comparison (the correlation coefficient is a function built in Matlab, which is between (-1, 1). Being close to 0 represents no correlation, and being close to ±1 indicates strong correlation); Subsequently, the second thread judges the test result according to this coefficient. If the correct output is not obtained, it can choose to end the test or perform heating treatment. For the same test vector, multiple threads can be set to perform multiple tests; if there is no result, the test of this chip is ended; if there is a result, continue. And so on, until the nth thread, switch to the next vector for testing. Through this process, the entire CPU can be tested.

[0095] To facilitate testers to customize test threads and avoid the burden of manually modifying Python code, the present invention also modularizes the test script and adopts graphical programming GUI, significantly reducing the usage threshold. As Figure 8 shown, the left side of the GUI contains all the logical modules required for testing. Testers can easily add the required modules, connect the front and back modules, and run the test task. Different threads can also be pre-bound by testers to share data. In addition, some common test processes can be saved for future direct use without re-building. Figure 8 In [figure] Heating represents heating, Init Probe represents initializing the instrument, Init Pad represents initializing the connection from the pad to the instrument, Measure Low-Temp Res represents measuring the low-temperature resistance, Random Pattern test represents randomly generating test vectors and performing tests, Init Supply represents initializing the power supply, Reset represents reset, Run MatlabTest represents conventional tests, and Default Pattern represents default test vectors.

[0096] Finally, this embodiment also adds a multi-dimensional particle swarm optimization algorithm test module, and the running process is asFigure 9 As shown, testers can use this module to replace the conventional bias scan module to perform a wider range of automatic bias scans. The entire bias adjustment process can be regarded as an optimization problem, abstracted as finding one or more sets of solution vectors in a multi-dimensional space to maximize the similarity between the actual output waveform and the expected output waveform. Therefore, a series of heuristic algorithms similar to the particle swarm algorithm are very suitable for such problems. The present invention appropriately improves the PSO (Particle Swarm Optimization) algorithm according to the superconducting circuit test process, adding the bias setting script and the chip output waveform reading script to the particle swarm algorithm. The multi-dimensional position vector of each particle corresponds to a multi-dimensional vector composed of the current values of all bias partitions of the chip. For example, if there are 13 partitions, the particle position is a 1×13 vector. The particle swarm will randomly update its position, similar to manually adjusted bias, but the speed is restricted to avoid exceeding the expected bias range and being less than the resolution of the measuring instrument. A random mutation function is also added to improve the coverage rate of bias adjustment. In multiple iterations, the PSO algorithm searches for the maximum value of the absolute value of the correlation coefficient, which represents the normal operation of the chip. The overall algorithm uses matrix calculations to improve the operation speed. Under the condition of scanning the same number of biases, the speed is four times that of manual bias scanning, drawing, and judging whether it is correct, which means that within the same time, the PSO algorithm can automatically scan more bias points.

[0097] Optionally, the process of the particle swarm algorithm may include:

[0098] Step 1: Randomly generate the initial positions of each particle, which represent the values of all bias partitions of the chip. The bias partition values can refer to the bias values of the chip partitions, and the partitions of the chip can be flexibly set according to the actual situation, which will not be elaborated in this embodiment.

[0099] Step 2: Calculate the objective function to obtain the historical maximum value (pbest) and the global maximum value (gbest) of a single particle, specifically by obtaining the absolute value of the correlation coefficient between the output and the expectation through power-on testing.

[0100] Step 3: Update the speeds and positions of all particles. The update speed of the particles can be flexibly set according to the actual situation, and this embodiment does not clearly limit it.

[0101] Step 4: Randomly mutate new speeds and positions, and return to Step 2.

[0102] Step 5: Determine whether the number of iterations has been reached. If so, return the optimal solution and exit the program to end. Otherwise, return to Step 3.

[0103] After completing the automated test, the platform will discretely store the test data with a higher correlation coefficient in the chip test project, reducing the occupied storage space and preparing for subsequent use.

[0104] In several embodiments provided by the present disclosure, it should be understood that the disclosed device or method can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of modules / units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple modules or units can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some interfaces. The indirect coupling or communication connection of devices or modules or units can be in electrical, mechanical or other forms.

[0105] The modules / units described as separate components may or may not be physically separated. The components shown as modules / units may or may not be physical modules, that is, they can be located in one place or distributed to multiple network units. Some or all of the modules / units can be selected according to actual needs to achieve the purpose of the embodiments of the present disclosure. For example, in each embodiment of the present disclosure, the various functional modules / units can be integrated in a processing module, or each module / unit can exist physically alone, or two or more modules / units can be integrated in one module / unit.

[0106] Those of ordinary skill in the art should further realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of the examples have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present disclosure.

[0107] Figure 10 is a schematic block diagram of an electronic terminal provided by an embodiment of the present application. As Figure 10 shown, the electronic terminal 1000 includes: at least one processor 1001, a memory 1002, at least one network interface 1003, and a user interface 1005. Each component in the device is coupled together through a bus system 1004. It can be understood that the bus system 1004 is used to realize the connection and communication between these components. In addition to including a data bus, the bus system 1004 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clear illustration, in Figure 10 all kinds of buses are labeled as the bus system.

[0108] Among them, the user interface 1005 may include a display, a keyboard, a mouse, a trackball, a pointing gun, a key, a button, a touchpad, or a touch screen, etc.

[0109] It can be understood that the memory 1002 can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM, Read Only Memory), a programmable read-only memory (PROM, Programmable Read-Only Memory), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM, Static Random Access Memory), synchronous static random access memory (SSRAM, Synchronous Static Random Access Memory). The memory described in the embodiments of the present invention is intended to include but not limited to these and any other suitable categories of memories.

[0110] The memory 1002 in the embodiments of the present invention is used to store various categories of data to support the operation of the electronic terminal 1000. Examples of these data include: any executable program for operating on the electronic terminal 1000, such as the operating system 10021 and the application program 10022; the operating system 10021 contains various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application program 10022 can include various application programs, such as a media player (Media Player), a browser (Browser), etc., for implementing various application services. Implementing the probability table update method provided by the embodiments of the present invention can be included in the application program 10022.

[0111] The method disclosed in the above embodiments of the present invention can be applied to or implemented by the processor 1001. The processor 1001 may be an integrated circuit chip with signal processing capabilities. During implementation, the steps of the above method can be completed by the integrated logic circuit in hardware or instructions in software form in the processor 1001. The above-mentioned processor 1001 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor 1001 can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. The general-purpose processor 1001 may be a microprocessor or any conventional processor, etc. Combining the steps of the accessory optimization method provided in the embodiments of the present invention can be directly embodied as being completed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium, which is located in the memory. The processor reads the information in the memory and combines its hardware to complete the steps of the foregoing method.

[0112] In an exemplary embodiment, the electronic terminal 1000 may be an application-specific integrated circuit (ASIC), a DSP, a programmable logic device (PLD), or a complex programmable logic device (CPLD) for executing the foregoing method.

[0113] The embodiments of the present disclosure also provide a computer-readable storage medium. Those of ordinary skill in the art can understand that all or part of the steps of implementing the method in the above embodiments can be completed by instructing the processor through a program. The program can be stored in a computer-readable storage medium, and the storage medium is a non-transitory medium, such as a random access memory, a read-only memory, a flash memory, a hard disk, a solid-state drive, a magnetic tape, a floppy disk, an optical disc, and any combination thereof. The above storage medium may be any available medium that the computer can access or a data storage device such as a server or a data center that includes one or more integrated available media. The available medium may be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a digital video disc (DVD)), or a semiconductor medium (such as a solid-state drive (SSD)), etc.

[0114] Embodiments of the present disclosure may also provide a computer program product, which includes one or more computer instructions. When the computer instructions are loaded and executed on a computing device, they generate, in whole or in part, the processes or functions described in the embodiments of the present disclosure. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from a website, computer, or data center to another website, computer, or data center by wire (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wirelessly (such as infrared, wireless, microwave, etc.).

[0115] When the computer program product is executed by a computer, the computer executes the method described in the foregoing method embodiments. The computer program product may be a software installation package. In the case where the foregoing method is required, the computer program product may be downloaded and executed on the computer.

[0116] The descriptions of the processes or structures corresponding to the foregoing various drawings each have their own emphases. For parts not detailed in a certain process or structure, reference may be made to the relevant descriptions of other processes or structures.

[0117] The foregoing embodiments merely illustrate the principles and effects of the present disclosure and are not intended to limit the present disclosure. Any person familiar with this technology may make modifications or changes to the foregoing embodiments without departing from the spirit and scope of the present disclosure. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present disclosure should still be covered by the claims of the present disclosure.

Claims

1. A circuit testing method, characterized in that, Including: Automatically read the pad information of the superconducting integrated circuit to be tested; Process the pad information through a script generator to automatically generate a test script; Call the computing engine and automatically connect the test instrument; Perform multi-threaded testing on the superconducting integrated circuit to be tested based on the test script and preset test vectors to obtain test results.

2. The circuit testing method according to claim 1, wherein The implementation method for performing multi-threaded testing on the superconducting integrated circuit to be tested based on the test script and preset test vectors to obtain test results includes: Based on the test script, preset test vectors, and preset expected results, test the superconducting integrated circuit to be tested through the first thread to obtain the correlation coefficient between the actual output result of the superconducting integrated circuit to be tested and the preset expected result; Process the correlation coefficient through the second thread to obtain test results; End the test according to the test results or perform a heating process on the superconducting integrated circuit to be tested.

3. The circuit testing method according to claim 2, wherein The implementation method for testing the superconducting integrated circuit to be tested through the first thread based on the test script, preset test vectors, and preset expected results to obtain the correlation coefficient between the actual output result of the superconducting integrated circuit to be tested and the preset expected result includes: Based on the test script, the preset test vectors, the preset expected results, the bias setting script of the superconducting integrated circuit to be tested, and the read output waveform script, use the particle swarm optimization algorithm to test the superconducting integrated circuit to be tested through the first thread to obtain the correlation coefficient. The preset expected result is the expected output waveform, and the correlation coefficient represents the coefficient when the actual output waveform of the superconducting integrated circuit to be tested has the highest similarity with the expected output waveform. Among them, the position of each particle represents the bias of all dimensions of the superconducting integrated circuit to be tested.

4. The circuit testing method according to claim 3, wherein The objective function of the particle swarm optimization algorithm is the absolute value of the correlation coefficient between the actual output waveform and the expected output waveform.

5. The circuit testing method according to claim 3, characterized in that The implementation method for testing the superconducting integrated circuit to be tested through the first thread using the particle swarm optimization algorithm to obtain the correlation coefficient further includes: Generate a random bias; If the particle is less than the preset mutation probability, mutate the position of the particle to the random bias. Otherwise, the position of the particle remains unchanged.

6. The circuit testing method according to claim 5, wherein The positions of the particles form a particle position matrix, and the random biases form a random bias matrix. The particle position matrix and the random bias matrix are of the same type. The implementation method for mutating the position of the particle to the random bias includes: Obtain the index of the particle in the particle position matrix when the position of the particle mutates; Obtain the random bias in the random bias matrix based on the index; Mutate the position of the particle to the random bias.

7. The circuit test method according to claim 1, characterized in that, The implementation method for performing multi-threaded testing on the superconducting integrated circuit to be tested based on the test script and preset test vectors to obtain test results includes: Based on the test script, preset test vectors, and preset expected results, test the superconducting integrated circuit to be tested through several threads to obtain a test result set; If all the test results in the test result set are test failures, end the test; Otherwise, the Nth thread tests the superconducting integrated circuit under test based on the next preset test vector, where N is a positive integer.

8. A circuit test platform, characterized in that, It includes: A pad management tool for reading the pad information of the superconducting integrated circuit under test, saving the loaded preset test vectors, and displaying the pad information; A script generator for processing the pad information to generate a test script; A test launcher for calling a computing engine and automatically connecting to a test instrument; A circuit test module for performing multi-threaded testing on the superconducting integrated circuit under test based on the test script and the preset test vectors to obtain test results.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the circuit test method according to any one of claims 1 to 7.

10. An electronic terminal, comprising a memory, a processor, and a computer program stored on the memory, characterized in that The processor executes the computer program to implement the circuit test method according to any one of claims 1 to 7.

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