Starting method, radar and terminal equipment

Abstract

The embodiment of the invention relates to the technical field of radars, in particular to a starting method, a radar and terminal equipment. The starting method comprises the steps that ADC data are coded according to a first starting signal, first data are obtained, and a clock of the first starting signal is an ADC clock; asynchronous FIFO processing is carried out on the first data to obtain second data, and a clock of the second data is an FMCW frequency division clock; and starting an FMCW emission waveform according to the second data. And the phase drift of the FMCW radar can be eliminated, so that the accuracy of a target measurement result can be improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of radar, and particularly to a startup method, a radar, and a terminal device. Background Art

[0002] A Frequency Modulated Continuous Wave (FMCW) radar is a radar that measures information such as the distance, speed, and direction of a target using an FMCW signal. Its principle is to use the frequency difference between the echo signal generated by the transmitted FMCW signal reflected by the target and the transmitted FMCW signal to achieve target measurement.

[0003] However, the current FMCW radar has a problem of excessive phase drift, which easily leads to inaccurate target measurement results. Summary of the Invention

[0004] The embodiments of the present application provide a startup method, a radar, and a terminal device, which are beneficial to eliminating the phase drift of the FMCW radar to improve the accuracy of target measurement results.

[0005] According to some embodiments of the present application, on the one hand, an embodiment of the present application provides a startup method, including: encoding ADC data according to a first startup signal to obtain first data, where the clock of the first startup signal is the ADC clock; performing asynchronous FIFO processing on the first data to obtain second data, where the clock of the second data is the FMCW divided-frequency clock; starting the FMCW transmission waveform according to the second data.

[0006] In some embodiments, the encoding ADC data according to the first startup signal to obtain first data includes: expanding the ADC data to obtain third data; processing the third data to obtain the first data.

[0007] In some embodiments, the expanding the ADC data to obtain third data includes: performing sign-bit expansion on the ADC data to obtain the third data; or merging preset data into the ADC data to obtain the third data.

[0008] In some embodiments, the processing the third data according to the first startup signal to obtain the first data includes: modifying the expanded additional data in the third data when the first startup signal is received to obtain the first data; and / or using the third data as the first data when the first startup signal is not received.

[0009] In some embodiments, starting the FMCW transmission waveform according to the second data includes: generating a third start signal according to the second data, where the clock of the third start signal is the FMCW divided-frequency clock; and starting the FMCW transmission waveform according to the third start signal.

[0010] In some embodiments, starting the FMCW transmission waveform according to the second data includes: starting the ADC data reception while starting the FMCW transmission waveform according to the second data.

[0011] Before encoding the ADC data according to the first start signal to obtain the first data in some embodiments, the method further includes: receiving a second start signal provided by a register, where the clock of the second start signal is the register clock; and sampling the second start signal according to the ADC clock to obtain the first start signal.

[0012] In some embodiments, performing asynchronous FIFO processing on the first data to obtain the second data includes: writing the first data with the ADC clock as the write clock, and reading the data content of the written first data with the FMCW divided-frequency clock as the read clock signal to obtain the second data.

[0013] According to some embodiments of the present application, another aspect of the embodiments of the present application further provides a radar, including: an ADC configured to generate and output ADC data; an encoder connected to the ADC and configured to encode the ADC data according to a first start signal to obtain first data; an asynchronous FIFO connected to the encoder and configured to receive the first data and perform asynchronous FIFO processing on the first data to obtain second data, where the clock of the second data is the FMCW divided-frequency clock; a decoder connected to the asynchronous FIFO and configured to receive the second data and start the FMCW transmission waveform according to the second data; and an FMCW module connected to the decoder and configured to start the FMCW transmission waveform according to the signal output by the decoder.

[0014] In some embodiments, it further includes a register connected to the encoder; the register is configured to generate and output a second start signal; and the encoder is further configured to receive the second start signal and sample the second start signal to obtain the first start signal.

[0015] In some embodiments, it further includes a processing module connected to the decoder, and the decoder is further configured to start the processing module according to the second data; the processing module is configured to start the ADC data reception according to the signal output by the decoder.

[0016] According to some embodiments of the present application, on the other hand, an embodiment of the present application further provides a terminal for implementing the startup method described in any of the foregoing embodiments, or including a radar described in any of the foregoing embodiments.

[0017] The technical solutions provided by the embodiments of the present application have at least the following advantages:

[0018] Since the first data is obtained by encoding the ADC data according to the first startup signal, the first data not only contains the ADC data but also implicitly contains the information of the first startup signal. Therefore, by performing asynchronous FIFO processing on the first data, the ADC data and the first startup signal can be forced to be synchronized to the FMCW division clock domain. Furthermore, when starting according to the second data, the FMCW transmission waveform can be completely synchronized with the startup of ADC data reception. That is to say, the startup error between the FMCW transmission waveform and ADC data reception is eliminated in the embodiments of the present application, which is beneficial to eliminating the phase drift of the FMCW radar and improving the accuracy of target measurement results. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] One or more embodiments are illustrated by way of example in the accompanying drawings, which illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, unless otherwise stated, and the figures in the drawings do not constitute a scale limitation.

[0020] Figure 1 is a flowchart of a startup method in the prior art;

[0021] Figure 2 is Figure 1 the signal timing waveform diagram corresponding to the startup method shown;

[0022] Figure 3 is a flowchart of another startup method in the prior art;

[0023] Figure 4 is Figure 3 the signal timing waveform diagram corresponding to the startup method shown;

[0024] Figure 5 is a flowchart of a startup method provided in the embodiments of the present application;

[0025] Figure 6 is another flowchart of a startup method provided in the embodiments of the present application;

[0026] Figure 7 is yet another flowchart of a startup method provided in the embodiments of the present application;

[0027] Figure 8It is a schematic structural diagram of a radar provided in an embodiment of the present application;

[0028] Figure 9 It is another schematic structural diagram of a radar provided in an embodiment of the present application;

[0029] Figure 10 It is yet another schematic structural diagram of a radar provided in an embodiment of the present application;

[0030] Figure 11 It is still another schematic structural diagram of a radar provided in an embodiment of the present application;

[0031] Figure 12 is based on the one provided in the embodiment of the present application Figure 11 shown radar, it is a schematic diagram of the processing flow of the startup method;

[0032] Figure 13 is based on the one provided in the embodiment of the present application Figure 12 The provided startup method's processing flow is used to provide a signal timing waveform diagram. Detailed implementation manners

[0033] As can be seen from the background art, the current FMCW radar has a problem of excessive phase drift.

[0034] Upon analysis, it is found that the reason for the above problems in the current FMCW radar is as follows: Since the FMCW radar needs to determine the frequency difference between the echo signal generated by the reflection of the transmitted FMCW signal by the target and the transmitted FMCW signal for target measurement, therefore, when the FMCW radar starts transmitting the FMCW signal at the transmitting end, it needs to start receiving the data of the Analog-to-Digital Converter (ADC) to facilitate subsequent digital signal processing and extraction of radar measurement information. At the same time, to avoid interference between transmitted signals, the FMCW radar also needs to start transmitting the next frame of FMCW signal at the transmitting end and start signal reception and processing at the receiving end after the transmission of the FMCW signal in the current frame and the ADC data processing are completed. Generally, in order to control the transmission and processing of multiple frames of FMCW, the FMCW radar will adopt a software-controlled hardware method to start the generation of the FMCW signal at the transmitting end and the reception of ADC data. Considering that the FMCW clock domain corresponding to the generation of the FMCW signal and the ADC clock domain where the ADC is located are two different clock domains, therefore, each time the software starts the FMCW transmission waveform and ADC data reception, it will inevitably cause a time delay, resulting in a phase drift between the generation of the FMCW signal and the reception of ADC data, thus affecting the accuracy of target measurement by the FMCW radar. In particular, for FMCW radars such as vehicle-mounted radars used to observe the internal (or external) environment of vehicles and radars used for vital sign monitoring, low measurement accuracy will pose a safety hazard in verification.

[0035] For this reason, a startup method has been proposed. As shown in Process 1, first, the register generates a startup signal based on the configuration data stored internally and outputs it. Then, both the FMCW signal generator and the ADC receive this startup signal and start the FMCW signal generator to generate the FMCW signal and start the ADC data reception to process the echo signal. Among them, since the startup signal is generated in the register, the clock domain of the startup signal output by the register is the register clock domain. And because the FMCW signal generator and the ADC have their own clock domains, before starting the FMCW signal generator and the ADC, the startup signal needs to be clock-synchronized based on the FMCW clock domain on the FMCW signal generator and based on the ADC clock domain on the ADC. In the above solution, generally, the frequency of the register clock domain is less than the frequency of the FMCW clock domain and the frequency of the ADC clock domain. Therefore, the maximum delay between the startup signal in the register clock domain and the startup signal synchronized to the FMCW clock domain can be one clock cycle of the FMCW clock domain, and the maximum delay between the startup signal in the register clock domain and the startup signal synchronized to the ADC clock domain can be one clock cycle of the ADC clock domain. Further, generally, the frequency of the FMCW clock domain is greater than the frequency of the ADC clock domain. Therefore, the maximum delay between the startup signal synchronized to the FMCW clock domain and the startup signal synchronized to the ADC clock domain may reach one clock cycle of the ADC clock domain, that is, the maximum delay between the startup of the FMCW signal generator and the startup of the ADC may reach one clock cycle of the ADC clock domain. Specifically, as Figure 2 shown, after the startup signal changes from invalid to valid, the first rising edge of the FMCW clock domain appears at time T1. Therefore, the startup timing indicated after the startup signal is synchronized to the FMCW clock domain is time T1; and after the startup signal changes from invalid to valid, the first rising edge of the ADC clock domain appears at time T2. Therefore, the startup timing indicated after the startup signal is synchronized to the ADC clock domain is time T2. Therefore, the delay between the startup of the FMCW signal generator and the startup of the ADC is T2 - T1, which is close to one clock cycle of the ADC clock domain.

[0036] Another startup method has also been proposed. As shown in Process 3, first, the register generates a startup signal based on the configuration data stored internally and outputs it. Then, the FMCW signal generator will receive the startup signal output by the register and synchronize it to the FMCW clock domain. The FMCW signal generator will also output a startup signal synchronized to the FMCW clock, and at the same time, start generating the FMCW signal based on the startup signal synchronized to the FMCW clock. After receiving the startup signal synchronized to the FMCW clock, the ADC will synchronize the startup signal synchronized to the FMCW clock to the ADC clock domain again to start the ADC. In the above solution, generally, the frequency of the FMCW clock domain is greater than that of the ADC clock domain. Therefore, the maximum delay between the startup signal synchronized to the FMCW clock domain and the startup signal synchronized to the ADC clock domain may reach one clock cycle of the ADC clock domain, that is, the maximum delay between the startup of the FMCW signal generator and the startup of the ADC may reach one clock cycle of the ADC clock domain. Specifically, as Figure 4 shown, after the startup signal changes from invalid to valid, the first rising edge of the FMCW clock domain appears at time T1. Therefore, the startup timing indicated after the startup signal is synchronized to the FMCW clock domain is time T3. At this time, the startup signal synchronized to the FMCW clock domain is as Figure 3 shown, and its first change from invalid to valid is at time T3. After time T3, the first rising edge of the ADC clock domain appears at time T4. Therefore, the startup timing indicated after the startup signal is synchronized to the ADC clock domain is time T4. Therefore, the delay between the startup of the FMCW signal generator and the startup of the ADC is T4 - T3, which is close to one clock cycle of the ADC clock domain.

[0037] That is to say, the current startup method can only control the phase drift of the FMCW radar within one clock cycle of the ADC clock domain, which is still relatively large.

[0038] To solve the above technical problems, an embodiment of the present application provides a startup method, a radar, and a terminal device. By encoding ADC data according to a first startup signal to obtain first data, performing asynchronous FIFO processing on the first data to obtain second data, and starting the FMCW transmission waveform and ADC data reception according to the second data, the phase drift of the FMCW radar is eliminated, and the accuracy of the target measurement result is improved. Among them, since the first data is obtained by encoding ADC data according to the first startup signal, the first data not only contains ADC data but also implicitly contains the information of the first startup signal. Therefore, performing asynchronous FIFO processing on the first data can force both the ADC data and the first startup signal to be synchronized to the FMCW division clock domain. Furthermore, when starting according to the second data, the startup of the FMCW transmission waveform and the ADC data reception can be fully synchronized. That is to say, compared with the prior art, the startup error between the FMCW transmission waveform and the ADC data reception will be controlled within one ADC clock cycle. The embodiment of the present application eliminates the startup error between the FMCW transmission waveform and the ADC data reception, which is beneficial to eliminating the phase drift of the FMCW radar and improving the accuracy of the target measurement result.

[0039] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present application, many technical details are provided to help readers better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions required to be protected by the present application can still be implemented.

[0040] The division of the following embodiments is for convenience of description and should not constitute any limitation on the specific implementation manner of the present application. The various embodiments can be combined and cross-referenced with each other on the premise of no conflict.

[0041] On the one hand, an embodiment of the present application provides a startup method applied to an FMCW radar. In some embodiments of the present application, the flow of the startup method is as Figure 5 shown, including the following steps:

[0042] Step 501: Encode the ADC data according to the first startup signal to obtain first data.

[0043] Step 502: Perform asynchronous FIFO processing on the first data to obtain second data.

[0044] Step 503: Start the FMCW transmission waveform according to the second data.

[0045] In this way, since the first data is obtained by encoding the ADC data according to the first start signal, the first data not only contains the ADC data but also implicitly contains the information of the first start signal. Therefore, performing asynchronous FIFO processing on the first data can force both the ADC data and the first start signal to be synchronized to the FMCW division clock domain. Furthermore, when starting according to the second data, the start of the FMCW transmission waveform and the reception of the ADC data can be started simultaneously. That is to say, compared with the prior art where the start error between the FMCW transmission waveform and the ADC data reception is controlled within one ADC clock cycle, this embodiment eliminates the start error between the FMCW transmission waveform and the ADC data reception, which is beneficial to eliminating the phase drift of the FMCW radar and improving the accuracy of the target measurement result.

[0046] To facilitate better understanding of the start method provided in the above embodiment by those skilled in the art, the following will be explained and illustrated.

[0047] In step 501, the ADC data is encoded according to the first start signal to obtain the first data. Among them, the clock of the first start signal is the ADC clock. It can be understood that the ADC clock is the working clock of the ADC.

[0048] It should be noted that this embodiment does not limit the source of the first start signal, which can be from any circuit, chip, unit, or module that can generate and output signals according to a certain strategy.

[0049] In some examples, encoding the ADC data according to the first start signal to obtain the first data can be achieved in the following way: expanding the ADC data to obtain the third data; processing the third data according to the first start signal to obtain the first data. It should be noted that this example does not limit the expansion method or the modification method. The following will explain it.

[0050] In some cases, expanding the ADC data to obtain the third data can be achieved in the following way: performing sign-bit expansion on the ADC data to obtain the third data. Taking the ADC data before expansion as N bits and the first data obtained by expanding the ADC data as M + N bits as an example, when the ADC data is positive, M bits of data 0 are added before the ADC data; when the ADC data is negative, M bits of data 1 are added before the ADC data, where "0" and "1" are the 0 and 1 defined in binary.

[0051] In this way, the value of the data corresponding to the expanded third data remains unchanged compared with the ADC data, avoiding modifying the value of the ADC data, which is beneficial to improving the accuracy of the ADC data transmission.

[0052] In some cases, the ADC data is expanded to obtain the third data, which can also be achieved in the following way: the preset data is merged into the ADC data to obtain the third data. Among them, this embodiment does not limit the data content of the preset data, which can be any binary combination. For example, the ADC data before expansion is N bits, and the first data obtained by expanding the ADC data is M+N bits. The preset data consists of N bits of data 0, or the preset data consists of N bits of data 1. This embodiment also does not limit the way of merging. For example, the preset data can be added to the front of the ADC data, or the preset data can be added to the back of the ADC data, or the preset data can be added to a specified position in the ADC data, etc. They will not be described one by one here.

[0053] In this way, the ADC data can be expanded through the preset data to achieve greater flexibility. In particular, in some cases, the preset data can also carry some information without the need for additional bits to transmit the information.

[0054] In some cases, the third data is processed according to the first start signal to obtain the first data, which can be achieved in the following manner: when the first start signal is received, the data added by the expansion in the third data is modified to obtain the first data; and / or, when the first start signal is not received, the third data is used as the first data. That is, if the first start signal is received, the third data is modified to obtain the first data, and if the first start signal is not received, the third data is not processed. In this way, whether the startup is required is determined by whether the first data carries the data feature corresponding to the expansion mode, so that the startup information is implicit in the ADC data.

[0055] In this way, on the basis of eliminating the phase drift of the FMCW radar and improving the accuracy of the target measurement results, when the first start signal is not received, the expanded ADC data can be maintained, so that a certain method can be used later to restore the ADC data, so that ADC data processing can be performed to detect the target. In other words, the startup process and the ADC data transmission process are combined, so that the startup process and the data processing process both include ADC data expansion and FIFO processing steps, so that part of the hardware can be shared without providing a set of additional hardware to support the startup method provided in the embodiment of the present application, which is conducive to reducing the complexity of the FMCW radar, the difficulty of layout design, etc.

[0056] Among them, regarding the modification of the data added during the mid-extension of the third data, the main purpose is to destroy the data characteristics added to the extended ADC data. For example, when extending with the sign bit, if there are consecutive "0"s or "1"s in the first data, it indicates that it is unmodified data, that is, the corresponding situation is: the first start signal is received. Therefore, to achieve the above purpose, the processing of the third data can be to modify the data added during the mid-extension of the third data. For example, randomly invert i bits of data, where i is a positive integer greater than 0 and less than M. Even, in some cases, the position of the i bits of data can be randomly selected from the high M bits of the third data, etc., which will not be elaborated here one by one.

[0057] Of course, the above is only an exemplary description. In some examples, when the first start signal is received, it can also be to replace the preset data with certain characteristics into the third data, or, in some examples, when using sign-bit extension and the first start signal is received, the third data can be used as the first data; and / or, when the first start signal is not received, modify the data added during the mid-extension of the third data to obtain the first data, etc., which will not be elaborated here one by one.

[0058] In step 502, perform asynchronous FIFO processing on the first data to obtain the second data. Among them, the clock of the second data is the FMCW divided clock. It can be understood that the FMCW divided clock is the working clock for generating the FMCW waveform.

[0059] It can be understood that the foregoing steps are for the first data obtained by encoding the ADC data. Therefore, the frequency of the first data is the clock of the ADC data, that is, the ADC clock. That is to say, step 502 is actually to convert the data from the ADC clock domain to the FMCW divided clock domain.

[0060] In some examples, performing asynchronous FIFO processing on the first data to obtain the second data can be achieved in the following way: perform a write operation on the first data with the ADC clock as the write clock, and perform a read operation on the data content of the written first data with the FMCW divided clock as the read clock signal to obtain the second data.

[0061] In this way, the first data is converted to obtain the second data through simple read and write operations, with low implementation difficulty, low cost, and high efficiency.

[0062] Of course, the above is only an exemplary description. In some examples, the conversion from the first data to the second data can also be achieved through sampling, which will not be elaborated here one by one.

[0063] In step 503, start the FMCW transmit waveform according to the second data.

[0064] In some examples, according to the second data, starting the FMCW transmission waveform can be achieved in the following way: according to the second data, generate a third start signal, where the clock of the third start signal is the FMCW divided clock; according to the third start signal, start the FMCW transmission waveform.

[0065] In this way, starting the FMCW transmission waveform and ADC data reception through the start signal is beneficial to improving the start efficiency.

[0066] It can be understood that although the source of the first start signal can be various, such as chips, registers, etc. However, if a relatively complex structure is introduced to provide the first start signal, it is easy to increase the complexity of the radar, the difficulty of design layout, etc., which is not conducive to production and application. Therefore, some embodiments of the present application also provide a start method, where the first start signal can come from a register. The flow of the provided start method is as Figure 6 shown, and the start method includes the following steps:

[0067] Step 601, receive the second start signal provided by the register, where the clock of the second start signal is the register clock.

[0068] Step 602, sample the second start signal according to the ADC clock to obtain the first start signal.

[0069] Step 603, encode the ADC data according to the first start signal to obtain the first data.

[0070] Step 604, perform asynchronous FIFO processing on the first data to obtain the second data.

[0071] Step 605, start the FMCW transmission waveform according to the second data.

[0072] Among them, steps 603 - 605 are substantially the same as steps 501 - 503 of the Figure 5 shown embodiment, and will not be elaborated here one by one.

[0073] In this way, providing the first start signal through a register with both a small area and volume is beneficial to reducing the design difficulty of the chip in the FMCW radar and reducing the cost of the FMCW radar.

[0074] It can be understood that the start method provided by the embodiments of the present application is mainly to achieve synchronization between the FMCW transmission waveform and ADC data reception. Therefore, the second data can also start ADC data reception, so that there is no need to provide a corresponding start signal to start ADC data reception. Based on this, in some embodiments, the flow of the start method is as Figure 7 shown, and includes the following steps:

[0075] Step 701: Encode the ADC data according to the first start signal to obtain the first data.

[0076] Step 702: Perform asynchronous FIFO processing on the first data to obtain the second data.

[0077] Step 703: Start the FMCW transmit waveform and ADC data reception according to the second data.

[0078] It should be noted that steps 701 - 702 in the above embodiments are substantially the same as steps 501 - 502 provided in the foregoing embodiments, and will not be elaborated herein one by one.

[0079] It should also be noted that step 703 in the above embodiments is substantially the same as step 503 provided in the foregoing embodiments. The main difference lies in that the starting objects include not only the FMCW transmit waveform but also the ADC data reception, and the start of the ADC data reception is substantially the same as the start of the FMCW transmit waveform. Therefore, it will not be elaborated herein one by one.

[0080] The step division of the above various methods is only for clear description. When implemented, they can be combined into one step or some steps can be split into multiple steps. As long as the same logical relationship is included, they are all within the protection scope of this patent; adding insignificant modifications to the algorithm or process or introducing insignificant designs, but not changing the core design of the algorithm and process, are all within the protection scope of this patent.

[0081] Another aspect of the embodiments of the present application further provides a radar, as Figure 8 shown, including: an ADC, an encoder, an asynchronous FIFO, a decoder, and an FMCW module.

[0082] Among them, the ADC is configured to generate and output ADC data; the encoder is connected to the ADC and is configured to encode the ADC data according to the first start signal to obtain the first data; the asynchronous FIFO is connected to the encoder and is configured to receive the first data and perform asynchronous FIFO processing on the first data to obtain the second data, where the clock of the second data is the FMCW divided clock; the decoder is connected to the asynchronous FIFO and is configured to receive the second data and start the FMCW transmit waveform according to the second data; the FMCW module is connected to the decoder and is configured to start the FMCW transmit waveform according to the signal output by the decoder.

[0083] In this way, since the encoder encodes the ADC data according to the first start signal, the first data output by the encoder contains the ADC data and also implicitly contains the information of the first start signal. Thus, when the asynchronous FIFO processes the first data asynchronously, the ADC data and the first start signal in the second data can be forced to be synchronized to the FMCW division clock domain. Furthermore, when starting according to the second data through the third start signal generated by the encoder, the start of the FMCW transmission waveform can be fully synchronized with the start of the ADC data reception. That is to say, compared with the prior art where the start error between the FMCW transmission waveform and the ADC data reception will be controlled within one ADC clock cycle, in this embodiment, the start error between the FMCW transmission waveform and the ADC data reception is eliminated, which is beneficial to eliminating the phase drift of the FMCW radar and improving the accuracy of the target measurement result.

[0084] In some embodiments, as Figure 9 shown, the radar further includes a register connected to the encoder, where the register is configured to generate and output a second start signal. Correspondingly, the encoder is further configured to receive the second start signal and sample the second start signal to obtain the first start signal.

[0085] It should be noted that Figure 9 the ADC, encoder, asynchronous FIFO, decoder, and FMCW module in the embodiment shown in Figure 8 have substantially the same connection relationship and functions as the encoder, asynchronous FIFO, decoder, and FMCW module in the embodiment shown in Figure 9 . The main difference is that

[0086] in Figure 10 the encoder is also connected to the register, so the encoder also has the function of receiving the second start signal and sampling the second start signal to obtain the first start signal. The same parts will not be elaborated here one by one.

[0086] In some embodiments, as Figure 10 shown, the radar further includes a processing module connected to the decoder. Correspondingly, the decoder is further configured to start the processing module according to the second data. The processing module is configured to start the ADC data reception according to the signal output by the decoder.

[0087] It should be noted that Figure 10 the ADC, encoder, asynchronous FIFO, decoder, and FMCW module in the embodiment shown in Figure 8 have substantially the same connection relationship and functions as the encoder, asynchronous FIFO, decoder, and FMCW module in the embodiment shown in Figure 10In the figure, the decoder is further connected to the processing module, so that the decoder also has the function of controlling the start of the processing module according to the second data. The same parts will not be described in detail here.

[0088] It should also be noted that Figure 8 - 10 The illustrated embodiments are only exemplary descriptions of the components of the radar and their connection relationships. In some embodiments, the components of the radar and their connection relationships may also be as Figure 11 shown. The radar Figure 9 and Figure 10 On the basis of the illustrated embodiments, the radar further includes a sampler. The register is no longer connected to the ADC, but is connected to the encoder through the sampler. The process of sampling the second start signal generated by the register to obtain the first start signal occurs on the sampler, rather than on the ADC. Furthermore, the first start signal will be output from the sampler to the encoder, etc. This will not be described in detail here.

[0089] It is not difficult to find that the above embodiments are product embodiments corresponding to the method embodiments, and the above embodiments can be implemented in cooperation with the method embodiments. The relevant technical details mentioned in the method embodiments are still valid in the above embodiments. To avoid repetition, they will not be described here. Correspondingly, the relevant technical details mentioned in the above embodiments can also be applied to the method embodiments.

[0090] It is worth mentioning that each component of the radar involved in the product embodiments can be a physical unit, a part of a physical unit, or a combination of multiple physical units in actual applications. In addition, to highlight the innovative part of this application, units that are not closely related to solving the technical problems proposed in this application are not introduced in the product embodiments, but this does not mean that there are no other units in the product embodiments.

[0091] To facilitate those skilled in the art to better understand the technical solutions provided by the embodiments of this application, the following will take the Figure 11 shown radar as an example, and in combination with the Figure 12 shown signal flow process, Figure 13 shown signal timing diagram, illustrate the start method and the achievable effects.

[0092] As Figure 12As described above, the operating clock of the register is the register clock. Therefore, the clock of the second start signal generated by the register is the register clock; the operating clock of the ADC is the ADC clock. Therefore, the clock of the ADC data generated and output by the ADC is the ADC clock. Obviously, there is a clock difference between the ADC clock and the register clock, and the ADC data cannot be directly encoded according to the second start signal. Otherwise, time delay will occur. Therefore, the register inputs the second start signal into the sampler. In this way, when the sampler uses the ADC clock as the sampling clock, the sampler will be able to convert the clock domain of the signal to the ADC clock domain, that is, the sampler converts the second start signal with the register clock as the clock to the second start signal with the ADC clock as the clock and outputs it to the encoder. The encoder can then process the third data obtained by expanding the ADC data according to the second start signal to obtain the first data. Furthermore, the FIFO will perform FIFO processing on the received first data and output it to the encoder. The encoder decodes the received data and detects the decoding result. For example, it detects whether it includes preset data (such as whether it is all 0 or all 1) to confirm whether the received data has been encoded with the ADC data according to the first start signal, that is, to confirm whether a start signal has been generated currently: when it is detected that the decoding result does not contain the preset data, that is, a start signal has been generated currently. Therefore, the encoder needs to generate a third start signal and output it to the FMCW module and the processing module respectively to start the FMCW transmission waveform and ADC data reception; when it is detected that the decoding result contains the preset data, that is, a start signal has not been generated currently. Therefore, the encoder gives the data content of the ADC data in the decoding result to the processing module for data processing to achieve the measurement of information such as the target speed, angle, and distance.

[0093] As Figure 13 shown, taking the extension of the ADC data as an example of sign-bit extension, when the start timing (T5) arrives, the register generates and outputs the second start signal, that is, the signal output by the register changes from invalid to valid at the T5 moment, forming the second start signal. When the second start signal is sampled with the ADC clock as the sampling clock, it is sampled at the first ADC clock rising edge (T6 moment) after the T5 moment, and only one ADC clock cycle is collected, thereby generating the first start signal that is valid from the T6 moment to the T7 moment. The ADC data corresponding to the first ADC clock rising edge after the valid part of the first start signal appears will trigger the action of modifying the data after expanding the ADC data according to the first start signal, so that the encoder outputs the first data (i.e., Figure 13The first data represented by the filled part in the middle forms the second data represented by the shaded part in the back-end. At this time, the value of the first data no longer corresponds to the value of the ADC data, while the result after the extension of the ADC data output at other times is not modified. Therefore, the value of the first data at other times corresponds to the value of the ADC data. Further, the first data is input into the asynchronous FIFO. Among them, since the read clock of the asynchronous FIFO is the FMCW divided clock, the output of the asynchronous FIFO needs to wait for the first rising edge of the FMCW divided clock after the first ADC data. That is, the second data output by the asynchronous FIFO has a time delay of one FMCW divided clock cycle relative to the input first data. That is, the asynchronous FIFO starts to output data from T9. Therefore, the encoder can determine whether to start the FMCW transmission waveform according to whether the decoded result data includes consecutive multiple bits all being 0 or all being 1 starting from the first bit. Therefore, the encoder will detect at T10 that the decoded result data no longer includes consecutive multiple bits all being 0 or all being 1 starting from the first bit, thereby determining that the FMCW transmission waveform needs to be started currently, and then generating a third start signal and outputting it to the FMCW module and the processing module, so as to start the FMCW module to perform FMCW waveform transmission at T10, and start the processing module to receive ADC data. From Figure 13 It can be seen that the start-up time delay between the FMCW module and the processing module is completely eliminated.

[0094] On the other hand, an embodiment of the present application further provides a terminal device. The terminal device includes a radar provided in any previous embodiment, and can be components and products applied to fields such as transportation, consumer electronics, monitoring, in-cabin detection, and healthcare. For example, the terminal can be an intelligent transportation device (such as a car, motorcycle, ship, subway, train, etc.), a security device (such as a camera), a liquid level / flow rate detection device, an intelligent wearable device (such as a bracelet, glasses, etc.), a smart home device (such as a sweeping robot, a door lock, a TV, an air conditioner, a smart light, etc.), various communication devices (such as a mobile phone, a tablet computer, etc.), and various industrial robotic arms (or robots) such as a gate, an intelligent traffic light, an intelligent sign, a traffic camera, etc., and can also be various instruments for detecting life characteristic parameters and various devices equipped with the instrument, such as in-cabin detection of a car, indoor personnel monitoring, intelligent medical devices, consumer electronic devices, etc.

[0095] In yet another alternative embodiment, when the above terminal is applied to an Advanced Driving Assistance System (ADAS), the wireless electrical device as an in-vehicle sensor can provide various functional safety guarantees for the ADAS system, such as automatic emergency braking (i.e., AEB), blind spot detection (BSD), lane change assist warning (i.e., LCA), and rear cross-traffic alert (i.e., RCTA).

[0096] It is not difficult to find that this embodiment is a device embodiment corresponding to the radar embodiment, and this embodiment can be implemented in cooperation with the radar embodiment. The relevant technical details mentioned in the radar embodiment are still valid in this embodiment, and in order to reduce repetition, they will not be elaborated here. Correspondingly, the relevant technical details mentioned in this embodiment can also be applied to the circuit embodiment.

[0097] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present application, and in actual applications, various changes can be made to them in form and details without departing from the spirit and scope of the present application.

Claims

1. A startup method, characterized in that, Including: Encoding the ADC data according to a first start signal to obtain first data, wherein the clock of the first start signal is the ADC clock; Performing asynchronous FIFO processing on the first data to obtain second data, wherein the clock of the second data is the FMCW divided-frequency clock; Starting the FMCW transmission waveform according to the second data.

2. The starting method according to claim 1, wherein The encoding the ADC data according to the first start signal to obtain first data includes: Expanding the ADC data to obtain third data; Processing the third data according to the first start signal to obtain the first data.

3. The starting method according to claim 2, characterized in that, The expanding the ADC data to obtain third data includes: Performing sign-bit expansion on the ADC data to obtain the third data; Or, Merging preset data into the ADC data to obtain the third data.

4. The starting method according to claim 2, characterized in that, The processing the third data according to the first start signal to obtain the first data includes: When the first start signal is received, modifying the extended additional data in the third data to obtain the first data; and / or, When the first start signal is not received, using the third data as the first data.

5. The starting method according to any one of claims 1 to 4, characterized in that, The starting the FMCW transmission waveform according to the second data includes: Generating a third start signal according to the second data, wherein the clock of the third start signal is the FMCW divided-frequency clock; Starting the FMCW transmission waveform according to the third start signal.

6. The starting method according to any one of claims 1 to 4, characterized in that The starting the FMCW transmission waveform according to the second data includes: When starting the FMCW transmission waveform according to the second data, starting to receive ADC data at the same time.

7. The starting method according to any one of claims 1 to 4, characterized in that, Before the encoding the ADC data according to the first start signal to obtain first data, the method further includes: Receiving a second start signal provided by a register, wherein the clock of the second start signal is the register clock; Sampling the second start signal according to the ADC clock to obtain the first start signal.

8. The startup method according to any one of claims 1 to 4, characterized in that The performing asynchronous FIFO processing on the first data to obtain second data includes: Writing the first data with the ADC clock as the write clock, and reading the data content of the written first data with the FMCW divided-frequency clock as the read clock signal to obtain the second data.

9. A radar, characterized in that, Including: An ADC configured to generate and output ADC data; An encoder connected to the ADC and configured to encode the ADC data according to a first start signal to obtain first data; An asynchronous FIFO connected to the encoder and configured to receive the first data and perform asynchronous FIFO processing on the first data to obtain second data, wherein the clock of the second data is the FMCW divided-frequency clock; A decoder connected to the asynchronous FIFO and configured to receive the second data and start the FMCW transmission waveform according to the second data; An FMCW module connected to the decoder and configured to start the FMCW transmission waveform according to the signal output by the decoder.

10. The radar according to claim 9, characterized in that, It further includes a register connected to the encoder; The register is configured to generate and output a second start signal; The encoder is further configured to receive the second start signal and sample the second start signal to obtain the first start signal.

11. The radar according to claim 9 or 10, characterized in that, It further includes a processing module connected to the decoder, The decoder is further configured to start the processing module according to the second data; The processing module is configured to start ADC data reception according to the signal output by the decoder.

12. A terminal device, characterized in that, It is used to implement the start method according to any one of claims 1 to 8, or includes a radar according to any one of claims 9 to 11.

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