Preparation method of display panel and halftone mask plate

Abstract

The invention relates to the technical field of display, in particular to a preparation method of a display panel and a halftone mask plate, and aims to solve the problem of how to optimize the removal effect of an inorganic encapsulation layer in a cutting channel region on the premise of not additionally increasing the burden of a mask process. The method comprises the following steps: patterning a photoresist layer by using a halftone mask plate; the patterned photoresist layer is used as a mask for etching, and the etching depth of the cutting channel region is a first depth, so that at least the touch interlayer dielectric layer and a part of the inorganic packaging layer at the cutting channel region are removed; the etching depth of the lap joint hole region is a second depth, so that the touch interlayer dielectric layer at the lap joint hole region is removed, and the metal layer located below the touch interlayer dielectric layer is exposed to form a lap joint hole; the first depth is greater than the second depth. On the premise of not additionally increasing the burden of the mask process, the removal effect of the inorganic encapsulation layer is optimized, the reliability of the panel is improved, and the manufacturing cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to a method for manufacturing a display panel and a halftone mask. Background Art

[0002] With the booming development of the active matrix organic light emitting diode (AMOLED) technology, more and more users pursue a more extreme narrow bezel design, or even a curved bezel design. However, this brings greater process challenges. Especially during the encapsulation process (EN), the inherent process characteristics cause a chemical vapor deposition (CVD) shadow effect to form around the panel.

[0003] Since the CVD layer is mainly composed of silicon nitride (SiNx) and silicon oxide (SiOx), such inorganic materials are highly brittle. As the panel bezel gradually becomes narrower, the thickness increase of the deposition layer caused by the CVD shadow effect cannot be ignored, reaching an increase of about 6000 angstroms. When the thickened position is above or near the scribe lane, during the subsequent laser cutting process, cracks are likely to occur at the edges of the inorganic layer. These cracks may further expand during the reliability test and extend to the active area (AA), resulting in the problem of poor GDS (black spot growth), and ultimately leading to failure.

[0004] To address the above problems, the industry usually optimizes by adding an extra mask process. A typical solution is to introduce a touch layer etching (TCE, TSP CVD Etch) mask process during manufacturing to thin the CVD inorganic layer on the MDL scribe lane (including three sides and the hole area), thereby preventing cracks from spreading to the AA area and improving the reliability of the panel. However, the existing processing solutions have problems such as complex process steps, increased manufacturing costs, reduced production efficiency, and impact on the yield rate, and have obvious limitations.

[0005] Correspondingly, there is a need in the art for a new manufacturing solution for display panels to solve the above problems. Summary of the Invention

[0006] To overcome the above defects, the present application is proposed to solve or at least partially solve the technical problem of how to optimize the removal effect of the inorganic encapsulation layer in the scribe lane area without adding an extra burden to the mask process.

[0007] In a first aspect, the present application provides a method for manufacturing a display panel, including:

[0008] A substrate is provided, which has a display area and a peripheral area surrounding the display area. The peripheral area includes a bonding area located on one side of the display area. A dicing channel area is provided in the display area and the peripheral area, and a lapping hole area is provided in at least one of the display area and the peripheral area.

[0009] A functional layer, an inorganic encapsulation layer, and a touch interlayer dielectric layer are sequentially formed on the substrate. Among them, a first metal layer is further formed between the inorganic encapsulation layer and the touch interlayer dielectric layer in the lapping hole area.

[0010] A photoresist layer is formed on the surface of the touch interlayer dielectric layer.

[0011] The photoresist layer is patterned. Among them, the patterning uses a halftone mask to completely remove the photoresist layer at the dicing channel area and retains the photoresist layer at the lapping hole area with a preset thickness.

[0012] Etching is performed using the patterned photoresist layer as a mask. Among them, the etching depth of the dicing channel area is a first depth, so as to at least remove the touch interlayer dielectric layer and part of the inorganic encapsulation layer at the dicing channel area; the etching depth of the lapping hole area is a second depth, so as to remove the touch interlayer dielectric layer at the lapping hole area and expose the first metal layer to form a lapping hole; the first depth is greater than the second depth.

[0013] In a technical solution of the above method for manufacturing a display panel, a barrier layer is further provided between the touch interlayer dielectric layer and the inorganic encapsulation layer; the etching using the patterned photoresist layer as a mask further includes:

[0014] Removing the touch interlayer dielectric layer, the barrier layer, and part of the inorganic encapsulation layer at the dicing channel area.

[0015] In a technical solution of the above method for manufacturing a display panel, the dicing channel area includes:

[0016] A first dicing channel area located in the peripheral area, including an area opposite to the bonding area and areas on both sides of the bonding area, where the opposite area and the areas on both sides are respectively preset with dicing channel positions; and

[0017] A second dicing channel area located in the display area, where a hole dicing channel position is preset in the second dicing channel area.

[0018] In a technical solution of the above method for manufacturing a display panel, the first depth is 10000 - 12000 angstroms; the second depth is 4000 - 6000 angstroms.

[0019] In a technical solution of the above method for manufacturing a display panel, the first depth is d1, the second depth is d2, the etching rate for the touch interlayer dielectric layer and the inorganic encapsulation layer is a, and the etching rate for the photoresist layer is b;

[0020] The preset thickness is (d1 - d2) / a * b.

[0021] In a technical solution of the above method for manufacturing a display panel, the etching time t of the etching is the ratio of the first depth d1 to the etching rate a.

[0022] In a technical solution of the above method for manufacturing a display panel, after etching using the patterned photoresist layer as a mask, it further includes:

[0023] Form a second metal layer on the surface of the touch interlayer dielectric layer, the second metal layer fills the overlapping holes and contacts the first metal layer.

[0024] In a technical solution of the above method for manufacturing a display panel, the method further includes:

[0025] Form a first organic protection layer on the second metal layer and the exposed touch interlayer dielectric layer;

[0026] Form a second organic protection layer on the surface of the first organic protection layer.

[0027] In a second aspect, a halftone mask is provided, which is applied to the method for manufacturing a display panel according to any one of the above technical solutions; wherein,

[0028] The transmittance of the position corresponding to the overlapping hole area of the halftone mask is designed to be Tr = (a × c - d2 × b) / (d1 × b), where a is the etching rate for the touch interlayer dielectric layer and the inorganic encapsulation layer, b is the etching rate for the photoresist layer, c is the thickness of the pre-coated photoresist layer, d1 is the first depth to be achieved, and d2 is the second depth to be achieved.

[0029] In a technical solution of the above halftone mask, the transmittance of the position corresponding to the scribe line area of the halftone mask is designed to be 100%.

[0030] One or more of the above technical solutions of the present application have at least one or more of the following beneficial effects:

[0031] In the technical solution of the method for manufacturing a display panel provided by the present application, without additionally increasing the burden of the mask process, the removal effect of the inorganic encapsulation layer in the scribe line area and the overlapping hole area is optimized, the reliability of the panel is improved, and the manufacturing cost is reduced. Description of the Drawings

[0032] Referring to the accompanying drawings, the disclosure of the present application will become more understandable. It is easily understood by those skilled in the art that these drawings are only for illustrative purposes and are not intended to limit the scope of protection of the present application. Among them:

[0033] Figure 1 is a schematic flowchart of a method for manufacturing a display panel provided by an embodiment of the present application;

[0034] Figure 2 is a schematic structural diagram of a display panel provided by an embodiment of the present application;

[0035] Figure 3 is a schematic cross-sectional view of a display panel provided by an embodiment of the present application;

[0036] Figures 4A - 4C is a schematic cross-sectional view of steps of a method for manufacturing a display panel provided by an embodiment of the present application;

[0037] Figures 5A - 5C is a schematic cross-sectional view of steps of another method for manufacturing a display panel provided by an embodiment of the present application;

[0038] Figures 6A - 6E is a schematic cross-sectional view of steps of another method for manufacturing a display panel provided by an embodiment of the present application. Detailed Embodiments

[0039] Some embodiments of the present application will be described below with reference to the accompanying drawings. It should be understood by those skilled in the art that these embodiments are only used to explain the technical principle of the present application and are not intended to limit the scope of protection of the present application.

[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present application without creative efforts shall fall within the scope of protection of the present application.

[0041] Unless otherwise defined, the technical terms or scientific terms used in this application shall have the ordinary meanings as understood by those of ordinary skill in the art to which this application pertains. The terms "first", "second" and similar terms used in this application do not denote any order, quantity or importance, but are only used to distinguish different components. Words such as "comprising" or "including" mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "upper", "lower", "left" and "right" are only used to indicate relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0042] In the current AMOLED display panel, the main function of the Touch Layer Dielectric (TLD) layer is to form electrode overlap holes. For the related TLD layer etching process, its etching ability is about 5000 angstroms. It is difficult to meet the removal effect of the inorganic encapsulation layer (such as SiNx) in the scribe line area only relying on this process. Therefore, the current process usually introduces the TCE process and additionally adds a mask (TCE Mask) to thin the inorganic encapsulation layer.

[0043] If one attempts to achieve sufficient SiNx removal by simply prolonging the etching time of the TLD layer, many negative impacts will be brought, such as the opening of the AA area and other areas becoming larger, affecting device performance; the sidewall angle (Taper) being too steep, affecting the compatibility of subsequent processes; over-etching of the metal layer, which may lead to problems such as electrical connection failure or performance degradation, and it is impossible to effectively remove the SiNx layer in the scribe line area while ensuring reliability.

[0044] Based on this, this application provides a method for manufacturing a display panel, which optimizes the removal effect of the inorganic encapsulation layer in the scribe line area and the overlap hole area without additionally increasing the burden of the masking process.

[0045] Figure 1 is a schematic flow chart of a method for manufacturing a display panel provided by an embodiment of this application. As Figure 1 shown, this method mainly includes the following steps S1 to S5.

[0046] Step S1, provide a substrate.

[0047] Combined Figure 2Schematic structural diagram of the display panel shown. The substrate 20 has a display area AA and a peripheral area NAA surrounding the display area AA, that is, a non-display area. The peripheral area NAA includes a bonding area BA on one side of the display area AA, which is usually located below the display area AA and is an area for connecting a driving IC (driving chip) or an FPC (flexible printed circuit board).

[0048] Meanwhile, a scribing lane area 21 is provided in the display area AA and the peripheral area NAA, and a via hole area 22 is provided in at least one of the display area AA and the peripheral area NAA.

[0049] Among them, the scribing lane area 21 is used for the panel dicing process, which refers to the area near the panel scribing lane where the inorganic encapsulation layer needs to be thinned, including but not limited to the first scribing lane area 21a in the peripheral area NAA, including the area opposite to the bonding area BA and the areas on both sides of the bonding area BA, where scribing lane positions are preset in the opposite area and the areas on both sides respectively; and the second scribing lane area 21b in the display area AA, where a via scribing lane position is preset in the second scribing lane area 21b.

[0050] Specifically, the first scribing lane area 21a corresponds to the module scribing lanes on three sides (except the side of the bonding area BA) of the display panel and is mainly used for dicing the panel during the module manufacturing process; the second scribing lane area 21b corresponds to the scribing lanes of specific functional holes such as camera openings and sensor areas.

[0051] By etching the scribing lane area 21, the thickness of the inorganic encapsulation layer can be thinned, thereby reducing the stress concentration and the risk of crack propagation during the cutting process. In the subsequent panel dicing process, the scribing lane is usually located in the middle of the scribing lane area 21 to ensure the cutting accuracy and reliability.

[0052] Optionally, the via hole area 22 is provided in specific areas of the display area AA and the peripheral area NAA and is used for electrical connection of different conductive layers, including but not limited to the 22a area for electrical connection between conductive layers in the display area AA or signal trace areas, and the 22b area for electrical connection between conductive layers in the IC bonding area.

[0053] Please refer to Figure 3 Schematic cross-sectional diagram of the shown display panel. The method for manufacturing the display panel further includes the following steps:

[0054] Step S2, a functional layer 201, an inorganic encapsulation layer 202, and a touch interlayer dielectric layer 203 are sequentially formed on the substrate 20. Among them, a first metal layer 204 is further formed between the inorganic encapsulation layer 202 and the touch interlayer dielectric layer 203 in the via hole area 22.

[0055] Among them, the functional layer 201 may include, but is not limited to, layer structures such as a TFT (Thin Film Transistor) layer, a light-emitting layer, etc.

[0056] Optionally, the inorganic encapsulation layer 202 may be formed by a chemical vapor deposition (CVD) process, abbreviated as the CVD layer. Figure 2 The L3 boundary shown in is the boundary of the CVD layer. In some embodiments, below the inorganic encapsulation layer 202, there are also other layer structures formed by the CVD process with different boundaries, such as the CVD1 and CVD2 layers. Figure 2 The L1 boundary shown in is the boundary of the CVD1 layer, and the L2 boundary is the boundary of the CVD2 layer.

[0057] In the embodiments of the present application, the touch interlayer dielectric layer 203 may also be referred to as the TLD layer, and its boundary is Figure 2 the L3 boundary shown in. The above-mentioned inorganic encapsulation layer 202 and touch interlayer dielectric layer 203 are both inorganic material layers. Exemplarily, the preparation materials thereof can be selected from inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride.

[0058] It can be understood that for the touch display panel, the first metal layer 204 is a patterned metal layer, specifically, it can be an outer touch metal (touch metal a, TMA) layer. Subsequently, an inner touch metal (touch metal b, TMB) layer still needs to be further formed. The TMA layer and the TMB layer work together to achieve precise touch operations; the touch interlayer dielectric layer 203 is used to isolate the above-mentioned TMA layer and TMB layer. In addition, the first metal layer 204 can also be other metal layer structures to be formed for electrical connection.

[0059] It should be noted that the first metal layer 204 is not only disposed in the overlap hole region 22. Those skilled in the art can arrange the first metal layer 204 on the display panel as needed.

[0060] Step S3, form a photoresist layer (Photoresist, PR) on the surface of the touch interlayer dielectric layer 203.

[0061] Optionally, the photoresist layer can be a positive photoresist (Positive PR), which undergoes photodegradation after exposure and is removed during the development process; or it can be a negative photoresist (Negative PR), which undergoes a polymerization reaction after exposure and the unexposed areas are removed during the development process. In the subsequent steps, the present application will take the positive photoresist as an example to illustrate the preparation method of the display panel.

[0062] Step S4: Pattern the photoresist layer. Specifically, in this patterning process, a halftone mask is used to completely remove the photoresist layer in the scribe lane area 21, while retaining the photoresist layer in the overlap hole area 22 with a preset thickness.

[0063] In some embodiments, the preset thickness can be calculated based on the required depths of etching the scribe lane area 21 and the overlap hole area 22. If the etching depth of the scribe lane area 21 is the first depth d1, the etching depth of the overlap hole area 22 is the second depth d2, the etching rate of the touch interlayer dielectric layer 203 and the inorganic encapsulation layer 202 is a, and the etching rate of the photoresist layer is b, then the preset thickness is (d1 - d2) / a * b.

[0064] By designing different transmittances for the halftone masks corresponding to different regions of the display panel, the exposure dose is thereby changed, achieving the adjustment of the photoresist layer thickness. Thus, the purpose of simultaneously etching the scribe lane area 21 and the overlap hole area 22 can be achieved through a single mask etching process.

[0065] Step S5: Etch using the patterned photoresist layer as a mask. Among them, the etching depth of the scribe lane area 21 is the first depth d1, so as to at least remove the touch interlayer dielectric layer 203 and part of the inorganic encapsulation layer 202 in the scribe lane area 21; the etching depth of the overlap hole area 22 is the second depth d2 (as Figure 6A shown), so as to remove the touch interlayer dielectric layer 203 in the overlap hole area 22, exposing the first metal layer 204 to form an overlap hole; the first depth d1 is greater than the second depth d2.

[0066] In one embodiment, the first depth d1 is 10000 - 12000 angstroms; the second depth d2 is 4000 - 6000 angstroms.

[0067] Optionally, when the etching rate of the touch interlayer dielectric layer 203 and the inorganic encapsulation layer 202 is a, the etching time t for the above etching is the ratio of the first depth d1 to the etching rate a, that is, t = d1 / a. That is, the etching time t should at least meet the requirement of completing the etching of the deepest part of this thinning process.

[0068] Optionally, in one embodiment, please refer to Figures 4A - 4C the cross-sectional schematic diagram of the steps of the method for manufacturing a display panel shown, which specifically shows a cross-sectional schematic diagram of a display panel in the MM' direction.

[0069] In some embodiments, the display panel further includes a barrier layer 205, also known as the Bar layer, which can block moisture, oxygen, etc. from entering the functional layer 201, ensuring the reliability of the display panel. The boundary of the barrier layer 205 is also the L3 boundary.

[0070] As shown in Figure 4A , the etching boundary therein is the etching boundary of the first cutting channel region 21a. In this embodiment, its first depth d1 = 11,000 angstroms. Correspondingly, the etching time t = 11,000 / a.

[0071] A barrier layer 205 is further provided between the touch interlayer dielectric layer 203 and the inorganic encapsulation layer 202. Therefore, when etching with the patterned photoresist layer as a mask, it further includes:

[0072] Removing the touch interlayer dielectric layer 203, the barrier layer 205 and a part of the inorganic encapsulation layer 202 in the cutting channel region 21.

[0073] After the etching is completed, the structure as shown in Figure 4B is obtained. Among them, the touch interlayer dielectric layer 203 and the barrier layer 205 within the etching boundary are completely removed, and the inorganic encapsulation layer 202 can be completely removed or partially retained according to needs (refer to Figure 5B ).

[0074] As shown in Figure 4C , after etching with the patterned photoresist layer as a mask, it is necessary to further form a first organic protection layer 206 and a second organic protection layer 207.

[0075] Optionally, for the touch display panel, the first organic protection layer 206 is also called a TOC (touch overcoat) layer.

[0076] Optionally, the second organic protection layer 207 is formed by an inkjet printing (IJP) process. Since there is usually also a 1st IJP layer formed by the IJP process on the side of the inorganic encapsulation layer 202 close to the functional layer 201, the second organic protection layer 207 in this embodiment can also be called the 2nd IJP layer.

[0077] Optionally, in another embodiment, please refer to the cross-sectional schematic diagram of the steps of the method for manufacturing a display panel as shown in Figures 5A - 5C , which specifically shows a cross-sectional schematic diagram of a display panel in the NN' direction.

[0078] As shown in Figure 5A , the etching boundary therein is the etching boundary of the second cutting channel region 21b. In this embodiment, its first depth d1 = 11,000 angstroms. Correspondingly, the etching time t = 11,000 / a. After the etching is completed, the structure as shown in Figure 5B is obtained.

[0079] Compared with the etching of the hole cutting path position using the TCE technology in the related art, in the embodiment of the present application, the depth of the second cutting path region 21b is increased, so that more of the inorganic encapsulation layer 202 can be removed during etching, in order to better realize the opening of specific functional holes such as cameras in subsequent processes.

[0080] As Figure 5C shown, after etching using the patterned photoresist layer as a mask, it is necessary to further form a first organic protection layer 206 and a second organic protection layer 207.

[0081] Optionally, in another embodiment, please refer to Figures 6A - 6E the cross-sectional schematic diagram of the steps of the preparation method of the display panel shown, which specifically shows a cross-sectional schematic diagram of a display panel in the OO' direction.

[0082] As Figure 6A shown, the etching boundary therein is the etching boundary of the overlapping hole region 22. In this embodiment, its second depth d2 = 5000 angstroms. Since the first depth d1 of the etching cutting path region 21 = 11000 angstroms, the etching time t is still 11000 / a.

[0083] Figure 6A shows the exposed photoresist layer 301. The initial thickness of the photoresist layer 301 is c. After using the halftone mask to remove the photoresist layer at the overlapping hole region 22, the thickness of the photoresist layer 301 remaining at the overlapping hole region 22 is c2. c2 = (d1 - d2) / a * b, where d1 is the first depth, that is, the etching depth of the cutting path region 21, d2 is the second depth, that is, the etching depth of the overlapping hole region 22, a is the etching rate of the etching solution to the touch interlayer dielectric layer 203 and the inorganic encapsulation layer 202, and b is the etching rate of the etching solution to the photoresist layer 301. In this embodiment, c2 = (11000 - 5000) / a * b.

[0084] As Figure 6B shown, etching is performed using the exposed photoresist layer 301 as a mask, that is, overlapping holes 302 are formed.

[0085] Since the photoresist layer 301 retains a thickness of c2 at the overlapping hole region 22 after exposure, during etching, the photoresist layer 301 retained at the overlapping hole region 22 is first etched, and then the touch interlayer dielectric layer 203 is etched to obtain overlapping holes with an etching depth of d2. At the same time, the cutting path region 21 has the photoresist layer 301 completely removed, and the etching depth is d1 (refer to Figure 4B 、 5B ). Therefore, after etching in this embodiment, the etching depth of the cutting path region 21 is 11000 angstroms, and the etching depth of the overlapping hole region 22 is 5000 angstroms.

[0086] After stripping the photoresist layer 301, the structure as shown in Figure 6C is obtained.

[0087] As shown in Figure 6D , after etching using the patterned photoresist layer 301 as a mask, the method of the present invention further includes:

[0088] forming a second metal layer 208 on the surface of the touch interlayer dielectric layer 203, where the second metal layer 208 fills the via hole 302 and contacts the first metal layer 204.

[0089] Further, as shown in Figure 6E , the method further includes:

[0090] forming a first organic protection layer 206 on the second metal layer 208 and the exposed touch interlayer dielectric layer 203;

[0091] forming a second organic protection layer 207 on the surface of the first organic protection layer 206.

[0092] Based on the method described in the above steps S1 to S5, it is possible to simultaneously perform etching on the scribe line area 21 and the via hole area 22 without additionally increasing the mask process burden, optimize the removal effect of the inorganic encapsulation layer 202, improve the reliability of the panel, and reduce the manufacturing cost.

[0093] It should be noted that although the above embodiments describe the steps in a specific order, those skilled in the art can understand that in order to achieve the effects of the present application, different steps do not necessarily have to be executed in such an order, and they can be executed simultaneously (in parallel) or in other orders. These adjusted solutions are equivalent technical solutions to the technical solutions described in the present application, and thus will also fall within the protection scope of the present application.

[0094] On the other hand of the present application, a halftone mask is provided, which is applied to the method for manufacturing a display panel according to any one of the above technical solutions; wherein,

[0095] the transmittance of the position corresponding to the via hole area 22 of the halftone mask is designed to be Tr = (a×c - d2×b) / (d1×b), where a is the etching rate of the touch interlayer dielectric layer 203 and the inorganic encapsulation layer 202, b is the etching rate of the photoresist layer 301, c is the thickness of the pre-coated photoresist layer 301, d1 is the pre-reached first depth, and d2 is the pre-reached second depth.

[0096] Optionally, the transmittance of the position corresponding to the scribe line area 21 of the halftone mask is designed to be 100%.

[0097] The above halftone mask is applied to the manufacturing process of the display panel to implement the above manufacturing method. By designing different transmittances for different regions of the display panel, the exposure amount is changed to adjust the thickness of the photoresist layer, and finally, the purpose of simultaneously etching the scribe line region 21 and the via hole region 22 and optimizing the removal effect of the inorganic encapsulation layer 202 through a single mask etching process is achieved.

[0098] It can be understood that since the display panel has substantially the same technical effects as the manufacturing method of the foregoing display panel, for the sake of brevity, the technical effects of this display panel will not be described again here.

[0001] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For the parts not detailed or recorded in a certain embodiment, reference may be made to the relevant descriptions of other embodiments. All the above optional technical solutions can be combined arbitrarily to form the optional embodiments of the present application, which will not be elaborated one by one here.

[0099] So far, the technical solutions of the present application have been described in conjunction with one embodiment shown in the drawings. However, those skilled in the art can easily understand that the protection scope of the present application is obviously not limited to these specific embodiments. Without departing from the principle of the present application, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the protection scope of the present application.

Claims

1. A method for manufacturing a display panel, comprising: providing a substrate (20), the substrate (20) having a display area (AA) and a peripheral area (NAA) surrounding the display area (AA), the peripheral area (NAA) including a bonding area (BA) located on one side of the display area (AA), a dicing channel area (21) being provided in the display area (AA) and the peripheral area (NAA), and a lapping hole area (22) being provided in at least one of the display area (AA) and the peripheral area (NAA); successively forming a functional layer (201), an inorganic encapsulation layer (202), and a touch interlayer dielectric layer (203) on the substrate (20), wherein a first metal layer (204) is further formed between the inorganic encapsulation layer (202) and the touch interlayer dielectric layer (203) in the lapping hole area (22); forming a photoresist layer on the surface of the touch interlayer dielectric layer (203); patterning the photoresist layer (301), wherein the patterning uses a halftone mask to completely remove the photoresist layer (301) at the dicing channel area (21), and retains the photoresist layer at the lapping hole area (22) with a preset thickness; etching using the patterned photoresist layer (301) as a mask, wherein the etching depth of the dicing channel area (21) is a first depth so as to at least remove the touch interlayer dielectric layer (203) and part of the inorganic encapsulation layer (202) at the dicing channel area (21); the etching depth of the lapping hole area (22) is a second depth so as to remove the touch interlayer dielectric layer (203) at the lapping hole area (22) and expose the first metal layer (204) to form a lapping hole (302); the first depth is greater than the second depth.

2. The preparation method according to claim 1, characterized in that, A barrier layer (205) is further provided between the touch interlayer dielectric layer (203) and the inorganic encapsulation layer (22); the etching using the patterned photoresist layer (301) as a mask further includes: removing the touch interlayer dielectric layer (203), the barrier layer (205), and part of the inorganic encapsulation layer (202) at the dicing channel area (21).

3. The preparation method according to claim 1, characterized in that, The dicing channel area (21) includes: a first dicing channel area (21a) located in the peripheral area (NAA), including an area opposite to the bonding area (BA) and areas on both sides of the bonding area (BA), wherein the opposite area and the areas on both sides are respectively preset with dicing channel positions; and a second dicing channel area (21b) located in the display area (AA), wherein a hole dicing channel position is preset in the second dicing channel area (21b).

4. The preparation method according to claim 1, characterized in that, The first depth is 10000 - 12000 angstroms; the second depth is 4000 - 6000 angstroms.

5. The preparation method according to any one of claims 1-4, characterized in that, The first depth is d1, the second depth is d2, the etching rate of the touch interlayer dielectric layer (203) and the inorganic encapsulation layer (202) is a, and the etching rate of the photoresist layer (301) is b; The preset thickness is (d1 - d2) / a * b.

6. The preparation method according to claim 5, characterized in that, The etching time t of the etching is the ratio of the first depth d1 to the etching rate a.

7. The method according to claim 1, wherein After etching using the patterned photoresist layer as a mask, it further includes: Forming a second metal layer (208) on the surface of the touch interlayer dielectric layer (203), the second metal layer (208) filling the overlapping hole (302) and contacting the first metal layer (204).

8. The method according to claim 7, wherein The method further includes: Forming a first organic protection layer (206) on the second metal layer (208) and the exposed touch interlayer dielectric layer (203); Forming a second organic protection layer (207) on the surface of the first organic protection layer (206).

9. A halftone mask, characterized in that, Applied to the manufacturing method of a display panel as described in any one of claims 1-8; wherein, The transmittance at the position corresponding to the overlapping hole area (22) of the halftone mask is designed as Tr = (a×c - d2×b) / (d1×b), where a is the etching rate of the touch interlayer dielectric layer (203) and the inorganic encapsulation layer (202), b is the etching rate of the photoresist layer (301), c is the thickness of the pre-coated photoresist layer (301), d1 is the first depth to be achieved, and d2 is the second depth to be achieved.

10. The halftone mask according to claim 9, wherein The transmittance at the position corresponding to the scribe line area (21) of the halftone mask is designed as 100%.

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