Semiconductor structure and forming method thereof

Abstract

The method comprises the following steps: forming a sacrificial layer on a substrate; patterning the sacrificial layer to form: a first sacrificial block having a first height; and a second sacrificial block having a second height greater than the first height. The second sacrificial block is spaced apart from the first sacrificial block by a space. The method further includes reflowing the first sacrificial block and the second sacrificial block; and performing an etching process to etch the first sacrificial block, the second sacrificial block, and the substrate. As a result of the etching, a first portion of the substrate directly underneath the first sacrificial block forms a microlens, and a second portion of the substrate directly underneath the second sacrificial block forms a protective wall. The embodiment of the invention also relates to a semiconductor structure and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. Background Art

[0002] Electric and optical signals, as well as processing, are technologies for signal transmission and processing. In recent years, optical signals and processing have been used in more and more applications, and are generally combined with electric signals and processing to provide comprehensive applications. Thus, a package may include an optical (photonic) die and an electronic die, the optical (photonic) die including optical devices and the electronic die including electronic devices.

[0003] A microlens is used to converge an optical signal. The microlens may be formed by etching a transparent substrate such that the surface of the etched portion of the transparent substrate is rounded. Summary of the Invention

[0004] Some embodiments of the present application provide a method of forming a semiconductor structure, including: forming a sacrificial layer on a substrate; patterning the sacrificial layer to form: a first sacrificial block having a first height; and a second sacrificial block having a second height greater than the first height, wherein the second sacrificial block is spaced apart from the first sacrificial block by a space; causing the first sacrificial block and the second sacrificial block to reflow; and performing an etching process to etch the first sacrificial block, the second sacrificial block, and the substrate, wherein a first portion of the substrate directly under the first sacrificial block forms a microlens, and a second portion of the substrate directly under the second sacrificial block forms a protection wall.

[0005] Some other embodiments of the present application provide a semiconductor structure, including: a substrate; a microlens located on the surface of the substrate, wherein the microlens includes a transparent material and the microlens includes a first top surface; and a protection wall including a first portion, wherein in a top view of the substrate, the first portion surrounds the microlens, wherein the first portion includes a second top surface higher than the first top surface, and wherein the protection wall is spaced apart from the microlens by a space.

[0006] Some other embodiments of the present application provide a semiconductor structure, including: a photonic package, including: a photonic die; and an electronic die located on the photonic die; and a transparent substrate located above the photonic die, wherein the transparent substrate includes: a recess located on the surface of the transparent substrate; a microlens located in the recess; and a portion of the transparent substrate surrounding the microlens, wherein the microlens is laterally spaced apart from the nearest portion of the portion of the transparent substrate by a space. Description of the Drawings

[0007] As will be best understood from the following detailed description when read in conjunction with the accompanying drawings, it should be noted that the various components are not drawn to scale in accordance with standard practice in the industry. In fact, for clarity of discussion, the dimensions of the various components can be increased or decreased arbitrarily.

[0008] Figure 1 , Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figures 3 to 6 , Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 7E , Figure 7F , and Figure 7G show views of intermediate stages in the formation of microlenses according to some embodiments;

[0009] Figures 8 to 9 show views of intermediate stages in the formation of microlenses according to alternative embodiments;

[0010] Figure 10 show a photonics package including microlenses according to some embodiments;

[0011] Figure 11 show a process flow for forming microlenses according to some embodiments. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where additional components may be formed between the first and second components such that the first and second components are not in direct contact. Additionally, the present invention may repeat reference numerals and / or letters in various instances. This repetition is for simplicity and clarity purposes and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Moreover, for ease of description, spatial relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another (or other) element or component as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be correspondingly interpreted in the same manner.

[0014] A microlens structure and a method for forming the same are provided. According to some embodiments of the present invention, the microlens may be formed from a transparent substrate such as a silicon substrate. The forming process may include a single lithography process (which may include one exposure process or two exposure processes, and one photolithography process) and an etching process for etching the silicon substrate.

[0015] The embodiments discussed herein are intended to provide examples to enable the making or use of the subject matter of the present disclosure, and those of ordinary skill in the art will readily understand the modifications that can be made while remaining within the scope of the different embodiments. Throughout the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. Although method embodiments may be discussed as being implemented in a particular order, other method embodiments may be implemented in any logical order.

[0016] Figures 1 to 7A 、 Figure 7B 、 Figure 7C 、 Figure 7D 、 Figure 7E 、 Figure 7F 、and Figure 7G show views of intermediate stages in the formation of a microlens according to some embodiments of the present invention. The corresponding processes are also schematically reflected in process flow 200 as shown in Figure 11 as shown.

[0017] Referring to Figure 1 , a wafer 10 is formed. The wafer 10 includes a substrate 20. According to some embodiments, there are no integrated circuit devices in the wafer 10. For example, the wafer 10 may not include any active devices (such as transistors) and passive devices (such as resistors, capacitors, inductors, etc.). The substrate 20 may be a blanket transparent substrate formed of a uniform material such as silicon (doped or undoped), where there are no metal regions, dielectric regions, etc.

[0018] According to an alternative embodiment, the wafer 10 can be a device wafer that includes integrated circuit devices. For example, the wafer 10 can include active devices such as transistors, and passive devices such as resistors, capacitors, inductors, etc. The active devices can be formed on the bottom surface of the substrate 20, while other devices such as metal lines and dielectric layers can be formed under the substrate 20 and electrically connected to the integrated circuit devices. The passive devices can also be formed in the dielectric layer and can or cannot extend from the dielectric layer into the substrate 20.

[0019] In the following discussion, it is assumed that the wafer 10 is a blanket wafer in which there are no active and passive devices. This discussion can also be applied to device wafers when the microlenses are directly formed in the semiconductor substrate of the device wafer.

[0020] The wafer 10 can include multiple dielectric layers, such as layers 22, 24, and 26. According to some embodiments, layer 22 can be formed of or include a dielectric material, which can be an oxide-based material, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), etc. Spin coating, flowable chemical vapor deposition (FCVD), etc. can be used to form layer 22.

[0021] According to an alternative embodiment of the present invention, layer 22 is formed by oxidizing the surface layer of the substrate 20 to form a thermal oxide layer. According to some embodiments, the entire layer 22 is formed of a uniform material in which there are no other materials different from the uniform material.

[0022] Layer 24 can be formed of or include a dielectric material, which can be a nitride-based material, such as silicon nitride, although it can also be formed of or include other materials, such as silicon oxynitride (SiON).

[0023] According to some embodiments, layer 26 is formed of or include a dielectric material, which can be an oxynitride-based material, such as silicon oxynitride (SiON), although it can also be formed of or include other materials, such as silicon oxide, silicon oxycarbide (SiOC), silicon carbonitride (SiCN), etc.

[0024] Alignment marks 28 can be formed in dielectric layers 22, 24, and / or 26, such as in dielectric layer 24. According to some embodiments, alignment marks 28 include metals, metal alloys, metal compounds, etc., to increase the contrast of alignment marks 28 relative to the surrounding materials. According to some embodiments, alignment marks 28 include metal regions formed of copper, copper alloys, tungsten, nickel, and / or the like, or include these materials. A bonding layer can be formed, or not formed, under the metal region and the pad metal region. The bonding layer can be formed of titanium, titanium nitride, tantalum, tantalum nitride, etc., or include these materials.

[0025] The process of forming alignment marks 28 can include: etching the corresponding dielectric layer (such as dielectric layer 24) to form an opening, depositing the bonding layer (if formed) as a conformal layer, for example, using physical vapor deposition (PVD), depositing a metal material over the bonding region, and then performing a chemical mechanical polishing (CMP) process to remove the excess of the bonding layer and the metal material, leaving alignment marks 28 in dielectric layer 24.

[0026] Reference Figure 2A , a photoresist layer 30 is coated on substrate 20. The corresponding process is shown as process 202 in process flow 200 shown in Figure 11 . According to some embodiments, photoresist layer 30 is formed of a material capable of reflowing at high temperatures. After coating photoresist layer 30, photoresist layer 30 is soft baked to drive off the solvent and harden.

[0027] According to some embodiments, before coating photoresist layer 30, the entire top surface of substrate 20 is exposed, and there are no other layers and materials such as oxide layers contacting the top surface of substrate 20. There is also no deposition layer between photoresist layer 30 and substrate 20.

[0028] According to some embodiments, before coating photoresist layer 30, a cleaning process can be performed to remove any native oxide on the top surface of substrate 20. The coated photoresist layer 30 can be located on the exposed top surface of substrate 20 with no oxide therebetween. The cleaning process can be performed by a dry etching process, and the coating of photoresist 30 can also be performed in the same vacuum chamber where the cleaning process is performed without interruption of the vacuum.

[0029] According to an alternative embodiment, a native oxide layer can exist before photoresist layer 30 and substrate 20, and no other layers are deposited on substrate 20 and between photoresist layer 30 and substrate 20. If present, the native oxide layer can have a thickness of less than about 2 nm.

[0030] The photolithography mask 32 is a grayscale photolithography mask and is placed above the photoresist layer 30. According to some embodiments, the photolithography mask 32 includes a plurality of opaque portions 32A, a plurality of transparent portions 32B, and a plurality of partially transparent portions 32C. Throughout the description, the transparency TP of an object is calculated as the ratio of the energy of the light passing through the object to the energy of the light incident on the object.

[0031] According to some embodiments, the opaque portions 32A are completely opaque, where the transparency TP 32A is equal to 0% or close to 0% (e.g., less than about 10% or 5%). The transparent portions 32B can be completely transparent, where the transparency TP 32B is equal to 100% or close to 100% (e.g., greater than about 90% or 95%). The partially transparent portions 32C have a transparency TP 32C greater than the transparency TP 32A , but less than the transparency TP 32B . Each of the transparency differences (TP 32B -TP 32C ) and (TP 32C -TP 32A ) can be greater than about 10%, and can be in the range between about 20% and 80%.

[0032] Perform an exposure process 34 to expose the photoresist layer 30. Control the dose of light such that the portion of the photoresist layer 30 directly below the partially transparent portion 32C has its top sufficiently exposed while the bottom is not sufficiently exposed. The portion of the photoresist layer 30 directly below the transparent portion 32B is sufficiently exposed. The entire portion of the photoresist layer 30 directly below the opaque portion 32A is not exposed. Throughout the description, the sufficiently exposed photoresist will be removed in the development process, while the unexposed or insufficiently exposed photoresist will be retained after the development process.

[0033] Figure 2B 、 Figure 2C 、 Figure 2D 、 Figure 2E 、and Figure 2F show a top view of some exemplary photolithography masks 32 according to some embodiments. Referring to Figure 2B , the plurality of partially transparent portions 32C are spaced apart from each other. Each of the plurality of partially transparent portions 32C is surrounded by a transparent portion 32B, and the transparent portion 32B is further surrounded by an opaque portion 32A, and the opaque portion 32A surrounds all the transparent portions 32B.

[0034] Figure 2C shows a photolithography mask 32 according to an alternative embodiment. The photolithography mask 32 according to these embodiments is the same as Figure 2Bis basically the same, except that, Figure 2B the transparent portion 32B in Figure 2C has a circular top view shape, while Figure 2C the transparent portion 32B in Figure 2C can have a square top view shape. According to other embodiments, the transparent portion 32B can have other shapes, such as hexagonal, octagonal, elliptical, etc.

[0035] In Figure 2B and Figure 2C each partial transparent portion 32C is surrounded by discrete transparent portions 32B. Figure 2D shows a photolithography mask 32 according to an alternative embodiment. The common transparent portion 32B surrounds a plurality of partial transparent portions 32C, which, according to some embodiments, can be arranged in a row.

[0036] Figure 2E shows a photolithography mask 32 according to yet another alternative embodiment. The photolithography mask 32 according to these embodiments is basically the same as that in Figure 2D except that, Figure 2D the transparent portion 32B in Figure 2E has a rectangular top view shape, while Figure 2E the transparent portion 32B in Figure 2E has a pod shape.

[0037] Figure 2F shows a photolithography mask 32 according to an alternative embodiment. According to some embodiments, the common transparent portion 32B surrounds a plurality of partial transparent portions 32C, which are arranged in multiple rows and columns and can be formed into an array, a honeycomb pattern, etc.

[0038] After the exposure process 34, the exposed photoresist layer 30 may or may not be subjected to a hard bake. Then a development process is implemented to remove the exposed portions of the photoresist layer 30. The resulting structure is as shown in Figure 3 . The corresponding process is shown as process 206 in the process flow 200 shown in Figure 11 . Hereinafter, the remaining portion of the photoresist layer 30 is referred to as the photoresist block 30. The photoresist block 30 will be etched in subsequent processes and thus also serves as and is referred to as the sacrificial block 30.

[0039] The photoresist block 30 includes a photoresist block 30A and a photoresist block 30C. The photoresist block 30A is the remaining portion of the photoresist 30 that is directly below the opaque portion 32A of the photomask 32. The photoresist block 30A has a height H1. The photoresist block 30C is the remaining portion of the photoresist 30 that is directly below the partially transparent portion 32C of the photomask 32. The top of the photoresist 30 that is directly below the partially transparent portion 32C of the photomask 32 is removed. Accordingly, the photoresist block 30C has a height H2 that is less than the height H1. According to some embodiments, the ratio H2 / H1 can range between about 10% and about 80%, depending on the desired curvature of the subsequently formed microlens. The ratio H2 / H1 is further affected by the transparency TP 32C , where the larger the TP 32C , the smaller the ratio H2 / H1 and the greater the curvature will be.

[0040] Further referring Figure 3 , a reflow process 36 is implemented. The corresponding process is shown as process 208 in the process flow 200 shown in Figure 11 . The reflow process is implemented at a high temperature above the softening temperature of the photoresist block 30. According to some embodiments, the reflow process 36 is implemented in a temperature range between about 155°C and about 165°C. The reflow process 36 can be implemented, for example, in a duration range between about 300 seconds and about 350 seconds. The actual temperature and duration are related to the material of the photoresist block 30 and can be higher / longer or lower / shorter.

[0041] Figure 4 Illustrates the reflowed photoresist blocks 30A and 30C according to some embodiments. The reflowed photoresist block 30C has a circular top surface. The reflowed photoresist block 30A has rounded corners, and some large photoresist blocks 30A may have a flat top surface connected to the rounded corners. The bottom of the sidewall of the photoresist block 30A can be straight and vertical, straight and inclined, or continuously curved. The upper part of the sidewall of the photoresist block 30A is curved. Some small photoresist blocks 30A may also have a completely curved top surface (without a flat portion), which has a profile similar to the dashed line 55 shown in Figure 7B .

[0042] When observed in a top view, the reflowed photoresist block 30C can be circular. The top view shape of the reflowed photoresist block 30C may be substantially the same as the top view shape of the microlens 44 to be formed shown in Figure 7C . The top view size of the reflowed photoresist block 30C can be the same as, slightly larger than, or slightly smaller than the top view shape of the microlens 44 shown in Figure 7C . The reflowed photoresist block 30( Figure 4) The lateral dimension W1 can be in the range between approximately 100 μm and approximately 120 μm. The lateral dimension W1 can be a diameter because the reflowed photoresist block 30 can have a circular top view shape.

[0043] Then, an etching process 40 (as shown in Figure 4 ) is implemented to form the microlens 44, as shown in Figure 5 . The corresponding process is shown as process 210 in the process flow 200 shown in Figure 11 . At the start of the etching process 40, the reflowed photoresist block 30 can be in physical contact with the material of the substrate 20 (such as silicon). Alternatively, there may be a very thin native oxide layer between the reflowed photoresist block 30 and the substrate 20, and there is no deposition layer on the native oxide layer.

[0044] The etching process 40 is an anisotropic etching process, which is implemented by using an etching gas that erodes both the substrate 20 and the reflowed photoresist block 30. The etching rate ER30 of the reflowed photoresist block 30 and the etching rate ERM20 of the substrate 20 can also be close to each other. For example, the etching rate ratio ER20 / ER30 can be in the range between approximately 0.8 and approximately 1.2, and can be in the range between approximately 0.9 and approximately 1.1. According to some embodiments, the etching process 40 is implemented using an etching gas including NF3, CO, O2, CF4, Cl2, and / or the like.

[0045] As the etching process 40 progresses, both the exposed portions of the reflowed photoresist block 30 and the substrate 20 are etched downward. As the etching process progresses, an increasing number of surface portions of the reflowed photoresist block 30 are consumed, exposing the surface portion of the substrate 20 directly below the edge portion of the reflowed photoresist block 30, and the exposed portion of the substrate 20 is also etched. An increasing number of portions of the substrate 20 directly below the reflowed photoresist block 30 are exposed and start to be etched. Accordingly, the shape and surface profile of the reflowed photoresist block 30 are transferred into the substrate 20.

[0046] As shown in Figure 4 , before the start of the etching process 40, the substrate 20 has a top surface 20TS1. As shown in Figure 5 , the etching process 40 causes the height of the flat top surface of some portions of the substrate 20 to be reduced to the top surface 20TS2 as shown in Figure 5 . The height difference between the top surfaces 20TS2 and 20TS1 is greater than the height H3 of the microlens 44.

[0047] The etching process 40 continues until all of the reflowed photoresist block 30C is completely consumed. However, there are still some remaining portions of the reflowed photoresist block 30A. According to some embodiments, asFigure 5 As shown in Figure 5 , the top surface of the etched portion of the substrate 20 directly beneath the photoresist block 30C is circular, thereby forming the microlens 44.

[0048] Then, the remaining photoresist 30 is removed, and the resulting structure is as Figure 6 shown in Figure 6 . The microlens 44 is formed in the recess 52 of the substrate 20. The substrate 20 includes the protective wall 54. The protective wall 54 includes a portion surrounding the microlens 44, and a portion located between adjacent recesses 52 and adjacent microlenses 44 and separating the adjacent recesses 52 and adjacent microlenses 44. According to some embodiments, the top end of the microlens 44 is flush with the top surface of the protective wall 54 (which may be the non-recessed top surface 20TS1), or lower than the top surface of the protective wall 54. According to some embodiments, the height difference ΔH1, that is, the height difference between the topmost end of the microlens 44 and the top surface 20TS1, is greater than 0 μm and less than about 20 μm. As the difference ΔH1 is greater than 0 μm, the top end of the microlens 44 is recessed to be lower than the top surface 20TS1. Accordingly, when the wafer 10 is flipped and placed on another surface, the microlens 44 will be higher than and spaced apart from the other surface and will not be damaged.

[0049] The lateral dimension W1’ of the microlens 44 can be the diameter because the reflowed photoresist block 30 can have a circular top view shape. The lateral dimension W2 (or length or width) of the recess 52 is less than the pitch P1 of the microlenses 44 to allow space for forming the protective wall 54. According to some embodiments, the width W3 of the protective wall 54 can be in the range between about 100 μm and about 300 μm, and depending on the application, a larger or smaller width can be employed. The spacing S1 between the edge of the microlens 44 and the corresponding nearest edge of the protective wall 54 can be greater than about 0.1 μm and can be in the range between about 0.1 μm and about 5 μm, or also in the range between about 1 μm and about 5 μm.

[0050] Figure 7A shows the formation of the protective layer 56 according to some embodiments. The protective layer 56 can be formed of or include a transparent material, such as silicon oxide, silicon oxynitride, etc. The formation process can include a conformal deposition process, such as ALD, CVD, etc. Alternatively, the protective layer 56 can be formed by thermal oxidation of the substrate 20, for example, by forming silicon oxide. Then, a sawing process can be formed to cut the wafer 10 into die 10’.

[0051] According to Figure 7AIn some of the embodiments shown, the top surface of the protective wall 54 includes a planar portion 54TP that is connected to the rounded surface 54RC. The planar portion 54TP can also be the original top surface 20TS1 of the substrate 20 before etching. The rounded surface 54RC is formed as a result of etching the corners of the substrate 20. The protective wall 54 can have a vertical and straight edge that is located below the rounded surface 54RC and is connected to the rounded surface 54RC. Alternatively, the continuous rounded surface 54RC is continuously curved and extends from the top surface 20TS2 and all the way to the planar portion 54TP of the top surface of the protective wall 54.

[0052] According to Figure 7B In an alternative embodiment shown, the top surface of the protective wall 54 does not include a planar portion. Instead, the opposing rounded surfaces 54RC are connected at the apex TMP of the surface of the protective wall 54, and the apex TMP can be the midpoint of the opposing edges of the protective wall 54. The protective wall 54 can have a vertical and straight edge 54SE that is located below the rounded surface 54RC and is connected to the rounded surface 54RC. Alternatively, the continuous rounded surface 54RC is continuously curved and extends from the top surface 20TS2 and all the way to the apex TMP of the top surface of the protective wall 54.

[0053] Figure 7B Also shown is a protective wall 54 according to an alternative embodiment. When the photoresist block 30A used to form the protective wall is narrow enough, due to lateral etching, these portions of the photoresist block 30A may be etched faster than a larger photoresist block 30A. As a result, these portions of the photoresist block 30A can be completely removed, and the underlying protective wall 54 will also be etched downward. The top surface 55 of the resulting protective wall 54 (as shown by the dashed line) can also be circular. Additionally, the topmost point of the top surface 55 can be lower by a height difference ΔH2 than the top surface 20TS1. According to these embodiments, the height difference ΔH2 is less than the height difference ΔH1 ( Figure 6 ).

[0054] Figure 7C A top view of a portion of a wafer 10 and a device die 10' according to some embodiments is shown. The recesses 52 are formed as discrete recesses that are spaced apart from each other by the protective walls 54. According to some embodiments, due to the use of a grayscale photomask (or two binary photomasks as shown in Figure 8 and Figure 9 ), the top view shape of the recesses 52 is different from the top view shape of the microlenses 44. For example, the recesses 52 can have a square top view shape, while the lenses 44 can have a circular top view shape.

[0055] According to an alternative embodiment, the recesses 52 can have other top view shapes, including but not limited to circular, hexagonal, octagonal, etc. As shown in Figure 7CAs shown, the protective wall 54 forms a grid, and the recess 52 is the grid opening of the grid. The microlens 44 is located at the center of the recess 52, or may be slightly offset in the same direction from the corresponding center of the recess 52.

[0056] According to some embodiments, different portions of the microlens 44 may have different spacings from the nearest portions of the protective wall 54. For example, the spacing S1'-A may be different from the spacing S1'-B. Additionally, the recess 52 may be concentric with the corresponding microlens 44 therein. Alternatively, the center of the recess 52 is eccentric with respect to the center of the corresponding microlens 44 therein.

[0057] Figure 7D An embodiment is shown in which the recess 52 also has a circular top view shape. According to some embodiments, the microlens 44 and the corresponding recess 52 have a common center. Alternatively, the center of the recess 52 may be slightly offset from the center of the corresponding microlens 44 therein.

[0058] Figure 7E An embodiment is shown in which there are multiple microlenses 44 in a single recess 52. The multiple microlenses 44 are arranged in a row. The single recess 52 has a rectangular top view shape.

[0059] Figure 7F An embodiment is shown in which there are multiple microlenses 44 in a single recess 52. The multiple microlenses 44 are arranged in a row. The single recess 52 has a pod top view shape.

[0060] Figure 7G An embodiment is shown in which there are multiple microlenses 44 in a single recess 52. The multiple microlenses 44 are arranged in an array.

[0061] Figure 8 and Figure 9 Illustrates the formation of the wafer 10 and the die 10' according to alternative embodiments. These embodiments are substantially the same as the previous embodiments, except that two binary lithography masks are used instead of a gray-scale lithography mask. Unless otherwise stated, the materials, structures, and formation processes of the components in these embodiments are substantially the same as those of the same components denoted by the same reference numerals in the previous embodiments. Throughout the description, details regarding the materials, structures, and formation processes provided for each embodiment may be applied to any other embodiment as long as applicable.

[0062] Refer to Figure 8 to form the wafer 10. The structure and material of the wafer 10 are substantially the same as those discussed with reference to Figure 1 and will not be repeated here. A photoresist layer 30 is coated on the wafer 10. According to some embodiments, discuss Figure 8 and Figure 9The exemplary embodiment shown assumes that the photoresist layer 30 is a positive photoresist, where the exposed portions will become soluble and be removed during development. According to an alternative embodiment, the photoresist layer 30 can be a negative photoresist, and the corresponding process can be implemented from the embodiments discussed.

[0063] As Figure 8 shown, the first photomask 132-1 is placed above the photoresist layer 30. The photomask 132-1 is a binary mask that includes an opaque portion 132A and a transparent portion 132B. The transparency of the opaque portion 132A is equal to 0% or close to 0% (e.g., less than about 10% or 5%). The transparency of the transparent portion 132B is equal to 100% or close to 100% (e.g., greater than about 90% or 95%). The pattern of the transparent portion 132B can be substantially the same as the pattern of the transparent portion 32B shown in Figure 2B , Figure 2C , Figure 2D , Figure 2E , or Figure 2F .

[0064] Implement the first exposure process 134-1. The portion 30FE of the photoresist layer 30 directly below the transparent portion 32B is completely exposed from top to bottom and is referred to as the fully exposed portion 30FE. The dose of light for the exposure process 134-1 is high enough to achieve full exposure.

[0065] Refer to Figure 9 , and place the second photomask 132-2 above the photoresist layer 30. The photomask 132-2 is also a binary mask that includes an opaque portion 132A' and a transparent portion 132B'. The transparency of the opaque portion 132A' is equal to 0% or close to 0% (e.g., less than about 10% or 5%). The transparency of the transparent portion 132B' is equal to 100% or close to 100% (e.g., greater than about 90% or 95%). The pattern of the transparent portion 132B' can be substantially the same as the pattern of the partially transparent portion 32C shown in Figure 2B , Figure 2C , Figure 2D , Figure 2E , or Figure 2F .

[0066] Perform the second exposure process 134-2. The portion 30PE of the photoresist layer 30 that is directly below the transparent portion 132B' is partially exposed, hereinafter referred to as the partially exposed portion 30PE. The top of the partially exposed portion 30PE is fully exposed, and the bottom 30C of the partially exposed portion 30PE is not fully exposed. Control the light dose for the exposure process 134-2 to achieve partial exposure. For example, the light dose for the exposure process 134-2 can be controlled to be 80% less, 50% less, or lower than the exposure dose in the first exposure process 134-1.

[0067] According to an alternative embodiment, the order of the first exposure process 134-1 and the second exposure process 134-2 can be opposite to the order Figure 8 and Figure 9 shown. According to some embodiments, the edge of the fully exposed portion 30FE is aligned with the edge of the partially exposed portion 30PE such that the fully exposed portion 30FE and the adjacent partially exposed portion 30C are connected (but do not overlap). According to an alternative embodiment, the fully exposed portion 30FE and the adjacent partially exposed portion 30PE slightly overlap. Thus, the overlapping portion is also fully exposed.

[0068] After the first exposure process 134-1 and the second exposure process 134-2, perform a development process to remove the top of the partially exposed portion 30PE and the fully exposed portion 30FE. The resulting structure is also as Figure 3 shown. The subsequent processes are substantially the same as the processes Figures 3 to 7A - Figure 7G shown and will not be repeated here. The resulting structure is also substantially the same as Figures 7A - 7G shown.

[0069] Figure 10 FIG. shows a photon package 58 according to some embodiments, in which a die 10' as Figures 7A - 7G shown is employed. According to some embodiments, the photon package 58 includes a photon die 60, an electronic die 62 located above and bonded to the photon die 60, and a die 10' located above and bonded to the electronic die 62. The bonding of the die 10' to the electronic die 62 can be by fusion bonding, and the bonding of the electronic die 62 to the photon die 60 can be by hybrid bonding, including metal-to-metal direct bonding and fusion bonding.

[0070] According to some embodiments, the photon die 60 can include photon devices such as waveguides, grating couplers, edge couplers, modulators, and / or the like. For example, a grating coupler 64 is shown as an example. The grating coupler 64 can be used to emit or receive a laser beam 66 emitted from an optical fiber 68, or can be received by another coupler.

[0071] The electronic die 62 can be, for example, a semiconductor device, die, or chip that communicates with the photonic die 60 using electrical signals. The electronic die 62 includes a semiconductor substrate 67, an interconnect structure 68, and an electrical connector 70, which can be, for example, a conductive pad, a conductive pillar, etc.

[0072] The electronic die 62 can include an integrated circuit for interfacing with the photonic die 60, such as a circuit for controlling the operation of the photonic die 60. For example, the electronic die 62 can include a controller, a driver, an amplifier, etc., or a combination thereof. The electronic die 62 can also include a CPU. According to some embodiments, the electronic die 62 includes a circuit for processing electrical signals received from the photonic die 60. According to some embodiments, the electronic die 62 can also control the high-frequency signals of the photonic die 60 based on electrical signals (digital or analog) received from other devices or dies. According to some embodiments, the electronic die 62 can be an electronic integrated circuit (EIC) that provides serializer / deserializer (SerDes) functionality, etc. In this way, the electronic die 62 can act as part of an I / O interface between optical and electrical signals.

[0073] As discussed above, the die 10' can have a microlens 44. The forming process can be substantially the same as that discussed in the previous embodiments. According to some embodiments, after forming a reconstructed wafer by bonding and encapsulating multiple electronic dies to a photonic wafer, and after the wafer 10 ( Figure 1 ) is bonded to the reconstructed wafer, the microlens 44 is formed. The process of forming the microlens is implemented on the resulting wafer including the wafer 10 and the reconstructed wafer. According to an alternative embodiment, the die 10' is formed using the process discussed in the previous embodiments, and then the corresponding wafer 10 is bonded to a package (or reconstructed wafer) including the photonic die 60 and the electronic die 62.

[0074] As Figure 10 shown, the microlens 44 has the function of converging the laser beam 66 that travels through the transparent dielectric layer 72 in the optical path. Accordingly, the optical fiber 68 and the photonic die 64 are used to transmit optical signals.

[0075] Embodiments of the present invention have some advantageous features. By using a one-photon one-etch (1P1E) process to form the microlens, the resulting wafer has a reduced thickness loss, possibly around 1 μm or less. Since the protective wall and the microlens are formed in a single etching process, the roughness of the microlens is low. The radius of curvature can be controlled by adjusting the gray level (when using a gray-scale photomask) or the exposure dose (when using two binary photomasks).

[0076] According to some embodiments of the present invention, a method includes: forming a sacrificial layer on a substrate; patterning the sacrificial layer to form: a first sacrificial block having a first height; and a second sacrificial block having a second height greater than the first height, wherein the second sacrificial block is spaced apart from the first sacrificial block by a space; reflowing the first sacrificial block and the second sacrificial block; and performing an etching process to etch the first sacrificial block, the second sacrificial block, and the substrate, wherein a first portion of the substrate directly under the first sacrificial block forms a microlens, and a second portion of the substrate directly under the second sacrificial block forms a protective wall.

[0077] In one embodiment, when the etching process ends, the second sacrificial block includes a remaining portion. In one embodiment, when the etching process ends, the second sacrificial block is removed to expose the top surface of the substrate directly under the second sacrificial block. In one embodiment, the second sacrificial block is located at a position between the microlens and an adjacent microlens. In one embodiment, forming the sacrificial layer includes coating a photoresist layer. In one embodiment, patterning the sacrificial layer includes: exposing the sacrificial layer using a grayscale photomask; and developing the sacrificial layer.

[0078] In one embodiment, the grayscale photomask includes: an opaque portion, wherein, after development, a first portion of the sacrificial layer directly under the opaque portion forms the second sacrificial block; a transparent portion, wherein, after development, a second portion of the sacrificial layer directly under the transparent portion is removed to leave a space; and a partially transparent portion, wherein, after development, a third portion of the sacrificial layer directly under the partially transparent portion remains as the first sacrificial block.

[0079] In one embodiment, patterning the sacrificial layer includes: performing a first exposure process on the sacrificial layer using a first binary photomask, wherein the first exposure process is performed with a first light dose; and performing a second exposure process on the sacrificial layer using a second binary photomask, wherein the second exposure process is performed with a second light dose lower than the first light dose. In one embodiment, the method further includes: a developing process for developing the exposed sacrificial layer using both the first exposure process and the second exposure process. In one embodiment, patterning the sacrificial layer is a single lithography process.

[0080] According to some embodiments of the present invention, a structure includes: a substrate; a microlens located on the substrate surface, wherein the microlens includes a transparent material and the microlens includes a first top surface; and a protective wall including a first portion, wherein, in a top view of the substrate, the first portion surrounds the microlens, wherein the first portion includes a second top surface higher than the first top surface, and wherein the protective wall is spaced apart from the microlens by a space.

[0081] In one embodiment, the transparent material includes silicon. In one embodiment, the structure further includes: a plurality of microlenses located on the surface of the substrate, wherein the protective wall includes an intermediate portion that separates the plurality of microlenses from each other. In one embodiment, the intermediate portion of the protective wall includes a third top surface that is coplanar with the first top surface.

[0082] In one embodiment, the intermediate portion of the protective wall includes a third top surface that is higher than the first top surface and lower than the second top surface. In one embodiment, the portion of the substrate directly below the space includes a flat top surface. In one embodiment, the microlenses have different distances from the respective portions of the first portion of the protective wall.

[0083] According to some embodiments of the present invention, a structure includes: a photonics package including: a photonics die; and an electronics die located on the photonics die; and a transparent substrate located above the photonics die, wherein the transparent substrate includes: a recess located on the surface of the transparent substrate; a microlens located in the recess; and a portion of the transparent substrate surrounding the microlens, wherein the microlens is laterally spaced apart from the nearest portion of the portion of the transparent substrate by a space.

[0084] In one embodiment, the portion of the transparent substrate surrounding the microlens forms a full ring, wherein a first top-down shape of the full ring is different from a second top-down shape of the microlens. In one embodiment, the portion of the substrate directly below the space includes a flat surface.

[0085] Some embodiments of the present application provide a method of forming a semiconductor structure, including: forming a sacrificial layer on a substrate; patterning the sacrificial layer to form: a first sacrificial block having a first height; and a second sacrificial block having a second height greater than the first height, wherein the second sacrificial block is spaced apart from the first sacrificial block by a space; refluxing the first sacrificial block and the second sacrificial block; and performing an etching process to etch the first sacrificial block, the second sacrificial block, and the substrate, wherein a first portion of the substrate directly below the first sacrificial block forms a microlens, and a second portion of the substrate directly below the second sacrificial block forms a protective wall.

[0086] In some embodiments, when the etching process ends, the second sacrificial block includes a remaining portion. In some embodiments, when the etching process ends, the second sacrificial block is removed to expose the top surface of the substrate directly beneath the second sacrificial block. In some embodiments, the second sacrificial block is located at a position between the microlens and an adjacent microlens. In some embodiments, forming the sacrificial layer includes coating a photoresist layer. In some embodiments, patterning the sacrificial layer includes: exposing the sacrificial layer using a grayscale photomask; and developing the sacrificial layer. In some embodiments, the grayscale photomask includes: an opaque portion, wherein, after the development, a first portion of the sacrificial layer directly beneath the opaque portion forms the second sacrificial block; a transparent portion, wherein, after the development, a second portion of the sacrificial layer directly beneath the transparent portion is removed to leave the space; and a partially transparent portion, wherein, after the development, a third portion of the sacrificial layer directly beneath the partially transparent portion remains as the first sacrificial block. In some embodiments, patterning the sacrificial layer includes: performing a first exposure process on the sacrificial layer using a first binary photomask, wherein the first exposure process is performed with a first light dose; and performing a second exposure process on the sacrificial layer using a second binary photomask, wherein the second exposure process is performed with a second light dose lower than the first light dose. In some embodiments, the method further includes: a developing process for developing the exposed sacrificial layer using both the first exposure process and the second exposure process. In some embodiments, patterning the sacrificial layer is a single lithography process.

[0087] Some other embodiments of the present application provide a semiconductor structure, including: a substrate; a microlens located on the surface of the substrate, wherein the microlens includes a transparent material and the microlens includes a first top surface; and a protective wall including a first portion, wherein, in a top view of the substrate, the first portion surrounds the microlens, wherein the first portion includes a second top surface higher than the first top surface, and wherein the protective wall is spaced apart from the microlens by a space.

[0088] In some embodiments, the transparent material includes silicon. In some embodiments, the semiconductor structure further includes: a plurality of microlenses located on the surface of the substrate, wherein the protective wall includes an intermediate portion that separates the plurality of microlenses from each other. In some embodiments, the intermediate portion of the protective wall includes a third top surface that is coplanar with the first top surface. In some embodiments, the intermediate portion of the protective wall includes a third top surface that is higher than the first top surface and lower than the second top surface. In some embodiments, the portion of the substrate directly below the space includes a flat top surface. In some embodiments, the microlenses have different distances from respective portions of the first portion of the protective wall.

[0089] Some further embodiments of the present application provide a semiconductor structure, including: a photonics package, including: a photonics die; and an electronics die located on the photonics die; and a transparent substrate located above the photonics die, wherein the transparent substrate includes: a recess located on the surface of the transparent substrate; a microlens located in the recess; and a portion of the transparent substrate surrounding the microlens, wherein the microlens is laterally spaced apart from the nearest portion of the portion of the transparent substrate by a space.

[0090] In some embodiments, the portion of the transparent substrate surrounding the microlens forms a full ring, wherein a first top-down shape of the full ring is different from a second top-down shape of the microlens. In some embodiments, the portion of the substrate directly below the space includes a flat surface.

[0091] The features of several embodiments are outlined above so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages. Those skilled in the art should also realize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A method of forming a semiconductor structure, comprising: forming a sacrificial layer on a substrate; patterning the sacrificial layer to form: a first sacrificial block having a first height; and a second sacrificial block having a second height greater than the first height, wherein the second sacrificial block is spaced apart from the first sacrificial block by a space; reflowing the first sacrificial block and the second sacrificial block; and performing an etching process to etch the first sacrificial block, the second sacrificial block, and the substrate, wherein a first portion of the substrate directly below the first sacrificial block forms a microlens, and a second portion of the substrate directly below the second sacrificial block forms a protective wall.

2. The method according to claim 1, wherein, When the etching process ends, the second sacrificial block includes a remaining portion.

3. The method according to claim 1, wherein, When the etching process ends, the second sacrificial block is removed to expose a top surface of the substrate directly below the second sacrificial block.

4. The method according to claim 3, wherein, The second sacrificial block is located at a position between the microlens and an adjacent microlens.

5. The method according to claim 1, wherein The forming of the sacrificial layer includes coating a photoresist layer.

6. The method according to claim 1, wherein The patterning of the sacrificial layer includes: exposing the sacrificial layer using a grayscale photomask; and developing the sacrificial layer.

7. The method according to claim 6, wherein, The grayscale photomask includes: an opaque portion, wherein, after the development, a first portion of the sacrificial layer directly below the opaque portion forms the second sacrificial block; a transparent portion, wherein, after the development, a second portion of the sacrificial layer directly below the transparent portion is removed to leave the space; and a partially transparent portion, wherein, after the development, a third portion of the sacrificial layer directly below the partially transparent portion remains as the first sacrificial block.

8. The method according to claim 1, wherein The patterning of the sacrificial layer includes: performing a first exposure process on the sacrificial layer using a first binary photomask, wherein the first exposure process is performed with a first light dose; and performing a second exposure process on the sacrificial layer using a second binary photomask, wherein the second exposure process is performed with a second light dose lower than the first light dose.

9. A semiconductor structure, comprising: a substrate; a microlens located on the substrate surface, wherein the microlens includes a transparent material and the microlens includes a first top surface; and a protective wall including a first portion, wherein, in a top view of the substrate, the first portion surrounds the microlens, wherein the first portion includes a second top surface higher than the first top surface, and wherein the protective wall is spaced apart from the microlens by a space.

10. A semiconductor structure, comprising: a photon package, comprising: a photon die; and an electronic die located on the photon die; and a transparent substrate located above the photon die, wherein the transparent substrate includes: a recess located on the transparent substrate surface; a microlens located in the recess; and a portion of the transparent substrate surrounding the microlens, wherein the microlens is laterally spaced apart from a nearest portion of the portion of the transparent substrate by a space.

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