MCU chip adaptation evaluation method

Abstract

The invention discloses an MCU (Microprogrammed Control Unit) chip adaptation evaluation method. The method comprises the following steps: determining a corresponding MCU computing power demand based on each application scene of a vehicle controller; abstracting each MCU computing power demand based on the computing elements to construct an MCU operation assessment test case corresponding to each application scene; determining the assessment proportion or weight of each MCU operation assessment test case based on the demand ratio of each application scene to the MCU computing power, and combining each test case based on the assessment proportion or weight to form a combined test case; performing MCU operation assessment test on each MCU chip based on the combined test case to obtain the minimum execution time of each MCU chip for completing a typical algorithm corresponding to the combined test case; and determining the most adaptive MCU chip based on the minimum execution time. According to the invention, MCU chip computing power suitability evaluation based on vehicle controller application scene calculation requirements is realized, and MCU model selection adaptation time and cost can be reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip evaluation, and more specifically, relates to a method for evaluating the adaptation of MCU chips. Background Art

[0002] At present, with the rapid development of vehicle intelligent networking, automotive chips have become the core driving force to promote this process. Among them, automotive-grade microcontroller (MCU) chips, with their excellent performance and high integration, are widely used in a series of key components such as vehicle control unit (ECU) and battery management system (BMS). These key components are like the "nerve center" and "energy steward" of the vehicle. The MCU chip undertakes the important task of executing core control algorithms, which are directly related to whether the various functions of the vehicle can be accurately realized and whether the life and property safety of the driver and passengers can be reliably guaranteed.

[0003] However, looking at the current testing status of MCU chips, the main testing methods only rely on chip manuals, as well as reliability testing standards such as AEC - Q100 and functional safety standards such as ISO26262. Although these traditional testing methods can evaluate the basic performance and safety of chips to a certain extent, they have obvious limitations. They seriously lack customized testing methods and professional equipment for the core control algorithm requirements of MCU chips. This leads to the inability to comprehensively, deeply, and accurately evaluate whether the MCU chip is truly suitable for the corresponding vehicle controller application scenario in actual applications. Due to the lack of effective evaluation, it is difficult for automotive manufacturers and related R & D personnel to obtain targeted and guiding reference opinions when selecting MCU chips, which may in turn affect the optimization of the overall vehicle performance, the expansion of functions, and the improvement of safety, hindering the efficient development of vehicle intelligent networking.

[0004] The information disclosed in the background art section of the present invention is only intended to deepen the understanding of the general background art of the present invention, and should not be regarded as an admission or any form of suggestion that this information constitutes prior art known to those skilled in the art. Summary of the Invention

[0005] The object of the present invention is to propose a method for evaluating the adaptation of MCU chips, which solves the problem that traditional evaluation methods cannot comprehensively, deeply, and accurately evaluate whether the MCU chip is truly suitable for the application scenario of the corresponding vehicle controller and is difficult to match the actual requirements, and can accurately evaluate and screen out MCU chips suitable for the vehicle controller application scenario.

[0006] To achieve the above object, the present invention proposes a method for evaluating the adaptation of MCU chips, including: Determine the corresponding MCU computing power requirements based on various application scenarios of the vehicle controller; Abstract the MCU computing power requirements based on computing elements to construct MCU operation assessment test cases corresponding to various application scenarios; Determine the assessment ratio or weight of each MCU operation assessment test case based on the demand ratio of each application scenario for MCU computing power; Combine each MCU operation assessment test case based on the assessment ratio or weight to form a combined test case; conduct MCU operation assessment tests on each MCU chip based on the combined test case, and obtain the minimum execution time of the typical algorithm corresponding to the combined test case for each MCU chip; determine the most suitable MCU chip based on the minimum execution time of the typical algorithm of the combined test case for each MCU chip.

[0007] Optionally, it further includes: Conduct MCU operation assessment tests on each MCU chip based on each MCU operation assessment test case, and obtain the minimum execution time of the typical algorithm corresponding to each MCU operation assessment test case for each MCU chip; Select the one with the smallest sum of the product of the minimum execution time of the typical algorithm of each MCU operation assessment test case for each MCU chip and the assessment ratio or weight as the most suitable MCU chip.

[0008] Optionally, the computing elements include: Computing paradigm, computing volume, and storage volume.

[0009] Optionally, the determining the most suitable MCU chip based on the minimum execution time of the typical algorithm of each test case for each MCU chip further includes: Compare the minimum execution time of the typical algorithm of the combined test case for each MCU chip, and select the one with the shortest total minimum execution time as the most suitable MCU chip.

[0010] Optionally, conducting the MCU operation assessment test based on the combined test case or each MCU operation assessment test case includes: Load the combined test case or each MCU operation assessment test case into the MCU chip through a hardware-in-the-loop system, and control the MCU chip to execute the relevant operations of the combined test case or each MCU operation assessment test case.

[0011] Optionally, the MCU chip is designed as an MCU chip test board, and the hardware-in-the-loop system is communicatively connected to the MCU chip test board.

[0012] Optionally, the hardware-in-the-loop system includes a signal sending unit, a signal acquisition unit, and a result processing unit; The signal sending unit is used to send control signals and test case data to the MCU chip test board; The signal acquisition unit is used to acquire the start time and end time when the MCU chip test board executes the combined test case or each MCU operation assessment test case; The result processing unit is used to calculate the minimum execution time when the MCU chip test board executes the combined test case or each MCU operation assessment test case, and calculate the total minimum execution time when the MCU chip test board executes each MCU operation assessment test case based on the minimum execution time of each MCU operation assessment test case.

[0013] Optionally, the control signals include a wake-up signal, an ignition signal, and a test instruction; The wake-up signal is used to activate the communication between the MCU chip test board and the hardware-in-the-loop system; The ignition signal is used to control the power supply and initialization of the MCU chip test board; The test instruction is used to control the MCU chip to call each MCU operation assessment test case or combined test case.

[0014] Optionally, the formula for the result processing unit to calculate the total minimum execution time of each MCU operation assessment test case is:

[0015] where, , is the minimum execution time of the i-th test case, is the assessment ratio or weight of the i-th test case, , is the end time of the i-th test case, the start time of the i-th test case, and m is the total number of MCU operation assessment test cases.

[0016] Optionally, the formula for the result processing unit to calculate the minimum execution time of the combined test case is:

[0017] where, T 2 is the start time of the combined test case, T 1 is the end time of the combined test case.

[0018] The beneficial effects of the present invention are as follows: Starting from various application scenarios of the vehicle controller, the present invention converts the computing power requirements into quantifiable test indicators, avoiding the problem of the disconnection between traditional tests and real working conditions, and ensuring that the selected MCU chips meet the actual control requirements; by allocating test weights according to the proportion of application scenario requirements, combined test cases are formed, and the minimum execution time is used as the core quantitative indicator to provide a unified and objective horizontal comparison benchmark for MCU chips of different manufacturers and models, reducing the selection decision-making cost; ensuring that the selected MCU chips can still efficiently run typical algorithms under multi-scenario mixed loads, optimizing the real-time response ability and stability of the vehicle controller, indirectly improving the vehicle functional safety and intelligent networking level, establishing a closed-loop methodology from requirement analysis to test verification, providing a reusable industry standard for the selection of automotive-grade MCU chips, helping to solve the technical pain points of the lack of pertinence in traditional tests, and accelerating the localization process of automotive chips. The present invention can realize the evaluation of the computing power adaptability of MCU chips based on the computing requirements of vehicle controller application scenarios, avoid the situation that the MCU chips are not suitable for the corresponding vehicle controller computing power requirements or extreme requirements, can reduce the selection and adaptation time and cost of vehicle manufacturers and controller manufacturers, and can also be used by chip design companies to better discover chip definition deviations and problems in the early stage and guide vehicle design.

[0019] The system of the present invention has other characteristics and advantages, which will be obvious from the accompanying drawings incorporated herein and the subsequent detailed description, or will be described in detail in the accompanying drawings incorporated herein and the subsequent detailed description, and these accompanying drawings and detailed description are used together to explain the specific principles of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] By describing the exemplary embodiments of the present invention in more detail in conjunction with the accompanying drawings, the above and other objects, features and advantages of the present invention will become more obvious. In the exemplary embodiments of the present invention, the same reference numerals generally represent the same components.

[0021] Figure 1 FIG. shows a flowchart of the steps of a method for evaluating the adaptability of an MCU chip according to Embodiment 1 of the present invention.

[0022] Figure 2 FIG. shows a schematic diagram of a hardware-in-the-loop system according to Embodiment 1 of the present invention. DETAILED DESCRIPTION

[0023] The present invention will be described in more detail below with reference to the accompanying drawings. Although the preferred embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to make the present invention more thorough and complete, and to convey the scope of the present invention fully to those skilled in the art.

[0024] Embodiment 1

[0025] An MCU chip adaptation evaluation method according to the present invention includes: S1. Determine the corresponding MCU computing power requirements based on various application scenarios of the vehicle controller; Specifically, the computing power requirements of the MCU (microcontroller unit) of the vehicle controller are directly related to the complexity, real-time requirements, and data processing volume of its application scenarios. Different controllers (such as the powertrain system, chassis system, body electronics, etc.) have significant differences in indicators such as the main frequency, number of cores, storage capacity, and bus bandwidth of the MCU due to functional differences. For example, the application scenarios of the motor controller include motor vector control, torque closed-loop control, field weakening control, overheat protection, energy recovery, etc. in electric vehicles / hybrid vehicles. The motor controller is responsible for controlling the motor speed, torque, and position, and executing algorithms such as vector control (FOC) and PID regulation. Its computing power requirements are characterized by high-speed fixed-point operations (such as coordinate transformation), serial real-time response (microsecond-level control cycle), and fixed storage control parameter table; the application scenarios of the battery controller include charging, discharging, battery safety protection, etc. The battery controller needs to process real-time data such as battery voltage, current, and temperature, and execute algorithms such as state estimation (such as SOC / SOH) and equalization control. Its computing power requirements are characterized by high-frequency floating-point operations (such as Kalman filtering), parallel processing of multi-cell data, and dynamic storage of the battery state table; the application scenarios of the transmission controller include automatic shifting, hybrid coupling, transmission protection and fault diagnosis, etc. The shifting controller is responsible for coordinating signals of multiple components such as the clutch, transmission, and engine, and executing shifting logic and torque coordination algorithms; its computing power requirements are characterized by heterogeneous computing (logical control + real-time scheduling), high storage throughput (caching multi-component state data), and mixed-precision operations (fixed-point + floating-point).

[0026] S2. Abstract the MCU computing power requirements for each based on the computing elements to construct MCU operation assessment test cases corresponding to each application scenario; Among them, the computing elements include: computing paradigm, computing volume, and storage volume; Specifically, in this embodiment, the computing power requirements of each MCU are abstracted from three dimensions: computing paradigm, computing volume, and storage volume, converting fuzzy computing requirements into standardized and executable test items, and constructing MCU operation assessment test cases corresponding to each application scenario; the computing paradigm refers to the algorithm type and processing logic when the MCU executes tasks, which directly affects its operation complexity and architecture adaptability. Considering the different requirements of serial computing and parallel computing, where parallel computing can be further divided according to rules such as homogeneous computing and heterogeneous computing; the computing volume is used to quantify the operation task intensity of the MCU per unit time, usually measured by the number of instruction executions or floating-point operation times. Considering different operation models such as floating-point operation and fixed-point operation, where floating-point operation can be further divided into single-precision floating-point operation and double-precision floating-point operation, etc.; the storage volume considers the constraints on the storage space distribution after different operation models are deployed on the MCU chip, such as whether it can be dynamically expanded, the upper limit of storage space allocation, etc. For example, in the dimension of computing paradigm, the test item for serial computing is to execute the sensor data verification algorithm in a single-threaded loop to verify the sequential execution efficiency; the test item for homogeneous computing in parallel computing is to process the three-phase current sampling data of the motor synchronously in multiple threads to test the multi-core load balancing ability; the test item for heterogeneous computing is for the CPU + DSP combination to execute the battery balancing algorithm (the CPU is responsible for logical scheduling, and the DSP processes floating-point operations) to verify the cooperation efficiency of heterogeneous cores. In the dimension of computing volume, the test item for floating-point operation is the single-precision test: execute 100,000 single-precision floating-point addition operations (simulating motor speed integration) and count the operation time-consuming; the double-precision test: execute the double-precision floating-point iterative calculation of the battery model (such as the ampere-hour integration method) to verify the high-precision operation ability; the test item for fixed-point operation is to execute 100,000 fixed-point multiplication operations (simulating PWM duty cycle calculation) to test the integer operation throughput. In the dimension of storage volume, the test item is the static storage test: load 1MB of control program code into Flash to verify the storage read / write speed and space utilization rate; the dynamic storage test: run the real-time data caching task (such as storing 1000 groups of motor status data in RAM) to test the dynamic memory allocation efficiency and overflow protection mechanism.

[0027] S3. Determine the assessment ratio or weight of each MCU operation assessment test case based on the demand ratio of the computing power of each MCU in each application scenario; Specifically, determine its demand ratio according to the importance and usage frequency of the computing power requirements of each application scenario of the vehicle controller in actual operation; for example, in the battery controller, the assessment ratio or weight of the MCU operation assessment test case corresponding to the charging scenario is 35%, the assessment ratio or weight of the MCU operation assessment test case corresponding to the discharging scenario is 30%, and the assessment ratio or weight of the MCU operation assessment test case corresponding to the battery safety protection scenario is 35%.

[0028] S4. Combine the MCU operation assessment test cases based on the assessment ratio or weight to form combined test cases; conduct MCU operation assessment tests on each MCU chip respectively based on the combined test cases, and obtain the minimum execution time of each MCU chip for the typical algorithms corresponding to the combined test cases; determine the most suitable MCU chip based on the minimum execution time of each MCU chip for the typical algorithms of the combined test cases.

[0029] Specifically, integrate the scenario test cases with assessment ratios or weights to form a set of combined test cases that simulate the mixed computing load during the actual operation of the vehicle controller; for example, for the battery controller, the combined test cases include 35% of the charging scenario test cases, 30% of the discharging scenario test cases, and 35% of the battery protection scenario test cases. Conduct MCU operation assessment tests on each MCU chip respectively through the combined test cases, and obtain the minimum execution time of each MCU chip for the typical algorithms corresponding to the combined test cases. The typical algorithms refer to the algorithm models that can represent the core computing requirements of specific application scenarios. These algorithms are usually abstracted from actual applications and are representative computing tasks used to simulate and verify the computing power performance of the MCU in real scenarios; finally, determine the most suitable MCU chip based on the minimum execution time of each MCU chip for the typical algorithms of the combined test cases.

[0030] In this step, it also includes: conduct MCU operation assessment tests on each MCU chip respectively based on each MCU operation assessment test case, and obtain the minimum execution time of each MCU chip for the typical algorithms corresponding to each MCU operation assessment test case; Select the one with the minimum sum as the most suitable MCU chip based on the sum of the products of the minimum execution time of each MCU chip for the typical algorithms of each MCU operation assessment test case and the assessment ratio or weight.

[0031] Specifically, in this step, instead of using combined test cases for testing, the MCU arithmetic assessment tests can be directly performed on each MCU chip using each MCU arithmetic assessment test case, so as to obtain the minimum execution time of each MCU chip for completing the typical algorithms corresponding to each MCU arithmetic assessment test case. Then, based on the sum of the products of the minimum execution time of each MCU chip for completing the typical algorithms of each MCU arithmetic assessment test case and the assessment ratio or weight, the one with the minimum sum of the product of the minimum execution time and the assessment ratio or weight is selected as the most suitable MCU chip. For example, the assessment ratio or weight of the MCU arithmetic assessment test case corresponding to the charging scenario is 35%, the assessment ratio or weight of the MCU arithmetic assessment test case corresponding to the discharging scenario is 30%, and the assessment ratio or weight of the MCU arithmetic assessment test case corresponding to the battery safety protection scenario is 35%. The minimum execution time of MCU-A for the charging scenario is 20.3, the minimum execution time for the discharging scenario is 20.5, and the minimum execution time for the safety protection scenario is 7.9. The minimum execution time of MCU-B for the charging scenario is 12.7, the minimum execution time for the discharging scenario is 13.4, and the minimum execution time for the safety protection scenario is 5.4. The minimum execution time of MCU-C for the charging scenario is 8.8, the minimum execution time for the discharging scenario is 10.1, and the minimum execution time for the safety protection scenario is 3.9. The total score of MCU-A is: 20.3 × 35% + 20.5 × 30% + 7.9 × 35% = 15.95. The total score of MCU-B is 10.355, and the total score of MCU-C is 7.475. Then MCU-C is the most suitable MCU chip.

[0032] In this step, performing the MCU arithmetic assessment test based on the combined test cases or each MCU arithmetic assessment test case includes: Loading the combined test cases or each MCU arithmetic assessment test case into the MCU chip through a hardware-in-the-loop system, and controlling the MCU chip to execute the relevant operations of the combined test cases or each MCU arithmetic assessment test case.

[0033] As Figure 2 shown, the MCU chip is designed as an MCU chip test board, and the hardware-in-the-loop system is communicatively connected to the MCU chip test board.

[0034] The hardware-in-the-loop system includes a signal sending unit, a signal acquisition unit, and a result processing unit; The signal sending unit is used to send control signals and test case data to the MCU chip test board; The signal acquisition unit is used to collect the start time and end time of the MCU chip test board executing the combined test cases or each MCU arithmetic assessment test case; The result processing unit is used to calculate the minimum execution time for the MCU chip test board to execute the combined test cases or each MCU operation assessment test case, and calculate the total minimum execution time for the MCU chip test board to execute each MCU operation assessment test case based on the minimum execution time of each MCU operation assessment test case.

[0035] The control signals include a wake-up signal, an ignition signal, and a test instruction; The wake-up signal is used to activate the communication between the MCU chip test board and the hardware-in-the-loop system; The ignition signal is used to control the power supply and initialization of the MCU chip test board; The test instruction is used to control the MCU chip test board to call each MCU operation assessment test case or combined test case.

[0036] The formula for the result processing unit to calculate the minimum execution time of the combined test case is:

[0037] Where, T 2 is the start time of the combined test case, T 1 is the end time of the combined test case.

[0038] The formula for the result processing unit to calculate the total minimum execution time of each MCU operation assessment test case is:

[0039] Where, , is the minimum execution time of the i-th test case, is the assessment ratio or weight of the i-th test case, , is the end time of the i-th test case, The start time of the i-th test case, m is the total number of MCU operation assessment test cases.

[0040] Specifically, in this embodiment, the test cases are loaded into the MCU chip through the hardware-in-the-loop system, and the MCU chip is controlled to execute the relevant operations of the test case combination. The MCU chip is designed as an MCU chip test board. The hardware-in-the-loop system includes a signal sending unit, a signal acquisition unit, and a result processing unit. The signal sending unit sends a wake-up signal to the MCU chip test board through the GPIO interface to activate the communication link between the MCU chip test board and the hardware-in-the-loop system, so that the MCU chip test board is ready to receive and process subsequent instructions and data; sends an ignition signal to the MCU chip test board through the CANFD1 interface to simulate the vehicle ignition action, so that the MCU chip test board performs power supply and initialization operations to prepare for the formal test; sends a test instruction to the MCU chip test board through the AD interface to instruct the MCU chip test board to call the corresponding test case and start the specific test process. The test data (data 1, data 2... data N) are sent to the MCU chip test board through the SPI (Serial Peripheral Interface), I2C (Inter-Integrated Circuit Interface), and AD interfaces. These data simulate the actual data collected by various sensors during the vehicle operation and provide input for the arithmetic test of the MCU chip. The MCU chip test board calls each test case (case 1, case 2... case X) according to the test data for the arithmetic test; the signal acquisition unit collects the test start time T1 and the test end time T2 from the MCU chip test board through the CANFD2 interface and sends them to the result processing unit. The result processing unit calculates the minimum execution time for the MCU chip test board to execute each MCU arithmetic assessment test case or combined test case based on the collected test start time T1 and test end time T2, and calculates the total minimum execution time for the MCU chip test board to execute each MCU arithmetic assessment test case based on the minimum execution time of each MCU arithmetic assessment test case. Finally, the calculated results and other relevant test information are sorted out to generate a test report for output, which is convenient for testers to evaluate and analyze the performance of each MCU chip. The HIL system simulates the vehicle signal interaction to standardize the test process and reproduce the results, reducing the manual debugging cost.

[0041] The test process is as follows: The signal sending unit of the HIL system first sends a wake-up signal to activate the communication between the MCU chip and the outside, and then sends an ignition signal to enable the MCU chip to complete power supply and initialization. Then, it sends a test instruction to instruct the MCU chip to call the test case; at the same time, the test data module of the HIL system sends various test data to the MCU chip test board; after the MCU chip test board calls the test case and receives the data, it starts to perform arithmetic tests; during the test, the signal acquisition unit of the HIL system records the test start time T1 and the test end time T2; finally, the result processing unit of the HIL system calculates the minimum execution time ΔT for the MCU chip to complete the combined test case or the total minimum execution time for each MCU arithmetic assessment test case based on the collected time information, and outputs a test report.

[0042] The various embodiments of the present invention have been described above. The above description is exemplary and not exhaustive, and is also not limited to the disclosed embodiments. Many modifications and variations are obvious to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A method for evaluating the adaptation of an MCU chip, characterized in that, Including: Determine the corresponding MCU computing power requirements based on various application scenarios of the vehicle controller; Abstract the MCU computing power requirements based on computing elements to construct MCU operation assessment test cases corresponding to various application scenarios; Determine the assessment ratio or weight of each MCU operation assessment test case based on the demand ratio of each application scenario for MCU computing power; Combine each MCU operation assessment test case based on the assessment ratio or weight to form a combined test case; perform MCU operation assessment tests on each MCU chip based on the combined test case to obtain the minimum execution time of each MCU chip for the typical algorithm corresponding to the combined test case; Determine the most suitable MCU chip based on the minimum execution time of each MCU chip for the typical algorithm of the combined test case.

2. The MCU chip adaptation evaluation method according to claim 1, wherein Also including: Perform MCU operation assessment tests on each MCU chip based on each MCU operation assessment test case to obtain the minimum execution time of each MCU chip for the typical algorithm corresponding to each MCU operation assessment test case; Select the one with the smallest sum of the products of the minimum execution time of each MCU chip for the typical algorithm of each MCU operation assessment test case and the assessment ratio or weight as the most suitable MCU chip.

3. The MCU chip adaptation evaluation method according to claim 1, characterized in that The computing elements include: Computing paradigm, computing volume, and storage volume.

4. The MCU chip adaptation evaluation method according to claim 1, characterized in that, The determining the most suitable MCU chip based on the minimum execution time of each MCU chip for the typical algorithm of the combined test case further includes: Compare the minimum execution time of each MCU chip for the typical algorithm of the combined test case, and select the one with the shortest total minimum execution time as the most suitable MCU chip.

5. The MCU chip adaptation evaluation method according to claim 2, wherein, Performing MCU operation assessment tests based on the combined test case or each MCU operation assessment test case includes: Load the combined test case or each MCU operation assessment test case into the MCU chip through a hardware-in-the-loop system, and control the MCU chip to execute the relevant operations of the combined test case or each MCU operation assessment test case.

6. The MCU chip adaptation evaluation method according to claim 5, wherein The MCU chip is designed as an MCU chip test board, and the hardware-in-the-loop system is communicatively connected to the MCU chip test board.

7. The MCU chip adaptation evaluation method according to claim 6, wherein The hardware-in-the-loop system includes a signal sending unit, a signal acquisition unit, and a result processing unit; The signal sending unit is used to send control signals and test case data to the MCU chip test board; The signal acquisition unit is used to collect the start time and end time of the MCU chip test board executing the combined test case or each MCU operation assessment test case; The result processing unit is used to calculate the minimum execution time of the MCU chip test board for executing the combined test case or each MCU operation assessment test case, and calculate the total minimum execution time of the MCU chip test board for executing each MCU operation assessment test case based on the minimum execution time of each MCU operation assessment test case.

8. The MCU chip adaptation evaluation method according to claim 7, wherein The control signals include wake-up signals, ignition signals, and test instructions; The wake-up signal is used to activate the communication between the MCU chip test board and the hardware-in-the-loop system; The ignition signal is used to control the power supply and initialization of the MCU chip test board; The test instruction is used to control the MCU chip test board to call each MCU operation assessment test case or combined test case.

9. The MCU chip adaptation evaluation method according to claim 7, wherein The formula for the result processing unit to calculate the total minimum execution time of each MCU operation assessment test case is: Among them, is the minimum execution time of the i-th test case, is the assessment ratio or weight of the i-th test case, , is the end time of the i-th test case, is the start time of the i-th test case, and m is the total number of MCU operation assessment test cases.

10. The MCU chip adaptation evaluation method according to claim 7, characterized in that, The formula for the result processing unit to calculate the minimum execution time of the combined test case is: Among them, T 2 is the start time of the combined test case, T 1 is the end time of the combined test case.

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