PRBS code generator, detector, core particle and electronic equipment

Abstract

The embodiment of the invention provides a PRBS code generator, a detector, a core particle and electronic equipment, and the PRBS code generator comprises a first data shift unit which comprises a plurality of shift registers, and the shift registers are used for receiving and storing to-be-output data of preset data bits; the first pre-operation unit is used for generating update data based on the to-be-output data and sending the update data as the to-be-output data to the corresponding shift register after the shift register outputs the to-be-output data; wherein the first pre-operation unit generates a preset number of update data in a clock period, and the preset number is greater than or equal to 2; and the first serial-parallel conversion unit is used for outputting the to-be-output data in the preset number of shifting registers in the first data shifting unit in parallel. According to the scheme, the generation of the data sequence applied to the parallel scene is realized.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of computer integrated circuit design and manufacturing, and specifically to a PRBS code generator, a detector, a core particle and an electronic device. Background Art

[0002] PRBS (Pseudo-Random Binary Sequence) is a repeatable binary sequence that appears to be random but is actually generated by a specific algorithm or circuit. It can be used for bit error rate testing of high-speed serial channels, such as PCBE, USB, Ethernet and other protocol testing, and can also be used for chip functional testing and system-level testing.

[0003] Among them, the existing hardware solution for generating PRBS is only applicable to serial data transmission scenarios.

[0004] However, as the application scope of parallel data transmission solutions gradually expands, how to provide a hardware solution for generating PRBS to adapt to parallel data transmission scenarios has become a technical problem that needs to be urgently solved in this field. Summary of the invention

[0005] In view of this, an embodiment of the present application provides a PRBS code generator, a detector, a core particle and an electronic device, which realize the generation of a data sequence applied to a parallel scenario.

[0006] To achieve the above objectives, the present application provides the following technical solutions:

[0007] The present application provides a PRBS code generator, including:

[0008] A first data shift unit, comprising a plurality of shift registers, wherein the shift registers are used to receive and store data to be outputted with preset data bits;

[0009] a first pre-operation unit, configured to generate update data based on the data to be output, and after the shift register outputs the data to be output, send the update data as the data to be output to the corresponding shift register; wherein the first pre-operation unit generates a preset number of update data within one clock cycle, and the preset number is greater than or equal to 2;

[0010] The first serial-to-parallel conversion unit is used to output the to-be-output data in a preset number of shift registers in the first data shift unit in parallel.

[0011] Optionally, the first pre-operation unit includes at least a preset number of XOR gates; wherein the input end of each XOR gate is connected to the shift register of the corresponding data bit based on the calculation method of the corresponding update data.

[0012] Optionally, the first pre - operation unit further includes a plurality of pre - operation caches, wherein one pre - operation cache corresponds to one shift register and is used to store the data to be output corresponding to the shift register in the next clock cycle.

[0013] Optionally, the preset quantity is less than the number of shift registers in the first data shift unit, the number of pre - operation caches is the preset quantity, the data to be output corresponding to the next clock cycle stored in the pre - operation cache is the preset quantity of updated data generated in the current clock cycle, and the updated data is used to be sent to the first preset quantity of shift registers in the first data shift unit;

[0014] The shift registers in the first data shift unit are connected to the shift registers corresponding to the data bits with a preset difference from their data bits, and the preset difference is equal to the preset quantity.

[0015] Optionally, the preset quantity is less than or equal to the number of shift registers in the first data shift unit, the number of pre - operation caches is the number of shift registers in the first data shift unit, the data to be output corresponding to the next clock cycle stored in the pre - operation cache is the preset quantity of updated data generated in the current clock cycle, and the data to be output for shifting in the next clock cycle;

[0016] Among them, the pre - operation caches for storing updated data are sequentially connected to the shift registers corresponding to the first preset quantity of data bits in the first data shift unit, and the pre - operation caches for storing the data to be output for shifting in the next clock cycle are sequentially connected to the shift registers corresponding to the last Y data bits in the first data shift unit, where Y is the difference between the number of shift registers in the first data shift unit and the preset quantity.

[0017] Optionally, the first serial - to - parallel conversion unit is used to connect to the shift registers corresponding to the last preset quantity of data bits to output the data to be output with the last preset quantity of data bits.

[0018] Optionally, the preset quantity is greater than the number of shift registers in the first data shift unit, the number of pre - operation caches is a positive - integer multiple of the number of shift registers in the first data shift unit and the number of pre - operation caches is greater than or equal to the preset quantity;

[0019] The pre - operation caches in the first pre - operation unit are divided into multiple layers. Among them, the number of data in one layer of pre - operation cache is the same as the number of shift registers in the first data shift unit, and each layer of pre - operation cache is sorted in sequence and stores the pre - operation results of at least the preset quantity of updated data based on the corresponding sorting.

[0020] Optionally, the PRBS code generator is further configured with a first output buffer for storing data bits that exceed the number of shift registers, where a first output buffer is for storing data of one data bit.

[0021] Optionally, the first serial-to-parallel conversion unit includes a plurality of parallel sub-units. If the preset number is less than or equal to the number of shift registers in the first data shift unit, the parallel sub-units are sequentially connected to the shift registers in the first data shift unit whose data bits are the preset number of bits at the back;

[0022] If the preset number is greater than the number of shift registers in the first data shift unit, the parallel sub-units are sequentially connected to each shift register in the first data shift unit and the first output buffer.

[0023] Optionally, the parallel sub-unit includes parallel lines for outputting the data to be output of the connected shift registers.

[0024] Optionally, the parallel sub-unit further includes an inverter and a selector connected to the parallel lines. Wherein, the input end of the inverter is for connecting to the parallel lines to invert the data in the parallel lines, and the output end is connected to the selector. The input end of the selector is connected to the parallel lines and the inverter for selecting the data to be output, and the output end is for outputting the selected data.

[0025] Optionally, the parallel sub-unit further includes an error injector. The input end of the error injector is for connecting to the output end of the selector and the error injection signal end for injecting errors into the data based on the control of the error injection signal end.

[0026] An embodiment of the present application further provides a PRBS code detector, including:

[0027] A second data shift unit including a plurality of shift registers, where the shift registers are for receiving and storing the data to be detected of a preset number of data bits;

[0028] A second pre-operation unit for generating a preset number of data to be compared based on the data to be detected in the second data shift unit in the current clock cycle; wherein, the second pre-operation unit generates a preset number of updated data in one clock cycle, and the preset number is greater than or equal to 2;

[0029] An error detection unit for determining whether the data to be detected in the next clock cycle is in error based on the data to be compared after the second data shift unit receives the data to be detected in the next clock cycle, and outputting the corresponding error information in parallel;

[0030] The second serial-parallel conversion unit is configured to output in parallel the data to be output in a preset number of shift registers in the first data shift unit.

[0031] Optionally, it further includes: a second input buffer, which is connected to the input end of the shift register, and is configured to pre-obtain at least a preset number of data to be detected, and input the data to be detected in parallel into the shift registers corresponding to the corresponding number of bits, wherein one second input buffer is used to buffer one data bit.

[0032] Optionally, the number of the second input buffers is the preset number. When the preset number is less than the number of shift registers in the second data shift unit, the preset number of second input buffers are used to be sequentially connected to the shift registers corresponding to the first preset number of data bits based on the arrangement order of the data bits;

[0033] The shift register is connected to the shift register corresponding to the data bit with a preset difference from its data bit, and the preset difference is the preset number.

[0034] Optionally, the preset number is greater than the number of shift registers in the second data shift unit, and the PRBS code detector further includes a second output buffer, which is configured to store the data of the data bits exceeding the number of shift registers, wherein one second output buffer is used to store the data of one data bit;

[0035] The number of the second input buffers is an integer multiple of the number of shift registers in the second data shift unit and the number of the second input buffers is greater than or equal to the preset number, and at least the preset number of the second input buffers are sequentially connected to the shift register and the second output buffer based on the arrangement order of the data bits.

[0036] Optionally, the second pre-operation unit includes at least a preset number of exclusive-OR gates; wherein the input ends of the exclusive-OR gates are connected to the shift registers corresponding to the corresponding data bits based on the calculation method of the data to be compared corresponding to them.

[0037] Optionally, the second pre-operation unit further includes a plurality of pre-operation buffers, wherein one pre-operation buffer corresponds to one shift register and is configured to store the data to be compared corresponding to the shift register in the next clock cycle.

[0038] Optionally, the preset number is less than the number of shift registers in the second data shift unit;

[0039] The number of the pre-operation buffers is the preset number, and the pre-operation buffers are used for the data to be compared; or the number of the pre-operation buffers is the number of shift registers in the second data shift unit, and the pre-operation buffers are used to store the data to be compared and the data to be detected for shifting in the next clock cycle.

[0040] Optionally, the preset quantity is greater than the number of shift registers in the second data shift unit;

[0041] The number of pre-operation caches is a positive integer multiple of the number of shift registers in the second data shift unit, and the number of pre-operation caches is greater than or equal to the preset quantity;

[0042] The pre-operation caches in the second pre-operation unit are divided into multiple layers. Among them, the number of data in one layer of pre-operation cache is the same as the number of shift registers in the second data shift unit, and each layer of pre-operation caches is sorted in sequence and stores the pre-operation results of at least the preset quantity of data to be compared based on the corresponding sorting.

[0043] Optionally, the PRBS code generator is further configured with a second output cache, and the second output cache is used to store the data bits of the data exceeding the number of shift registers, wherein one second output cache is used to store the data of one data bit.

[0044] Optionally, the error detection unit includes:

[0045] Data comparison logic, which is used to compare the data to be compared and the data to be detected to determine whether the data to be detected is in error. The number of data comparison logics is greater than or equal to the preset quantity;

[0046] Output logic, which is used to output the error information obtained by comparison in parallel.

[0047] Optionally, the second serial-to-parallel conversion unit includes multiple parallel sub-units. If the preset quantity is less than or equal to the number of shift registers in the second data shift unit, the parallel sub-units are sequentially connected to the shift registers with the last preset quantity of data bits in the second data shift unit;

[0048] If the preset quantity is greater than the number of shift registers in the first data shift unit, the parallel sub-units are sequentially connected to each shift register in the second data shift unit and the second output cache.

[0049] Optionally, an error correction unit is further included, and the error correction unit includes error location logic and error correction logic;

[0050] Among them, the error location logic is used to pre-obtain the data to be detected for 2 clock cycles, calculate the data to be compared based on the data to be detected in the previous clock cycle, and perform comparison of the data to be detected in the subsequent clock cycle based on the data to be compared to determine the data to be detected in error.

[0051] The error correction logic is used to correct the in-error data bits.

[0052] The embodiment of the present application also provides a die, including the PRBS code generator, and / or including the PRBS code detector.

[0053] The embodiment of the present application also provides an electronic device, including the die as described above. Wherein, the PRBS code generator and the PRBS code detector are disposed in at least one die, or one die is provided with the PRBS code generator, and another die is provided with the PRBS code detector.

[0054] The embodiment of the present application provides a PRBS code generator, a detector, a die, and an electronic device. The PRBS code generator includes: a first data shift unit, including a plurality of shift registers, wherein the shift registers are used to receive and store the data to be output of a preset data bit; a first pre-operation unit, configured to generate updated data based on the data to be output, and after the shift register outputs the data to be output, send the updated data as the data to be output to the corresponding shift register; wherein, the first pre-operation unit generates a preset number of updated data within one clock cycle, and the preset number is greater than or equal to 2; a first serial-to-parallel conversion unit, configured to parallelly output the data to be output in a preset number of shift registers in the first data shift unit.

[0055] It can be seen that for the PRBS code generator, detector, die, and electronic device provided by the embodiment of the present application, wherein, the first pre-operation unit generates a preset number of updated data within one clock cycle based on the data to be output, and sends the updated data as the data to be output to the corresponding register of the first data shift unit, so that the first serial-to-parallel conversion unit can parallelly output the data to be output in a preset number of shift registers in the first data shift unit, realizing the generation of a data sequence applied to a parallel scenario. Description of the Drawings

[0056] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0057] Figure 1 It is an optional structural example diagram of a PRBS code generator;

[0058] Figures 2 to 5 It is an optional structural schematic diagram of the PRBS code generator provided by the embodiment of the present application;

[0059] Figures 6 to 10This is an optional structural schematic diagram of the PRBS code detector provided by the embodiments of the present application. Detailed implementation manners

[0060] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0061] Refer to Figure 1 An optional structural example diagram of a PRBS code generator shown. The PRBS code generator includes a plurality of sequentially connected shift registers and an exclusive-OR gate for data update.

[0062] Among them, a shift register is used to store a binary data (that is, store the data of a data bit). The data in the shift register is sequentially shifted and transmitted from the head to the tail based on the corresponding connection order, and the data is output based on the shift register at the tail (see Figure 1 PRBS_OUT in

[0063] The exclusive-OR gate is connected to the shift register corresponding to a specific data bit, and is used to generate updated data based on the data in the shift register to which it is connected and send the updated data to the shift register at the head. Correspondingly, during the data flow process, the shift register at the head inputs the updated data one by one, and the shift register at the tail outputs the data one by one, thereby forming a logical loop of the data.

[0064] Taking a generator for generating PRBS7 code as an example, it includes 7 shift registers R0 to R6, corresponding to data bits 0 to 6 respectively. The inputs of the exclusive-OR gate are connected to the shift registers R5 and R6 corresponding to data bits 5 and 6.

[0065] Among them, the data generation process of the PRBS code generator is iterated based on the drive of a clock signal. At the initial moment, initial values are configured for the shift registers. In one clock cycle, the data in the shift register is shifted one bit to the right by bit. The data at the highest bit is shifted out of the register, and the exclusive-OR gate outputs updated data according to the connected register and sends the updated data to the shift register at the lowest bit. By repeating this process in each clock cycle, the shift register is continuously shifted and the data is updated, and a seemingly random binary sequence, that is, the PRBS code, is output.

[0066] It can be seen that the existing hardware solutions for generating PRBS can only be applied to the serial data transmission scenario.

[0067] However, as the application scope of parallel data transmission solutions gradually expands, how to provide a hardware solution for generating PRBS to adapt to parallel data transmission scenarios has become a technical problem that needs to be urgently solved in this field.

[0068] In view of this, an embodiment of the present application provides a PRBS code generator, a detector, a core particle and an electronic device, wherein the PRBS code generator includes: a first data shift unit, including multiple shift registers, wherein the shift register is used to receive and store data to be output of preset data bits; a first pre-operation unit, used to generate update data based on the data to be output, and after the shift register outputs the data to be output, the update data is sent to the corresponding shift register as the data to be output; wherein the first pre-operation unit generates a preset number of update data within one clock cycle, and the preset number is greater than or equal to 2; a first serial-to-parallel conversion unit, used to output the data to be output in a preset number of shift registers in the first data shift unit in parallel.

[0069] Among them, the first pre-operation unit generates a preset number of update data within one clock cycle based on the data to be output, and sends the update data as the data to be output to the corresponding register of the first data shift unit, so that the first serial-to-parallel conversion unit can output the data to be output in the preset number of shift registers in the first data shift unit in parallel, thereby realizing the generation of data sequences applied to parallel scenarios.

[0070] In order to better understand the solution provided in the embodiment of the present application, the specific content of the hardware solution for generating PRBS is further explained below.

[0071] In an embodiment of the present application, a PRBS code generator is provided, referring to Figures 2 to 5 An optional structural schematic diagram of a PRBS code generator is shown, wherein the PRBS code generator comprises:

[0072] The first data shift unit 200 includes a plurality of shift registers, wherein the shift registers are used to receive and store data to be output of preset data bits; the first pre-operation unit 210 is used to generate update data based on the data to be output, and after the shift register outputs the data to be output, the update data is sent as the data to be output to the corresponding register of the first data shift unit; wherein the first pre-operation unit generates a preset number of update data within one clock cycle, and the preset number is greater than or equal to 2; the first serial-to-parallel conversion unit 220 is used to output in parallel the data to be output in a preset number of shift registers in the first data shift unit.

[0073] The data to be output is used to indicate the data stored in the shift register. Among them, the data bits of the data to be output match the corresponding data bits of the shift register where each data is located.

[0074] It can be understood that the shift register is used to shift and store one data bit within one clock cycle. In view of the fact that the PRBS code generates a data sequence based on multiple data bits, the number of shift registers in the first data shift unit is multiple, and this number matches the PRBS code generation mechanism. In an alternative example, the PRBS code stream patterns may include PRBS7, PRBS9, PRBS31, etc. Correspondingly, the number of shift registers in PRBS7 is 7, the number of shift registers in PRBS9 is 9, and the number of shift registers in PRBS31 is 31.

[0075] It should be noted that in the first data shift unit, the shift registers (taking Figure 3 and Figure 4 R0 - R6 in it as an example) are arranged based on a preset data bit order, so that they correspond one by one to the preset data bits. Furthermore, when it is necessary to obtain the data of a certain data bit, the data of this data bit can be obtained from the corresponding shift register based on the corresponding relationship.

[0076] In the embodiment of the present application, the shift registers are not connected in sequence based on the arrangement order of the corresponding preset data bits. This is because in the embodiment of the present application, it is necessary to output multiple bits of data in parallel. Taking the output of the preset number N of data as an example, correspondingly, the shift register should shift the preset number N times within one clock cycle. In view of the fact that the connection scheme of connecting in sequence based on the arrangement order of the corresponding preset data bits can only perform one shift within one clock cycle, it obviously cannot meet the requirements of the present application.

[0077] In a specific implementation, the shift register can be connected to the first pre - operation unit, and the first pre - operation unit calculates the data to be output that each shift register should store in the corresponding clock cycle, so as to receive and store the corresponding data to be input.

[0078] Among them, if the preset number N is less than the number P1 of shift registers in the first data shift unit, the shift register can also be connected to the shift register corresponding to the data bit with a preset difference M1 from its data bit. This preset difference M1 can be equal to the preset number N, so as to skip some shift registers for data shifting, and make it appear that it shifts the preset number N of data bits within one clock cycle from the perspective of data flow. Refer to Figure 3As shown, taking 7 shift registers R0 to R6 corresponding to data bits 0 to 6 respectively and the preset quantity being 4 as an example, correspondingly, in order to make the difference of the data bits be 4, the shift register R0 corresponding to the data bit 0 can be connected to the shift register R4 corresponding to the data bit 4; the shift register R1 corresponding to the data bit 1 can be connected to the shift register R5 corresponding to the data bit 5; the shift register R2 corresponding to the data bit 2 can be connected to the shift register R6 corresponding to the data bit 6.

[0079] It should be noted that at the initial moment, an initial value can be configured for the shift register, so as to generate corresponding updated data based on this initial value.

[0080] The first pre-operation unit is used to generate a preset quantity of updated data within one clock cycle, so as to supplement the corresponding quantity of updated data for the shift register, so that after the data to be output in the shift register is output in parallel, the logical loop of data flow can still be maintained. It should be noted that to ensure the normal flow of data, the first pre-operation unit can perform an initial pre-operation for one or more clock cycles after the initial moment. Among them, if the preset quantity N is less than or equal to the quantity P1 of shift registers in the first data shift unit, the first pre-operation unit can perform an initial pre-operation for one clock cycle after the initial moment; if the preset quantity N is greater than the quantity P1 of shift registers in the first data shift unit, the first pre-operation unit can perform an initial pre-operation for multiple clock cycles after the initial moment until the first pre-operation unit generates updated data greater than or equal to the preset quantity N.

[0081] Among them, the generation method of the preset quantity of updated data is determined based on the generation mechanism of the PRBS code. In the generation mechanism of the PRBS7 code, PRBS7 = X^7 + X^6 + 1, that is, the data in the shift register R6 corresponding to the data bit 6 is exclusive-ORed with the data in the shift register R5 corresponding to the data bit 5, that is, R6⊕R5. When multiple updated data need to be generated, they are inferred and determined one by one based on the generation mechanism of the next updated data. In the generation mechanism of the PRBS7 code, the next updated data can be obtained by exclusive-ORing the data in the shift register R5 corresponding to the data bit 5 with the data in the shift register R4 corresponding to the data bit 4, that is, R5⊕R4, and so on. Taking the preset quantity N as 4 as an example (refer to Figure 3 and Figure 4 ), the calculation methods corresponding to the 4 required updated data B0 - B3 can be inferred as B3 = R6⊕R5, B2 = R5⊕R4, B1 = R4⊕R3, B0 = R3⊕R2; if the preset quantity N is 8 (refer to Figure 5), the calculation methods for the required 8 updated data B10 - B16 and B26 can be inferred, where B16 = R6⊕R5, B15 = R5⊕R4, B14 = R4⊕R3, B13 = R3⊕R2, B12 = R2⊕R1, B11 = R1⊕R0, B10 = R0⊕(R6⊕R5), and B26 = (R6⊕R5)⊕(R5⊕R4), and so on. Correspondingly, the hardware solution of the first pre - operation unit can implement the calculation methods corresponding to each data bit.

[0082] Specifically, the first pre - operation unit may include at least a preset number of exclusive - OR gates (not shown in the figure); among them, the input terminals of each exclusive - OR gate are connected to the shift registers corresponding to the data bits based on the calculation method of the corresponding updated data; for example, for the updated data B3 = R6⊕R5, the input terminals of the corresponding exclusive - OR gate are connected to the shift registers R6 and R5 to implement the corresponding exclusive - OR calculation.

[0083] In an alternative example, the first pre - operation unit may further include a plurality of pre - operation caches. One pre - operation cache corresponds to one shift register and is used to store the data to be output corresponding to the shift register in the next clock cycle. The number of pre - operation caches may be a preset number N, or a positive integer multiple of the number P1 of shift registers in the first data shift unit, and the positive integer multiple of the number of shift registers is greater than or equal to the preset number.

[0084] In the scenario where the preset number N is less than or equal to the number P1 of shift registers in the first data shift unit, the number of pre - operation caches may be the preset number N, or the number P1 of shift registers in the first data shift unit. Specifically, the solution of the present application may be as follows:

[0085] In the example where the number of pre - operation caches in the first pre - operation unit is the preset number N, the pre - operation caches (refer to Figure 3 B0 - B3 therein) are used to store the data to be output corresponding to the next clock cycle, which are the preset number N of updated data generated in the current clock cycle. It should be noted that in this example, the shift registers in the first data shift unit are connected to the shift registers corresponding to the data bits with a preset difference M1 from their data bits, and the preset difference may be equal to the preset number N, so as to realize the logical loop of the data flow.

[0086] Among them, the updated data generated by the first pre - operation unit is multi - bit. Correspondingly, the updated data is sent to the first N shift registers of the first data shift unit. In an alternative example, the pre - operation caches are sequentially connected to the shift registers corresponding to the first N data bits of the first data shift unit (refer to Figure 3), so that the preset number N of updated data is sent to the shift registers corresponding to the first preset number N of data bits of the first data shift unit.

[0087] In the example where the number of pre-computed caches in the first pre-computation unit is the same as the number of shift registers in the first data shift unit, when N is less than the number P1 of shift registers in the first data shift unit, refer to Figure 4 , the pre-computed cache (such as Figure 4 B0 - B6 in) is used to store the data to be output corresponding to the next clock cycle, which is the preset number N of updated data generated in the current clock cycle, and the data to be output for shifting in the next clock cycle. Still taking the preset number N as 4 as an example, the pre-computed cache is used to store the data to be output corresponding to the next clock cycle, which is the preset number N of updated data B0 - B3 generated in the current clock cycle, and the data to be output for shifting in the next clock cycle, R0 - R2.

[0088] In a specific solution, the updated data is used to be sent to the first preset number N of shift registers of the first data shift unit, and the data to be output for shifting in the next clock cycle is used to be sent to the next Y (Y = P1 - N, where P1 is the total number of shift registers in the first data shift unit) shift registers of the first data shift unit. In an alternative example, the pre-computed cache for storing the updated data is sequentially connected to the shift registers corresponding to the first preset number N of data bits of the first data shift unit, so that the preset number N of updated data is sent to the shift registers corresponding to the first preset number N of data bits of the first data shift unit; the pre-computed cache for storing the data to be output for shifting in the next clock cycle is sequentially connected to the shift registers corresponding to the next Y data bits of the first data shift unit, so that the data to be output for shifting in the next clock cycle is sent to the shift registers corresponding to the next Y data bits of the first data shift unit.

[0089] It should be noted that during the data calculation and data transmission process, the data corresponding to each pre-computed cache and the data corresponding to each shift register correspond to each other based on the data bits to avoid data disorder problems.

[0090] In the scenario where the preset number N is greater than the number P1 of shift registers in the first data shift unit, the number of pre-computed caches can be a positive integer multiple of the number P1 of shift registers in the first data shift unit, and the number of pre-computed caches is greater than or equal to the preset number. Specifically, the solution of this application can be as follows:

[0091] The pre-computed caches in the first pre-computation unit can be divided into multiple layers (see Figure 5B10 - B16 is one layer, and B20 - B26 is one layer), where the number of data in the pre - operation cache of one layer is the same as the number of shift registers in the first data shift unit, and the pre - operation caches of each layer are sorted in sequence and store the pre - operation results of at least a preset number of updated data based on the corresponding sorting.

[0092] It can be understood that after the initial moment, during the initial pre - operation for multiple clock cycles, it is possible to calculate only a preset number N of updated data, or calculate the updated data suitable for the number of pre - operation caches, and fill the updated data into the pre - operation cache in the first pre - operation unit, so that in the subsequent process, the updated data is continuously calculated to complete the logical loop of data flow.

[0093] It should be noted that in the embodiments of the present application, when the preset number N is greater than the number P1 of shift registers in the first data shift unit, the PRBS code generator can also configure a first output cache, and the first output cache is used to store the data bits of the data exceeding the number P1 of shift registers, where one first output cache is used to store the data of one data bit. Correspondingly, the number of the first output caches is the difference between the preset number N and the number P1 of shift registers. For example, when the PRBS7 code generator generates parallel data with a preset number N of 8, 1 first output cache can be configured (see Figure 5 ), to store the data bits of the data exceeding the shift register; correspondingly, when the PRBS7 code generator generates parallel data with a preset number N of 16, 9 first output caches can be configured.

[0094] Among them, the first output cache is used to connect to the first pre - operation unit to obtain the number of data to be output, which is the difference between the number P1 of shift registers in the first pre - operation unit and the preset number N, and output the data to be output to the first serial - to - parallel conversion unit.

[0095] The first serial - to - parallel conversion unit is connected to the first data shift unit to output a preset number of data to be output in parallel. Among them, when the preset number N is less than or equal to the number P1 of shift registers in the first data shift unit, the first serial - to - parallel conversion unit is used to output the data bits of the last N bits of the data to be output. Correspondingly, the first serial - to - parallel conversion unit is used to connect to the shift registers corresponding to the last N bits of the data bits.

[0096] Among them, when the preset number N is greater than the number P of shift registers in the first data shift unit, the first serial - to - parallel conversion unit is further connected to the first output cache and is used to output the number of data to be output, which is the difference between the number P1 of shift registers and the preset number N.

[0097] In the specific implementation, refer to Figure 3 orFigure 4 The first serial-to-parallel conversion unit includes a plurality of parallel sub-units. When the preset quantity N is less than or equal to the quantity P of shift registers in the first data shift unit, the parallel sub-units are sequentially connected to the shift registers with the last N bits of data bits in the first data shift unit, so as to output the data to be output in the last N bits of shift registers in parallel. When the preset quantity N is greater than the quantity P of shift registers in the first data shift unit, the parallel sub-units are further connected to each shift register in the first data shift unit and the first output buffer, so as to output the N bits of data to be output in parallel.

[0098] In a specific example, the parallel sub-unit includes parallel lines for outputting the data to be output of the connected shift registers (refer to Figures 3 - 4 , where PRBS_OUT1, PRBS_OUT2, PRBS_OUT3, and PRBS_OUT4 are the output terminals of the corresponding parallel lines).

[0099] In a further example, the PRBS code generator can also be configured with a structure for inverting the polarity. Specifically, the parallel sub-unit can also include an inverter and a selector (see Figure 3 / Figure 4 ), where the input terminal of the inverter is used to connect to the parallel lines for inverting the data in the parallel lines, and the output terminal is connected to the selector. The input terminals of the selector are connected to the parallel lines and the inverter for selecting the data to be output, and the output terminal is used to output the selected data.

[0100] In a further example, the PRBS code generator can also be configured with a structure for injecting errors into the data. Specifically, the parallel sub-unit can also include an error injector. The input terminal of the error injector is used to connect to the output terminal of the selector and the error injection signal terminal (inject_err) for realizing the injection of errors into the data based on the control of the error injection signal terminal. In a specific example, the error injector can be, for example, an inverter.

[0101] It can be seen that in the embodiment of the present application, the first pre-operation unit generates a preset quantity of updated data within one clock cycle and sends the updated data as the data to be output to the corresponding registers in the first data shift unit, so that the first serial-to-parallel conversion unit can output the data to be output in the preset quantity of shift registers in the first data shift unit in parallel, realizing the generation of a data sequence applied to a parallel scenario.

[0102] In the embodiment of the present application, a PRBS code detector is further provided. Refer to Figures 5 to 10Schematic diagram of an optional structure of the PRBS code detector shown, the PRBS code detector includes:

[0103] A second data shift unit 300, including a plurality of shift registers, wherein the shift registers are used to receive and store the data to be detected of a preset number of data bits; a second pre-operation unit 310, configured to generate a preset number of data to be compared based on the data to be detected in the second data shift unit in the current clock cycle; wherein, the second pre-operation unit generates a preset number of data to be detected in one clock cycle, and the preset number is greater than or equal to 2; an error detection unit 330, configured to determine whether the data to be detected in the next clock cycle is in error based on the data to be compared after the second data shift unit receives the data to be detected in the next clock cycle, and output the corresponding error information in parallel; a second serial-to-parallel conversion unit 320, configured to output the data to be output in the preset number of shift registers in the second data shift unit in parallel.

[0104] The data to be detected is used to indicate the data received and stored in the shift register. Wherein, the number of data bits of the data to be detected matches the data bits corresponding to the shift register where each data is located.

[0105] It should be noted that the PRBS detector described in this application is used to detect whether the PRBS code transmitted through the transmission path to be detected is in error, and provides a data basis for calculating the corresponding error rate when transmitting data corresponding to the transmission path to be detected. Wherein, the transmission path to be detected can be a transmission path within a chiplet or a transmission path between chiplets. Based on this application, the generation and detection of data sequences in a parallel scenario can be realized, and the parallel data transmission characteristics between chiplets can be adapted, so that the solution provided by this application can test the transmission path between chiplets with a small hardware overhead.

[0106] It can be understood that the shift register is used to shift and store one data bit in one clock cycle. In view of the fact that the PRBS code detects the data sequence based on multiple data bits, the number of shift registers in the second data shift unit is multiple, and this number matches the PRBS code detection mechanism. In an optional example, the PRBS code stream mode can include PRBS7, PRBS9, PRBS31, etc. The number of shift registers corresponding to PRBS7 is 7, the number of shift registers corresponding to PRBS9 is 9, and the number of shift registers corresponding to PRBS31 is 31.

[0107] It should be noted that in the second data shift unit, the shift register (taking Figure 7 and Figure 8Taking R0 - R6 in it as an example), they are arranged based on a preset order, so that they correspond one by one to the preset data bits. Furthermore, when it is necessary to obtain the data of a certain data bit, the data of this data bit can be obtained from the corresponding shift register based on the corresponding relationship.

[0108] In the embodiment of the present application, the shift registers are not connected in sequence based on the arrangement order corresponding to the preset data bits. This is because in the embodiment of the present application, it is necessary to detect and input multiple bits of data in parallel. Taking the parallel input of the preset number N of data as an example, correspondingly, the shift register should shift the preset number N times within one clock cycle. In view of the connection scheme of connecting in sequence based on the arrangement order corresponding to the preset data bits, which can only perform one shift within one clock cycle, it obviously cannot meet the requirements of the present application.

[0109] Wherein, when the preset number is greater than the number of shift registers in the second data shift unit, the PRBS code detector can further configure a second output buffer for storing the data of the data bits exceeding the number of shift registers, wherein one second output buffer is used for storing the data of one data bit.

[0110] In a specific implementation, the PRBS code detector is further configured with a second input buffer (see Figure 7 K0 - K3 in it), and the second input buffer can be connected to the input end of the shift register for pre - obtaining at least the preset number of data to be detected and parallel - inputting the data to be detected into the shift registers corresponding to the corresponding number of bits.

[0111] In a specific implementation, one second input buffer is used for buffering one data bit, and the number of the second input buffers can be the preset number. If the preset number N is less than or equal to the number P2 of shift registers in the second data shift unit, the preset number of second input buffers are connected to the shift registers corresponding to the first preset number of data bits in sequence based on the arrangement order of the data bits.

[0112] If the preset quantity N is less than the quantity P2 of shift registers in the second data shift unit, the shift registers can be connected to the shift registers corresponding to the data bits with a preset difference M2, and the preset difference M2 can be the preset quantity N, so as to skip some shift registers for data shifting, making it appear that N data bits are shifted in one clock cycle from the perspective of data flow. Taking 7 shift registers R0 - R6 corresponding to data bits 0 - 6 respectively and the preset quantity being 4 as an example, correspondingly, to make the difference between data bits be 4, the shift register R0 corresponding to data bit 0 can be connected to the shift register R4 corresponding to data bit 4; the shift register R1 corresponding to data bit 1 can be connected to the shift register R5 corresponding to data bit 5; the shift register R2 corresponding to data bit 2 can be connected to the shift register R6 corresponding to data bit 6.

[0113] In another implementation, when the preset quantity N is greater than the quantity P2 of shift registers in the second data shift unit, the quantity of the second input buffers can also be an integer multiple of the quantity P2 of shift registers in the second data shift unit (refer to K0 - K6 in Figure 8 or Figure 9 K0 - K6 in Figure 10 or K10 - K16 and K20 - K26 in

[0114] and the quantity of the second input buffers is greater than or equal to the preset quantity. Among them, at least the preset quantity of the second input buffers are sequentially connected to the shift registers and the second output buffer based on the arrangement order of data bits.

[0114] Furthermore, the shift register is also connected to a second pre - operation unit, and the second pre - operation unit generates a preset quantity of data to be compared based on the data to be detected in the second data shift unit in the current clock cycle.

[0115] The second pre - operation unit is used to generate a preset quantity of data to be compared in the current clock cycle, so as to provide a comparison basis for the data to be detected in the next clock cycle received by the second data shift unit to determine the corresponding error information.

[0116] It should be noted that to ensure the normal flow of data, the second pre - operation unit can perform one or more clock cycles of initial pre - operation after the initial moment. Among them, if the preset quantity N is less than or equal to the quantity P2 of shift registers in the second data shift unit, the second pre - operation unit can perform one clock cycle of initial pre - operation after the initial moment; if the preset quantity N is greater than the quantity P2 of shift registers in the second data shift unit, the second pre - operation unit can perform multiple clock cycles of initial pre - operation after the initial moment until the second pre - operation unit generates data to be compared that is greater than or equal to the preset quantity N.

[0117] Among them, the generation method of the preset number of data to be compared is the same as that of the aforementioned updated data, that is, it is determined based on the generation mechanism of the PRBS code. In the generation mechanism of the PRBS7 code, PRBS7 = X^7 + X^6 + 1, that is, the data in the shift register R6 with a data bit of 6 is XORed with the data in the shift register R5 with a data bit of 5, that is, R6⊕R5. When multiple data to be compared need to be generated, they are inferred and determined one by one based on the generation mechanism of the next data to be compared. In the generation mechanism of the PRBS7 code, the next data to be compared can be obtained by XORing the data in the shift register R5 with a data bit of 5 and the data in the shift register R4 with a data bit of 4, that is, R5⊕R4, and so on. Taking the preset number N as 4 as an example, the calculation methods corresponding to the 4 data to be compared I0 - I3 can be inferred: I3 = R6⊕R5, I2 = R5⊕R4, I1 = R4⊕R3, I0 = R3⊕R2; if the preset number N is 8, the calculation methods corresponding to the 8 data to be compared I16 - I10 and I26 can be inferred, where I16 = R6⊕R5, I15 = R5⊕R4, I14 = R4⊕R3, I13 = R3⊕R2, I12 = R2⊕R1, I11 = R1⊕R0, I10 = R0⊕(R6⊕R5), I26 = (R6⊕R5)⊕(R5⊕R4), and so on. Correspondingly, the hardware solution of the second pre-operation unit can implement the calculation methods corresponding to each data bit.

[0118] Specifically, the second pre-operation unit may include at least a preset number of exclusive-OR gates; among them, the input terminals of each exclusive-OR gate are connected to the shift registers corresponding to the data bits based on the calculation method of the corresponding data to be compared; for example, if the data to be compared is calculated based on R6⊕R5, the input terminals of the corresponding exclusive-OR gate are connected to the shift registers R6 and R5 to implement the corresponding exclusive-OR calculation.

[0119] In an alternative example, the second pre-operation unit may further include a plurality of pre-operation caches. One pre-operation cache corresponds to one shift register and is used to store the data to be compared corresponding to the shift register in the next clock cycle. The number of pre-operation caches may be the preset number N or a positive integer multiple of the number P2 of shift registers in the second data shift unit.

[0120] In the scenario where the preset number N is less than the number P2 of shift registers in the second data shift unit, the number of pre-operation caches may be the preset number N or the number P2 of shift registers in the second data shift unit. Specifically, the solution of the present application may be as follows:

[0121] In an example where the number of pre - operation caches is a preset number N, the data to be compared corresponding to the next clock cycle stored in the pre - operation cache is generated based on the data to be detected in the second data shift unit during the current clock cycle. Among them, the data to be compared generated by the second pre - operation unit is multi - bit. Correspondingly, the data to be compared is sent to the pre - operation cache to determine whether the data to be detected in the next clock cycle is in error based on the data to be compared.

[0122] In an example where the number of pre - operation caches is the number of shift registers in the second data shift unit, when N is less than the number of shift registers P2 in the second data shift unit, the data to be compared corresponding to the next clock cycle stored in the pre - operation cache is the preset number N of data to be compared generated during the current clock cycle, and the data to be detected for shifting in the next clock cycle. Still taking the preset number N as 4 as an example, the data to be output corresponding to the next clock cycle stored in the pre - operation cache is the preset number N of data to be compared I0 - I3 generated during the current clock cycle, and the data to be output R0 - R2 for shifting in the next clock cycle.

[0123] It should be noted that during the data calculation and data transmission processes, the data corresponding to each pre - operation cache and the data corresponding to each shift register correspond in sequence based on the data bits to avoid data disorder problems.

[0124] In a scenario where the preset number N is greater than the number of shift registers P2 in the second data shift unit, the number of pre - operation caches can be a positive integer multiple of the number of shift registers P2 in the second data shift unit and the number of pre - operation caches is greater than or equal to the preset number. Specifically, the solution of this application can be as follows:

[0125] The pre - operation caches in the second pre - operation unit can be divided into multiple layers. Among them, the number of data in one - layer pre - operation cache is the same as the number of shift registers in the second data shift unit, and each layer of pre - operation caches is sorted in sequence and stores the pre - operation results of at least the preset number of data to be compared based on the corresponding sorting.

[0126] It can be understood that after the initial pre - operation is performed for multiple clock cycles after the initial moment, the pre - operation caches in the second pre - operation unit can be completely filled, so as to continuously calculate the data to be compared in the subsequent process and complete the logical loop of data flow.

[0127] In a further example, the error - detection unit can include data comparison logic, and the data comparison logic is used to compare the data to be compared and the data to be detected to determine whether the data to be detected is in error.

[0128] Among them, it should be noted that in the clock sequence, taking the current clock cycle as T1 and the next clock cycle of the current clock cycle as T2 as an example, the process in which the second pre-operation unit calculates the data to be compared based on the data to be detected in the current clock cycle T1 of the shift register and stores it in the pre-operation cache consumes one clock cycle, and the calculated data to be compared is exactly the data to be detected updated by the shift register in the next clock cycle T2. Correspondingly, when the comparison logic makes a comparison, the data to be compared in the next clock cycle T2 is compared with the data to be detected of the shift register in the next clock cycle T2, so as to ensure the correspondence of data in different clock cycles.

[0129] In a specific example, the data comparison logic can be an exclusive-OR logic, so as to determine whether there is an error based on the compared data. It can be understood that when the exclusive-OR result is "0", it indicates that the compared data is consistent and there is no error; when the exclusive-OR result is "1", it indicates that the compared data is inconsistent, that is, the data has an error.

[0130] In a specific implementation, in the error detection unit, the number of the data comparison logics is greater than or equal to the preset number N, so as to perform parallel comparison on the data in the shift registers corresponding to each data bit.

[0131] In a further example, the error detection unit may further include an output logic for parallel outputting the error information obtained by comparison.

[0132] The second serial-to-parallel conversion unit is connected to the second data shift unit to parallel output a preset number of data to be detected. Among them, when the preset number N is less than or equal to the number P2 of the shift registers in the second data shift unit, the second serial-to-parallel conversion unit is used to output the data to be detected with the last N bits as data bits. Correspondingly, the second serial-to-parallel conversion unit is used to connect to the shift registers corresponding to the data bits of the last N bits.

[0133] Among them, when the preset number N is greater than the number P2 of the shift registers in the second data shift unit, the second serial-to-parallel conversion unit is further connected to each shift register and the second output cache in the second data shift unit to output the number of data to be detected that is the difference between the number P2 of the shift registers and the preset number N.

[0134] In a specific implementation, the second serial-to-parallel conversion unit includes a plurality of parallel sub-units. When the preset number N is less than or equal to the number P2 of shift registers in the second data shift unit, the parallel sub-units are sequentially connected to the shift registers with the last N data bits in the second data shift unit, so as to parallelly output the data to be detected in the last N shift registers. When the preset number N is greater than the number P2 of shift registers in the second data shift unit, the parallel sub-units are further connected to each shift register in the second data shift unit and the second output buffer, so as to parallelly output the N-bit data to be detected.

[0135] In a specific example, the parallel sub-unit includes parallel lines for outputting the data to be detected of the connected shift register (refer to Figures 7 - 9 , where PRBS_OUT1, PRBS_OUT2, PRBS_OUT3, and PRBS_OUT4 are the output terminals of the corresponding parallel lines).

[0136] In a further example, the PRBS code detector can also be configured with a structure for polarity inversion. Specifically, the parallel sub-unit can further include an inverter and a selector. Among them, the input terminal of the inverter is used to connect to the parallel lines for inverting the data in the parallel lines, and the output terminal is connected to the selector. The input terminals of the selector are connected to the parallel lines and the inverter for selecting the data to be output, and the output terminal is used to output the selected data.

[0137] In a further example, the PRBS code detector can also be configured with a structure for data injection error. Specifically, the parallel sub-unit can further include an error injector. The input terminal of the error injector is used to connect to the output terminal of the selector and the error injection signal terminal for realizing data injection error based on the control of the error injection signal terminal. Among them, in a specific example, the error injector can be an inverter, for example.

[0138] It can be understood that in the generation mechanism of the PRBS code, the data in the next clock cycle is generated based on the data in the previous clock cycle. During the PRBS code detection process, if the data in the previous clock cycle is incorrect, it will cause the data to be compared generated in the next clock cycle to be incorrect, resulting in inaccurate error information obtained subsequently. In view of this, the PRBS code detector described in this application is further configured with a structure for data error correction.

[0139] In a further implementation, specifically, the PRBS code detector can include an error correction unit, and the error correction unit can include error location logic and error correction logic. Among them, the error location logic is used to determine the incorrect data bit, and the error correction logic is used to correct the incorrect data bit.

[0140] In a specific implementation, the error location logic is used to pre-obtain the data to be detected for two clock cycles, calculate the data to be compared based on the data to be detected in the previous clock cycle, and compare the data to be detected in the next clock cycle based on the data to be compared to determine the data to be detected with errors. In a specific example, the error location logic may include an error location buffer for temporarily storing the data to be detected for two clock cycles, a calculation logic for calculating the data to be compared based on the data to be detected in the previous clock cycle, and an exclusive OR logic for comparing the data to be detected in the next clock cycle based on the data to be compared to determine the data to be detected with errors.

[0141] It can be understood that after determining the data to be detected with errors, the error correction logic can be connected to the output end of the shift register, so as to control the data output of the shift register and make the correct data output at the output end of the shift register. It should be noted that within one clock cycle of the shift register storing data, the second pre-operation unit first compares based on the data to be detected therein to determine whether the corresponding data to be detected is in error. Then, before the second pre-operation unit performs pre-operations based on the data to be detected therein to determine the data to be compared in the next clock cycle, the error correction logic is enabled, and the shift register outputs the correct data, and then calculates the corresponding data to be compared based on the correct data.

[0142] It can be understood that after correcting the data based on the error correction logic, the error rate of the data can be determined more accurately, thereby improving the accuracy of the test.

[0143] It can be seen that the solution provided by this application can provide a higher code stream bit width, supporting x4 / x8 / x16 bit widths, etc. At the same time, by improving the PRBS generation technology, it can output multiple data bits in one clock cycle to meet the code stream bit width required by the application. And this application uses a pre-operation method, supporting dynamic switching of the number of pre-operations, such as pre-operating 4 times, 8 times, 16 times, to improve the prbs generation speed. In the parallel operation logic, the additional control logic is reduced, and at the same time, the design area loss is reduced and the power consumption is reduced.

[0144] The embodiment of this application also provides a chiplet, which is configured with a PRBS code generator and / or a PRBS code detector;

[0145] The embodiment of this application also provides an electronic device, which may include the chiplet as described above.

[0146] The above describes multiple embodiment solutions provided by the embodiments of the present application. Each optional manner introduced in each embodiment solution can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible embodiment solutions, all of which can be considered as the embodiment solutions disclosed and made public by the embodiments of the present application.

[0147] Although the embodiments of the present application are disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A PRBS code generator, characterized in that, Comprising: A first data shift unit, including a plurality of shift registers, wherein the shift registers are used to receive and store the data to be output of a preset number of data bits; A first pre-operation unit, configured to generate updated data based on the data to be output, and after the shift register outputs the data to be output, send the updated data as the data to be output to the corresponding shift register; wherein, the first pre-operation unit generates a preset number of updated data within one clock cycle, and the preset number is greater than or equal to 2; A first serial-to-parallel conversion unit, configured to parallelly output the data to be output in a preset number of shift registers in the first data shift unit.

2. The PRBS code generator according to claim 1, wherein The first pre-operation unit includes at least a preset number of exclusive-OR gates; wherein, the input ends of the exclusive-OR gates are connected to the shift registers corresponding to the data bits corresponding to the calculation methods of the updated data corresponding to them.

3. The PRBS code generator according to claim 2, wherein The first pre-operation unit further includes a plurality of pre-operation caches, wherein one pre-operation cache corresponds to one shift register, and is used to store the data to be output corresponding to the shift register in the next clock cycle.

4. The PRBS code generator according to claim 3, wherein The preset number is less than the number of shift registers in the first data shift unit, the number of pre-operation caches is the preset number, the data to be output corresponding to the next clock cycle stored in the pre-operation caches is the preset number of updated data generated in the current clock cycle, and the updated data is used to be sent to the first preset number of shift registers in the first data shift unit; The shift registers in the first data shift unit are connected to the shift registers corresponding to the data bits with a preset difference from their data bits, and the preset difference is equal to the preset number.

5. The PRBS code generator according to claim 3, wherein The preset number is less than or equal to the number of shift registers in the first data shift unit, the number of pre-operation caches is the number of shift registers in the first data shift unit, the data to be output corresponding to the next clock cycle stored in the pre-operation caches is the preset number of updated data generated in the current clock cycle, and the data to be output for shifting in the next clock cycle; Wherein, the pre-operation caches for storing updated data are sequentially connected to the shift registers corresponding to the first preset number of data bits in the first data shift unit, and the pre-operation caches for storing the data to be output for shifting in the next clock cycle are sequentially connected to the shift registers corresponding to the last Y data bits in the first data shift unit, where Y is the difference between the number of shift registers in the first data shift unit and the preset number.

6. The PRBS code generator according to claim 5, wherein, The first serial-to-parallel conversion unit is configured to be connected to the shift registers corresponding to the data bits of the last preset number of bits to output the data to be output with the data bits of the last preset number of bits.

7. The PRBS code generator according to claim 3, wherein The preset number is greater than the number of shift registers in the first data shift unit, the number of pre-operation caches is a positive integer multiple of the number of shift registers in the first data shift unit and the number of pre-operation caches is greater than or equal to the preset number; The pre-operation cache in the first pre-operation unit is divided into multiple layers. Among them, the number of data in one layer of the pre-operation cache is the same as the number of shift registers in the first data shift unit, and each layer of the pre-operation cache is sorted in sequence and stores the pre-operation results of at least a preset number of updated data based on the corresponding sorting.

8. The PRBS code generator according to claim 7, wherein The PRBS code generator is further configured with a first output cache, and the first output cache is used to store the data bits of the data exceeding the number of shift registers, wherein one first output cache is used to store the data of one data bit.

9. The PRBS code generator according to claim 8, wherein The first serial-parallel conversion unit includes multiple parallel sub-units. If the preset number is less than or equal to the number of shift registers in the first data shift unit, the parallel sub-units are sequentially connected to the shift registers in the first data shift unit whose data bits are the subsequent preset number of bits. If the preset number is greater than the number of shift registers in the first data shift unit, the parallel sub-units are sequentially connected to each shift register in the first data shift unit and the first output cache.

10. The PRBS code generator according to claim 9, characterized in that, The parallel sub-unit includes parallel lines for outputting the data to be output of the connected shift registers.

11. The PRBS code generator according to claim 10, wherein The parallel sub-unit further includes an inverter and a selector connected to the parallel lines. Among them, the input end of the inverter is used to connect to the parallel lines to invert the data in the parallel lines, and the output end is connected to the selector. The input end of the selector is connected to the parallel lines and the inverter to select the data to be output, and the output end is used to output the selected data.

12. The PRBS code generator according to claim 11, wherein The parallel sub-unit further includes an error injector. The input end of the error injector is used to connect to the output end of the selector and the error injection signal end to inject errors into the data based on the control of the error injection signal end.

13. A PRBS code detector, characterized in that, Comprising: A second data shift unit, including multiple shift registers, wherein the shift registers are used to receive and store the data to be detected of a preset number of data bits. A second pre-operation unit for generating a preset number of data to be compared based on the data to be detected in the second data shift unit in the current clock cycle; wherein the second pre-operation unit generates a preset number of updated data in one clock cycle, and the preset number is greater than or equal to 2. An error detection unit for determining whether the data to be detected in the next clock cycle is in error based on the data to be compared after the second data shift unit receives the data to be detected in the next clock cycle, and parallelly outputting the corresponding error information. A second serial-parallel conversion unit for parallelly outputting the data to be output in the preset number of shift registers in the second data shift unit.

14. The PRBS code detector according to claim 13, characterized in that, Further comprising: A second input cache, which is connected to the input end of the shift register, is used to pre-acquire at least a preset number of data to be detected, and parallelly input the data to be detected into the shift registers of the corresponding number of bits, wherein one second input cache is used to cache one data bit.

15. The PRBS code detector according to claim 14, wherein The number of the second input caches is the preset number. When the preset number is less than the number of shift registers in the second data shift unit, the preset number of second input caches are used to be sequentially connected to the shift registers corresponding to the first preset number of data bits based on the arrangement order of the data bits; The shift register is connected to the shift register corresponding to the data bit with a preset difference from its data bit, and the preset difference is the preset number.

16. The PRBS code detector according to claim 14, wherein When the preset number is greater than the number of shift registers in the second data shift unit, the PRBS code detector further includes a second output cache for storing the data of the data bits exceeding the number of shift registers, wherein one second output cache is used to store the data of one data bit; The number of the second input caches is an integer multiple of the number of shift registers in the second data shift unit and the number of the second input caches is greater than or equal to the preset number. At least the preset number of second input caches are sequentially connected to the shift registers and the second output cache based on the arrangement order of the data bits.

17. The PRBS code detector according to claim 13, wherein The second pre-operation unit includes at least the preset number of exclusive-OR gates; wherein, the input ends of the exclusive-OR gates are connected to the shift registers corresponding to the data bits corresponding to them based on the calculation method of the data to be compared corresponding to them.

18. The PRBS code detector according to claim 17, characterized in that, The second pre-operation unit further includes a plurality of pre-operation caches, wherein one pre-operation cache corresponds to one shift register and is used to store the data to be compared corresponding to the shift register in the next clock cycle.

19. The PRBS code detector according to claim 18, wherein, The preset number is less than the number of shift registers in the second data shift unit; The number of the pre-operation caches is the preset number, and the pre-operation caches are used for the data to be compared; or, the number of the pre-operation caches is the number of shift registers in the second data shift unit, and the pre-operation caches are used to store the data to be compared and the data to be detected for shifting in the next clock cycle.

20. The PRBS code detector according to claim 18, wherein The preset number is greater than the number of shift registers in the second data shift unit; The number of the pre-operation caches is a positive integer multiple of the number of shift registers in the second data shift unit, and the number of the pre-operation caches is greater than or equal to the preset number; The pre-operation caches in the second pre-operation unit are divided into multiple layers, wherein the number of data in one layer of pre-operation caches is the same as the number of shift registers in the second data shift unit, and the pre-operation caches of each layer are sorted in sequence and store the pre-operation results of at least the preset number of data to be compared based on the corresponding sorting.

21. The PRBS code detector according to claim 13, wherein The PRBS code generator is further configured with a second output cache for storing the data of the data bits exceeding the number of shift registers, wherein one second output cache is used to store the data of one data bit.

22. The PRBS code detector according to claim 21, wherein The second serial-to-parallel conversion unit includes a plurality of parallel sub-units. If the preset number is less than or equal to the number of shift registers in the second data shift unit, the parallel sub-units are sequentially connected to the shift registers of the last preset number of data bits in the second data shift unit; If the preset quantity is greater than the number of shift registers in the first data shift unit, the parallel sub-unit is sequentially connected to each shift register in the second data shift unit and the second output buffer.

23. The PRBS code detector according to claim 13, wherein The error detection unit includes: Data comparison logic for comparing the data to be compared and the data to be detected to determine whether the data to be detected is in error, and the number of the data comparison logics is greater than or equal to the preset quantity; Output logic for parallelly outputting the error information obtained by comparison.

24. The PRBS code detector according to claim 13, wherein An error correction unit is further included, and the error correction unit includes error location logic and error correction logic; Among them, the error location logic is used to pre-acquire the data to be detected for two clock cycles, calculate the data to be compared based on the data to be detected in the previous clock cycle, and compare the data to be detected in the subsequent clock cycle based on the data to be compared to determine the data to be detected in error; The error correction logic is used to correct the in-error data bits.

25. A die, characterized in that, Includes the PRBS code generator according to any one of claims 1-12, and / or includes the PRBS code detector according to any one of claims 13-24.

26. An electronic device, characterized in that, Includes the die according to claim 25, wherein the PRBS code generator and the PRBS code detector are provided in at least one die, or one die is provided with the PRBS code generator and the other die is provided with the PRBS code detector.

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