Fault detection system, method, storage medium, electronic device and program product

Abstract

The present application discloses a fault detection system, method, storage medium, electronic device, and program product, relating to the field of computer technology. The system includes: a system disk, a processor, and a basic input / output system chip, wherein the processor is connected to the system disk and the basic input / output system chip, respectively. In response to an exception occurring in the processor during a system management interrupt triggering process, the processor calls an exception location program in the system disk. The processor sequentially performs fault detection on an enable register and a count register in the processor based on the exception location program to obtain a hardware detection result of the processor. If the processor determines that the hardware detection result does not contain an exception, the processor performs fault detection on the software information of the system management interrupt in the basic input / output system chip to obtain a software detection result. The processor generates fault location information of the system management interrupt based on the hardware detection result and the software detection result. The present application determines the abnormal location information.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a fault detection system, method, storage medium, electronic device, and program product. Background Art

[0002] A System Management Interrupt (SMI) is the only way for the processor to enter System Management Mode (SMM). The SMI is triggered by the SMI pin on the server processor or by a SMI signal received via the Advanced Programmable Interrupt Controller Bus (APIC Bus), causing the CPU to enter SMM. The SMI is a non-maskable external interrupt.

[0003] Currently, in the process of triggering a system management interrupt, related technologies may result in software functions failing to execute successfully. However, since the system management interrupt triggering and the system management interrupt installation are involved, it is impossible to accurately detect the fault location of the system management interrupt. Summary of the Invention

[0004] The present disclosure provides a fault detection system, method, storage medium, electronic device, and program product. Its primary purpose is to address the problem in related technologies where, during the triggering of a system management interrupt, software functions may fail to execute successfully. However, due to the involvement of both the triggering and installation of the system management interrupt, the fault location of the system management interrupt cannot be accurately detected.

[0005] In a first aspect, the present application provides a fault detection system, comprising: a system disk, a processor, and a basic input / output system chip, wherein the processor is connected to the system disk and the basic input / output system chip respectively;

[0006] In response to an exception occurring in the processor during the process of triggering the system management interrupt, the processor calls an exception locating program in the system disk, the exception locating program being embedded in the system management interrupt program;

[0007] The processor performs fault detection on the enable register and the count register in the processor in sequence based on the exception location program to obtain a hardware detection result of the processor;

[0008] When the processor determines that there is no abnormality in the hardware detection result, it performs fault detection on the software information of the system management interrupt in the basic input and output system chip to obtain a software detection result;

[0009] The processor generates fault location information of the system management interrupt based on the hardware detection result and the software detection result.

[0010] In a second aspect, the present application provides a fault detection method, comprising:

[0011] In response to an exception occurring in the processor during the process of triggering the system management interrupt, calling an exception locating program, the exception locating program being embedded in the system management interrupt program;

[0012] Based on the exception location program, fault detection is performed on the enable register and the count register in the processor in sequence to obtain the hardware detection result of the processor;

[0013] When it is determined that the hardware detection result does not have an abnormality, performing fault detection on software information of the system management interrupt in the basic input and output system chip to obtain a software detection result;

[0014] Generate fault location information of the system management interrupt based on the hardware detection results and the software detection results.

[0015] In a third aspect, the present application provides a fault detection device, comprising:

[0016] a calling module configured to call an exception locating program in response to an exception occurring in the process of triggering a system management interrupt by the processor, the exception locating program being embedded in a system management interrupt program;

[0017] The detection module is configured to perform fault detection on the enable register and the count register in the processor in sequence based on the abnormality location program to obtain a hardware detection result of the processor;

[0018] The detection module is further configured to, when it is determined that the hardware detection result does not have an abnormality, perform fault detection on the software information of the system management interrupt in the basic input and output system chip to obtain a software detection result;

[0019] The generating module is configured to generate fault location information of the system management interrupt according to the hardware detection result and the software detection result.

[0020] In a fourth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, which implements the method of the first aspect when the computer program is executed by a processor.

[0021] In a fifth aspect, the present application provides an electronic device comprising a storage medium, a processor, and a computer program stored on the storage medium and executable on the processor, wherein the processor implements the method of the first aspect when executing the computer program.

[0022] In a sixth aspect, the present application provides a computer program product having a computer program stored thereon, which implements the method of the first aspect when the computer program is executed by a processor.

[0023] The present disclosure provides a fault detection system, method, storage medium, electronic device, and program product, wherein the system includes: a system disk, a processor, and a basic input / output system chip, wherein the processor is connected to the system disk and the basic input / output system chip, respectively; in response to an exception occurring in the processor during the process of triggering a system management interrupt, the processor calls an exception location program in the system disk, wherein the exception location program is embedded in the system management interrupt program; the processor sequentially performs fault detection on an enable register and a count register in the processor based on the exception location program to obtain a hardware detection result of the processor; when the processor determines that there is no exception in the hardware detection result, the processor performs fault detection on software information of the system management interrupt in the basic input / output system chip to obtain a software detection result; and the processor generates fault location information of the system management interrupt based on the hardware detection result and the software detection result. Compared with the related art, the present application can call the exception location program pre-embedded in the system management interrupt program when the system management interrupt is abnormal. The exception location program can detect the enable register and count register in the processor to determine whether there is an abnormality in the hardware part of the processor, which in turn causes the system management interrupt abnormality; the software information of the system management interrupt can also be detected to analyze whether there is an abnormality in the program code of the system management interrupt, which in turn causes the system management interrupt abnormality. According to the results of the hardware detection and the software detection results, the location information causing the system management interrupt abnormality is determined, that is, the enable register, count register or software program information. In addition, the manpower and time investment required by R&D personnel to determine the fault location after the system management interrupt is abnormal can be reduced.

[0024] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present application, nor is it intended to limit the scope of the present application. Other features of the present application will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0026] Figure 1 A schematic structural diagram of a fault detection system provided in an embodiment of the present application is shown;

[0027] Figure 2A schematic diagram of a process flow of a fault detection method provided in an embodiment of the present application is shown;

[0028] Figure 3 A schematic diagram showing a flow chart of another fault detection method provided in an embodiment of the present application is shown;

[0029] Figure 4 A schematic diagram showing an example provided by an embodiment of the present application is shown;

[0030] Figure 1 middle:

[0031] 1-System disk;

[0032] 2-processor;

[0033] 3-Basic input and output system chip. DETAILED DESCRIPTION

[0034] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0035] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0036] The Basic Input / Output System (BIOS), the most direct and lowest-level hardware configuration and control manager on a server motherboard, provides a wide range of simple, user-friendly features. The BIOS bridges the gap between hardware devices and software programs. During the boot process, the BIOS first performs a self-test and initialization of the hardware devices. This self-test includes self-tests of the central processing unit (CPU), memory, motherboard, serial and parallel ports, and hard disk devices, and also loads drivers for peripheral component interconnect express (PCIe) devices and input / output (I / O) devices. After the hardware device test is complete, the BIOS loads the startup items and boots the operating system, allowing the user to complete desired operations.

[0037] SMI is the only way for the processor to enter System Management Mode (SMM). SMI is an SMI signal that can be received through the SMI# pin on the server processor or through the Advanced Programmable Interrupt Controller Bus (APIC Bus). SMI is a non-maskable external interrupt. After an SMI is issued, the CPU enters the SMM state. SMM is an Intel CPU execution mode in the x86 architecture that can only be entered through an SMI. SMM is a special-purpose operating mode that provides functions for power management, system hardware control, or code execution by the Original Equipment Manufacturer Handler (OEM handler). SMM can provide an independent and easily isolated processor environment that is transparent to the operating system or other software. When an SMI is generated, the processor will wait for all instructions to be executed and all storage operations to be completed, and then it will switch to a special operating environment defined by a new address space. The SMI handler will be executed in this special environment. The key code and data of the SMI execution program are located in a physical memory area of the space, the System Management RAM (SMRAM). The processor will also save the current state to the SMRAM and then start executing the SMI handler.

[0038] Therefore, after the machine boots into the operating system, it can trigger SMI to handle system events, implement hardware control, implement special functions or virtual hardware functions, or circumvent hardware errors (bugs). Server systems also often use SMI to implement special functions. After an SMI function completes, the CPU resumes the program that was executing before the SMI trigger.

[0039] SMIs are categorized by triggering method as software-triggered system management interrupts (SMIs) and hardware-triggered system management interrupts (Hardware SMIs). Software SMIs trigger the corresponding function by writing a function number to the input / output port (IO Port) 0xB2. As the name implies, Software SMIs implement SMI functionality through the combination of software code, which is installed and executed in the BIOS. The overall implementation of SoftWare SMIs involves setting the function to be executed after an SMI is triggered in the BIOS. This function is installed in the BIOS during the server boot-up and BIOS execution process, but is not executed at this time. It is only executed when the corresponding SMI is triggered. Multiple Software SMI functions can be installed in the BIOS code, distinguished by a defined number. These Software SMI functions are linked to a Software System Management Interrupt Handler List through functions. When a Software SMI is triggered under the OS, the corresponding function number written in IO port 0xB2 by the SoftWare SMI triggered under the OS will be used to enter the SW SMI main entry function on the BIOS side. In the entry function, the function with the corresponding function number in the SofteWareSMI handler list will be found according to certain rules, and then this function will be executed to implement the user-defined function.

[0040] Implementing a user-specific function through Software SMI is mainly divided into the following processes: 1. First, install a Software SMI function with a specific function number on the BIOS side; 2. Under the OS, write the corresponding function number to IO port 0xB2 by executing a program or tool; so the implementation of the entire Software SMI function is divided into two parts: BIOS-side function installation and SMI triggering under the OS. In addition, due to the characteristics of the CPU's SMM state, all interrupts and SMIs are blocked in the SMM state, and the SMI handler cannot be reentered. The next SMI program will only be executed after the current SMI is executed. If other SMIs come during the execution of the current SMI, only one SMI will be latched. After the current SMI is executed, the latched SMI will be executed, and the other SMIs will be ignored.

[0041] However, during the normal SMI function triggering process, there may be factors that cause the software function to fail to execute successfully. However, since it involves two parts: SMI triggering and SMI installation, and these two parts are on different carriers, the debugging process of R&D personnel is hindered. Usually, BIOS R&D and OS R&D need to work together to locate where the problem lies, and then the problem is solved by the party with the problem. Therefore, locating the problem in the early stage will consume a lot of manpower and time, resulting in a serious waste of resources.

[0042] In order to improve the related technology, in the process of triggering the system management interrupt, there may be a situation where the software function cannot be successfully executed. However, due to the two parts of triggering the system management interrupt and installing the system management interrupt, it is impossible to accurately detect the fault location of the system management interrupt. This embodiment provides a fault detection system, such as Figure 1 As shown, the system includes: a system disk 1, a processor 2 and a basic input and output system chip 3, and the processor 2 is connected to the system disk 1 and the basic input and output system chip 3 respectively; in response to an exception occurring in the process of the processor 2 triggering the system management interrupt, the processor 2 calls the exception location program in the system disk 1, and the exception location program is embedded in the system management interrupt program; the processor 2 sequentially performs fault detection on the enable register and the count register in the processor 2 based on the exception location program to obtain the hardware detection result of the processor 2; when the processor 2 determines that there is no exception in the hardware detection result, the processor 2 performs fault detection on the software information of the system management interrupt in the basic input and output system chip 3 to obtain the software detection result; the processor 2 generates the fault location information of the system management interrupt based on the hardware detection result and the software detection result.

[0043] In this embodiment of the present application, a system disk refers to the storage device where the operating system and its associated files are installed. It not only hosts the core components of the operating system, such as the kernel, drivers, and services, but may also store applications, user data, and various configuration files. For example, in this embodiment of the present application, system disk 1 stores an anomaly location program, which can be used to determine the location of a fault when processor 2 triggers a system management interrupt.

[0044] Optionally, this embodiment provides a fault detection method, such as Figure 2 As shown, the processor applied to the above fault detection system includes the following steps:

[0045] Step 101: In response to an exception occurring in a processor during a process of triggering a system management interrupt, an exception location program is called.

[0046] The exception locating program is embedded in the system management interrupt program.

[0047] In the embodiments of the present application, a processor-triggered System Management Interrupt (SMI) is a special hardware interrupt mechanism, typically triggered by the motherboard chipset or Basic Input / Output System (BIOS), used to perform low-level system management tasks. An SMI has a higher priority than all other interrupts (including non-maskable interrupts (NMIs) and normal interrupts) and operates in System Management Mode (SMM), independent of the operating system.

[0048] In some examples, methods for triggering a system management interrupt may include, but are not limited to: 1. Chipset triggering: The motherboard chipset notifies the processor to trigger an SMI via a specific signal (e.g., writing to I / O port 0xB2). 2. Timer triggering: A hardware timer can periodically trigger an SMI to periodically check system status. 3. External event triggering: Events such as power button presses and thermal sensor alarms. 4. BIOS / firmware: The BIOS or firmware can trigger an SMI via specific instructions or operations. 5. Operating system: Low-level drivers or tools trigger an SMI by writing to a specific I / O port (e.g., 0xB2).

[0049] In this embodiment, an exception occurring during the triggering of a system management interrupt can cause system instability, crashes, or other unexpected behavior. Specifically, the causes of the exception may include, but are not limited to, the following: Hardware level: 1. Motherboard or chipset failure: A failure in the motherboard chipset or related hardware may prevent the SMI from being properly triggered or handled. 2. Power supply issues: An unstable power supply may interfere with the execution of the SMI. 3. Overheating or voltage anomalies: High temperatures or voltage fluctuations may trigger hardware errors. Firmware / BIOS level: 1. BIOS configuration errors: BIOS settings (such as power management policies) may cause SMI exceptions. 2. BIOS firmware errors: Errors in the BIOS or firmware may affect the execution of the SMI handler. 3. Incompatible firmware versions: Using a BIOS version that does not match the hardware. Software level: 1. Incorrect function number: Writing an invalid function number to an I / O port (such as 0xB2) may prevent the chipset from properly handling the function. 2. Driver conflicts: An underlying driver may interfere with the triggering or execution of the SMI. 3. Operating system issues: Modules in the operating system may conflict with the SMI handler. System Management RAM (SMRAM) related issues: 1. SMRAM memory corruption: If the data in SMRAM is accidentally modified or corrupted, the SMI handler cannot run properly. 2. SMRAM address conflict: If other software or hardware occupies the SMRAM address space, the SMI handler fails.

[0050] It should be noted that the exception location program implemented in the present application is embedded in the system management interrupt program. Specifically, a program tool running under an operating system (OS), namely, the exception location program in the embodiment of the present application, can be set up, and this program tool can be embedded in the program process triggered by the system management interrupt (SMI). When the software system management interrupt (SW SMI) cannot be executed normally, this program tool, namely, the exception location program in the embodiment of the present application, is called.

[0051] Step 102: Based on the abnormality location program, fault detection is performed on the enable register and the count register in the processor in sequence to obtain a hardware detection result of the processor.

[0052] In an embodiment of the present application, the enable register may be a Software System Management Interrupt Enable Register (SMI_EN) in the processor, which is used to control and enable a system management interrupt (SMI). An SMI is a special hardware interrupt that allows the operating system or firmware to perform low-level system management tasks, such as power management and thermal monitoring. An SMI has a higher priority than all other interrupt types, including non-maskable interrupts (NMIs), and runs in a separate SMM.

[0053] Exemplarily, the functions of the SMI_EN register, i.e., the enable register in the embodiment of the present application, may include but are not limited to: 1. Enable / disable the SMI enable bit; when a specific enable bit is set, a specific type of SMI may be allowed to occur. Disable bit: Clearing the corresponding enable bit can prohibit some types of SMI, thereby avoiding unnecessary system management operations. 2. Configure SMI trigger conditions; SMIs from different sources: You can control which hardware events or software commands will trigger SMI by configuring the SMI_EN register. For example, an alarm for overtemperature, a low battery status, or other hardware monitoring signals. Software trigger: The software can manually trigger SMI by writing a specific value to an I / O port or a memory-mapped register.

[0054] For this embodiment, the use of the SMI_EN register, i.e., the enable register in the embodiment of the present application, may include but is not limited to: 1. Accessing the SMI_EN register; permission requirements: Modifying the SMI_EN register usually requires higher permissions because it involves the underlying operations of the system. This can usually only be done by the BIOS or the Unified Extensible Firmware Interface (UEFI) or an operating system module with corresponding permissions. Location: The specific location of the SMI_EN register depends on the processor architecture and motherboard design, and is located in the I / O space or the memory-mapped address space. 2. Reading and modifying; reading the current status: In order to understand which types of SMI are currently enabled, it is necessary to first read the contents of the SMI_EN register. Modifying the enable status: Modify specific bits in the register as needed. For example, to enable an SMI related to a certain function, set the corresponding bit position to 1; to disable it, set it to 0.

[0055] It should be noted that by detecting the enable register, it can be determined whether the system management interrupt (SMI) is temporarily disabled due to the loading of other software under the operating system (OS).

[0056] For example, within an operating system (OS), some software does cause the System Management Interrupt (SMI) to be temporarily disabled. The following are some reasons and scenarios: 1. OS kernel control of the SMI; Reason: OS kernel modules temporarily disable the SMI to avoid interfering with critical tasks or to improve performance. Scenario: Tasks with high real-time requirements: In a real-time operating system (RTOS) or tasks requiring low latency, triggering the SMI introduces unpredictable delays. Therefore, the OS temporarily disables the SMI. Performance optimization: Frequent triggering of the SMI impacts CPU performance, so the SMI is disabled. 2. Driver or firmware operations; Reason: The driver or underlying firmware modifies the SMI control register (such as SMI_EN), temporarily disabling the SMI. Scenario: Device initialization: When initializing hardware devices, the driver disables the SMI to prevent hardware conflicts. Debug mode: When debugging hardware or firmware, the SMI is disabled to better capture system status. 3. Security-related software; Reason: Security software disables the SMI to prevent malicious code from exploiting the SMI. Scenario: Preventing rootkit attacks: The high-privilege nature of the SMI makes it a potential security threat. Security software disables SMI to prevent malicious code from running in SMM. Virtualized environments: In a virtualized environment, the host machine disables the client's SMI to ensure isolation and security. 4. BIOS / UEFI settings; Reason: BIOS / UEFI settings affect the behavior of SMI, and these settings are dynamically adjusted by the operating system or software. Scenario: Power management policy: Energy-saving policies disable SMI to reduce unnecessary interrupts. Advanced configuration: Advanced users or administrators adjust BIOS / UEFI settings through software tools, thereby affecting the enabled state of SMI.

[0057] In this embodiment, the counter register may be a register (SMI_COUNT) in the processor that counts the number of system management interrupt triggers. Specifically, the SMI_COUNT register, i.e., the counter register in this embodiment, is a hardware register specifically used to record the number of SMI triggers. Whenever an SMI is triggered, the value of this register automatically increments. By reading the value of this register, the frequency and number of SMI triggers in the system can be determined.

[0058] In some examples, the main uses of the count register may include, but are not limited to: 1. Performance monitoring: Frequently triggered SMIs will have a negative impact on system performance (such as increased latency). By monitoring SMI_COUNT, you can analyze whether the triggering frequency of SMI is too high. 2. Troubleshooting: If the system has an abnormality (such as high latency, no response, etc.), you can check SMI_COUNT to determine whether it is related to the frequent triggering of SMI. 3. Debugging and optimization: During the development or debugging phase, engineers can use SMI_COUNT to determine which operations or events caused the triggering of SMI, thereby optimizing the system design. 4. Security analysis: The high-privilege nature of SMI makes it a target of attack. By monitoring SMI_COUNT, potential security issues can be discovered.

[0059] Exemplarily, the working principle of SMI_COUNT, i.e., the counting register in the embodiment of the present application, may include but is not limited to: 1. Automatic increment mechanism; each time SMI is triggered, the processor will automatically add 1 to the value of the SMI_COUNT register. This register is usually a read-only register, and the user cannot directly modify its value. 2. Access method; register location: SMI_COUNT is usually located in a specific I / O address space or memory mapping area, and the specific location depends on the processor architecture and motherboard design. Reading method: The value of SMI_COUNT can be read through assembly language or the underlying driver. 3. Overflow handling: If the bit width of the SMI_COUNT register is limited (for example, 32 bits or 64 bits), an overflow will occur when the count value reaches the maximum value. It will be cleared to zero and continue counting when it overflows, or an additional flag bit will be provided to indicate the overflow status.

[0060] Exemplary application scenarios of SMI_COUNT may include, but are not limited to: 1. Performance tuning; if the value of SMI_COUNT grows too quickly, it indicates that hardware events (such as power management and thermal monitoring) frequently trigger SMI. At this time, you can adjust the BIOS settings or optimize the hardware configuration. 2. Fault diagnosis; when the system has performance problems or abnormal behavior, you can determine whether there are too many SMI triggers by comparing the SMI_COUNT values in different time periods. 3. Security auditing; if the growth rate of SMI_COUNT is abnormal, it indicates that there is malware attempting to exploit SMI to attack. Combined with other security tools, potential threats can be further analyzed. 4. BIOS / firmware development; when developing or debugging BIOS / firmware, SMI_COUNT is an important debugging tool that can help developers verify the behavior of the SMI handler.

[0061] It should be noted that by detecting the enable counter, it can be determined whether other system management interrupt functions (SMI functions) are occupying the system management interrupt (SMI) channel, causing the software system management interrupt function (SWSMI function) to fail to execute successfully.

[0062] Step 103: When it is determined that there is no abnormality in the hardware detection result, a fault detection is performed on the software information of the system management interrupt in the basic input and output system chip to obtain a software detection result.

[0063] In an embodiment of the present application, if fault detection is performed on the enable register and count register in the processor to determine that there is no abnormality, it is necessary to perform fault detection on the software information of the system management interrupt, specifically to detect whether there is an error in the program code of the system management interrupt.

[0064] It should be noted that by performing fault detection on software information, it can be determined whether the failure of the software system management interrupt function (SW SMI function) to execute normally has reached the basic input and output system (BIOS) end, and whether it is caused by the system management interrupt function (SMI function) under the basic input and output system (BIOS).

[0065] For example, if the System Management Interrupt (SMI) function in the Basic Input / Output System (BIOS) causes a System Management Interrupt (SMI) exception, this can affect normal system operation and lead to system crashes, performance degradation, or other unexpected behavior. Specific causes may include, but are not limited to: 1. BIOS firmware issues; Incompatible BIOS versions: Using a BIOS version that doesn't match the hardware can prevent the SMI function from executing correctly. 2. Firmware errors: Errors in the BIOS or related firmware affect the triggering or processing of the SMI. 3. Hardware failures: Motherboard or chipset issues: Hardware failures in the motherboard or chipset can interfere with the normal operation of the SMI. 4. Unstable power supply: An unstable power supply can cause hardware errors, triggering SMI exceptions. 5. Overheating or voltage fluctuations: High temperatures or voltage fluctuations can also cause hardware errors, leading to SMI processing exceptions. 6. Configuration errors: Incorrect BIOS settings (such as power management policies) can cause SMI exceptions. 7. Conflicting device settings: Device settings conflict with the SMI function, causing exceptions. 8. Improper external event triggering: Frequent SMI triggering: Frequent SMI triggering by hardware or software can exceed system processing capabilities, leading to exceptions. External hardware signal problem: External events such as power button pressing and thermal sensor alarm trigger SMI exceptions.

[0066] Step 104: Generate fault location information of the system management interrupt based on the hardware detection result and the software detection result.

[0067] It should be noted that the embodiments of the present application can generate fault location information of the system management interrupt based on the hardware detection results and / or software detection results; for example, if an abnormality is detected in the enable register during the hardware detection process, the fault location information of the system management interrupt can be generated based on the detection result of the enable register; if an abnormality is detected in the count register, the fault location information of the system management interrupt can be generated based on the detection result of the count register; if an abnormality is detected in the software information during the software detection process, the fault location information of the system management interrupt can be generated based on the software detection result.

[0068] Compared with related technologies, this embodiment can call an exception location program pre-embedded in the system management interrupt program when a system management interrupt is abnormal. The exception location program can detect the enable register and count register in the processor to determine whether there is an abnormality in the hardware part of the processor, which in turn causes the system management interrupt abnormality; the software information of the system management interrupt can also be detected to analyze whether there is an abnormality in the program code of the system management interrupt, which in turn causes the system management interrupt abnormality. According to the results of the hardware detection and the software detection results, the location information that causes the system management interrupt abnormality is determined, that is, the enable register, count register or software program information. In addition, the manpower and time investment required by R&D personnel to determine the fault location after the system management interrupt is abnormal can be reduced.

[0069] Furthermore, as a refinement and extension of the above embodiment, the embodiment of the present application provides a fault detection method, such as Figure 3 As shown, the method includes:

[0070] Step 201: In response to an exception occurring in a processor during a process of triggering a system management interrupt, an exception location program is called.

[0071] The exception locating program is embedded in the system management interrupt program.

[0072] In an embodiment of the present application, an exception locating program can be embedded in the system management interrupt program by setting up a program tool running under an operating system (OS), namely, the exception locating program in the embodiment of the present application. This program tool is embedded in the program process triggered by the system management interrupt (SMI), and when the software system management interrupt (SW SMI) cannot be executed normally, this program tool, namely, the exception locating program in the embodiment of the present application, is called.

[0073] Step 202: Perform fault detection on the enable register based on the abnormality location program to obtain a first detection result.

[0074] Optionally, step 202 may specifically include: reading an enable register in the exception location program to determine the byte information corresponding to the enable register; judging whether the loading status of the software in the processor has an impact on the system management interrupt based on the byte information, and determining a first detection result based on the judgment result.

[0075] In an embodiment of the present application, the enable register byte composition may include: A typical enable register is usually an 8-bit, 16-bit, or 32-bit register. Each bit represents the enable status of a specific function or module, where 1 represents enable (Enable) and 0 represents disable (Disable). The functions of the byte information may include: Function control: Each bit controls a specific function or module. Configuration flexibility: By setting different bit combinations, multiple functions can be flexibly enabled or disabled.

[0076] Optionally, when executing "reading the enable register in the exception locating program and determining the byte information corresponding to the enable register", it may include but is not limited to: reading the enable register in the exception locating program, determining the target byte corresponding to the enable register, and detecting whether the target byte is set; if it is determined that the target byte is set, generating first byte information indicating that there is no setting exception for the target byte; if it is determined that the target byte is not set, generating second byte information indicating that there is a setting exception for the target byte.

[0077] In some examples, the current enable register value is read through I / O operations or memory mapping to determine which functions are enabled or disabled. Based on the read enable register value, the state of each bit is analyzed to determine which types of SMIs are enabled or disabled. For example, if byte (Bit) 2 (Software SMI Enable) is 1, it indicates that SMI is allowed to be triggered by software. If Bit 2 is 0, it indicates that SMI is prohibited from being triggered by software.

[0078] In an embodiment of the present application, if the target bytes are byte (Bit) 0 and byte (Bit) 5, the software system management interrupt control and enable register (SMI_EN) in the processor can be read to parse byte (Bit) 0 and byte (Bit) 5, and check whether byte (Bit) 0 and byte (Bit) 5 are set. If byte (Bit) 0 and byte (Bit) 5 are set, it is necessary to generate first byte information indicating that there is no set exception in the target byte; on the contrary, if byte (Bit) 0 and byte (Bit) 5 are not set, then a second byte information indicating that there is a set exception in the target byte is generated.

[0079] It should be noted that in the software system management interrupt control and enable register (SMI_EN) in the processor, Bit 0 is a reserved bit and is usually not used. Bit 5 is the hardware event SMI enable, which controls whether hardware events are allowed to trigger SMI.

[0080] In this embodiment, Bit 0: Function: Reserved bit, typically unused. Default value: Typically 0, indicating that this bit does not enable any function. Bit 5: Function: Controls whether hardware events are allowed to trigger an SMI. If Bit 5 = 1, hardware events are allowed to trigger an SMI. If Bit 5 = 0, hardware events are prohibited from triggering an SMI. Purpose: Used to manage SMIs triggered by hardware signals (such as power button presses and overtemperature alarms).

[0081] For example, a bitwise AND operation (&) is used to check whether a specific bit is 1. Assuming that the read SMI_EN register value is 0x21 (binary 00100001), then: Bit 0 is set (value is 1), indicating that the reserved bit is set. Bit 5 is set (value is 1), indicating that the hardware event SMI is enabled.

[0082] Optionally, when executing "determining whether the loading status of the software in the processor has an impact on the system management interrupt based on the byte information, and determining the first detection result based on the judgment result", it may include but is not limited to: determining that the loading status has an impact on the system management interrupt based on the second byte information, and then determining the first detection result as an abnormality in the enable register.

[0083] In an embodiment of the present application, if the second byte information is generated, that is, the target byte is not set, it can be determined that the loading situation has an impact on the system management interrupt, then it can be determined that there is an abnormality in the enable register, and abnormal location information can be generated based on the enable register.

[0084] Exemplarily, if the target bytes are byte (Bit) 0 and byte (Bit) 5, and the second byte information is generated, it can be determined that the loading of software under the operating system (OS) has caused the system management interrupt (SMI) to be temporarily disabled.

[0085] Optionally, the method of this embodiment further includes: when the first detection result is determined to be that an abnormality exists in the enable register, setting a target byte in the enable register.

[0086] In the embodiments of the present application, setting a byte bit (bit) to 1 is typically accomplished using a bitwise OR operator. The bitwise OR operator performs a logical OR operation on each bit of the two operands. For example, if any bit is 1, the result bit is 1. If both bits are 0, the result bit is 0.

[0087] In some examples, the steps for setting a byte may include, but are not limited to: 1. Determine the bit to be set: Determine the bit number to be set (counting from 0). Construct a mask in which the bits to be set are 1 and the remaining bits are 0. 2. Perform a bitwise OR operation on the original value and the mask to obtain the new byte value. 3. Write the value back to a register or storage; if the operation is performed on a hardware register, the new value must be written back to the register.

[0088] Step 203: When it is determined that there is no abnormality in the first detection result, a fault detection is performed on the counting register based on the abnormality location program to obtain a second detection result.

[0089] The first detection result and the second detection result constitute the hardware detection result.

[0090] Optionally, step 203 may specifically include: when the first detection result is determined to be that there is no abnormality in the enable register, triggering the system management interrupt again and determining the response status of the counting register; judging whether the system management interrupt channel in the processor is occupied based on the re-triggering status and the response status, and determining the second detection result based on the judgment result.

[0091] In the embodiment of the present application, triggering the system management interrupt again when the first detection result is determined to be that there is no abnormality in the enable register means triggering the system management interrupt again when an abnormality occurs in the system management interrupt.

[0092] In some examples, scenarios for re-triggering SMI may include, but are not limited to: 1. Debugging and diagnosis If there is an error in the SMI handler, more context information can be captured by re-triggering SMI for debugging. For example, in embedded system or BIOS development, register status or memory contents can be checked by re-triggering SMI. 2. Fault recovery: It is necessary to try to restore the system to a normal state by re-triggering SMI. For example, when the SMI exception is caused by a temporary hardware error (such as signal interference), re-triggering SMI helps to restore normal operation. 3. Testing and verification: During the development or testing phase, multiple SMI triggers need to be simulated to verify the stability and robustness of the system.

[0093] In this embodiment, methods for re-triggering the SMI may include, but are not limited to: 1. Software-triggered SMI: Most processors support manually triggering the SMI by writing to a specific I / O port (such as 0xB2 or 0x92). 2. Hardware-triggered SMI: Hardware events (such as power button presses and overtemperature alarms) can automatically trigger the SMI. In a debugging environment, the SMI can be triggered by simulating hardware events. 3. Using a debugging tool: Use a hardware debugging tool (such as the JTAG interface) to force the SMI. Debugging tools allow direct intervention in processor behavior and are suitable for use during development and testing.

[0094] Optionally, when executing "triggering the system management interrupt again and determining the response status of the counting register", it may include but is not limited to: writing the target function number to the target port in the input and output port, triggering the system management interrupt again, and reading the response value of the counting register.

[0095] Optionally, when executing "determining whether the system management interrupt channel in the processor is occupied based on the re-triggering situation and the response situation, and determining the second detection result based on the judgment result", it may include but is not limited to: determining whether the processor has multiple consecutive system management interrupts based on the re-triggering situation and the response value; if it is determined that the processor has multiple consecutive system management interrupts, it is determined that the system management interrupt channel is occupied, and the second detection result is determined as an abnormality in the counting register.

[0096] In the embodiment of the present application, the system management interrupt (SMI) is triggered again by writing the function number (function number) through the I / O port number 0xB2 (IO Port 0xB2) to see whether it can be successfully triggered, and the value of the register (SMI_COUNT) that counts the number of system management interrupt triggers in the processor is read to see whether there are frequent system management interrupts (SMI) generated, so as to rule out whether other system management interrupt functions (SMI functions) are occupying the system management interrupt (SMI) channel, causing the software system management interrupt function (SW SMI function) to fail to execute successfully.

[0097] In some examples, frequent system management interrupts refer to system management interrupts that are triggered frequently within a short period of time. Due to the high priority of SMIs and the fact that they run in system management mode, frequent SMIs can significantly affect system performance, stability, and response time.

[0098] For this embodiment, the reasons for the intensive system management interrupts may include but are not limited to: 1. Hardware failure; power supply problems: unstable power supply or voltage fluctuations frequently trigger SMIs related to power management. Temperature monitoring: If the system has poor heat dissipation, excessively high temperatures will frequently trigger thermal monitoring SMIs. Hardware errors: hardware failures such as bus errors and memory errors also frequently trigger SMIs. 2. BIOS / firmware configuration; unreasonable settings: BIOS settings (such as overly sensitive power management policies) cause SMIs to be triggered frequently. Bugs or design flaws: Bugs in BIOS or firmware cause unnecessary SMI triggering. 3. Software problems; driver conflicts: underlying drivers interfere with the normal processing of SMIs, resulting in frequent triggering. Operating system modules: modules in the operating system (such as power management services) frequently request SMIs. 4. Malware rootkit attacks: malware uses the high-privilege characteristics of SMI to perform covert operations, resulting in frequent triggering.

[0099] In an embodiment of the present application, SMI_COUNT is a register that records the number of SMI triggering times. By reading this register, the triggering frequency of SMI can be understood; specifically, if the system management interrupt can be triggered again and the response value is low, it can be determined that the processor does not have multiple consecutive system management interrupts.

[0100] For example, if the system management interrupt cannot be triggered again or the response value is high, it can be determined that the processor has multiple consecutive system management interrupts.

[0101] Optionally, the method of this embodiment further includes: repeatedly triggering a system management interrupt when the second detection result is determined to be an abnormality in the counting register.

[0102] Optionally, after executing "determining whether the system management interrupt channel in the processor is occupied based on the re-triggering situation and the response situation, and determining a second detection result based on the judgment result", the embodiment method also includes: if it is determined that the processor does not have multiple consecutive system management interrupts, then determining that the system management interrupt channel is not occupied, and determining the second detection result as there is no abnormality in the counting register.

[0103] In some cases, multiple SMI functions share the same system management interrupt (SMI) channel. If an SMI function occupies the channel or resources, other SMI functions (such as a software system management interrupt function (SW SMI function)) may fail to execute successfully.

[0104] In the embodiment of the present application, the reasons for SMI channel conflicts may include but are not limited to: 1. Shared SMI handler; SMI is a high-priority interrupt triggered by hardware or requested by software, and all SMIs will enter the same system management mode (SMM). In SMM, there is usually a unified SMI handler to distribute and handle different SMI functions (such as power management, thermal monitoring, debugging, etc.). If an SMI function occupies SMI handler resources for a long time (for example, it does not exit correctly or is in an infinite loop), other SMI functions will not be processed. (2) Resource competition; SMI functions need to exclusively occupy specific hardware resources (such as memory mapping areas, registers, etc.). If these resources are occupied, other SMI functions will fail. For example, SW SMI relies on registers or memory buffers, and these resources are occupied by other SMI functions. 3. Priority issues; SMI functions have higher priorities, causing low-priority SMI functions (such as SW SMI) to be delayed or ignored. For example, hardware-triggered SMIs (such as high temperature alarms) take precedence over software-triggered SMIs. 4. Abnormal state: If an SMI function encounters an exception during execution (such as stack overflow, address error, etc.), the entire SMI handler will crash, which will affect other SMI functions.

[0105] For this embodiment, the method for detecting whether other SMI functions occupy the channel may include but is not limited to: 1. Checking the SMI trigger frequency; using the SMI_COUNT register or other logging mechanisms to count the number and type of SMI triggers. If the SMI trigger frequency is found to be abnormally high, it means that the SMI function frequently occupies the channel. 2. Analyzing log information; embedding a logging function in the SMI handler to record the cause and context information of each SMI trigger. 3. Using debugging tools; using hardware debugging tools (such as JTAG or logic analyzer) to monitor the SMI trigger signal. Check whether there are multiple consecutive SMI trigger events and the source of the trigger. 4. Checking resource occupancy; checking whether SMI-related resources (such as registers and memory buffers) are occupied.

[0106] Step 204 : When it is determined that there is no abnormality in the hardware detection result, a fault detection is performed on the software information of the system management interrupt in the basic input and output system chip to obtain a software detection result.

[0107] Optionally, step 204 may specifically include: when the second detection result is determined to be that there is no abnormality in the counting register, determining software information of a system management interrupt in the basic input / output system; and performing fault detection on the software information to obtain a software detection result.

[0108] Optionally, when executing "determining the software information of the system management interrupt in the basic input and output system", it may include but is not limited to: determining the total entry function, processor list function, script function of the system management interrupt in the basic input and output system, and serial port printing information of the basic input and output system.

[0109] In the embodiments of this application, the SMI entry point function is the first code executed when the processor enters System Management Mode (SMM). It is responsible for initializing the SMI processing environment and dispatching specific SMI function handlers. Before entering the SMI, the SMI entry point function must save all register and stack contents to avoid interfering with normal operation. The SMI entry point function can also call the corresponding function handler based on the SMI trigger source (such as hardware events, software requests, etc.).

[0110] In some examples, in a multi-processor system, a processor list function is used to enumerate all available processors and determine which processors need to participate in SMI processing. The processor list function can use the CPUID instruction to obtain identification information of the processor and can also distinguish different processors by the local APIC ID of the Advanced Programmable Interrupt Controller (APIC).

[0111] In this embodiment, in the BIOS implementation, a script function is used to define and execute specific SMI handling logic. The script function is provided by the ACPI table or other configuration files. The script function needs to parse and execute a series of predefined commands. The script function allows the SMI handling logic to be dynamically adjusted without modifying the firmware code.

[0112] As an optional method, serial port printing is an important debugging tool during BIOS development and debugging. It can output key information during SMI processing to the serial terminal, facilitating problem analysis. Before using serial port printing, the serial port registers must be properly initialized. Serial port printing can output debugging information in real time, making it easier to track down problems during SMI processing.

[0113] Optionally, when executing "performing fault detection on software information to obtain software detection results", it may include but is not limited to: judging whether the system management interrupt in the basic input and output system is abnormal based on the main entry function, processor list function, script function and serial port printing information; and determining the software detection results based on the judgment results.

[0114] Optionally, when executing "determining whether the system management interrupt in the basic input and output system is abnormal based on the main entry function, the processor list function, the script function and the serial port printing information; determining the software detection result based on the judgment result", it may include but is not limited to: adding serial port printing information to the main entry function and the processor list function respectively; calling the serial port collection tool of the LAN serial transmission through the script function to collect the faulty serial port information of the system management interrupt in the basic input and output system; when the faulty serial port information is collected, determining that there is an abnormality in the system management interrupt in the basic input and output system, and saving the faulty serial port information in a predetermined log file.

[0115] In an embodiment of the present application, basic input and output system (BIOS) serial port printing information is added to the basic input and output system (BIOS) side software system management interrupt (SW SMI) total entry function and software system management interrupt handler list (SW SMI Handler List) function, and the LAN serial transmission (Sol) serial port collection tool is called in the script function to print and save the basic input and output system (BIOS) serial port information, which is used to determine whether the software system management interrupt function (SWSMI function) fails to execute normally and whether it reaches the basic input and output system (BIOS) side, and whether it is caused by the system management interrupt function (SMI function) under the basic input and output system (BIOS).

[0116] In some examples, the information read and collected in the embodiments of the present application will be integrated and printed into a log file (.log) document, and the document will eventually be saved in the root directory.

[0117] In some cases, BIOS serial port printing can be used to output debugging information, including: Enabling serial port debugging: Enable serial port redirection or debugging options in the BIOS setup. Reading output: Use a serial terminal program (such as PuTTY or TeraTerm) to connect to the specified serial port and view the output log information. Custom printing: If necessary, add custom print statements (such as SerialPrint("Debug Info")) to suspected problematic code sections to further narrow down the scope of the problem.

[0118] Optionally, when executing "determining a software detection result based on the judgment result", it may include but is not limited to: when it is determined that there is an abnormality in the system management interrupt in the basic input and output system, determining the software detection result as an abnormality in the software information.

[0119] Step 205: Generate fault location information of the system management interrupt based on the hardware detection result and the software detection result.

[0120] For this embodiment, in order to solve the problem that the SW SMI function cannot be executed normally, quickly locate where the problem occurs and provide it directly and quickly to the corresponding engineer for problem solving, the present invention proposes a method that can automatically locate the problem that the SW SMI cannot be executed normally. The method provides a relatively simple program code, which can be embedded in the program that triggers the SW SMI function. It is only called when the SW SMI Function execution fails, and it will not be called when the SW SMI function is executed normally. When the SW SMI function execution fails, it will be directly executed and the parsed file will be directly generated into a document and saved. This method is simple and fast. When an SW SMI function execution error occurs, the problem can be located and analyzed based on the saved document. This method can quickly locate the problem of the cause of the SWSMI Function not being triggered normally, and can reduce the manpower and time investment of R&D personnel.

[0121] It should be noted that the embodiment of the present application is illustrated using the server architecture of the Intel platform, but the method is not limited to servers on the Intel platform, nor is it limited to server systems. The fault monitoring method provided in the embodiment of the present application can still be used to perform fault detection on server systems of other platforms or other computer systems.

[0122] In order to illustrate the specific implementation process of this embodiment, the following specific application examples are given: Figure 4 As shown, but not limited to:

[0123] Set up a program tool running under an operating system (OS), embed this program tool into the program process triggered by a system management interrupt (SMI), and use this program tool when the software system management interrupt (SW SMI) cannot be executed normally. In this program tool, first read the software system management interrupt control and enable register (SMI_EN) in the processor to see if the corresponding byte (bit) of this register is set, so as to rule out whether the system management interrupt (SMI) is temporarily disabled due to the loading of other software under the operating system (OS); again trigger the system management interrupt (SMI) by writing the function number (function number) through the I / O port number 0xB2 (IOPort 0xB2) to see if it can be successfully triggered, and read the value of the register (SMI_COUNT) that counts the number of system management interrupt triggers in the processor to see if there are intensive system management interrupts (SMI) generated, so as to rule out whether other system management interrupt functions (SMI functions) are occupying the system management interrupt (SMI) channel, causing the software system management interrupt function (SW SMI) to be interrupted. function) cannot be successfully executed; add basic input and output system (BIOS) serial port printing information to the basic input and output system (BIOS) side software system management interrupt (SW SMI) general entry function and software system management interrupt handler list (SW SMI Handler List) function; call the LAN serial transmission (Sol) serial port collection tool in the script function to print and save the basic input and output system (BIOS) serial port information to determine whether the software system management interrupt function (SW SMI function) cannot be executed normally when it reaches the basic input and output system (BIOS) side, and whether it is caused by the basic input and output system (BIOS) system management interrupt function (SMI function); the above read and collected information will be integrated and printed into the log file (.log) document and finally saved to the root directory.

[0124] Compared with related technologies, this embodiment can call an exception location program pre-embedded in the system management interrupt program when a system management interrupt is abnormal. The exception location program can detect the enable register and count register in the processor to determine whether there is an abnormality in the hardware part of the processor, which in turn causes the system management interrupt abnormality; the software information of the system management interrupt can also be detected to analyze whether there is an abnormality in the program code of the system management interrupt, which in turn causes the system management interrupt abnormality. According to the results of the hardware detection and the software detection results, the location information that causes the system management interrupt abnormality is determined, that is, the enable register, count register or software program information. In addition, the manpower and time investment required by R&D personnel to determine the fault location after the system management interrupt is abnormal can be reduced.

[0125] An embodiment of the present application further provides a fault detection device, which includes: a calling module 31 , a detection module 32 , and a generation module 33 .

[0126] The calling module 31 is configured to call an exception locating program in response to an exception occurring in the process of triggering the system management interrupt, wherein the exception locating program is embedded in the system management interrupt program;

[0127] The detection module 32 is configured to perform fault detection on the enable register and the count register in the processor in sequence based on the abnormality location program to obtain a hardware detection result of the processor;

[0128] The detection module 32 is further configured to, when it is determined that there is no abnormality in the hardware detection result, perform fault detection on the software information of the system management interrupt in the basic input and output system chip to obtain a software detection result;

[0129] The generating module 33 is configured to generate fault location information of the system management interrupt according to the hardware detection result and the software detection result.

[0130] In some examples of this embodiment, the detection module 32 is specifically configured to perform fault detection on the enable register based on the abnormality location program to obtain a first detection result; when it is determined that there is no abnormality in the first detection result, the fault detection is performed on the counting register based on the abnormality location program to obtain a second detection result. The first detection result and the second detection result constitute the hardware detection result.

[0131] In some examples of this embodiment, the detection module 32 is further configured to read the enable register in the exception location program and determine the byte information corresponding to the enable register; determine whether the loading status of the software in the processor has an impact on the system management interrupt based on the byte information, and determine the first detection result based on the judgment result.

[0132] In some examples of this embodiment, the detection module 32 is further configured to read the enable register in the exception location program, determine the target byte corresponding to the enable register, and detect whether the target byte is set; if it is determined that the target byte is set, a first byte information indicating that there is no setting exception in the target byte is generated; if it is determined that the target byte is not set, a second byte information indicating that there is a setting exception in the target byte is generated.

[0133] In some examples of this embodiment, the detection module 32 is further configured to determine, based on the second byte information, that the loading condition has an impact on the system management interrupt, and then determine the first detection result as an abnormality in the enable register.

[0134] In some examples of this embodiment, the detection module 32 is further configured to set the target byte in the enable register when the first detection result is determined to be an abnormality in the enable register.

[0135] In some examples of this embodiment, the detection module 32 is further configured to determine, based on the first byte information, that the loading condition has no impact on the system management interrupt, and then determine the first detection result as no abnormality in the enable register.

[0136] In some examples of this embodiment, the detection module 32 is further configured to, when the first detection result is determined as no abnormality in the enable register, trigger the system management interrupt again and determine the response status of the counting register; based on the re-triggering status and the response status, determine whether the system management interrupt channel in the processor is occupied, and determine a second detection result based on the judgment result.

[0137] In some examples of this embodiment, the detection module 32 is further configured to write a target function number to a target port in the input / output port, trigger the system management interrupt again, and read a response value of the counter register.

[0138] In some examples of this embodiment, the detection module 32 is further configured to determine whether the processor has multiple consecutive system management interrupts based on the re-triggering situation and the response value; if it is determined that the processor has multiple consecutive system management interrupts, it is determined that the system management interrupt channel is occupied, and the second detection result is determined as an abnormality in the counting register.

[0139] In some examples of this embodiment, the detection module 32 is further configured to repeatedly trigger a system management interrupt when the second detection result is determined to be an abnormality in the counting register.

[0140] In some examples of this embodiment, the detection module 32 is further configured to determine that the system management interrupt channel is not occupied if it is determined that the processor does not have multiple consecutive system management interrupts, and determine the second detection result as there is no abnormality in the counting register.

[0141] In some examples of this embodiment, the detection module 32 is further configured to determine the software information of the system management interrupt in the basic input and output system when the second detection result is determined as there is no abnormality in the counting register; perform fault detection on the software information to obtain a software detection result.

[0142] In some examples of this embodiment, the detection module 32 is further configured to determine the total entry function, the processor list function, the script function of the system management interrupt in the basic input and output system, and the serial port printing information of the basic input and output system.

[0143] In some examples of this embodiment, the detection module 32 is further configured to determine whether the system management interrupt in the basic input and output system is abnormal based on the main entry function, the processor list function, the script function and the serial port printing information; and determine the software detection result based on the judgment result.

[0144] In some examples of this embodiment, the detection module 32 is further configured to add serial port printing information in the main entry function and the processor list function respectively; call the serial port collection tool of the LAN serial transmission through the script function to collect the faulty serial port information of the system management interrupt in the basic input and output system; when the faulty serial port information is collected, it is determined that there is an abnormality in the system management interrupt in the basic input and output system, and the faulty serial port information is saved in a predetermined log file.

[0145] In some examples of this embodiment, the detection module 32 is further configured to, when it is determined that there is an abnormality in the system management interrupt in the basic input / output system, determine the software detection result as an abnormality in the software information.

[0146] It should be noted that for other corresponding descriptions of the functional units involved in the fault detection device provided in this embodiment, please refer to Figure 2 The corresponding description in will not be repeated here.

[0147] Based on the above Figure 2 The method shown in FIG. 1 is a method for performing the above-mentioned steps. Accordingly, this embodiment further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the computer program can realize the above-mentioned steps. Figure 2 The method shown.

[0148] Based on the above Figure 2 The method shown in FIG. 1 is a method for performing the above-mentioned operations. Accordingly, this embodiment further provides a computer program product having a computer program stored thereon. When the computer program is executed by a processor, the above-mentioned Figure 2 The method shown.

[0149] Based on this understanding, the technical solution of the present application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, USB flash drive, mobile hard disk, etc.), and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute the methods of various implementation scenarios of the present application.

[0150] Based on the above Figure 2The method shown in the figure, and the embodiment of the virtual device, in order to achieve the above purpose, the embodiment of the present application also provides an electronic device, such as a personal computer, a server, the device including a storage medium and a processor; the storage medium is used to store a computer program; the processor is used to execute the computer program to achieve the above Figure 2 The method shown.

[0151] In some embodiments, the physical device may further include a user interface, a network interface, a camera, a radio frequency (RF) circuit, a sensor, an audio circuit, a Wi-Fi module, and the like. The user interface may include a display, an input unit such as a keyboard, and the like. Optional user interfaces may also include a USB interface and a card reader interface. In some embodiments, the network interface may include a standard wired interface or a wireless interface (such as a Wi-Fi interface).

[0152] Those skilled in the art will understand that the above-mentioned physical device structure provided in this embodiment does not constitute a limitation on the physical device, and may include more or fewer components, or combined components, or different component arrangements.

[0153] The storage medium may also include an operating system and a network communication module. The operating system is a program that manages the hardware and software resources of the physical device, supporting the execution of information processing programs and other software and / or programs. The network communication module is used to enable communication between components within the storage medium, as well as with other hardware and software within the physical information processing device.

[0154] Through the description of the above implementation methods, those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general hardware platform, or by hardware. By applying the solution of this embodiment, compared with the related art, this embodiment can call the exception location program pre-embedded in the system management interrupt program in the case of a system management interrupt exception. The exception location program can detect the enable register and count register in the processor to determine whether there is an exception in the hardware part of the processor, thereby causing the system management interrupt exception; the software information of the system management interrupt can also be detected to analyze whether there is an exception in the program code of the system management interrupt, thereby causing the system management interrupt exception. According to the results of the hardware detection and the software detection results, the location information that causes the system management interrupt exception is determined, that is, the enable register, count register or software program information. In addition, it can also reduce the manpower and time investment required by the R&D personnel to determine the fault location after the system management interrupt exception.

[0155] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device that includes the element.

[0156] The above are merely specific embodiments of the present application, which are intended to enable those skilled in the art to understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to these embodiments herein, but rather is intended to conform to the widest scope consistent with the principles and novel features of the present application.

Claims

1. A fault detection system, characterized in that: include: a system disk, a processor and a basic input / output system chip, wherein the processor is connected to the system disk and the basic input / output system chip respectively; In response to an exception occurring in the process of triggering a system management interrupt, the processor calls an exception locating program in the system disk, wherein the exception locating program is embedded in a program of the system management interrupt; The processor sequentially performs fault detection on an enable register and a count register in the processor based on the abnormality locating program to obtain a hardware detection result of the processor; When the processor determines that there is no abnormality in the hardware detection result, the processor performs fault detection on the software information of the system management interrupt in the basic input and output system chip to obtain a software detection result; The processor generates fault location information of the system management interrupt according to the hardware detection result and the software detection result; The processor sequentially performs fault detection on an enable register and a count register in the processor based on the exception locating program to obtain a hardware detection result of the processor, including: reading the enable register in the exception locating program, determining a target byte corresponding to the enable register, and detecting whether the target byte is set; if it is determined that the target byte is set, generating first byte information indicating that there is no set exception for the target byte; if it is determined that the target byte is not set, generating second byte information indicating that there is a set exception for the target byte; determining, based on the second byte information, that the loading status of the software in the processor has an impact on the system management interrupt, and determining the first detection result of the fault detection on the enable register based on the exception locating program as an exception for the enable register; The processor sequentially performs fault detection on an enable register and a count register in the processor based on the exception locating program to obtain a hardware detection result of the processor, further comprising: if the first detection result is determined to be that the enable register does not have an abnormality, triggering the system management interrupt again and determining a response condition of the count register; judging whether the processor has multiple consecutive system management interrupts based on the re-triggering condition and the response value; if it is determined that the processor has multiple consecutive system management interrupts, determining that a system management interrupt channel is occupied, and determining the second detection result as that the count register has an abnormality; When determining that the hardware detection result does not contain any abnormality, the processor performs fault detection on the software information of the system management interrupt in the basic input / output system chip to obtain a software detection result, including: judging whether the system management interrupt in the basic input / output system is abnormal based on the main entry function, processor list function, script function of the system management interrupt in the basic input / output system and the serial port print information of the basic input / output system; and determining the software detection result based on the judgment result.

2. A fault detection method, characterized in that: include: In response to an exception occurring in the processor during a process of triggering a system management interrupt, calling an exception locating program, wherein the exception locating program is embedded in a program of the system management interrupt; Performing fault detection on an enable register and a count register in the processor in sequence based on the abnormality locating program to obtain a hardware detection result of the processor; When it is determined that the hardware detection result does not have an abnormality, performing fault detection on software information of the system management interrupt in the basic input and output system chip to obtain a software detection result; generating fault location information of the system management interrupt according to the hardware detection result and the software detection result; Wherein, based on the exception locating program, fault detection is sequentially performed on the enable register and the count register in the processor to obtain the hardware detection result of the processor, including: reading the enable register in the exception locating program, determining the target byte corresponding to the enable register, and detecting whether the target byte is set; if it is determined that the target byte is set, generating first byte information indicating that there is no set exception for the target byte; if it is determined that the target byte is not set, generating second byte information indicating that there is a set exception for the target byte; determining, based on the second byte information, that the loading status of the software in the processor has an impact on the system management interrupt, and determining the first detection result of the fault detection on the enable register based on the exception locating program as the existence of an exception in the enable register; Performing fault detection on the enable register and the count register in the processor in sequence based on the exception locating program to obtain a hardware detection result of the processor, further comprising: if the first detection result is determined to be that the enable register does not have an abnormality, triggering the system management interrupt again and determining a response condition of the count register; judging whether the processor has multiple consecutive system management interrupts based on the re-triggering condition and the response value; if it is determined that the processor has multiple consecutive system management interrupts, determining that the system management interrupt channel is occupied, and determining the second detection result as that the count register has an abnormality; When it is determined that there is no abnormality in the hardware detection result, fault detection is performed on the software information of the system management interrupt in the basic input and output system chip to obtain a software detection result, including: judging whether the system management interrupt in the basic input and output system is abnormal based on the main entry function, processor list function, script function of the system management interrupt in the basic input and output system and the serial port printing information of the basic input and output system; and determining the software detection result based on the judgment result.

3. The method according to claim 2, characterized in that Performing fault detection on the enable register and the count register in the processor in sequence based on the abnormality locating program to obtain a hardware detection result of the processor includes: Performing fault detection on the enable register based on the abnormality locating program to obtain a first detection result; When it is determined that there is no abnormality in the first detection result, fault detection is performed on the counting register based on the abnormality locating program to obtain a second detection result. The first detection result and the second detection result constitute the hardware detection result.

4. The method according to claim 3, characterized in that The performing fault detection on the enable register based on the abnormality locating program to obtain a first detection result includes: Reading the enable register in the exception locating program to determine byte information corresponding to the enable register; It is determined whether the loading status of the software in the processor has an impact on the system management interrupt according to the byte information, and the first detection result is determined based on the determination result.

5. The method according to claim 4, characterized in that The method further comprises: When the first detection result is determined as an abnormality in the enable register, the target byte in the enable register is set.

6. The method according to claim 5, characterized in that The determining, based on the byte information, whether the loading status of the software in the processor affects the system management interrupt, and determining the first detection result based on the determination result, includes: If it is determined according to the first byte information that the loading condition has no impact on the system management interrupt, the first detection result is determined as no abnormality in the enable register.

7. The method according to claim 6, characterized in that When it is determined that there is no abnormality in the first detection result, performing fault detection on the counter register in the processor based on the abnormality locating program to obtain a second detection result includes: When the first detection result is determined to be that there is no abnormality in the enable register, triggering the system management interrupt again and determining a response status of the count register; Based on the re-triggering situation and the response situation, it is determined whether the system management interrupt channel in the processor is occupied, and the second detection result is determined based on the determination result.

8. The method according to claim 7, characterized in that Triggering the system management interrupt again and determining a response condition of the counter register includes: The target function number is written into the target port in the input / output port, the system management interrupt is triggered again, and the response value of the counting register is read.

9. The method according to claim 8, characterized in that The method further comprises: When the second detection result is determined as an abnormality in the counting register, the system management interrupt is repeatedly triggered.

10. The method according to claim 9, characterized in that After determining whether the processor has multiple consecutive system management interrupts based on the re-triggering condition and the response value, the method further includes: If it is determined that the processor does not have multiple consecutive system management interrupts, it is determined that the system management interrupt channel is not occupied, and the second detection result is determined as the count register does not have an abnormality.

11. The method according to claim 10, characterized in that When it is determined that the hardware detection result does not have an abnormality, performing fault detection on the software information of the system management interrupt in the basic input and output system chip to obtain a software detection result includes: When the second detection result is determined as no abnormality in the counting register, determining software information of the system management interrupt in the basic input and output system; Performing fault detection on the software information to obtain the software detection result.

12. The method according to claim 11, characterized in that The determining whether the system management interrupt in the basic input and output system is abnormal based on the main entry function, the processor list function, the script function and the serial port print information includes: Add the serial port printing information to the main entry function and the processor list function respectively; Calling a serial port collection tool for LAN serial transmission through the script function to collect fault serial port information of the system management interrupt in the basic input and output system; When the faulty serial port information is collected, it is determined that an abnormality exists in the system management interrupt in the basic input / output system, and the faulty serial port information is saved in a predetermined log file.

13. The method according to claim 12, characterized in that Determining the software detection result based on the judgment result includes: When it is determined that the system management interrupt in the basic input / output system is abnormal, the software detection result is determined as the software information being abnormal.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 2 to 13 is implemented.

15. An electronic device comprising a storage medium, a processor, and a computer program stored in the storage medium and executable on the processor, wherein: When the processor executes the computer program, the method according to any one of claims 2 to 13 is implemented.

16. A computer program product having a computer program stored thereon, characterized in that: When the computer program product is executed by a processor, the method according to any one of claims 2 to 13 is implemented.

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