PCIe-CIP protocol interconnection core particle conversion interface circuit supporting big data transmission

Abstract

The invention discloses a PCIe-CIP protocol interconnection core particle conversion interface circuit supporting big data transmission, a write processing controller comprises a transaction processing controller and a sending controller, data transmission between a PCIe clock domain and a network-on-chip clock domain is realized through an asynchronous FIFO, before a previous event is sent, the sending controller keeps read enabling of the asynchronous FIFO to be invalid, and after the previous event is sent, the read enabling of the asynchronous FIFO to be invalid, the read enabling of the asynchronous FIFO to be invalid; the transaction processing controller is pressed back through a fifofull signal so as to control the data receiving of the PCIe host; the read processing controller comprises a receiving controller and a data processing controller, the data flow from the on-chip network clock domain to the PCIe clock domain is processed through the asynchronous FIFO, before the PCIe host completes the acquisition of the last interruption information and the data load, the data processing controller keeps the read enabling of the FIFO to be invalid, and the receiving controller is reversely pressed through a fifofull signal, so that the data flow of the PCIe clock domain is processed. To manage data reception from the network-on-chip. According to the method, the efficiency and the performance of the PCIe host in large-scale data transmission and distributed computing are remarkably improved.

Description

Technical Field

[0001] The present invention relates to the technical field of ultra-large scale digital integrated circuit testing, and particularly relates to a PCIe-CIP protocol interconnected chiplet conversion interface circuit supporting large data transmission. Background Art

[0002] With the improvement of the transistor density of integrated circuits, the complexity and functional requirements of chips are increasing day by day, and Moore's Law is approaching its limit. Chiplet technology effectively reduces costs, improves performance and scalability by splitting large-scale chips into multiple functional chiplets and interconnecting them using advanced packaging technologies such as organic substrates, 2.5D silicon interposers or 3D stacking, thus constructing a high-performance and highly flexible chiplet system, and has become an important development direction in the post-Moore era.

[0003] CIP (Chiplet Interconnect Protocol) is a communication protocol for interconnecting chiplets, which defines the data interaction and communication process at the transaction layer and supports the interconnection and integration packaging of multi-die / chiplet systems with existing protocols and interfaces (such as PCIe, SRIO, DDR, AXI, etc.). The communication transaction types specified by the CIP protocol include: read transaction, write transaction, memory request transaction, memory release transaction, shared transaction, interrupt transaction, and user-defined transaction.

[0004] In PCIe bus communication, the interrupt mechanism is one of the key technologies for achieving efficient communication between an EP (Endpoint) and an RC (Root Complex). PCIe defines multiple interrupt mechanisms such as INTx, MSI, and MSI-X. The traditional INTx interrupt has obvious limitations in multi-core processors and complex system designs due to its support for only a single interrupt pin. In contrast, the MSI / MSI-X interrupt mechanism supports multiple interrupt vectors and flexible interrupt configuration, and can better meet the requirements of multi-core processors and high-performance computing clusters, and is widely used in modern high-performance computing scenarios.

[0005] However, in the large-scale data transmission scenario of the chiplet system, due to the cache capacity limitation of the CIP protocol, in the large data transmission scenario, frequent MSI interrupt requests will lead to a decrease in transmission efficiency and an increase in system latency. In addition, when the PCIe bus accesses the register bank of the interface circuit through memory semantic read and write operations, it needs to meet the data format and transmission requirements of the CIP protocol, which poses higher requirements for the adaptability of the interrupt mechanism and the on-chip network cache. Therefore, how to optimize the interrupt processing mechanism, reduce the interrupt latency, and improve the performance and efficiency of the PCIe master device in the large data transmission scenario while ensuring the reliability of data transmission has become a key problem to be solved urgently. Summary of the Invention

[0006] The object of the present invention is to provide a PCIe-CIP protocol interconnected chiplet conversion interface circuit supporting large data transmission to solve the problems in the background technology.

[0007] To solve the above technical problems, the present invention provides a PCIe-CIP protocol interconnected chiplet conversion interface circuit supporting large data transmission, including: a write processing controller, a read processing controller, and an MSI controller;

[0008] The write processing controller includes a transaction processing controller and a sending controller, and realizes data transmission between the PCIe clock domain and the on-chip network clock domain through an asynchronous FIFO. Before the previous event sending is completed, the sending controller will keep the read enable of the asynchronous FIFO invalid, and backpressure the transaction processing controller through the fifo_full signal to control the data reception of the PCIe host;

[0009] The read processing controller includes a receiving controller and a data processing controller, and also processes the data stream from the on-chip network clock domain to the PCIe clock domain through an asynchronous FIFO. Before the PCIe host completes the acquisition of the previous interrupt information and data payload, the data processing controller will keep the read enable of the FIFO invalid, and backpressure the receiving controller through the fifo_full signal to manage the data reception from the on-chip network.

[0010] In an implementation manner, when the PCIe host sends a request, it includes a control field and a data payload. The control field carries on-chip network routing information, on-chip network event type, read / write times, base address, offset address, and maximum read / write length information, which are processed and encapsulated into storage requests, sharing, release, write, and read transactions specified by the CIP protocol, and support abnormal retransmission.

[0011] In an implementation manner, the PCIe host configures various information in the request packet by operating the register bank; the write processing controller processes the control field information through a write processing state machine: if the event type is a write event, the register bank operation of the current data packet ends after the data payload is sent, otherwise the register bank operation ends after the control field information is sent;

[0012] The sending end controller of the on-chip network caches the information of this request to the retransmission buffer while sending the request to the on-chip network, and receives the response notification of the on-chip network from the read processing controller. According to the CIP protocol, the next transmission can be initiated only after one transaction transmission of the on-chip network is completed. If the transmission is abnormal and the response information is not received after exceeding the specified time, the sending end controller of the on-chip network resends the request from the retransmission buffer, and the retransmission buffer is released after receiving the response. At this time, the write processing controller makes the next request to the on-chip network.

[0013] In one embodiment, the PCIe host obtains interrupt information and read data payload through a memory semantic read operation, and can cache up to 32KB of data payload at most; the PCIe host reads the interrupt information from the reserved interrupt information register bank according to the read address offset, and reads the data payload from the data cache.

[0014] In one embodiment, the read processing controller supports the response information specified by the CIP protocol, including: storage request response, storage access response, read acknowledgment, read response, interrupt notification, write response, and supports timeout no-response processing;

[0015] After receiving the response information returned by the network-on-chip, the receiving end controller of the network-on-chip unpacks and verifies it. After the verification passes, the unpacked data information is returned to the data processing controller through an asynchronous FIFO; if no response is received within the timeout period, or the data verification fails, a timeout retransmission notification tx_retry is sent to the write processing controller;

[0016] The data processing controller is controlled by the read processing state machine of the read processing controller: if the response returns to the conversion interface, the response information is cached in the interrupt information buffer, and a retransmission buffer release notification is sent to the write processing controller; if the response is a read response, the read data payload is cached in the data buffer; if the network-on-chip interface times out without a response, a timeout unacknowledged notification NACK is written to the interrupt information buffer.

[0017] In one embodiment, for the response information returned by the network-on-chip, the conversion interface circuit returns an MSI interrupt to the host after parsing:

[0018] In the single transmission mode, if a response is received, it represents the completion of the transmission event, and an MSI interrupt is returned to the host; if no response is received within the timeout period, it represents the failure of the transmission, and an MSI interrupt is returned to the host;

[0019] In the large data transmission mode, the msi_req enable is controlled by the multi-transmission control signal multi_transfer_ctrl. At the beginning of the transmission, multi_transfer_ctrl is pulled high. During this period, the msi_req enable is invalid. The information in the register bank in the write processing controller is encapsulated and sent according to the CIP protocol format, and its response is received by the read processing controller and cached in the interrupt information buffer. When the data transmission is all completed, multi_transfer_ctrl is pulled low, and an MSI interrupt is returned to the host.

[0020] A PCIe-CIP protocol interposer conversion interface circuit supporting large data transmission provided by the present invention has the following beneficial effects:

[0021] (1) By introducing memory semantic read and write operations, it supports the consistency management of the distributed memory system, ensures the consistency of data access between multi-die chips, and improves the parallel processing ability and data reliability of the system;

[0022] (2) By adding a large data transfer mode control circuit, it supports the host to carry a large amount of data in a single request, and after all data transfers are completed, the conversion interface uniformly returns an interrupt signal to the host, thus avoiding the performance bottleneck caused by frequent interrupts, effectively solving the latency problem of the MSI interrupt mechanism in the large data transfer scenario, and optimizing the overall transfer performance. Brief Description of the Drawings

[0023] Figure 1 is the overall architecture block diagram of a PCIe-CIP protocol interconnected die conversion interface circuit supporting large data transfer of the present invention;

[0024] Figure 2 is the schematic diagram for explaining the data information of the transmission register bank of the present invention;

[0025] Figure 3 is the schematic diagram for explaining the corresponding relationship between the transmission transaction types and the carried information of the present invention;

[0026] Figures 4(a) and 4(b) are the transaction sending flowcharts of the present invention;

[0027] Figure 5 is the schematic diagram for explaining the data information of the interrupt register bank of the present invention;

[0028] Figure 6 is the schematic diagram of the process of a complete storage request event between the PCIe master device and the on-chip network;

[0029] Figure 7 is the schematic diagram of the process of a complete write event between the PCIe master device and the on-chip network;

[0030] Figure 8 is the schematic diagram of the process of a complete read event between the PCIe master device and the on-chip network;

[0031] Figure 9 is the schematic diagram of the process of a complete shared event between the PCIe master device and the on-chip network;

[0032] Figure 10 is the schematic diagram of the process of a complete storage release event between the PCIe master device and the on-chip network. Detailed Embodiments

[0033] The following further elaborates on a PCIe-CIP protocol interconnected chiplet conversion interface circuit that supports large data transmission proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0034] The present invention provides a PCIe-CIP protocol interconnected chiplet conversion interface circuit that supports large data transmission, as Figure 1 shown, which is composed of a write processing controller (WRITE CTRL), an MSI controller (MSI CTRL), and a read processing controller (READ CTRL). The write processing controller includes a transaction processing controller (Transaction Ctrl) and a transmit controller (TransmitCtrl), and realizes data transmission between the PCIe clock domain and the on-chip network clock domain through an asynchronous FIFO. Before the previous event transmission is completed, the transmit controller will keep the read enable of the asynchronous FIFO invalid and backpressure the transaction processing controller through the fifo_full signal to control the data reception of the PCIe host. The read processing controller is composed of a receive controller (Receive Ctrl) and a data processing controller (Parsing Ctrl), and also processes the data stream from the on-chip network clock domain to the PCIe clock domain through an asynchronous FIFO. Before the PCIe host completes the acquisition of the previous interrupt information and data payload, the data processing controller will keep the read enable of the FIFO invalid and backpressure the receive controller through the fifo_full signal to manage the data reception from the on-chip network.

[0035] The PCIe-CIP protocol interconnected chiplet conversion interface circuit processes various transactions in a memory semantics manner, and reserves a set of register banks and data buffers for the sent request packets and the received response packets respectively; the request side is the transmission register bank, and the response side is the interrupt register bank; the control fields are cached in this set of register banks, and the data payloads are cached in the data buffers. When the PCIe host initiates a request packet, the PCIe side operates on the reserved transmission register bank to configure information such as transaction control and data payload, and the PCIe-CIP protocol interconnected chiplet conversion interface circuit generates and sends a CIP request data packet; when receiving a response packet, the PCIe-CIP protocol interconnected chiplet conversion interface circuit parses and saves the data packet, and initiates an interrupt to the PCIe side to remind it of the change in the interrupt register bank. After receiving the interrupt, the PCIe host reads the interrupt register bank and the data buffer to obtain the response information.

[0036] When the PCIe host initiates a request, the host's configuration information includes: the number of read / write operations, the base address, the offset address, the read / write length, etc. According to different transmission transaction types, the request packet sent by the host consists of a control field and a data payload sent to the on-chip network of the chiplet interconnection. The response controller Resp_Ctrl in the write processing controller of the conversion interface returns a response to the host after each reception of the host's request packet is completed, indicating that the interface circuit has received the host's request.

[0037] The write processing controller reserves two types of register banks for different request packet types: the transaction control register bank and the data buffer. For transactions that do not perform data transmission (such as storage application requests, storage release requests, sharing requests, read requests, user-defined transactions, etc.), the transaction control register bank can be configured in sequence to be sent completely; for transactions that perform data transmission (such as write requests, user-defined transactions, etc.), the transaction control register bank and the data buffer need to be configured in sequence before being sent completely.

[0038] The transmission register bank contains information such as Figure 2 as shown. It is stipulated that the multiple transmission enables, event ID, event type, on-chip network ID (source node, destination node), routing node ID (source node, destination node), destination address, storage block size, shared holding node, and transmission packet length are configured in sequence.

[0039] The information extracted from the register bank for data packets of different event types is different. Each time a data packet is sent, the PCIe-CIP protocol interconnection chiplet conversion interface circuit obtains the corresponding information group packet through the packet type saved in the current register bank. The correspondence between the transmission transaction type and the carried information is as Figure 3 shown.

[0040] The sending of transactions is controlled by the write processing state machine, as Figure 4(a) and 4(b) shown. For transmissions without a data payload, configuring the register bank in the specified order can complete one transaction sending. The configuration process is as follows:

[0041] S1: Complete the configuration of flow control and type, including the on-chip network NODID, routing node RID, event type TTP, etc. At this time, the PCIe-CIP protocol interconnection chiplet conversion interface circuit starts to prepare the packet header for sending;

[0042] S2: Complete the configuration of the valid information carried by this event, including the destination address ADDR, etc. After that, the PCIe-CIP protocol interconnection chiplet conversion interface circuit starts to generate and send the CIP data packet;

[0043] S3: After the transmission is completed, if the buffer is full, the PCIe-CIP protocol interconnected chiplet conversion interface circuit will block the operations on the register bank until the buffer is released.

[0044] For the transmission carrying data, after configuring the register bank in the specified order, a sufficient amount of data needs to be sent according to the configured transmission length LEN to complete a transmission. The process is as follows:

[0045] S1: Complete the configuration of event flow control and types, including NODID, routing ID, event type, etc. At this time, the PCIe-CIP protocol interconnected chiplet conversion interface circuit starts to prepare the packet header for transmission;

[0046] S2: Complete the configuration of the valid information carried by the packet, including LEN, ADDR, etc. After that, the PCIe-CIP protocol interconnected chiplet conversion interface circuit generates the control information of the CIP data packet and sends it;

[0047] S3: Send the data payload carried by the packet and convert it into the data packet format. After the transmission scale reaches the "LEN" configured in S2, complete packet encapsulation and stop sending;

[0048] S4: After the transmission is completed, if the buffer is full, the PCIe-CIP protocol interconnected chiplet conversion interface circuit will block the operations on the register bank until the buffer is released.

[0049] The PCIe-CIP protocol interconnected chiplet conversion interface circuit reserves two types of register banks for different types of response packets: the interrupt control register bank and the data buffer. For transactions without data payload (such as memory request response, memory access response, read acknowledgment, interrupt notification, write response, and user-defined transactions, etc.), when data is received from the on-chip network, the data processing controller will sequentially cache it in the interrupt control register bank and notify the write processing controller to release the cache. At the same time, when the update of the interrupt register bank is completed or a response exception occurs, the circuit will raise the msi_req signal to trigger an interrupt; for transactions with data payload (such as read response, user-defined transactions, etc.), the data processing controller will sequentially cache the response information in the interrupt control register bank, and at the same time cache the data payload in the data buffer. When the data reception is completed, the circuit will notify the write processing controller to release the cache and raise the msi_req signal to trigger an interrupt.

[0050] The interrupt control register bank contains information such as Figure 5 shown. Sequentially parse out the access address, response count, notification information, interrupt type, event type, event ID, and transmission data length in order.

[0051] After receiving an interruption, the PCIe host sends a read request to the conversion interface circuit. When the PCIe host initiates a read request, its configuration information includes the number of read / write operations, the base address, the offset length, and the read / write length, etc. According to different transmission transaction types, the base address and offset length sent by the PCIe host will vary.

[0052] The read processing controller in the conversion interface circuit contains a data processing controller. After receiving the read request from the host, it returns the interruption information in the interruption control register bank according to the base address provided by the host, and at the same time returns the data payload in the data cache according to the base address and offset length. Only after the host completes the current read request can the data processing controller process new response data, thus ensuring the sequentiality and correctness of data processing.

[0053] The interruption processing between the conversion interface circuit and the PCIe host is completed through the MSI controller. The MSI controller receives the multi_transfer_ctrl signal from the write processing controller and the msi_req signal from the read processing controller, and manages the triggering and processing of interruptions according to the transaction type and data transmission mode.

[0054] For requests and response transactions without carrying data (such as memory application, memory release, sharing, etc.), only the single - transfer mode is adopted, multi_transfer_ctrl is 0. When receiving the msi_req signal from the read processing controller, the MSI controller sends an MSI interruption to the host and at the same time raises the msi_busy signal. During the period when msi_busy is raised, the interruption controller cannot process new response data to ensure the integrity of the current interruption processing.

[0055] For request or response transactions carrying data (such as read transactions and write transactions), single - transfer or multi - transfer modes are supported according to the data payload length. In the multi - transfer mode, the write - processing controller pulls high the multi_transfer_ctrl at the start of the transfer, and at this time, MSI enabling is invalid. During this period, when the read - processing controller receives a response packet from the on - chip network, it still sends msi_req to the interrupt controller, but the interrupt controller does not return an MSI interrupt to the host. After all the data payloads are sent, the write - processing controller pulls low the multi_transfer_ctrl. At this time, if the number of request packets sent by the on - chip network is equal to the number of received response packets, the interrupt controller sends an MSI interrupt to the host and writes the number of response packets into the 8 - bit register Resp_cnt in the interrupt - control register bank; if the number of request packets sent by the on - chip network is not equal to the number of received response packets, the interrupt controller sends an MSI interrupt to the host and writes the code representing a response exception into the 8 - bit register ACK in the interrupt - control register bank to ensure the integrity of data transfer and the accuracy of interrupt processing.

[0056] Embodiment 1:

[0057] As Figure 6 shown, before performing read and write operations on the memory die, the PCIe host needs to apply for the corresponding memory space first. In the storage - application event, the host configures the number of reads and writes as 1 and the length as 32 Bytes in the configuration information. The request sent by the host is the control word for storage application: that is, the first data packet is the storage - application event - type information and routing information, and the second data packet is the storage - application size. After receiving the information sent by the host, the conversion interface generates a storage - application request packet CIP_MEM_ALLOC_REQ. After that, the conversion interface needs to wait for the on - chip network to return a storage - application response.

[0058] After the on - chip network returns a response, the conversion interface caches the interrupt information in the interrupt buffer and generates an MSI interrupt to notify the host. After receiving the MSI notification, the host clears the interrupt notification in the interrupt controller and reads the interrupt - cache buffer. The interrupt type includes the response type, memory - access ACK (whether the application is successful), and event ID. ACK being 8’h00 represents a successful application, 8’h01 represents insufficient remaining space in the DDR, and ACK being 8’hff represents that the storage is not initialized. If the application is successful, the base address of the storage application can be read back through the address - cache buffer. Only after the host completes the above operations can it issue the next request command.

[0059] Embodiment 2:

[0060] As Figure 7As shown, when the PCIe host initiates a write event, the host configures the read / write count and data length according to the actual situation in the configuration information. The request sent by the host is the control field of the write request + data payload: that is, the first data packet is the write request event type information and routing information, and then followed by multi-transfer enable, write request address, length, and data payload for multiple transmissions.

[0061] During the write request transmission, the transmission mode is configured through the multi-transfer enable multi_transfer_ctrl signal in the transmission configuration packet. multi_transfer_ctrl being 0 represents entering the single transmission mode, and multi_transfer_ctrl being 1 represents entering the multi-transmission mode.

[0062] In the single transmission mode, after the conversion interface receives the write request sent by the host, it generates a write request packet CIP_WR_REQ. After that, the conversion interface needs to wait for the write response packet (or memory access response packet) returned by the on-chip network, and then generate an interrupt to notify the host. After the host receives the MSI notification, it clears the interrupt notification in the interrupt controller and obtains the interrupt information by reading the interrupt register. Only after the host completes the above operations can it issue the next request command.

[0063] In the multi-transmission mode, setting the multi-transfer enable signal multi_transfer_ctrl to 1 represents entering the multi-transmission mode. This control signal is received and processed in the conversion interface transmission configuration packet {multi_transfer_ctrl, tid, ttp, snodid, srid, dnodid, drid}. During the period when the multi_transfer_ctrl signal is valid, the conversion interface does not return an MSI interrupt to the host, but can receive the requests sent by the host. After completing the data transmission under the specified length, set the multi_transfer_ctrl signal to 0, representing exiting the multi-transmission mode. After that, the conversion interface needs to wait for the write response packet (or memory access response packet) returned by the on-chip network, and then generate an interrupt to notify the host. After the host receives the MSI notification, it clears the interrupt notification in the interrupt controller and obtains the interrupt information by reading the interrupt register.

[0064] The interruption information includes the type of the last response received by the conversion interface, the data length, the address, the number of write responses received during multiple transmissions, the memory access ACK, etc. The host can judge whether the information transmission of the on-chip network is successful through this information. If the write request is successful, the slave interface returns a write response event. If the number of received write responses is the same as the number of sent write requests, it means that all data payloads are successfully transmitted. If the write to the memory fails, the on-chip network returns a memory access response. Among them, ACK being 8’h41 means that the memory is not allocated, ACK being 8’h42 means that the source node does not hold the corresponding node, ACK being 8’h43 means that the write is out of bounds, and ACK being 8’hff means that the memory is not initialized.

[0065] Embodiment 3:

[0066] As Figure 8 shown, when the PCIe host initiates a read event, the host configures the number of read and write operations and the data length according to the actual situation in the configuration information. The request sent by the host is the control field of the read request: that is, the first data packet is the write request event type information and the routing information, and then followed by the multi-transmission enable, the read request address and length.

[0067] During the read request transmission, the transmission mode is configured through the multi_transfer_ctrl signal of the multi-transmission enable in the transmission configuration packet. multi_transfer_ctrl being 0 represents entering the single transmission mode, and multi_transfer_ctrl being 1 represents entering the multi-transmission mode.

[0068] In the single transmission mode, after the conversion interface receives the read request sent by the host, it generates a write request packet CIP_RD_REQ. After that, the conversion interface needs to wait for the read confirmation packet (or memory access response packet) returned by the on-chip network, and then generate an interruption to notify the host. The host obtains the interruption information by reading the interruption register. Only after the host completes the above operations can it issue the next request command. The host can issue the next request command in advance before the read response is returned. The conversion interface will cache the new request information, but it should avoid contaminating the data in the retransmission buffer before the previous read event is completed. Therefore, it will not issue a new on-chip network request packet. At the same time, due to the size limit of the FIFO for caching request commands, the ability of the conversion interface to receive new commands is limited before the previous read event is completed, which may cause congestion to the host. Therefore, only after the previous read event ends can it continue to receive new requests.

[0069] In the multiple - transfer mode, setting the multiple - transfer enable signal multi_transfer_ctrl to 1 indicates entering the multiple - transfer mode. This control signal is received and processed in the transfer - interface transmission configuration packet {multi_transfer_ctrl, tid, ttp, snodid, srid, dnodid, drid}. During the validity period of the multi_transfer_ctrl signal, the transfer interface does not return an MSI interrupt to the host, but can receive the command data sent by the host. After completing the data transfer of the specified length, set the multi_transfer_ctrl signal to 0, indicating exiting the multiple - transfer mode. After that, the transfer interface needs to wait for the read response packet (or memory - access response packet) returned by the on - chip network, and then generate an interrupt to notify the host. After receiving the MSI notification, the host clears the interrupt notification in the interrupt controller and obtains the interrupt information by reading the interrupt register.

[0070] The interrupt information includes the type of the last interrupt, the read address, the length, the memory - access ACK, etc. The host can judge whether the information transmission of the on - chip network is successful through this information. If the read request is successful, the slave interface returns a read response; if the memory read fails, the memory returns a memory - access response. Among them, ACK being 8’h31 represents that the memory is not allocated, ACK being 8’h32 represents that the source node does not hold the corresponding node, ACK being 8’h33 represents that the read is out of bounds, and ACK being 8’hff represents that the DDR is not initialized. If the read request is successful, the host reads the data in the buffer from 32’h 10000. The read request sent by the host includes the read length and the starting address.

[0071] Embodiment 4:

[0072] As Figure 9 shown, the PCIe host can share the memory die in the chiplet system with other master devices for access. In the sharing event, the host configures the read - write times as 1 and the length as 32 Bytes in the configuration information. The request sent by the host is the control word for memory sharing: that is, the first data packet is the information of the memory - sharing event type and the routing information, and the second data packet is the node one - hot code of the shared device and the starting - address information of the shared area. After receiving the information sent by the host, the transfer interface generates a memory - application request packet CIP_MEM_SHARE_REQ. After that, the transfer interface needs to wait for the memory - access response returned by the on - chip network.

[0073] After the Network-on-Chip returns a response, the conversion interface caches the interrupt information in the interrupt buffer and generates an MSI interrupt to notify the host. After receiving the MSI notification, the host clears the interrupt notification in the interrupt controller and reads the interrupt cache buffer. The interrupt type includes the response type, memory access ACK (whether the sharing is successful), and event ID. ACK being 8’h00 represents successful sharing, 8’h11 represents that the memory block is not allocated, 8’h12 represents that the source node has no memory block sharing permission, and 8’hff represents that the storage is not initialized. Only after the host completes the above operations can it issue the next request command.

[0074] Embodiment 5:

[0075] As Figure 10 shown, after the PCIe host finishes operating on the memory die, it needs to release the corresponding memory block. In the storage release event, the host configures the read / write count as 1 and the length as 32 Bytes in the configuration information. The request sent by the host is the control word for storage release: that is, the first data packet is the storage application event type information and routing information, and the second data packet is the starting address of the storage release. After receiving the information sent by the host, the conversion interface generates a storage application request packet CIP_MEM_FREE_REQ. After that, the conversion interface needs to wait for the Network-on-Chip to return a storage application response.

[0076] After the Network-on-Chip returns a response, the conversion interface caches the interrupt information in the interrupt buffer and generates an MSI interrupt to notify the host. After receiving the MSI notification, the host clears the interrupt notification in the interrupt controller and reads the interrupt cache buffer. The interrupt type includes the response type, memory access ACK (whether the release is successful), and event ID. ACK being 8’h00 represents successful release, 8’h21 represents that the memory block is not allocated, ACK being’h22 represents that the source node has no memory block release permission and the release fails, ACK being 8’h23 represents that the memory block has been shared and there are nodes that have not read the shared data and the release is successful, and ACK being 8’hff represents that the DDR is not initialized. Only after the host completes the above operations can it issue the next request command.

[0077] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure fall within the protection scope of the claims.

Claims

1. A PCIe-CIP protocol interconnected chiplet conversion interface circuit supporting large data transmission, characterized in that, Including: A write processing controller, a read processing controller, and an MSI controller; The write processing controller includes a transaction processing controller and a sending controller, which realizes data transmission between the PCIe clock domain and the on-chip network clock domain through an asynchronous FIFO. Before the previous event sending is completed, the sending controller will keep the read enable of the asynchronous FIFO invalid, and backpressure the transaction processing controller through the fifo_full signal to control the data reception of the PCIe host; The read processing controller includes a receiving controller and a data processing controller, which also processes the data stream from the on-chip network clock domain to the PCIe clock domain through an asynchronous FIFO. Before the PCIe host completes the acquisition of the previous interrupt information and data payload, the data processing controller will keep the read enable of the FIFO invalid, and backpressure the receiving controller through the fifo_full signal to manage the data reception from the on-chip network.

2. The PCIe-CIP protocol interposer conversion interface circuit for supporting big data transmission according to claim 1, wherein When the PCIe host sends a request, it includes a control field and a data payload. The control field carries on-chip network routing information, on-chip network event type, read / write times, base address, offset address, and maximum read / write length information, which are processed and encapsulated into storage requests, sharing, releases, and write / read transactions specified by the CIP protocol, and support abnormal retransmission.

3. The PCIe-CIP protocol interconnected die conversion interface circuit for supporting large data transmission according to claim 2, characterized in that The PCIe host configures various information in the request packet by operating the register bank; the write processing controller processes the control field information through a write processing state machine: if the event type is a write event, the register bank operation of this data packet ends after the data payload is sent, otherwise the register bank operation of this time ends after the control field information is sent; The sending end controller of the on-chip network caches the information of this request to the retransmission buffer while sending the request to the on-chip network, and receives the response notification of the on-chip network from the read processing controller. According to the CIP protocol, the next transmission can only be initiated after one transaction transmission of the on-chip network is completed. If the transmission is abnormal and the response information is not received after exceeding the specified time, the sending end controller of the on-chip network resends the request from the retransmission buffer, and the retransmission buffer is released after receiving the response. At this time, the write processing controller makes the next request to the on-chip network.

4. The PCIe-CIP protocol interconnection die conversion interface circuit for supporting large data transmission according to claim 3, wherein The PCIe host obtains interrupt information and reads the data payload through a memory semantic read operation, and supports caching up to 32KB of data payload at most; the PCIe host reads the interrupt information from the reserved interrupt information register bank according to the read address offset, and reads the data payload from the data cache.

5. The PCIe-CIP protocol interconnected die conversion interface circuit for supporting large data transmission according to claim 1, wherein The read processing controller supports the response information specified by the CIP protocol, including: storage request response, storage access response, read confirmation, read response, interrupt notification, write response, and supports timeout and no-response processing; The receiving end controller of the on-chip network unpacks and verifies the response information returned by the on-chip network, and returns the unpacked data information to the data processing controller through an asynchronous FIFO after passing the verification; if the corresponding is not received within the timeout or the data verification fails, a timeout retransmission notification tx_retry is sent to the write processing controller; The data processing controller is controlled by the read processing state machine of the read processing controller: if the response returns to the conversion interface, the response information is cached into the interrupt information buffer, and a retransmission buffer release notification is sent to the write processing controller; if the response is a read response, the read data payload is cached into the data buffer; if there is no response from the on-chip network interface due to timeout, a timeout unacknowledged notification NACK is written to the interrupt information buffer.

6. The PCIe-CIP protocol interposer conversion interface circuit for supporting large data transmission as claimed in claim 5, wherein, For the response information returned by the on-chip network, the conversion interface circuit returns an MSI interrupt to the host after parsing: In the single transmission mode, if a response is received, it indicates that the transmission event is completed, and an MSI interrupt is returned to the host; if no response is received due to timeout, it indicates that the transmission fails, and an MSI interrupt is returned to the host; In the large data transmission mode, the msi_req enable is controlled by the multi-transmission control signal multi_transfer_ctrl. At the start of the transmission, multi_transfer_ctrl is pulled high. During this period, the msi_req enable is invalid. The information in the register bank of the write processing controller is encapsulated and sent in accordance with the CIP protocol format, and its response is received by the read processing controller and cached in the interrupt information buffer. When the data transmission is all completed, multi_transfer_ctrl is pulled low, and an MSI interrupt is returned to the host.

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