I2C interface circuit, corresponding electronic device and operation method

Abstract

The invention relates to an I2C interface circuit, a corresponding electronic device and an operation method. A first comparator stage of the I2C interface circuit compares a received clock signal to a low threshold and a high threshold to generate a clock signal. A second comparator stage of the I2C interface circuit compares the received data signal to a low threshold and a high threshold to generate the data signal. The first comparator stage and the second comparator stage are default programmed to be in a first mode of operation in which the low threshold is a first score of the high pull-up voltage and the high threshold is a second score of the low pull-up voltage. In response to a received programming frame identifying a current pull-up voltage value, the first comparator stage and the second comparator stage are switchable to a second mode of operation in which the low threshold is a first score of the current pull-up voltage value and the high threshold is a second score of the current pull-up voltage value.

Description

[0001] Priority Claim

[0002] This application claims the priority benefit of Italian Patent Application No. 102024000000123, filed on January 5, 2024, the content of which is incorporated herein by reference in its entirety to the maximum extent permitted by law. Technical Field

[0003] This specification relates to electronic circuits (e.g., switching converters) provided with an inter-integrated circuit (I 2 C) interface.

[0004] A switching converter with an embedded I 2 C interface can be implemented, for example, in a class-D power amplifier (audio amplifier) used in an automotive radio device. Background Art

[0005] Switching devices (such as class-D amplifiers and switching converters) generate electronic noise that can propagate to the digital interfaces of the devices themselves, thereby affecting the normal operation of such interfaces. Generally, the higher the PWM switching frequency, current, and voltage of the switching device, the higher the associated electronic noise.

[0006] A digital interface that can be affected by noise is an I 2 C interface (for reference, see NXP's user manual UM10204, "I 2 C-bus specification and user manual", revision 7.0, October 1, 2021, incorporated herein by reference). The input comparator of an I 2 C interface designed to discriminate between high and low levels of an input digital signal is therefore typically designed to have a large hysteresis to achieve robustness against noise (i.e., to avoid spurious commutation due to noise). In this regard, the I 2 C specification defines an (external) pull-up voltage V pu , and also defines the high-level digital input logic voltage threshold V IH and the low-level digital input logic voltage threshold V IL of the input comparator according to the following constraints: V IH <0.7*V pu and V IL >0.3*V pu .

[0007] At the same time, it is desirable for the input comparator of the I 2 C interface to be associated with the pull-up voltage V puis compatible with at least two values, such as 1.8V and 3.3V (which are conventional values for supply voltages in CMOS technology).

[0008] On the one hand, a large hysteresis is required, and on the other hand, compatibility with at least two different pull-up voltage levels is required, which is in conflict. In fact, considering an example where it is desired to be compatible with both V pu18 = 1.8V and V pu33 = 3.3V, the values of the comparator thresholds V IH and V IL will be constrained by the following values:

[0009] V IH <0.7 * V pu18 = 0.7 * 1.8V = 1.26V

[0010] V IL > 0.3 * V pu33 = 0.3 * 3.3V = 0.99V

[0011] The maximum difference V IH - V IL = 0.27V is not sufficient to accommodate possible threshold mismatches, process variations, and parasitic voltage drops while still providing enough hysteresis to suppress noise.

[0012] A known solution to the problem discussed above is a solution that uses a pin of an electronic device to receive an external pull-up voltage V pu . By receiving the pull-up voltage in the electronic device, a high threshold V 2 and a low threshold V IH for the input comparator of the I IL C interface can be generated inside the device, and a wider range of hysteresis can be achieved. For example, again considering an example where it is desired to be compatible with both V pu18 = 1.8V and V pu33 = 3.3V, the thresholds V IH and V IL can be generated as follows: If V pu = 3.3V, then V IL = 0.99V and V IH = 2.31V; if V pu = 1.8V, then V IL = 0.54V and V IH = 1.26V. Therefore, if V pu = 3.3V, then the difference between the thresholds (which will be used for hysteresis and to accommodate mismatches) will be equal to 1.32V, while if V pu= 1.8V, then the difference will be equal to 0.72V. For example, such a solution can be known from the datasheet of the device TAS2764 of Texas Instruments, "TAS2764 Digital Input Mono Class-D Audio Amplifier With Speaker IV Sense", SLOS998A, December 2020, revised in September 2021, which is incorporated herein by reference.

[0013] However, a disadvantage of the known solutions discussed above is that conductive traces must be provided on the printed circuit board (PCB) to route the pull-up voltage V pu to the electronic device, and pins of the electronic device must be used to receive the external pull-up voltage V pu . In particular, for low-cost devices, the number of available pins is limited, and dedicating a pin to receive the external pull-up voltage V pu is not desirable.

[0014] Also refer to U.S. Patent No. 10,447,269B1, which is an interesting document in the technical field. This patent discloses a level shifter circuit that can be used in a comparator of an I 2 C interface. The level shifter circuit shifts the level of the received / transmitted I 2 C signal when the internal logic of the chip operates at a certain voltage (e.g., 1.8V), and the certain voltage is different from the voltage (e.g., 1.2V) of an external device coupled to the I 2 C interface.

[0015] Reference is also made to other interesting documents in the art, including: Chinese Application No. 112650377A; PCT Patent Publication WO 2020 / 218472 A1; Chinese Patent No. 106788354B; US Patent No. 5,166,550A; US Patent Publication No. 2007 / 0296478A1; the document of Texas Instruments "TIDesigns - Precision: Verified Design - Comparator with Hysteresis Reference Design", TIDU020A, May 2013, revised in June 2014; the document of Texas Instruments "Analog Engineer’s Circuit - Programmable comparator circuit with hysteresis or latching output", SLAAE20, May 2021; and the document of Y. Yao and M. Jiang, "Design of Hysteresis Comparator with Wide Common Mode Operating Range", 2022 IEEE 4th International Conference on Circuits and Systems (ICCS), Chengdu, China, 2022, pp. 91 - 94, doi: 10.1109 / ICCS56666.2022.9936471. All of the above references are incorporated herein by reference.

[0016] None of these known solutions provides an I 2 C interface circuit that is compatible with two (or more) different pull - up voltage levels and is suitable for large hysteresis at the same time.

[0017] Therefore, there is a need in the art to provide an improved I 2 C interface circuit that facilitates the solution of the above - mentioned problems. SUMMARY OF THE INVENTION

[0018] One or more embodiments of the present disclosure contribute to providing an improved I 2 C interface circuit.

[0019] According to one or more embodiments, this object can be achieved by an I 2 C interface circuit.

[0020] One or more embodiments may relate to corresponding electronic devices (e.g., switch converters or switch power amplifiers).

[0021] One or more embodiments may relate to corresponding methods of operation.

[0022] In accordance with one aspect of the present specification, I 2 the I2C interface circuit may operate at a low pull-up voltage and at a high pull-up voltage. I 2 The I2C interface circuit includes a first pin configured to receive a clock signal and a second pin configured to receive a data signal. I 2 The I2C interface circuit includes a first comparator stage coupled to the first pin and configured to compare the received clock signal with a low threshold and a high threshold to generate an internal clock signal. I 2 The I2C interface circuit includes a second comparator stage coupled to the second pin and configured to compare the received data signal with a low threshold and a high threshold to generate an internal data signal. The first comparator stage and the second comparator stage are default programmed to operate in a first operating mode. In the first operating mode, the low threshold is set to a first fractional value of the high pull-up voltage, and the high threshold is set to a second fractional value of the low pull-up voltage (e.g., where the first fractional value is lower than the second fractional value). The first comparator stage and the second comparator stage may switch to a second operating mode after receiving a programming frame via the I 2 2C interface that conveys the current value of the pull-up voltage. In the second operating mode, the low threshold is set to a first fractional value of the current pull-up voltage, and the high threshold is set to a second fractional value of the current pull-up voltage.

[0023] Accordingly, one or more embodiments may provide an I 2 2C interface circuit that is 2 compatible with multiple values of the pull-up voltage and is robust in terms of comparison hysteresis without routing the pull-up voltage to the interface itself.

[0024] In accordance with another aspect of the present specification, an electronic device includes an I 2 2C interface circuit according to one or more embodiments, and a processing circuit. The processing circuit is configured to receive a programming frame that conveys the current value of the pull-up voltage via the I 2 2C interface circuit, and switch the first comparator stage and the second comparator stage of the I 2 2C interface circuit to the second operating mode based on the programming frame.

[0025] In accordance with another aspect of the present specification, a method of operating an I 2A method for a C interface circuit or an electronic device includes: receiving a clock signal at a first pin and receiving a data signal at a second pin; comparing the received clock signal with a low threshold and a high threshold in a first comparator stage and generating an internal clock signal; comparing the received data signal with a low threshold and a high threshold in a second comparator stage and generating an internal data signal; by default, programming the first comparator stage and the second comparator stage to operate in a first operating mode, where the low threshold is set to a first fractional value of a high pull-up voltage, and the high threshold is set to a second fractional value of a low pull-up voltage; and according to a programming frame received via an I 2 C interface that conveys the current value of the pull-up voltage, switching the first comparator stage and the second comparator stage to a second operating mode, where the low threshold is set to a first fractional value of the current pull-up voltage, and the high threshold is set to a second fractional value of the current pull-up voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] One or more embodiments will now be described by way of example with reference to the accompanying drawings, in which:

[0027] Figure 1 is an exemplary circuit diagram of an I 2 C interface circuit according to one or more embodiments of the present specification;

[0028] Figure 2 is a timing diagram including an exemplary waveform of a signal in an electronic device, the electronic device including an I 2 C interface circuit according to one or more embodiments of the present specification;

[0029] Figure 3 is an exemplary circuit diagram of an I 2 C interface circuit according to a further embodiment of the present specification; and

[0030] Figure 4 is an exemplary circuit diagram of an I 2 C interface circuit according to a still further embodiment of the present specification. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0031] In the following description, one or more specific details are set forth, aiming to provide an in-depth understanding of examples of embodiments of the present specification. Embodiments can be obtained without one or more of these specific details, or can be obtained using other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so as not to obscure certain aspects of the embodiments.

[0032] References to "an embodiment" or "one embodiment" in the framework of this specification are intended to indicate that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in one embodiment" that may appear in one or more places in this specification do not necessarily refer to the same embodiment. Moreover, particular configurations, structures, or characteristics may be combined in any appropriate manner in one or more embodiments.

[0033] The headings / reference numbers used herein are provided for convenience only and do not limit the scope of protection or the scope of the embodiments.

[0034] Throughout the drawings appended hereto, unless the context indicates otherwise, the same parts or elements are indicated by the same reference numerals / numbers, and the corresponding description will not be repeated for the sake of brevity.

[0035] As is known, I 2 The I C interface consists of two (bidirectional) communication lines, specifically the serial data line (SDA) and the serial clock line (SCL). 2 The C interface includes two I / O pins, each of which is connected to a corresponding comparator stage, which is configured to distinguish between a high level and a low level of a corresponding input digital signal. In order to provide at least two different pull-up voltage levels V pu_low (V pu Low value) and V pu_high (V pu ) (and therefore, is compatible with different levels of the input digital signal) and also has a large hysteresis I 2 C interface circuit, one or more embodiments relate to an I 2 C interface circuit, where (one or more) input comparator stages can be connected via I 2 C interface itself (i.e., without employing additional I / O pins) to switch between:

[0036] - A first operating mode in which the comparator stage operates with a small hysteresis but can be used for the value of the pull-up voltage V pu_low and V pu_high , (e.g., 1.8V or 3.3V); and

[0037] - A second operating mode, in which the comparator stage is programmed to have a larger hysteresis, the expected pull-up voltage value V pu_low and V pu_high The device operates on a specific one of the two voltages (e.g., 1.8 V or 3.3 V).

[0038] Specifically, at device startup, the comparator stage defaults to operating with a small hysteresis and can operate at any one of the possible values of the pull-up voltage V pu_low and V pu_high (e.g., 1.8V and 3.3V). During the startup phase, the device is idle and thus does not generate noise (e.g., because there is no ongoing switching activity), and the small hysteresis (obtained by setting V IH = 0.7 * V pu_low and V IL = 0.3 * V pu_high ) is not a problem. At this stage, the I 2 C interface receives a frame indicating whether the actual pull-up voltage is equal to V pu_low (e.g., 1.8V) or V pu_high (e.g., 3.3V). Depending on this message, the comparator stage is programmed with the corresponding thresholds V IH and V IL (e.g., if V pu = V pu_low , then V IH = 0.7 * V pu_low and V IL = 0.3 * V pu_low , and if V pu = V pu_high , then V IH = 0.7 * V pu_high and V IL = 0.3 * V pu_high , which respectively result in if V pu = V pu_low = 1.8V, then V IH = 1.26V and V IL = 0.54V, and if V pu = V pu_high = 3.3V, then V IH = 2.31V and V IL = 0.99V). Thus, after programming, the comparator stage operates with a larger hysteresis and provides good suppression of the noise generated by the switching elements of the device.

[0039] The above operations can be implemented through different architectures of the comparator stage of the I 2 C interface, such as illustrated in the exemplary embodiments of Figure 1 , Figure 3 and Figure 4 .

[0040] Figure 1 is an exemplary circuit diagram of the I 2 C interface circuit 10 according to one or more embodiments of the present specification. I2 The C interface includes a first I / O pin 12a configured to receive a clock signal I2Cclk and a second I / O pin 12b configured to receive a data signal I2Cdata. At least three comparators 14a, 16a, and 18a are coupled to pin 12a to receive the signal I2Cclk, and similarly, at least three comparators 14b, 16b, and 18b are coupled to pin 12b to receive the signal I2Cdata. Comparators 14a and 14b (also referred to as "combined" comparators) are compatible with all possible levels of the pull-up voltage (i.e., at least V pu_low and V pu_high ), and the I 2 C interface is expected to operate at all possible levels of this pull-up voltage (e.g., the possible values of the CMOS supply voltage). In other words, the comparison thresholds of comparators 14a and 14b are set as follows: V IH = 0.7 * V pu_low and V IL = 0.3 * V pu_high . As discussed previously, V pu_low can be equal to 1.8V and V pu_high can be equal to 3.3V, but other values are also possible; for example, the pull-up voltage can be equal to 5V. By setting these values of the thresholds V IH and V IL , comparators 14a and 14b have small hysteresis, but this is not a problem as long as there is no switching activity in the device (e.g., at startup), so the electronic noise is low. Comparators 16a and 16b are compatible with a specific one of the voltage levels of the pull-up voltage (e.g., specifically compatible with V pu_low ). In other words, the comparison thresholds of comparators 16a and 16b are set as follows: V IH = 0.7 * V pu_low and V IL = 0.3 * V pu_low . By setting these values of the thresholds V IH and V IL , comparators 16a and 16b have large hysteresis and are configured to operate at V 2 = V pu even if the I pu_low C interface is affected by switching noise. Similarly, comparators 18a and 18b are compatible with another specific one of the voltage levels of the pull-up voltage (e.g., specifically compatible with V pu_high ). In other words, the comparison thresholds of comparators 18a and 18b are set as follows: V IH = 0.7 * V pu_high and V IL = 0.3 * V pu_high . By setting the thresholds V IHand V IL For these values of, comparators 18a and 18b have large hysteresis and are configured to operate even if the I 2 C interface is affected by switching noise, with V pu = V pu_high operation. The first multiplexer (MUX) 20a is coupled to the output terminals of comparators 14a, 16a, and 18a in the first communication line of the I 2 C interface, and the second multiplexer (MUX) 20b is coupled to the output terminals of comparators 14b, 16b, and 18b in the second communication line of the I 2 C interface. Thus, multiplexer 20a propagates one of the output signals from comparators 14a, 16a, and 18a to the internal circuit of the device as the internal clock signal clk_in, while multiplexer 20b propagates one of the output signals from comparators 14b, 16b, and 18b to the internal circuit of the device as the internal data signal data_in. Multiplexers 20a and 20b are controlled by the selection signal REG provided by the programmable register 22. Comparators 14a, 16a, and 18a together with multiplexer 20a form the first comparator stage 24a, while comparators 14b, 16b, and 18b together with multiplexer 20b form the second comparator stage 24b.

[0041] By referring to Figure 2 , the operation of the I Figure 1 C interface circuit 10 illustrated in 2 can be additionally understood. Figure 2 is a timing diagram that illustrates the enable signal EN, the I 2 C signals I2Cclk and I2Cdata (collectively referred to as the signal I2C), the selection signal REG, and the possible waveforms of the output voltage V SW provided by the switching power stage in the electronic device. By default, at startup (indicated by the assertion of the enable signal EN at time t1), the register 22 sets the value of the selection signal REG such that multiplexers 20a and 20b respectively propagate the signals output by comparators 14a and 14b (combined comparators). Thus, at startup, the I 2 C interface 10 operates with small hysteresis and full compatibility with different values of the pull-up voltage, and immediately receives the I 2 C programming frame (write frame) that transmits the current value of the pull-up voltage (see Figure 2 at time t2). Once the programming frame is received, the device processes the programming frame and programs the register 22 with its output selection signal REG (see Figure 2At time t3), the selection signal REG controls multiplexers 20a and 20b to propagate the value of the signal output by comparators 16a, 16b or alternatively by 18a, 18b according to the current value of the pull-up voltage. Once the output from comparators 16a, 16b or 18a, 18b is selected, I 2 C interface circuit 10 operates with sufficient hysteresis such that even after the start of the switching activity of signal V SW (see Figure 2 at time t4), additional I 2 C frames (see Figure 2 at time t5) can be received and correctly decoded using the correct comparator.

[0042] Figure 3 is an exemplary circuit diagram of an I 2 C interface circuit 30 according to a further embodiment of the present specification. Elements that are the same as or similar to the elements discussed with reference to Figure 1 are denoted by the same or similar reference numerals, and the corresponding descriptions are not repeated for the sake of brevity. Different from the Figure 1 embodiment, Figure 3 the embodiment includes reconfigurable comparators 32a instead of comparators 16a and 18a and reconfigurable comparators 32b instead of comparators 16b and 18b (while comparators 14a and 14b remain the same as before). Comparators 32a and 32b can be selectively configured (e.g., programmed) to be compatible with a selected one of the voltage levels of the pull-up voltage depending on the value of an additional selection signal provided by an additional programmable register 36 (e.g., specifically compatible with V pu_low or V pu_high ). In other words, the comparison thresholds of comparators 32a and 32b can be set as follows: for a first value of the additional selection signal, V IH = 0.7 * V pu_low and V IL = 0.3 * V pu_low , while for a second value of the additional selection signal, V IH = 0.7 * V pu_high and V IL = 0.3 * V pu_highFor example, the configurability of comparators 32a and 32b can be obtained, for example, by implementing a comparator with a pass gate, which allows the threshold to be configured. Multiplexers 34a and 34b operate substantially the same as multiplexers 20a and 20b, directed by the selection signal REG output from register 22, but can select from the outputs of comparators 14a, 32a and 14b, 32b respectively. Comparators 14a and 32a together with multiplexer 34a form a first comparator stage 24a, while comparators 14b and 32b together with multiplexer 34b form a second comparator stage 24b.

[0043] As Figure 3 illustrated in 2 the operation of the I2C interface circuit 30 is substantially very similar to that of the Figure 1 circuit as discussed with reference to Figure 2 . At startup, register (REG1) 22 outputs a selection signal that controls multiplexers 34a and 34b to respectively propagate the signals output by comparators 14a and 14b (combined comparators). Once an I2C programming frame that conveys the current value of the pull-up voltage is received, the device processes the I2C programming frame and programs registers (REG1) 22 and (REG2) 36. In particular, register 22 is programmed in such a way that its output selection signal controls multiplexers 34a and 34b to propagate the signals output by comparators 32a and 32b (regardless of the current value of the pull-up voltage), and register 36 is programmed in such a way that its output another selection signal controls comparators 32a and 32b to set their thresholds according to the current value of the pull-up voltage. Once comparators 32a and 32b are programmed, the I2C interface circuit 30 operates with sufficient hysteresis such that even after the switching activity of signal V starts, another I2C frame can be received and correctly decoded. 2 C programming frame, the device processes the I2C programming frame and programs registers (REG1) 22 and (REG2) 36. In particular, register 22 is programmed in such a way that its output selection signal controls multiplexers 34a and 34b to propagate the signals output by comparators 32a and 32b (regardless of the current value of the pull-up voltage), and register 36 is programmed in such a way that its output another selection signal controls comparators 32a and 32b to set their thresholds according to the current value of the pull-up voltage. Once comparators 32a and 32b are programmed, the I2C interface circuit 30 operates with sufficient hysteresis such that even after the switching activity of signal V starts, another I2C frame can be received and correctly decoded. 2 C programming frame, the device processes the I2C programming frame and programs registers (REG1) 22 and (REG2) 36. In particular, register 22 is programmed in such a way that its output selection signal controls multiplexers 34a and 34b to propagate the signals output by comparators 32a and 32b (regardless of the current value of the pull-up voltage), and register 36 is programmed in such a way that its output another selection signal controls comparators 32a and 32b to set their thresholds according to the current value of the pull-up voltage. Once comparators 32a and 32b are programmed, the I2C interface circuit 30 operates with sufficient hysteresis such that even after the switching activity of signal V starts, another I2C frame can be received and correctly decoded. 2 C interface circuit 30 operates with sufficient hysteresis such that even after the switching activity of signal V starts, another I2C frame can be received and correctly decoded. SW starts, another I2C frame can be received and correctly decoded. 2 C frame.

[0044] Figure 4 is an exemplary circuit diagram of an I2C interface circuit 40 according to another embodiment of the present specification. Elements that are the same as or similar to the elements discussed with reference to 2 and Figure 1 are denoted by the same or similar reference numerals, and the corresponding descriptions are not repeated for the sake of brevity. Different from the embodiment of Figure 3 and Figure 1 , Figure 3 the embodiment of Figure 4Embodiments include a single reconfigurable comparator 42a coupled to pin 12a to receive the signal I2Cclk and generate the signal clk_in, and a single reconfigurable comparator 42b coupled to pin 12b to receive the signal I2Cdata and generate the signal data_in. Basically, comparators 42a and 42b can be selectively configured (e.g., programmed) to operate as "combinational" comparators 14a and 14b or as dedicated comparators 32a, 32b depending on the value of the select signal provided by the programmable register 44. In other words, depending on the value of the select signal output by register 44, the comparison thresholds of comparators 42a and 42b can be set as follows: for a first value of the select signal, V IH = 0.7 * V pu_low and V IL = 0.3 * V pu_high ; for a second value of the select signal, V IH = 0.7 * V pu_low and V IL = 0.3 * V pu_low ; and for a third value of the select signal, V IH = 0.7 * V pu_high and V IL = 0.3 * V pu_high . The reconfigurability of comparators 42a and 42b can be obtained, for example, by implementing a comparator with a pass gate, which allows the threshold to be configured. Figure 4 Embodiments do not include a multiplexer. Thus, comparator 42a constitutes the first comparator stage 24a, while comparator 42b constitutes the second comparator stage 24b.

[0045] As Figure 4 illustrated in 2 the operation of the I Figure 1 and Figure 3 circuit of Figure 2 is substantially very similar to the operation of the circuit of Figure 2 , as discussed with reference to Figure 2 . By default, at startup, the register (REG3) 44 outputs a select signal that controls comparators 42a and 42b to set their thresholds according to the "combinational" configuration. Once an I 2 C programming frame that conveys the current value of the pull-up voltage is received, the device processes the I 2 C programming frame and programs the register 44. In particular, the register 44 is programmed in such a way that its output select signal controls comparators 42a and 42b to set their thresholds according to the current value of the pull-up voltage. Once comparators 42a and 42b are programmed, the I 2 C interface circuit 40 operates with sufficient hysteresis such that even when the signal V SWAfter the switch activity of 2 starts, additional I

[0046] C frames can also be received and correctly decoded. 2 Using the novel architecture of the I pu C interface disclosed herein, it is not necessary to introduce the pull-up voltage V 2 into the device (as long as the value of the pull-up voltage V pu is transmitted to the device via an I

[0047] C message during the startup phase, and at this time the suppression of the noise pair is not a problem), thus saving a conductive trace on the PCB and reducing the number of pins of the integrated circuit.

[0048] Without departing from the underlying principles, details and embodiments can vary, even significantly, from what is described by way of example, without departing from the scope of protection.

[0049] The scope of protection is determined by the appended claims.

Claims

1. An inter-integrated circuit (I 2 C) interface circuit capable of operating at a low pull-up voltage and a high pull-up voltage, the I 2 C interface circuit comprising: A first pin configured to receive a clock signal; A second pin configured to receive a data signal; A first comparator stage coupled to the first pin and configured to compare the received clock signal with a low threshold and a high threshold to generate an internal clock signal; A second comparator stage coupled to the second pin and configured to compare the received data signal with the low threshold and the high threshold to generate an internal data signal; Wherein the first comparator stage and the second comparator stage are configured to operate in a first operating mode by default, wherein the low threshold is set to a first fractional value of the high pull-up voltage and the high threshold is set to a second fractional value of the low pull-up voltage; and Wherein when a programming frame conveying the current value of the pull-up voltage is received via the I 2 C interface, the first comparator stage and the second comparator stage may switch to a second operating mode, wherein the low threshold is set to the first fractional value of the current value of the pull-up voltage, and the high threshold is set to the second fractional value of the current value of the pull-up voltage.

2. The I as described in claim 1 2 a C interface circuit, wherein each of the first comparator stage and the second comparator stage includes: A first comparator having a low threshold set to the first fractional value of the high pull-up voltage and a high threshold set to the second fractional value of the low pull-up voltage; A second comparator having a low threshold set to the first fractional value of the low pull-up voltage and a high threshold set to the second fractional value of the low pull-up voltage; And A third comparator having a low threshold set to the first fractional value of the high pull-up voltage and a high threshold set to the second fractional value of the high pull-up voltage; And A multiplexer configured to propagate one of the outputs from the first comparator, the second comparator, and the third comparator according to the value of a programmable register; Wherein the programmable register is set to a first value by default, the first value causing the multiplexer to propagate the output from the first comparator, and the programmable register can be programmed by the programming frame to: A second value that causes the multiplexer to propagate the output from the second comparator when the current value of the pull-up voltage is equal to the low pull-up voltage, and A third value that causes the multiplexer to propagate the output from the third comparator when the current value of the pull-up voltage is equal to the high pull-up voltage.

3. The I as described in claim 1 2 a C interface circuit, wherein each of the first comparator stage and the second comparator stage includes: A first comparator having a low threshold set to the first fractional value of the high pull-up voltage and a high threshold set to the second fractional value of the low pull-up voltage; And A second comparator capable of selectively switching between a first comparison mode and a second comparison mode according to the value of a first programmable register, wherein in the first comparison mode, the low threshold is set to the first fractional value of the low pull-up voltage and the high threshold is set to the second fractional value of the low pull-up voltage, and in the second comparison mode, the low threshold is set to the first fractional value of the high pull-up voltage and the high threshold is set to the second fractional value of the high pull-up voltage; And A multiplexer configured to propagate one of the outputs from the first comparator and the second comparator according to the value of a second programmable register; wherein the second programmable register is default-set to a first value that causes the multiplexer to propagate the output from the first comparator, and the second programmable register is programmable to a second value in response to the received programming frame, the second value causing the multiplexer to propagate the output from the second comparator; and wherein the first programmable register is programmable by the programming frame to: a first value that causes the second comparator to operate in a first comparison mode when the current value of the pull-up voltage is equal to the low pull-up voltage, and a second value that causes the second comparator to operate in a second comparison mode when the current value of the pull-up voltage is equal to the high pull-up voltage.

4. The I as described in claim 1 2 a C interface circuit, wherein each of the first comparator stage and the second comparator stage includes a comparator that can be selectively switched between a first comparison mode, a second comparison mode, and a third comparison mode according to the value of a programmable register, wherein: In the first comparison mode, the low threshold is set to the first fractional value of the high pull-up voltage, and the high threshold is set to the second fractional value of the low pull-up voltage; In the second comparison mode, the low threshold is set to the first fractional value of the low pull-up voltage, and the high threshold is set to the second fractional value of the low pull-up voltage; and In the third comparison mode, the low threshold is set to the first fractional value of the high pull-up voltage, and the high threshold is set to the second fractional value of the high pull-up voltage; wherein the programmable register is default-set to a first value that causes the comparator to operate in a first comparison mode, and the programmable register is programmable by the programming frame to: a second value that causes the comparator to operate in a second comparison mode when the current value of the pull-up voltage is equal to the low pull-up voltage, and a third value that causes the comparator to operate in a third comparison mode when the current value of the pull-up voltage is equal to the high pull-up voltage.

5. The I as described in claim 1 2 C interface circuit, wherein the low pull-up voltage is equal to approximately 1.8V, and the high pull-up voltage is equal to approximately 3.3V.

6. The I as described in claim 1 2 C interface circuit, wherein the first fractional value is equal to approximately 0.3, and the second fractional value is equal to approximately 0.

7.

7. An electronic device, comprising: I as described in claim 1 2 C interface circuit; and processing circuitry configured to: Via I 2 Receive the programming frame that conveys the current value of the pull-up voltage via the C interface circuit; and Switch the first comparator stage and the second comparator stage of the I 2 C interface circuit to the second operating mode according to the programming frame.

8. A method of operating an inter-integrated circuit (I 2 C) interface circuit, the method comprising: receive a clock signal at a first pin; receive a data signal at a second pin; compare the received clock signal with a low threshold and a high threshold in a first comparator stage to generate an internal clock signal; compare the received data signal with the low threshold and the high threshold in a second comparator stage to generate an internal data signal; by default, program the first comparator stage and the second comparator stage to operate in a first operating mode, wherein the low threshold is set to the first fractional value of the high pull-up voltage, and the high threshold is set to the second fractional value of the low pull-up voltage; and Based on a programming frame conveying a current value of a pull-up voltage received via an I 2 C interface, switch the first comparator stage and the second comparator stage to a second operating mode, wherein the low threshold is set to the first fractional value of the current value of the pull-up voltage, and the high threshold is set to the second fractional value of the current value of the pull-up voltage.

9. The method of claim 8, wherein the low pull-up voltage is equal to approximately 1.8V, and the high pull-up voltage is equal to approximately 3.3V.

10. The method of claim 8, wherein the first fractional value is equal to approximately 0.3, and the second fractional value is equal to approximately 0.7.

Images