Data encryption method for storage device, data transmission method and electronic device

Abstract

The present invention provides a data encryption method, a data transmission method, and an electronic device for a storage device, belonging to the field of storage technology. The data encryption method for the storage device includes the following steps: determining the number of rows and columns of a key matrix based on the specifications of the hardware register storing the key in the storage device, and using a unit matrix with the determined number of rows and columns as the initial key matrix; arranging multiple numbers in random order to form an interchange array, and using the numbers in the interchange array to define the column position of element one in the initial key matrix to form an intermediate key matrix; performing a doubling elementary row transformation on each row of the intermediate key matrix to obtain a target key matrix, and obtaining a target decryption matrix corresponding to the target key matrix; and encrypting plaintext data using the target key matrix to form a ciphertext matrix. The data encryption method for a storage device provided by the present invention can provide users with a simple and secure data encryption method.

Description

Technical Field

[0001] The present invention belongs to the field of storage technology, and in particular relates to a data encryption method, a data transmission method and an electronic device of a storage device. Background Art

[0002] In Universal Flash Storage (UFS), the UFS Protocol Information Unit (UPIU) is the basic unit for information exchange between the host and the device. The UFS Protocol Information Units involved in data transmission include outbound UPIUs and inbound UPIUs. UPIUs are generated by the host and sent to the device, while UPIUs are generated by the device and sent to the host. Both types of UPIUs are processed by the host controller or the UFS Transport Protocol (UTP) engine and are not involved by the host software.

[0003] In the process of data transmission, in order to ensure the security of data, it is necessary to encrypt the data. The Universal Flash Storage Host Controller Interface (UFSHCI) protocol provides a variety of encryption algorithms, such as AES-XTS, Microsoft AES-CBC, AES-ECB or ESSIV-AES-CBC algorithms, but these algorithms require high costs during use. Summary of the Invention

[0004] The object of the present invention is to provide a data encryption method for a storage device, a data transmission method and an electronic device, which can provide a user-defined, concise and secure data encryption method.

[0005] To achieve the above object, the present invention provides a data encryption method for a storage device, and the data encryption method for a storage device includes at least the following steps:

[0006] Determining the number of rows and columns of the key matrix according to the specifications of the hardware registers in the storage device for storing the key, and using the identity matrix with the determined number of rows and columns as the initial key matrix;

[0007] Arrange a plurality of numbers in random order to form an interchange array, and use the numbers in the interchange array to define the column position of element one in the initial key matrix to form an intermediate key matrix;

[0008] Performing a doubling elementary row transformation on each row of the intermediate key matrix to obtain a target key matrix, and obtaining a target decryption matrix corresponding to the target key matrix; and

[0009] The target key matrix is ​​used to encrypt the plaintext data to form a ciphertext matrix, and the target decryption matrix is ​​used to decrypt the ciphertext matrix.

[0010] In one embodiment of the present invention, when forming the interchange array, the number and range of elements in the interchange array are first determined; wherein the number of elements in the interchange array is equal to the number of rows of the key matrix, and the elements in the interchange array are natural numbers from 1 to the number of columns.

[0011] In one embodiment of the present invention, after determining the number and range of elements in the swap array, multiple elements in the swap array are arranged in random order to form the swap array.

[0012] In one embodiment of the present invention, when the column position of element one in the initial key matrix is ​​limited by the numbers in the interchange array, each element in the interchange array is used to limit the column position of element one in each row of the initial key matrix according to the arrangement order of the elements to obtain the intermediate key matrix.

[0013] In one embodiment of the present invention, after the intermediate key matrix is ​​obtained, an intermediate decryption matrix corresponding to the intermediate key matrix is ​​obtained; and the intermediate decryption matrix is ​​a transposed matrix of the intermediate key matrix.

[0014] In one embodiment of the present invention, obtaining the target key matrix includes the following steps:

[0015] Randomly generate a doubling array;

[0016] Performing a doubling elementary row transformation on each row of the intermediate key matrix using each element in the doubling array to obtain the target key matrix; and

[0017] The value range of the target key matrix is ​​limited.

[0018] In one embodiment of the present invention, when generating the doubling array, the value range of the elements in the doubling array is first limited, and multiple elements are randomly selected within the limited value range to generate the doubling array; wherein the number of elements in the doubling array is equal to the number of rows of the intermediate key matrix.

[0019] In one embodiment of the present invention, when performing a doubling elementary row transformation on each row of the intermediate key matrix using each element in the doubling array, the elements in the doubling array are used as multiples to gradually multiply the elements of a row of the intermediate key matrix by an element in the doubling array, and the multiplication result is added to another row of elements in the intermediate key matrix to form the target key matrix; and each row of elements in the formed target key matrix has two non-zero elements.

[0020] In one embodiment of the present invention, a modulo operation is performed on each element in the target key matrix to limit the value range of the target key matrix.

[0021] In one embodiment of the present invention, the target decryption matrix is ​​an inverse matrix of the target key matrix.

[0022] In one embodiment of the present invention, when using the target key matrix to encrypt plaintext data to form a ciphertext matrix, the plaintext data is first split into multiple plaintext matrices, and then the target key matrix is ​​used to encrypt the plaintext matrices to form the ciphertext matrix.

[0023] The present invention also provides a data transmission method for a storage device, comprising at least the following steps:

[0024] Determine whether the host controller supports encryption operations;

[0025] When the host controller supports encryption operation, enabling encryption operation on the storage device;

[0026] Configuring hardware registers in the storage device;

[0027] When transmitting each plaintext data, generating the target key matrix and the target decryption matrix according to any one of the above data encryption methods, and storing the target key matrix and the target decryption matrix in the hardware register; and

[0028] Plaintext data is encrypted using the target key matrix, and the encrypted data is decrypted using the target decryption matrix.

[0029] The present invention further provides an electronic device, and the electronic device includes:

[0030] a memory storing program instructions; and

[0031] The processor runs the program instructions to implement the data encryption method of the storage device as described in any one of the above items.

[0032] In summary, the present invention provides a data encryption method, data transmission method, and electronic device for a storage device. During the process of obtaining the target key matrix, since the swap array and the doubling array are both true random numbers rather than pseudo-random numbers, the key matrix formed by the UFS undergoes a transformation, and the transformation is irregular, during each read and write data transmission. This prevents an attacker from simultaneously obtaining multiple plaintext matrices and ciphertext matrices and cracking the key matrix using a method that solves a system of threaded equations. The target key matrix formed by this method ensures data security. The process of forming the target key matrix is ​​equivalent to first swapping the element matrix and then performing a doubling row transformation. The combination of these two elementary row transformations ensures that the encrypted ciphertext matrix is ​​completely uncorrelated with the plaintext matrix. Furthermore, these two elementary row transformations ensure that each element in the inverse matrix of the target key matrix (i.e., the target decryption matrix) is an integer, preventing decimals in the target decryption matrix, which could cause errors between the decrypted data and the original plaintext data and affect the accuracy of data transmission. Because each row of the intermediate key matrix undergoes a doubling-row transformation, each row of the target key matrix contains non-zero elements in addition to the one zero element and multiple zero elements in the identity matrix. This ensures that each element in the plaintext matrix is ​​encrypted, thus ensuring the integrity of the encryption process. Furthermore, because each row of elements undergoes only one doubling-row transformation, each row of the target key matrix contains only two non-zero elements, resulting in as many zero elements as possible in the target key matrix, reducing the computational complexity during the data encryption and decryption processes. Therefore, through the data encryption method and data transmission method provided by this application, when the UFS performs operations such as reading and writing that require data transmission, a key matrix is ​​dynamically generated for each transaction. Different transactions have different key matrices, so even if the key is stolen, the data cannot be decrypted for new transactions. This ensures the security of the UFS during data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 It is a structural diagram of a storage device in one embodiment of the present application.

[0035] Figure 2 This is a flowchart of a data encryption method for a storage device in one embodiment of the present application.

[0036] Figure 3 yes Figure 2The flowchart of the method for obtaining the target key matrix in the test method flow shown is shown.

[0037] Figure 4 This is a flowchart of a data transmission method of a storage device in one embodiment of the present application.

[0038] Figure 5 It is a structural diagram of an electronic device in one embodiment of the application. DETAILED DESCRIPTION

[0039] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The accompanying drawings illustrate preferred embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the disclosure of the present application.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0041] In the description of the present invention, it should be understood that the orientations or positional relationships indicated by terms such as "center," "up," "down," "front," "back," "left," and "right" are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention. The degrees indicated by terms such as "high" and "low" are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or components referred to must have high or low, and therefore should not be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance.

[0042] See also Figure 1As shown, the storage device provided in this application is, for example, universal flash storage. The universal flash storage includes a central processing unit (CPU) 101, static random-access memory (SRAM) 102, a universal flash storage interface 103, a flash controller 104, and a flash block 105. The CPU 101 is responsible for executing host program instructions and processing data, and communicating with other components in the system through various interfaces. The SRAM 102 typically serves as a first- or second-level cache for the CPU 101, providing fast data access for the CPU 101 and improving overall system performance. The universal flash storage interface 103 connects the host and the storage device, allowing data to be transferred between the host and the storage device, supporting full-duplex communication, i.e., simultaneous read and write operations. The flash controller 104 manages the flash block 105 and processes data read and write requests from the CPU 101. The flash controller 104 controls data flow to ensure that data is correctly stored in or read from the flash block 105. The flash memory block 105 is a non-volatile storage medium that can retain data even in the event of a power outage.

[0043] See also Figure 2 As shown, the present invention provides a data encryption method for a storage device, which is applicable to the encryption process of data transmission between a universal flash memory storage and a host. Specifically, each time when plaintext data is transmitted, the data encryption method for the storage device includes steps S101 to S104.

[0044] Step S101: Determine the number of rows and columns of a key matrix according to the specifications of the hardware registers in the storage device for storing keys, and use the identity matrix with the determined number of rows and columns as the initial key matrix.

[0045] Step S102: Arrange multiple numbers in random order to form an interchange array, and use the numbers in the interchange array to define the column position of element one in the initial key matrix to form an intermediate key matrix.

[0046] Step S103: Perform a doubling elementary row transformation on each row of the intermediate key matrix to obtain a target key matrix, and obtain a target decryption matrix corresponding to the target key matrix.

[0047] Step S104: Use the target key matrix to encrypt the plaintext data to form a ciphertext matrix, and use the target decryption matrix to decrypt the ciphertext matrix.

[0048] See also Figure 2As shown, in one embodiment of the present invention, in step S101, in determining the number of rows and columns of the key matrix based on the specifications of the hardware registers within the storage device for storing the key, the hardware registers are hardware registers storing the target key matrix and the target decryption matrix. In this embodiment, the hardware registers storing the target key matrix and the target decryption matrix are hardware registers within the UFSHCI, namely the x-CRYPTOCFG-Crypto Configuration X register. Bits 511:000 of the x-CRYPTOCFG-Crypto Configuration X register store the key. Therefore, the key storage specification is such that it can store a maximum of 512 bits of data. Therefore, the maximum data size of each key matrix is ​​512 bits, or 64 bytes. Since each element in the key matrix is ​​1 byte, the key matrix is ​​an 8×8 matrix. Therefore, in this embodiment, the number of rows and columns of the key matrix is ​​both 8. In other embodiments, when the specifications of the hardware registers storing the target key matrix and the target decryption matrix are limited, the number of rows and columns of the key matrix is ​​also limited accordingly.

[0049] See also Figure 2 As shown, in one embodiment of the present invention, after the number of rows and columns of the key matrix is ​​determined, the identity matrix with the determined number of rows and columns is used as the initial key matrix. In this embodiment, the initial key matrix is ​​an 8×8 identity matrix.

[0050] See also Figure 2 As shown, in one embodiment of the present invention, in step S102, it is necessary to first determine the number and range of elements in the swap array. The number of elements in the swap array is equal to the number of rows in the key matrix, and the elements in the swap array are natural numbers ranging from 1 to the number of columns. In this embodiment, the swap array has 8 elements, and they are natural numbers ranging from 1 to 8. That is, the elements in the swap array are 1, 2, 3, 4, 5, 6, 7, and 8.

[0051] See also Figure 2 As shown, in one embodiment of the present invention, in step S102, after determining the number and range of elements in the swap array, multiple elements in the swap array are randomly arranged to form a swap array. In this embodiment, the srand(time(0)) function can be used to arrange multiple elements. Specifically, the current system time can be used to randomly generate a seed reference value, and then rand() can be used to generate a random number to generate the swap array. In this embodiment, the randomly generated swap element group S is, for example, S=[3 5 6 7 1 2 8 4]. In other embodiments, the elements in the swap element group can be arranged in any order.

[0052] See also Figure 2As shown, in one embodiment of the present invention, in step S102, when using elements in the swap array to define the column position of element one in the initial key matrix, each element in the swap array is used to define the column position of element one in each row of the initial key matrix in the numerical order, thereby obtaining an intermediate key matrix. In this embodiment, when the swap element group is S = [3 5 6 7 1 2 8 4], element one in the first row of the initial key matrix is ​​defined as the third column, element one in the second row of the initial key matrix is ​​defined as the fifth column, element one in the third row of the initial key matrix is ​​defined as the sixth column, element one in the fourth row of the initial key matrix is ​​defined as the seventh column, element one in the fifth row of the initial key matrix is ​​defined as the first column, element one in the sixth row of the initial key matrix is ​​defined as the second column, element one in the seventh row of the initial key matrix is ​​defined as the eighth column, and element one in the eighth row of the initial key matrix is ​​defined as the fourth column. At this time, the intermediate key matrix obtained is shown in the following formula:

[0053] ;

[0054] Wherein, K0 is the intermediate key matrix, and the unfilled elements in the intermediate key matrix K0 are all 0.

[0055] See also Figure 2 As shown, in one embodiment of the present invention, the intermediate key matrix is ​​equivalent to the identity matrix obtained by multiple row swaps (or column swaps), so the intermediate key matrix can be expressed by the following formula:

[0056] K0=E 13 E 16 E 12 E 15 E 47 E 48 E;

[0057] Among them, E is the identity matrix; E ij The elementary matrix obtained by swapping the i-th row and the j-th row (or the i-th column and the j-th column) of the identity matrix is ​​called the swap elementary matrix. ij Indicates that the matrix is ​​transformed into a corresponding elementary row and multiplied by E on the right. ij = represents a corresponding elementary column transformation. The intermediate key matrix K0 is obtained by sequentially swapping the fourth and eighth rows of the identity matrix, the fourth and seventh rows, the first and fifth rows, the first and second rows, the first and sixth rows, and the first and third rows.

[0058] See also Figure 2As shown, in one embodiment of the present invention, after obtaining the intermediate key matrix, it is also necessary to obtain the intermediate decryption matrix corresponding to the intermediate key matrix. The decryption matrix is ​​the inverse matrix of the key matrix. In this embodiment, since the intermediate key matrix is ​​an elementary matrix obtained by permuting rows of the identity matrix, the intermediate key matrix is ​​an orthogonal matrix, and the following formula holds:

[0059] K0K0 T =E;

[0060] Therefore, K0 -1 =K0 T .

[0061] Among them, K0 -1 is the inverse matrix of the intermediate key matrix K0, which is the intermediate decryption matrix. T is the transposed matrix of the intermediate key matrix K0. In this application, the intermediate decryption matrix is ​​the transposed matrix of the intermediate key matrix K0.

[0062] See also Figure 2 As shown, in one embodiment of the present invention, after obtaining the intermediate key matrix and the intermediate decryption matrix, step S103 is executed to perform a doubling elementary row transformation on each row of the intermediate key matrix to obtain a target key matrix and a target decryption matrix corresponding to the target key matrix. The doubling elementary row transformation involves multiplying the elements of a row of the intermediate key matrix by a natural number and then adding the multiplied number to the doubling row elements. The target key matrix obtained by performing the doubling elementary row transformation on each row of the intermediate key matrix ensures that, in addition to the single element and multiple zero elements in the identity matrix, the doubling rows also contain other non-zero elements.

[0063] See also Figures 2 to 3 As shown, in one embodiment of the present invention, performing a doubling elementary row transformation on each row of the intermediate key matrix to obtain the target key matrix includes steps S1031 to S1033.

[0064] Step S1031: randomly generate a doubling array.

[0065] In one embodiment of the present invention, when generating a doubling array, the value range of the elements in the doubling array is first limited, and a plurality of numbers are randomly selected within the limited value range to form a doubling array. The number of elements in the doubling array is equal to the number of rows of the intermediate key matrix, and each element in the doubling array may be equal or unequal. In this embodiment, each element in the doubling array is set to be unequal. Specifically, the value range of the numbers in the doubling array is set to a random integer between 2 and 100, for example, and then the srand(time(0)) function is used to randomly select, for example, 8 numbers within the value range to form a doubling array. The generated doubling array M is, for example, M=[3 9 2 7 11 4 17 13].

[0066] Step S1032: Use each element in the doubling array to gradually perform doubling elementary row transformation on each row of the intermediate key matrix to obtain the target key matrix.

[0067] In one embodiment of the present invention, after generating a multiplication array, elements in the multiplication array are used as multipliers to progressively multiply elements in a row of the intermediate key matrix by an element in the multiplication array. The multiplication result is then added to elements in another row (the multiplication row) of the intermediate key matrix. During the process of performing the multiplication elementary row transformation on each element in the multiplication array for each row of the intermediate key matrix, elements in the multiplication array, the rows of the intermediate key matrix multiplied by the elements in the multiplication array, and the multiplication row elements are not repeated. In one specific embodiment, the target key matrix K1 is obtained, for example, using the following formula:

[0068] K1=E 81 (13)E 12 (17)E 23 (4)E 34 (11)E 45 (7)E 56 (2)E 67 (9)E 78 (3)K0;

[0069] Among them, Eij(k) represents the elementary matrix obtained by adding k times the i-th row of the identity matrix to the j-th row (or k times the j-th column to the i-th column), which is called the doubled elementary matrix. And any matrix multiplied by Eij(k) on the left represents a corresponding elementary row transformation on the matrix, and any matrix multiplied by Eij(k) on the right represents a corresponding elementary column transformation. Then the target key matrix K1 is obtained by sequentially adding three times the seventh row element of the intermediate key matrix K0 to the eighth row, nine times the sixth row element to the seventh row, two times the fifth row element to the sixth row, seven times the fourth row element to the fifth row, eleven times the third row element to the fourth row, four times the second row element to the third row, seventeen times the first row element to the second row, and thirteen times the eighth row element to the first row. Then the target key matrix K1 obtained is:

[0070] ;

[0071] In this case, each row of the target key matrix contains non-zero elements in addition to 1 and 0. This prevents a row or column in the target key matrix from having only one 1 and all other zeros. When a row or column in the target key matrix contains only one 1 and zeros, encrypting the plaintext matrix is ​​equivalent to directly copying the plaintext matrix onto the ciphertext without performing any encryption, resulting in poor overall encryption.

[0072] Step S1033: limit the value range of the target key matrix.

[0073] In one embodiment of the present invention, when UFSHCI operates a read or write transaction, it encapsulates a UTP transfer request descriptor (UTP Transfer Request Descriptor, UTRD). UTRD describes the command to be executed and the data associated with it. The host software sends the command to the host controller by placing the UTRD in a list, and then notifies the host Controllerdoorbell to view the list. The commands dispatched for execution in sequence by UFSHCI are placed in the list, even if they may be completed out of order. The host controller manages all data transfer operations related to the command on behalf of the host. For commands to be updated in the list, a command completion interrupt or UTRD status field will be caused. While the command is running, the UFS software may add commands to the list.

[0074] In one embodiment of the present invention, a UTP Command Descriptor (UCD) is embedded within the UTRD. The UCD points to a Physical Region Description Table (PRDT), which contains the data address and byte count of the outbound UPIU and the inbound UPIU. According to the design of the PRDT, the unit of data transmission is byte, so each element in the matrix is ​​designed to be in byte units, and the size of each element ranges from 0 to 255. After obtaining the target key matrix, the value of each element in the target key matrix needs to be limited to between 0 and 255. In this embodiment, to ensure that the value of each element in the target key matrix is ​​limited to between 0 and 255, a remainder operation is performed on each element in the target key matrix, and the divisor is 256, that is, a mod256 operation.

[0075] In one embodiment of the present invention, the target key matrix K1 after limiting the range is obtained by the following formula:

[0076] K1=E 81 (13)E 12 (17)E 23 (4)E 34 (11)E 45 (7)E 56 (2)E 67 (9)E 78 (3)K0mod256;

[0077] See also Figure 1 As shown, in one embodiment of the present invention, in step S103, after obtaining the target key matrix, it is also necessary to obtain the target decryption matrix corresponding to the target key matrix. The target decryption matrix is ​​the inverse matrix of the target key matrix. In this embodiment, the target decryption matrix is ​​obtained by the following formula:

[0078] K1 -1 =K0 T E 78 (-3)E 67 (-9)E 56 (-2)E 45 (-7)E 34 (-11)E 23 (-4)E 12 (-17)E 81 (-13) mod256.

[0079] See also Figure 2As shown, in one embodiment of the present invention, in step S104, when the target key matrix is ​​used to encrypt the plaintext data to form a ciphertext matrix, the plaintext data is first split into multiple plaintext matrices, and then the target key matrix is ​​used to encrypt the plaintext matrix to form a ciphertext matrix. Specifically, the data structure of the physical region description table (Data structure for Physical Region Description Table) used in the UFS3.1 protocol is defined (4DW format), where the data byte count (Data Byte Count) of DW3 indicates that the data size to be transmitted in a transaction must be consistent with the UTRD descriptor. According to the definition of the Common Data Size (CDS) in bit 15:08 of DW2 in the UTRD descriptor, the maximum data size transmitted in a read and write transaction is 256KB. When the plaintext data size is not a multiple of 64, a random number can be used to padded so that the data size is a multiple of 64 bytes. The number of plaintext data after being cut into plaintext matrices can be obtained by the following formula:

[0080] 256KB / 8byte=256KB×1024byte / 8byte=32768;

[0081] That is, a 256KB plaintext data can be cut into 32768 plaintext matrices.

[0082] Afterwards, the ciphertext matrix C is obtained by the following formula:

[0083] C=K1P mod256;

[0084] Among them, K1 is the target key matrix after the limit, P is the plaintext matrix, and after the final target key matrix is ​​multiplied by the plaintext matrix, the remainder operation can be performed on the product of the target key matrix and the plaintext matrix, and the divisor is 256, that is, the mod256 operation.

[0085] Among them, each element in the ciphertext matrix C is obtained by the following formula:

[0086] ;

[0087] in, represents the element in row i and column j in the ciphertext matrix C, represents the i-th row element in the target key matrix K1, represents the element in the jth column of the plaintext matrix P, and l is a variable ranging from 0 to n. In this embodiment, the number of columns in the target key matrix K1 is equal to the number of rows in the plaintext matrix P, that is, n.

[0088] After receiving the ciphertext matrix on the host side, it can decrypt the ciphertext matrix according to the target decryption matrix to obtain the plaintext matrix.

[0089] P=K -1 C mod256;

[0090] ;

[0091] Among them, p ij represents the element in row i and column j in the plaintext matrix P, Represents the target decryption matrix The element of the i-th row, Represents the element of the jth column of the ciphertext matrix C, l is a variable ranging from 0 to n. In this embodiment, the target decryption matrix The number of columns is equal to the number of rows of the ciphertext matrix C, which is n.

[0092] See also Figures 2 to 3 As shown, in this application, in the process of obtaining the target key matrix, since the interchange array and the doubling array are both true random numbers rather than pseudo-random numbers, the key matrix formed by the UFS is transformed during each read and write data transmission, and the transformation is irregular. At this time, it can prevent the attacker from obtaining multiple plaintext matrices and ciphertext matrices at the same time and using the method of solving the threaded equation system to crack the key matrix. The target key matrix formed by this method can ensure the security of the data.

[0093] See also Figures 2 to 3 As shown, in this application, the process of forming the target key matrix is ​​equivalent to first interchanging the element matrix and then performing a doubling row transformation. The combination of these two elementary row transformations ensures that the encrypted ciphertext matrix is ​​completely uncorrelated with the plaintext matrix. Furthermore, these two elementary row transformations ensure that every element in the inverse matrix of the target key matrix (i.e., the target decryption matrix) is an integer, preventing decimals in the target decryption matrix, which could cause errors between the decrypted data and the original plaintext data, affecting the accuracy of data transmission.

[0094] See also Figures 2 to 3 As shown, in this application, since each row of the intermediate key matrix undergoes a doubling-row transformation, each row of the target key matrix contains non-zero elements in addition to the one 1 element and multiple zero elements in the identity matrix. This ensures that every element in the plaintext matrix is ​​encrypted, thus ensuring the integrity of the encryption process. Furthermore, since each row of elements undergoes only a single doubling-row transformation, each row of the target key matrix contains only two non-zero elements, resulting in as many zero elements as possible in the target key matrix, reducing the computational complexity during the data encryption and decryption processes.

[0095] See also Figure 4 As shown, the present invention also provides a data transmission method for a storage device, which specifically includes steps S201 to S206.

[0096] Step S201: determine whether the host controller supports encryption operations. If the host controller supports encryption operations, execute step S202. If the host controller does not support encryption operations, end the process.

[0097] Specifically, you can query whether the host controller supports encryption operations by reading the Crypto Support (CS) bit in the CAP-Controller Capabilities hardware register. The encryption support bit is, for example, bit 28. If bit 28 of the CAP-Controller Capabilities hardware register is 1, it indicates that the host controller supports encryption operations. If bit 28 of the CAP-Controller Capabilities hardware register is 0, it indicates that the host controller does not support encryption operations.

[0098] Step S202: Enable encryption operation on the storage device.

[0099] Specifically, for a transaction with UTRD.CE = 1, enabling encryption operation means setting UTRD.CE of the transaction to be encrypted to 1. In this embodiment, encryption operation can be enabled by setting bit 01 of the HCE-Host Controller Enable hardware register to 1.

[0100] Step S203: Configure the hardware registers in the storage device.

[0101] Specifically, the x-CRYPTOCAP-Crypto Capability X register can be configured to the supported data unit size bitmask (SDUSB), which describes the data unit size supported by this capability, encoded as a bitmask. The algorithm ID (ALGID) can be set to a value between 80h and FFh to form the encryption method identifier. Specifically, the algorithm ID can be 80h, for example.

[0102] Step S204: When transmitting each piece of plaintext data, generate a target key matrix and a target decryption matrix.

[0103] Specifically, when each piece of plaintext data is transmitted, the target key matrix and the target decryption matrix are generated using the method of steps S101 to S104 .

[0104] Step S205: Store the target key matrix and the target decryption matrix in a hardware register.

[0105] Specifically, first, the target key matrix and target decryption matrix are populated into the CRYPTOKEY[511:0] position of the x-CRYPTOCFG–CryptoConfiguration X register. Secondly, the target key matrix is ​​essentially an 8×8 matrix. Setting the Configuration Enable (CFGE) bit to 1 enables the host software to use the encryption configuration. Finally, the correspondence between the encryption configuration and the plaintext data is established by setting UTRD.CCI = x. The Crypto Configuration Index (CCI) field in the UTP Transfer Request Descriptor is the coefficient x of the current encryption configuration in the array. The Crypto Capability Index (CAPIDX) indicates the cryptographic capability coefficient used by the encryption configuration. Valid values ​​for the cryptographic capability coefficient range from 0 to 127. If CAPIDX = x, the corresponding x-CRYPTOCAP–Crypto Capability X register can be found.

[0106] Step S206: Encrypt the plaintext data using the target key matrix, and decrypt the encrypted data using the target decryption matrix.

[0107] Specifically, as described in steps S101 to S104, each piece of plaintext data can be divided into a ciphertext matrix C, and each segment of the plaintext data can be divided into 64 bytes. When the size of the plaintext data is not a multiple of 64, random numbers can be used to padded it so that the data size is a multiple of 64 bytes.

[0108] See also Figure 5 As shown, an electronic device provided in an embodiment of the present application includes a processor 201, a memory 202, and a program stored in the memory and runnable on the processor, and the processor executes the data encryption method and data transmission method of the above-mentioned storage device.

[0109] See also Figure 5As shown, the memory 202 includes at least one type of readable storage medium, including a flash memory, a mobile hard disk, a multimedia card, a card-type memory (e.g., SD or DX memory), a magnetic memory, a magnetic disk, an optical disk, etc. In some embodiments, the memory can be an internal storage unit of the electronic device, such as a mobile hard disk of the electronic device. In other embodiments, the memory can also be an external storage device of the electronic device, such as a plug-in mobile hard disk, a smart memory card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the electronic device. Furthermore, the memory can also include both an internal storage unit of the electronic device and an external storage device. The memory can be used not only to store application software installed in the electronic device and various types of data, but also to temporarily store data that has been output or is about to be output.

[0110] See also Figure 5 As shown, in some embodiments, the processor 201 may be comprised of an integrated circuit, such as a single packaged integrated circuit or multiple packaged integrated circuits with the same or different functions, including a combination of one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and various control chips. The processor is the control core (Control Unit) of the vehicle-mounted device, connecting the various components of the vehicle-mounted device using various interfaces and circuits. It executes programs or modules stored in the memory and accesses data stored in the memory to perform various functions of the vehicle-mounted device and process data.

[0111] The processor executes the operating system of the vehicle-mounted device and various installed application programs. The processor executes the application programs to implement the steps in the above method embodiment.

[0112] Exemplarily, the program may be divided into one or more modules, which are stored in the memory and executed by the processor to implement the present invention. The one or more modules may be a series of program instruction segments capable of implementing specific functions, and the instruction segments are used to describe the execution process of the program in the processor.

[0113] The above-mentioned integrated unit implemented in the form of a software functional module can be stored in a computer-readable storage medium. The above-mentioned software functional module stored in a storage medium includes a number of instructions for causing a computer device (which can be a personal computer, computer equipment, or network equipment, etc.) or a processor to perform part of the functions of the data encryption method and data transmission method of various embodiments of the present invention.

[0114] In summary, a data encryption method, a data transmission method, and an electronic device for a storage device are provided. The data encryption method for the storage device includes determining the number of rows and columns of a key matrix based on the specifications of the hardware registers in the storage device for storing keys, and using a unit matrix with the determined number of rows and columns as an initial key matrix; arranging multiple numbers in random order to form an interchange array, and using the numbers in the interchange array to define the column position of element one in the initial key matrix to form an intermediate key matrix; performing a doubling elementary row transformation on each row of the intermediate key matrix to obtain a target key matrix, and obtaining a target decryption matrix corresponding to the target key matrix; and using the target key matrix to encrypt plaintext data to form a ciphertext matrix. The data encryption method for a storage device provided by the present invention can provide users with a simple and secure data encryption method.

[0115] The embodiments of the present invention disclosed above are intended only to illustrate the present invention. They do not describe all details in detail, nor do they limit the present invention to the specific embodiments described. Obviously, many modifications and variations are possible based on the content of this specification. These embodiments are selected and described in detail in this specification to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better understand and utilize the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A data encryption method for a storage device, characterized in that: At least the following steps are included: Determining the number of rows and columns of the key matrix according to the specifications of the hardware registers in the storage device for storing the key, and using the identity matrix with the determined number of rows and columns as the initial key matrix; Arrange a plurality of numbers in random order to form an interchange array, and use the elements in the interchange array to define the column position of element one in the initial key matrix to form an intermediate key matrix; Performing a doubling elementary row transformation on each row of the intermediate key matrix to obtain a target key matrix, and obtaining a target decryption matrix corresponding to the target key matrix; as well as The target key matrix is ​​used to encrypt the plaintext data to form a ciphertext matrix, and the target decryption matrix is ​​used to decrypt the ciphertext matrix.

2. The data encryption method for a storage device according to claim 1, wherein: When forming the interchange array, the number and range of elements in the interchange array are first determined; wherein the number of elements in the interchange array is equal to the number of rows of the key matrix, and the elements in the interchange array are natural numbers from 1 to the number of columns.

3. The data encryption method for a storage device according to claim 2, wherein: After determining the number and range of elements in the swap array, multiple elements in the swap array are arranged in random order to form the swap array.

4. The data encryption method for a storage device according to claim 1, wherein: When the column position of element one in the initial key matrix is ​​limited by the numbers in the interchange array, each element in the interchange array is used to limit the column position of element one in each row of the initial key matrix according to the arrangement order of the elements to obtain the intermediate key matrix.

5. The data encryption method for a storage device according to claim 1, wherein: After obtaining the intermediate key matrix, an intermediate decryption matrix corresponding to the intermediate key matrix is ​​obtained; and the intermediate decryption matrix is ​​a transposed matrix of the intermediate key matrix.

6. The data encryption method for a storage device according to claim 1, wherein: Obtaining the target key matrix includes the following steps: Randomly generate a doubling array; Performing a doubling elementary row transformation on each row of the intermediate key matrix using each element in the doubling array to obtain the target key matrix; and The value range of the target key matrix is ​​limited.

7. The data encryption method for a storage device according to claim 6, characterized in that: When generating the doubling array, the value range of the elements in the doubling array is first limited, and multiple elements are randomly selected within the limited value range to generate the doubling array; wherein the number of elements in the doubling array is equal to the number of rows of the intermediate key matrix.

8. The data encryption method for a storage device according to claim 6, characterized in that: When using each element in the doubling array to perform a doubling elementary row transformation on each row of the intermediate key matrix, using the elements in the doubling array as multiples, gradually multiplying the elements of a row of the intermediate key matrix with an element in the doubling array, and adding the multiplication result to another row of elements in the intermediate key matrix to form the target key matrix; and each row of elements in the formed target key matrix has two non-zero elements.

9. The data encryption method for a storage device according to claim 6, characterized in that: A modulo operation is performed on each element in the target key matrix to limit a value range of the target key matrix.

10. The data encryption method for a storage device according to claim 1, wherein: The target decryption matrix is ​​the inverse matrix of the target key matrix.

11. The data encryption method for a storage device according to claim 1, wherein: When the target key matrix is ​​used to encrypt plaintext data to form a ciphertext matrix, the plaintext data is first split into multiple plaintext matrices, and then the target key matrix is ​​used to encrypt the plaintext matrices to form the ciphertext matrix.

12. A data transmission method for a storage device, characterized in that: At least the following steps are included: Determine whether the host controller supports encryption operations; When the host controller supports encryption operation, enabling encryption operation on the storage device; Configuring hardware registers in the storage device; When transmitting each plaintext data, generating the target key matrix and the target decryption matrix according to the data encryption method according to any one of claims 1 to 11, and storing the target key matrix and the target decryption matrix in the hardware register; as well as Plaintext data is encrypted using the target key matrix, and the encrypted data is decrypted using the target decryption matrix.

13. An electronic device, characterized in that: The electronic device comprises: a memory storing program instructions; and A processor runs the program instructions to implement the data encryption method of the storage device according to any one of claims 1 to 11.

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