Stacked chip architecture modeling method and stacked chip architecture modeling system

Abstract

The invention provides a stacked chip architecture modeling method and a stacked chip architecture modeling system. The method comprises the following steps: dividing an on-chip chip to be modeled into a plurality of core particles; the method comprises the following steps of: modeling a chip by adopting a three-stage joint modeling mode, and respectively executing core size level modeling, medium level modeling and substrate level modeling; arranging the placement positions of the core particles according to the factors of the time sequence of the key path, the bus length and the super-long path; according to the connection relation between the interior and the exterior of the core particle, and according to the weights of the internal netlist and the external netlist of the core particle or user input information, optimizing the positions of the internal elements of the core particle, and adjusting the positions of the micro convex points mapped by the elements; and carrying out automatic wiring based on the arrangement position of each core particle, removing a network with conflicts in wiring, carrying out labyrinth wiring on an area in which wiring is removed, and searching an optimal wiring path. The system is used for implementing the method. The invention provides a one-stop chip design EDA tool, and the design precision of the chip can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of stacked chip production and manufacturing. Specifically, it is a method for modeling a stacked chip rack and a stacked chip rack modeling system for implementing this method. Background Art

[0002] With the development of chip technology, three-dimensional stacked chips have been widely used. During the design process of three-dimensional stacked chips, it is necessary to model the three-dimensional chips. Currently, the common modeling method is to use electronic design automation (EDA) tools for modeling. Existing EDA tools have problems such as technical closure and high licensing fees. In addition to the above two problems, the current EDA tools generally have the following problems: First, the modeling process is fragmented and lacks system-level integration. Most existing EDA tools focus on single-link operations, such as through-silicon via modeling, thermal analysis, or signal integrity simulation. There is a lack of full-process integration from architecture design, physical modeling to multi-physics field simulation, resulting in designers needing to splice data across platforms, leading to low design efficiency of stacked chips. Due to operations such as multiple data conversions, for example, when performing electrical-thermal-stress coupling analysis during the interposer design, multiple data conversions are often required, thus affecting the design accuracy of stacked chips.

[0003] Second, the customizability and adaptability are insufficient. Current EDA tools are difficult to adapt to the diverse process requirements of chip design and production manufacturers. For example, they cannot meet the requirements of heterogeneous chip integration and die self-defined interconnection. Existing modeling systems usually preset fixed parameter templates and have insufficient support for emerging materials (such as glass substrates) or special packaging structures (such as local shielding layers), restricting the flexibility of chip design.

[0004] Third, the resource consumption is large and the technical threshold is high. Since the modeling of stacked chips involves a large amount of mesh generation and multi-physics field solution calculations, existing EDA tools rely heavily on hardware resources (such as GPU acceleration and distributed computing). Production and design manufacturers need to configure computers with very high hardware resources to meet the usage requirements of existing EDA tools, restricting the popularization and application of EDA tools. Summary of the Invention

[0005] The first objective of the present invention is to provide a method for modeling a stacked chip rack that can avoid affecting the design accuracy due to the need to convert data back and forth during the design process.

[0006] The second objective of the present invention is to provide a stacked chip rack modeling system for implementing the above-mentioned method for modeling a stacked chip rack.

[0007] To achieve the first object of the present invention, the method for modeling a stacked chip rack provided by the present invention includes dividing the on-chip chips to be modeled into multiple dielets; modeling the chips in a three-level joint modeling manner: when modeling at the dielet level, modeling each divided bare die, and arranging the internal components of the dielet according to the connection relationship of the netlist; when modeling at the dielectric layer level, modeling the dielectric layer according to the factor of the free area and determining the size of the dielectric layer; when modeling at the substrate level, modeling the substrate according to the factor of the free area; arranging the placement positions of the dielets according to the timing of the critical path, the bus length, and the factor of the extremely long path; optimizing the positions of the internal components of the dielet according to the internal and external connection relationships of the dielet, and according to the weights of the internal netlist and the external netlist of the dielet or user input information, and adjusting the positions of the microbumps mapped by each component; automatically routing based on the arranged positions of the dielets, removing the networks with conflicts in the routing, performing maze routing on the area where the routing is removed, and finding the optimal routing path.

[0008] As can be seen from the above solution, the present invention provides a one-stop complete design solution for the design of stacked chips. From the chip division, dielet arrangement to automatic routing, it can all be realized within the same EDA tool, without the need for designers to switch back and forth between multiple different tools, avoiding the accuracy loss caused by time switching, thereby ensuring that the designed stacked chips have high accuracy.

[0009] In addition, the present invention models the chips in a three-level joint modeling manner, making the modeling efficiency of the chips higher. Designers can quickly complete steps such as arranging the internal components of the dielet, determining the size of the dielectric layer, and completing the substrate modeling.

[0010] A preferred solution is that during the process of modeling the chips in a three-level joint modeling manner, when modeling at the dielectric layer level or the substrate level, if it is confirmed that the arrangement of the internal components of each dielet is unreasonable during the dielet level modeling, then re-execute the steps of the dielet level modeling, and re-execute the dielectric layer level modeling and the substrate level modeling based on the results of the re-executed dielet level modeling.

[0011] Thus, it can be seen that an iterative method is adopted during the three-level joint modeling process. Once it is found that the completed dielet plan is unreasonable, a new round of iterative calculation will be performed according to the new parameters, thereby optimizing the modeling effect.

[0012] A further solution is that arranging the internal components of the dielet according to the connection relationship of the netlist includes: initially arranging the IP circuits and instances inside the dielet according to the connection relationship of the netlist, and then planning the positions of the microbumps of the chip.

[0013] It can be seen that the IP circuit and the example inside the core particle are preliminarily arranged, and the present invention also plans the positions of the micro-bumps of the chip, so as to reasonably plan the positions of each micro-bump.

[0014] A further solution is to divide the on-chip chip to be modeled into multiple core particles, including: constructing a hypergraph of the core particles, with the vertices of the hypergraph representing the core particle component modules, and the edges of the hypergraph representing the connections of signal lines or pins; when constructing the hypergraph, the weights of the vertices and edges of the hypergraph are configured according to the acquired demand information.

[0015] It can be seen that when constructing a hypergraph, the present invention can obtain information input by designers to configure the weights of vertices and hyperedges in the hypergraph, realize the combination of manual intervention and algorithm automation, and realize multi-dimensional segmentation of stacked chips.

[0016] A further solution is to arrange the placement of each core particle and then perform the following: joint simulation to perform thermal analysis on the chip, and optimize the placement of the chip based on the evaluation results, and add redundant micro-bumps.

[0017] It can be seen that in the design process of stacked chips, EDA tools can perform thermal analysis on the current chip structure and integrate simulation analysis functions into the design steps, thereby avoiding the situation where chip design and chip simulation analysis are operated separately from each other, and further avoiding the loss of design accuracy due to data format conversion.

[0018] A further solution is that when automatic wiring is performed based on the arrangement positions of each core particle, electromagnetic simulation and thermal simulation of the chip are also performed. If the simulation results do not meet the preset requirements, the wiring is removed and re-wired.

[0019] It can be seen that EDA tools can perform electromagnetic simulation, thermal simulation and other operations after the preliminary design of the chip is completed, and once the simulation effect is found to be poor, the wiring can be removed and rewired in time, thereby completing the chip design and simulation operations within a set of EDA tools, and the wiring can be adjusted quickly.

[0020] A further solution is to perform power consumption simulation analysis to estimate the power distribution of each chip after automatic routing based on the arrangement position of each chip.

[0021] It can be seen that after the chip design is completed, the EDA tool can quickly implement power simulation analysis, and then estimate the power distribution of each chip, providing a basis for the optimized design of the chip.

[0022] A further solution is to perform real-time cost calculation in the core particle division stage, core particle modeling stage and wiring stage to calculate the chip manufacturing cost, packaging cost and testing cost.

[0023] Since the manufacturing cost, packaging cost, and testing cost can be calculated at each stage of chip design, designers can estimate the cost of the chip at each design stage, thereby providing basic data for the optimized design of the chip.

[0024] To achieve the above second objective, the stacked chip rack construction modeling system provided by the present invention includes a die partitioning module, a modeling module, a chip layout planning module, a layout implementation module, and an automatic routing module. Among them, the die partitioning module is used to partition the on-chip chip to be modeled into multiple dies; the modeling module uses a three-level joint modeling method to model the chip: when modeling at the die level, each segmented bare die is modeled, and the internal components of the die are placed according to the connection relationship of the netlist; when modeling at the dielectric layer level, the dielectric layer is modeled according to the factor of the free area, and the size of the dielectric layer is determined; when modeling at the substrate level, the substrate is modeled according to the factor of the free area; the chip layout planning module is used to arrange the placement positions of the dies according to the factors of the timing of the critical path, the bus length, and the very long path; the layout implementation module is used to optimize the positions of the internal components of the die according to the internal and external connection relationships of the die, and according to the weights of the internal netlist and the external netlist of the die or user input information, and adjust the positions of the microbumps mapped by each component; the automatic routing module is used to perform automatic routing based on the arranged positions of the dies, remove the networks with conflicts in the routing, perform maze routing on the area where the routing is removed, and find the optimal routing path.

[0025] A preferred solution is that the system is also provided with a multi-physical field simulator for performing thermal simulation and electromagnetic simulation on the chip.

[0026] It can be seen that by integrating a multi-physical field simulator, the present invention can perform simulation analyses such as electromagnetic analysis and thermal analysis on the chip during the chip design process, which is convenient for designers to optimize the design of the chip according to the results of the simulation analysis. Description of the Drawings

[0027] Figure 1 is a structural block diagram of an embodiment of the stacked chip rack construction modeling system of the present invention.

[0028] Figure 2 is a flowchart of an embodiment of the stacked chip rack construction modeling method of the present invention.

[0029] Figure 3 is an interface diagram when partitioning the chip in an embodiment of the stacked chip rack construction modeling method of the present invention.

[0030] Figure 4 is an interface diagram when routing the chip in an embodiment of the stacked chip rack construction modeling method of the present invention.

[0031] Figure 5It is the interface diagram of the entire chip cost analysis tree diagram when performing cost analysis on the chip in the embodiment of the stacked chip rack construction modeling method of the present invention.

[0032] Figure 6 It is the interface diagram of the pie chart of the cost analysis of a single die when performing cost analysis on the chip in the embodiment of the stacked chip rack construction modeling method of the present invention.

[0033] The present invention will be further described below in conjunction with the accompanying drawings and embodiments. Specific Embodiments

[0034] The stacked chip rack construction modeling system of the present invention is used to model stacked chips and provide a one-stop design solution. From the partitioning of dielets, chip layout to automatic routing, all can be realized in a set of EDA tools. Moreover, the stacked chip rack construction modeling system can also perform electromagnetic analysis, thermal analysis, etc. on the designed chips, avoiding the need for designers to continuously perform simulation analysis during the chip design process, which leads to data transmission between multiple different software, and in order to meet the format problems between different software, it is necessary to convert the involved data formats. Since once the format conversion is performed, it is easy to cause loss of the accuracy of the design data, resulting in insufficient accuracy of the designed chips. The stacked chip rack construction modeling method of the present invention is applied to the above-mentioned stacked chip rack construction modeling system.

[0035] Embodiment of the stacked chip rack construction modeling system: Refer to Figure 1 , the stacked chip rack construction modeling system 10 of this embodiment is implemented on a set of EDA tools, so that it is convenient for users to complete the design and testing of stacked chips only relying on a set of EDA tools. In particular, it can realize operations such as dielet partitioning and wiring of stacked chips, and can also perform electromagnetic simulation, thermal simulation, etc. through a simulator, avoiding designers from switching back and forth between multiple tools during the design process and avoiding loss of design accuracy due to data format conversion.

[0036] This embodiment has a dielet partitioning module 11, a modeling module 12, a chip layout planning module 13, a layout implementation module 14, an automatic routing module 15, a multi-physics field simulator 16, and a cost optimization control module 17.

[0037] Among them, the dielet partitioning module 11 is used to partition the on-chip chips to be modeled into multiple dielets. For example, the stacked chips to be modeled are partitioned into multiple dielets by establishing a hypergraph and combining manual and algorithmic automation methods.

[0038] The modeling module 12 models the chip in a three - level joint modeling manner, namely die - level modeling, interposer - level modeling, and substrate - level modeling. When performing die - level modeling, each divided die is modeled, and the internal components of the die are placed according to the connection relationship of the netlist. When performing interposer - level modeling, the interposer layer is modeled according to the factors of the free area, and the size of the interposer layer is determined. When performing substrate - level modeling, the substrate is modeled according to the factors of the free area.

[0039] The chip layout planning module 13 is used to arrange the placement positions of each die according to multiple factors such as the timing of the critical path, bus length, and very long path, so as to complete the preliminary layout design of the chip.

[0040] The layout implementation module 14 is used to optimize the positions of the internal components of the die according to the internal and external connection relationships of the die, and according to the weights of the internal netlist and external netlist of the die or user input information. Moreover, the layout implementation module 14 is also used to adjust the positions of the micro - bumps mapped by each component.

[0041] The automatic routing module 15 is used to perform automatic routing based on the arranged positions of each die, including global routing and detailed routing. In the global routing stage, the automatic routing module 15 first obtains a global routing solution based on the pattern routing algorithm, then removes the conflicting networks, and then re - performs a maze routing on the removed networks to find the optimal path and output the routing guide. In the detailed routing stage, the optimal routing solution is found from the maze routing according to the routing guide output by the global routing.

[0042] The multi - physical - field simulator 16 integrates multiple simulators, such as an electromagnetic simulator, a thermal simulator, a power simulator, etc., so as to facilitate designers to perform electromagnetic simulation, thermal simulation, power simulation, etc. on the chip during the chip design process.

[0043] The cost optimization control module 17 is used to calculate the cost metrics in real - time at each stage of chip design, identify the key cost factors through sensitivity analysis, automatically adjust the design parameters to converge the cost within the target range, and generate a detailed cost breakdown report, so that designers can clearly know the manufacturing cost, packaging cost, testing cost, etc. of the chip at each design stage of the chip.

[0044] Embodiment of the modeling method for stacked chip racks: The modeling method for stacked chip racks in this embodiment can run on a computer device, specifically, it can be implemented through EDA tools. The following combines Figure 2 to introduce each step of the modeling method for stacked chip racks.

[0045] First, perform step S1 to divide the on-chip chip to be modeled into multiple dielets, that is, perform the operations in the dielet division stage. Specifically, a large on-chip chip (SoC) is segmented to form multiple small dielets. This process can be implemented using the Partition algorithm based on hmetis of existing open-source tools. When implementing, the software constructs the input hypergraph, and hmetis performs the division. During the process of constructing the hypergraph, the vertices of the hypergraph represent component modules, and the edges (hyperedges) of the hypergraph represent signal lines or pin connections, thus forming a multi-module network. In addition, when constructing the hypergraph, the weights of the vertices and hyperedges of the hypergraph can be configured according to requirements to control the division result. When configuring the weights of the vertices of the hypergraph, the area factor of the component modules needs to be considered, while when configuring the weights of the hyperedges, factors such as the timing of the netlist and the number of ports of the netlist are considered.

[0046] In addition, when constructing the hypergraph, designers are also allowed to perform pre-allocation. For example, designers can specify the division attribution of some circuit modules and let the EDA tool complete the allocation of the remaining components. Therefore, when the dielet division module divides the dielets, it can combine manual intervention and algorithm automation to achieve multi-dimensional division of the chip. The operation interface of the dielet division stage is as Figure 3 shown.

[0047] Then, perform step S2 to model the chip in a three-level joint modeling manner, that is, model the dielet, dielectric layer, and substrate simultaneously. When modeling at the dielet level, each segmented bare die is modeled, and the internal components of the dielet are placed according to the connection relationship of the netlist. Specifically, each segmented bare die is independently parameterized and modeled to determine the shape and size of each dielet, and then the internal components of the dielet are initially placed according to the connection relationship of the netlist, including initially placing the IP and instances inside the dielet, so as to further plan the positions of the micro-bumps (u-bumps) of the dielet.

[0048] When modeling at the dielectric layer level, the dielectric layer is modeled according to the factor of the free area and the size of the dielectric layer is determined. Specifically, after initially placing the modeled dielets through connection relationships, wire lengths, and thermal effects, etc., the dielectric layer is modeled according to the free area to determine the shape and size of the dielectric layer. When modeling at the substrate level, the substrate is modeled according to the factor of the free area. Specifically, the substrate needs to be modeled according to the factor of the free area and the fan-out situation, etc.

[0049] In addition, the process of three-level joint modeling is iterative. That is to say, when modeling at the die level or the substrate level, if it is confirmed that the placement of the internal components of each die is unreasonable during die-level modeling, the steps of die-level modeling are re-executed, and the die-level modeling, substrate-level modeling are re-executed based on the results of the re-executed die-level modeling, so as to achieve iterative calculation. In this way, the model of the stacked chip obtained by modeling can be made more reasonable.

[0050] Next, step S3 is executed to arrange the placement positions of the dies according to the timing of the critical path, the bus length, and the factors of the ultra-long path, that is, the operations in the placement planning stage are performed. Specifically, when placing the dies, factors such as the timing of the critical path, the bus length, and the ultra-long path are considered simultaneously. For example, the dies with high-frequency interaction on the critical path need to be placed adjacent to each other, the timing-critical modules are preferably placed close to the clock source, dedicated wiring channels need to be reserved for the critical path across the die, the total length of the global signal lines should meet the bus length requirements of the process, and the appearance of ultra-long paths of the signal lines should be avoided during the arrangement. In addition, factors such as thermal management requirements and manufacturability requirements also need to be considered.

[0051] After the preliminary placement is completed, co-simulation is also performed to evaluate the hot spot area and optimize the placement result, and a certain number of redundant micro-bumps are added. Specifically for the micro-bumps in the hot spot area, more redundant micro-bumps will be allocated, which can play a role in shunting. The redundant micro-bumps can maintain the voltage stability of the power / ground network, reduce the voltage fluctuation, and ensure the power integrity. The redundant micro-bumps in the clock network can avoid the loss of the clock signal caused by a single-point failure, and can reduce the bit error rate for high-speed signal transmission; the redundant micro-bumps can also be used as design reserves. After the placement of the dies is completed, data indicators including the thermal map, wiring resource evaluation, and critical signal timing are provided for the designers to analyze, which are used to evaluate whether the current layout scheme is reasonable and also provide guiding opinions for the subsequent processes.

[0052] Then, step S4 is executed to optimize the positions of the internal components of the die according to the internal and external connection relationships of the die, and according to the weights of the internal netlist and external netlist of the die or user input information, and adjust the positions of the micro-bumps mapped by each component. Specifically, in the layout implementation stage, the internal and external connection relationships of the die are considered simultaneously, and the positions of the internal components of the die are optimized and adjusted through the default weights of the internal netlist and external netlist of the die or the information input by the involved personnel. At the same time, the positions of the micro-bumps mapped by these components are adjusted, so as to optimize the planning result of the entire die.

[0053] Finally, step S5 is executed to perform automatic routing based on the arrangement positions of the dielets, remove the networks with conflicts in the routing, perform maze routing on the area where the routing is removed, and find the optimal routing path, that is, perform the operations in the automatic routing stage. Specifically, the automatic routing module performs adaptive routing in a manner that combines global routing and detailed routing, adopting a routing framework of tearing and re-routing. In the global routing stage, first, a global routing solution is obtained based on the pattern routing algorithm, then the networks with conflicts are removed, and then based on the Dijkstra algorithm, a maze routing is performed again on the removed networks to find the optimal path and output the routing guide. In the detailed routing stage, in the routing guide output by the global routing, a maze routing based on the Dijkstra algorithm kernel is used to find the optimal routing solution. The interface diagram of using the EDA tool for routing is as Figure 4 shown.

[0054] For different types of networks, the routing order will be different. For example, power routing can be performed first, then the critical paths are processed, and then the remaining other routing operations are carried out. During the routing process, electromagnetic simulation and thermal simulation can be performed at any time, and then the routing is removed and re-routed according to the simulation results. The routing process is iterative and convergent, and continuously optimized. In this embodiment, the routing results of the global dielets, dielectric layers, and substrates will be considered simultaneously. For example, the routing in the substrate layer can be used to modify the routing in the dielectric layer in turn. Finally, the design files (.def) and layout files (.gds) corresponding to each dielet, dielectric layer, and substrate can be output for subsequent production and manufacturing processes.

[0055] It should be noted that the EDA tool integrates various analysis functions into a unified environment, can achieve signal integrity analysis, and automatically identify potential crosstalk and delay problems. For example, the EDA tool can perform power consumption analysis on the chip and accurately estimate the power consumption distribution of each dielet. For thermal analysis, the EDA tool can predict the system-level temperature field and identify hot spot areas. During cost analysis, it can track the material, manufacturing, and test costs in real time. In addition, various simulation tools can be called in real time during the modeling process, and the analysis results are intuitively displayed through the visualization interface, thus supporting design decisions and allowing designers to adjust and optimize the chip design according to the simulation results.

[0056] In addition, this embodiment also proposes a closed-loop cost optimization mechanism, and the iteration of the entire system will also be based on the premise of cost convergence. The EDA tool establishes a full-cost model including manufacturing, packaging, and testing, and performs real-time cost calculations at all stages of chip design, including the dielet partitioning stage, dielet modeling stage, and routing stage, calculates the manufacturing cost, packaging cost, and testing cost of the chip, identifies the key cost factors through sensitivity analysis, automatically adjusts the design parameters to make the cost converge within the target range, and generates a detailed cost breakdown report. For example, the tree diagram of cost analysis is as Figure 5As shown, the pie chart of the single die cost analysis is as Figure 6 shown.

[0057] Compared with traditional EDA tools, the present invention can realize the function of dividing the on-chip chip into multiple dies and modeling them, making the chip modeling more flexible. In addition, the present invention enables the linkage between chip design and simulation, and can output information such as the simulation results of electrothermal signals, thermograms, the timing of critical paths, and wiring resource evaluation after layout, and can also add redundant microbumps according to the hot spots.

[0058] In addition, after the chip layout planning, the present invention will also optimize and adjust the positions of the modules and microbumps inside the die. During the automatic wiring, it can support the co-routing of the die to the dielectric layer and the substrate. And during the die design process, a collaborative iteration method is used, that is, when it is found that the previous design link is unreasonable in the subsequent design link, the design of the previous link is adjusted, and the simulation tool can also be called during the design process to simulate the current design, and the current design is optimized and adjusted according to the simulation results. Finally, the present invention can estimate the cost in all links of the chip design, which is convenient for designers to optimize the design according to the estimated cost.

[0059] Finally, it should be emphasized that the above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for modeling a stacked chip rack, characterized in that include: Divide the chip on a chip to be modeled into multiple core particles; The chip is modeled by a three-level joint modeling method: when modeling at the core particle level, each split die is modeled, and the internal components of the core particles are placed according to the connection relationship of the netlist; When modeling at the medium level, the medium layer is modeled according to the factor of the idle area, and the size of the medium layer is determined; when modeling at the substrate level, the substrate is modeled according to the factor of the idle area; Arranging the placement of each of the core particles according to the timing of the critical path, the total length and the factors of the super-long path; According to the connection relationship between the inside and outside of the core particle, and according to the weight of the inner network table and the outer network table of the core particle or the user input information, the position of the internal component of the core particle is optimized, and the position of the micro-bump mapped by each component is adjusted; Automatic routing is performed based on the arrangement positions of the core particles, and conflicting networks in the routing are removed. Maze routing is performed on the area where the routing is removed, and an optimal routing path is found.

2. The stacked chip architecture modeling method according to claim 1, characterized in that: In the process of modeling the chip using the three-level joint modeling method, during medium level modeling or substrate level modeling, if it is confirmed that the placement of the internal components of each core particle is unreasonable during core particle level modeling, the core particle level modeling steps are re-executed, and the medium level modeling and substrate level modeling are re-executed based on the results of the re-executed core particle level modeling.

3. The stacked chip architecture modeling method according to claim 1, characterized in that: Placing the components inside the core particle according to the connection relationship of the netlist includes: preliminarily arranging the IP circuits and instances inside the core particle according to the connection relationship of the netlist, and then planning the positions of the micro-bumps of the chip.

4. The stacked chip architecture modeling method according to any one of claims 1 to 3, characterized in that: Dividing the chip to be modeled into a plurality of core particles includes: constructing a hypergraph of the core particles, wherein the vertices of the hypergraph represent the core particle component modules, and the edges of the hypergraph represent the connection lines of signal lines or pins; When constructing the hypergraph, the weights of the vertices and edges of the hypergraph are configured according to the acquired demand information.

5. The stacked chip architecture modeling method according to any one of claims 1 to 3, characterized in that: After arranging the placement positions of the core particles, the following steps are further performed: performing a joint simulation to perform a thermal analysis on the chip, and optimizing the placement positions of the chip according to the evaluation results, and adding redundant micro-bumps.

6. The stacked chip architecture modeling method according to any one of claims 1 to 3, characterized in that: When automatic wiring is performed based on the arrangement positions of the core particles, electromagnetic simulation and thermal simulation of the chip are also performed. If the simulation results do not meet the preset requirements, the operation of removing the wires and rewiring is performed.

7. The stacked chip architecture modeling method according to any one of claims 1 to 3, characterized in that: After automatic routing is performed based on the arrangement positions of the core particles, power consumption simulation analysis is performed to estimate the power distribution of the core particles.

8. The method for modeling a stacked chip rack according to any one of claims 1 to 3, characterized in that: Real-time cost calculation is performed during the die partitioning stage, die modeling stage, and wiring stage to calculate the manufacturing cost, packaging cost, and testing cost of the chip.

9. Stacked chip carrier modeling system, characterized in that, It includes: A die partitioning module for partitioning the on-chip chip to be modeled into multiple dies; A modeling module that models the chip in a three-level joint modeling manner: when modeling at the die level, each divided die is modeled, and the internal components of the die are placed according to the connection relationship of the netlist; When modeling at the dielectric layer level, the dielectric layer is modeled according to the factor of the free area, and the size of the dielectric layer is determined; when modeling at the substrate level, the substrate is modeled according to the factor of the free area; A chip layout planning module for arranging the placement positions of the dies according to the factors of the timing of the critical path, bus length, and ultra-long path; A layout implementation module for optimizing the positions of the internal components of the die according to the internal and external connection relationships of the die, and according to the weights of the internal netlist and external netlist of the die or user input information, and adjusting the positions of the microbumps mapped by the components; An automatic wiring module for automatically wiring based on the arranged positions of the dies, removing the networks with conflicts in the wiring, performing maze wiring on the area where the wiring is removed, and finding the optimal wiring path.

10. The stacked chip rack modeling system according to claim 9, characterized in that: The system is further provided with a multi-physics field simulator for performing thermal simulation and electromagnetic simulation on the chip.

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