Pixel and display device including same

Abstract

Disclosed are a pixel and a display device including the same. The pixel may include: a light emitting device; and a pixel circuit connected to the first to third gate control lines and the light emitting device, the pixel circuit including first to fourth nodes. The pixel circuit may include: a driving transistor connected to first to third nodes; a first transistor connected to the first gate control line and the first and second nodes; a second transistor connected to a second gate control line, a second node, and a first driving voltage line; a third transistor connected to the first gate control line, the third and fourth nodes; a fourth transistor connected to the first gate control line, a fourth node, and an initialization voltage line; a fifth transistor connected to the third gate control line, the third node, and the data line; and a storage capacitor disposed between the first and fourth nodes. Accordingly, by sharing gate control signals in adjacent horizontal rows, a narrow bezel may be achieved and power consumption may be reduced.

Description

[0001] This application is a divisional application of the invention patent application with the application date of August 1, 2022, application number 202210916943.3, and invention name "Pixel and Display Device Comprising the Pixel".

[0002] Cross - reference to related applications

[0003] This application claims the benefit of Korean Patent Application No. 10 - 2021 - 0101890, filed on August 3, 2021, which is incorporated herein by reference as if fully set forth herein. Technical field

[0004] The present disclosure relates to a pixel and a display device including the pixel. Background art

[0005] With the progress of information technology, the market for display devices as a connection medium between users and information is increasing. In addition to information transmission based on letters between users, various types of communications are also active. As the type of information changes, the performance of display devices for displaying information is improving. Therefore, the use of various types of display devices such as organic light - emitting display devices, liquid crystal display (LCD) devices, micro - light - emitting diode (LED) display devices, and quantum dot (QD) display devices is increasing.

[0006] In a light - emitting display device, pixels including light - emitting devices and driving transistors are arranged in a matrix type, and the brightness of an image displayed through the pixels is adjusted based on the gray level of image data. The driving transistor controls the driving current flowing in the light - emitting device based on the voltage applied between its gate electrode and source electrode. The amount of light emitted from the light - emitting device is determined based on the driving current, and the brightness of the image is determined based on the amount of light emitted from the light - emitting device.

[0007] For example, in a light - emitting display device, when a gate signal and a data signal are provided to a sub - pixel, the light - emitting device of the selected sub - pixel can emit light, and thus an image can be displayed. The light - emitting device can be implemented based on an organic material or an inorganic material.

[0008] The light - emitting display device displays an image based on the light emitted from the light - emitting devices of the sub - pixels, and thus has various advantages, but it is necessary to improve the accuracy of the pixel driving circuit for controlling the light emission of the sub - pixels, thereby improving the image quality. For example, the accuracy of the pixel driving circuit can be improved by compensating the threshold voltage of the driving transistor included in the pixel driving circuit.

[0009] In addition to a driving transistor and a switching transistor for providing a data voltage, the pixel driving circuit may further include a compensation circuit including a plurality of switching transistors and capacitors, and may provide a plurality of scan signals for driving the compensation circuit.

[0010] The above background is what the inventors of the present application have to derive the present disclosure, or the technical information obtained when deriving the present disclosure. The above background is not necessarily the known technology publicly available to the public before applying the present disclosure. SUMMARY OF THE INVENTION

[0011] As the resolution and power consumption of a light-emitting display device increase, a driving technology for reducing the power consumption of the light-emitting display device is being developed. To reduce power consumption, the pixels may be driven at a low frequency by reducing the frame rate during a specific period.

[0012] However, in order to improve the image quality characteristics of low-frequency driving, it is necessary to increase the number of gate control signals for driving the pixel compensation circuit. As a result, the design area of the gate driving circuit that generates and provides the gate control signals increases, making it difficult to implement a narrow border.

[0013] In addition, due to the switching of the clock for generating a plurality of gate control signals in the gate driving circuit during low-frequency driving, there is a problem that the effect of reducing power consumption is reduced.

[0014] One aspect of the present disclosure aims to provide a pixel and a display device including the pixel, in which the number of gate control signals required for the pixel driving circuit is reduced by sharing gate control signals in adjacent horizontal rows, thereby achieving a narrow border and reducing power consumption.

[0015] Other advantages and features of the present disclosure will be partly set forth in the following description and will partly become apparent to those of ordinary skill in the art upon examination of the following, or may be learned from the practice of the present disclosure. The objectives and other advantages of the present disclosure may be realized and attained by the structures particularly pointed out in the written description and claims and the accompanying drawings.

[0016] To achieve these and other advantages and in accordance with the purpose of the present disclosure, as embodied and broadly described herein, there is provided a pixel including: a light-emitting device; and a pixel circuit connected to a first gate control line, a second gate control line, a third gate control line, and the light-emitting device, the pixel circuit including a first node, a second node, a third node, and a fourth node, wherein the pixel circuit includes: a driving transistor connected to the first node to the third node; a first transistor connected to the first gate control line and the first node and the second node; a second transistor connected to the second gate control line, the second node, and a first driving voltage line; a third transistor connected to the first gate control line, the third node, and the fourth node; a fourth transistor connected to the first gate control line, the fourth node, and an initialization voltage line; a fifth transistor connected to the third gate control line, the third node, and a data line; and a storage capacitor disposed between the first node and the fourth node.

[0017] In another aspect of the present disclosure, there is provided a display device including: a display panel including a display area and a non-display area disposed near the display area, in which a plurality of pixels are arranged in a first direction and a second direction intersecting the first direction; and a gate driver disposed in the non-display area to provide a scan signal, a first light emission control signal, and a second light emission control signal to each of the plurality of pixels, wherein one or more of the first light emission control signal and the second light emission control signal are shared by two pixels adjacent to each other in the second direction among the plurality of pixels.

[0018] In another aspect of the present disclosure, there is provided a display device including: a display panel including a display area and a first non-display area and a second non-display area parallel to each other with the display area therebetween, in which an nth pixel and an (n + 1)th pixel adjacent to each other vertically are arranged in the display area, where n is an odd number of 1 or greater; a first gate driver that provides a first light emission control signal to the nth pixel and the (n + 1)th pixel in the first non-display area; and a second gate driver that provides a second light emission control signal to the nth pixel and the (n + 1)th pixel in the second non-display area, wherein each of the nth pixel and the (n + 1)th pixel emits light based on the first light emission control signal and the second light emission control signal.

[0019] It should be understood that the foregoing general description and the following detailed description of the present disclosure are both exemplary and explanatory, and are intended to provide further explanation of the claimed present disclosure. Description of the Drawings

[0020] The drawings are used to provide a further understanding of the present disclosure and are incorporated into and constitute a part of this application. These drawings illustrate embodiments of the present disclosure and, together with the description, are used to explain the principles of the present disclosure. In the drawings:

[0021] Figure 1 is a block diagram of a display device according to an embodiment of the present disclosure;

[0022] Figure 2 is a circuit diagram of a pixel circuit and a light-emitting device according to an embodiment of the present disclosure;

[0023] Figure 3 is a waveform diagram of the voltage of a specific node and the gate signal input to the pixel circuit according to an embodiment of the present disclosure;

[0024] Figures 4 to 8 is a diagram for describing a driving method of a pixel circuit according to an embodiment of the present disclosure;

[0025] Figure 9 is a block diagram illustrating a part of a gate driving circuit according to an embodiment of the present disclosure; and

[0026] Figure 10 is a waveform diagram of the voltage of a specific node and the sum of the gate signals input to the pixel circuits of each vertically adjacent pixel according to an embodiment of the present disclosure. Detailed Embodiments

[0027] The advantages and features of the present disclosure and the methods for implementing them will become clearer through the following embodiments described in conjunction with the drawings. However, the present disclosure can be implemented in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided to make the present disclosure thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art. In addition, the present disclosure is only defined by the scope of the claims.

[0028] The shapes, sizes, proportions, angles, and quantities disclosed in the drawings for describing the embodiments of the present disclosure are only examples. Therefore, the present disclosure is not limited to the details shown. Throughout the application, the same reference numerals refer to the same elements. In the following description, when the detailed description of related known functions or configurations is determined to unnecessarily obscure the focus of the present disclosure, the detailed description will be omitted.

[0029] In the case of using "comprising", "having", and "including" described in the present application, another part may be added unless "only~" is used. Unless otherwise stated, terms in the singular form may include the plural form.

[0030] When interpreting an element, the element is interpreted as including a range of error, although no explicit description is made.

[0031] When describing a positional relationship, for example, when the positional relationship is described as "on~", "above~", "under~", and "next to~", one or more additional parts may be arranged between the two parts unless "exactly" or "directly" is used.

[0032] When describing a temporal relationship, for example, when the temporal order is described as "after", "subsequently", "next", and "before", discontinuous cases may be included unless "exactly" or "directly" is used.

[0033] It should be understood that although terms such as "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to separate one element from another. For example, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element, without departing from the scope of the present disclosure.

[0034] The terms "first horizontal axis direction", "second horizontal axis direction", and "vertical axis direction" should not be interpreted only based on the geometric relationship that each direction is perpendicular to each other, and may refer to directions with a wider directivity within the range where the components in the present disclosure can function.

[0035] The term "at least one" should be understood to include any and all combinations of one or more of the related listed items. For example, the meaning of "at least one of the first item, the second item, and the third item" represents a combination of two or more of the first item, the second item, and the third item and all items presented by the first item, the second item, or the third item.

[0036] The features of the various embodiments of the present disclosure may be partially or wholly coupled or combined with each other, and may interoperate with each other in various ways and be technically driven as can be fully understood by those skilled in the art. The embodiments of the present disclosure may be implemented independently of each other or may be jointly implemented in an interdependent relationship.

[0037] Here, a pixel circuit and a gate driving circuit provided on a substrate of a display panel can be implemented with N-type or P-type transistors. For example, the transistors can be implemented as transistors having an N-type or P-type metal oxide semiconductor field effect transistor (MOSFET) structure. The transistor can be a three-electrode element including a gate electrode, a source electrode, and a drain electrode. The source electrode and the drain electrode of the transistor can be not fixed and can be switched between them based on an applied voltage.

[0038] The gate signal of the transistor used as a switching element can swing between a gate-on voltage and a gate-off voltage. The gate-on voltage can be set as a voltage for turning on the transistor, and the gate-off voltage can be set as a voltage for turning off the transistor. In an N-type transistor, the gate-on voltage can be a gate high voltage (VGH) having a first voltage level, and the gate-off voltage can be a gate low voltage (VGL) having a second voltage level lower than the gate high voltage (VGH). In a P-type transistor, the gate-on voltage can be a gate low voltage (VGL) having a second voltage level, and the gate-off voltage can be a gate high voltage (VGH) having a first voltage level.

[0039] At least a first gate control line, a second gate control line, and a third gate control line can be provided between the gate driving circuit and the pixel circuit. The signal provided to the first gate control line can be referred to as a first signal, a first gate signal, a first gate control signal, or a first light emission control signal. In addition, the signal provided to the second gate control line can be referred to as a second signal, a second gate signal, a second gate control signal, or a second light emission control signal. In addition, the signal provided to the third gate control line can be referred to as a third signal, a third gate signal, a third gate control signal, or a third light emission control signal. In the following description, the signal provided to the first gate control line can be referred to as the "first light emission control signal", the signal provided to the second gate control line can be referred to as the "second light emission control signal", and the signal provided to the third gate control line can be referred to as the "scan signal".

[0040] Hereinafter, preferred embodiments of a pixel according to the present disclosure and a display device including the pixel will be described in detail with reference to the drawings. Where possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts. Since, for ease of description, the scale of each element shown in the drawings is different from the actual scale, the present disclosure is not limited to the shown scale.

[0041] Figure 1 is a block diagram of a display device 100 according to an embodiment of the present disclosure.

[0042] Refer to Figure 1, the display device 100 according to an embodiment of the present disclosure may include a display panel 110 and a plurality of driving circuits that provide driving signals to the display panel 110. A plurality of data lines DL and a plurality of gate lines GL are arranged in the display panel 110, and a plurality of pixels PX connected to the plurality of data lines DL and the plurality of gate lines GL are arranged.

[0043] It is illustrated that a plurality of pixels PX are arranged in a matrix type to construct a pixel array, but the embodiments of the present disclosure are not limited thereto, and the plurality of pixels PX may be arranged in various types.

[0044] The driving circuits may include a data driving circuit 120 that provides data signals to the plurality of data lines DL, a gate driving circuit GD that provides gate signals to the plurality of gate lines GL, and a controller 130 that controls the data driving circuit 120 and the gate driving circuit GD.

[0045] The display panel 110 may include a display area DA for displaying an image and a non-display area NDA provided near the display area DA. The plurality of pixels PX, the data lines DL for transmitting data signals to the plurality of pixels PX, and the gate lines GL for transmitting gate signals to the plurality of pixels PX may be arranged in the display area DA.

[0046] The plurality of gate lines GL arranged in the display area DA may extend to the non-display area NDA and may be electrically connected to the gate driving circuit GD. The gate lines GL may electrically connect the gate driving circuit GD to the plurality of pixels PX arranged in a first direction (or row direction). In addition, gate driving related lines required for generating various gate signals or driving the plurality of pixels PX by using the gate driving circuit GD may be arranged in the non-display area NDA. For example, the gate driving related lines may include one or more high-level gate voltage lines for transmitting a high-level gate voltage to the gate driving circuit GD, one or more low-level gate voltage lines for transmitting a low-level gate voltage to the gate driving circuit GD, a plurality of clock lines for transmitting a plurality of clock signals to the gate driving circuit GD, and one or more start lines for transmitting one or more start signals to the gate driving circuit GD.

[0047] The plurality of data lines DL arranged in the display area DA may extend to the non-display area NDA and may be electrically connected to the data driving circuit 120. The data lines DL may electrically connect the data driving circuit 120 to the plurality of pixels PX arranged in a second direction (or column direction) intersecting the first direction and may be implemented as a single line, or may be implemented by connecting a plurality of lines through contact holes by using connection lines.

[0048] In the display panel 110, a plurality of data lines DL and a plurality of gate lines GL may be arranged together with the pixel array. As described above, the plurality of data lines DL and the plurality of gate lines GL may be arranged in rows or columns. For the sake of description, it may be assumed that the plurality of data lines DL are arranged in columns and the plurality of gate lines GL are arranged in rows. However, embodiments of the present disclosure are not limited thereto.

[0049] The controller 130 may start scanning the data signal based on the timing implemented in each frame, convert the input video data input from the outside based on the data signal format used in the data driving circuit 120 to output the converted image data, and control the data driving circuit 120 at an appropriate time based on the scanning.

[0050] The controller 130 may receive timing signals including a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, and a clock signal from the outside together with the input video data. The timing controller 130 may receive the timing signals to generate and output control signals for controlling the data driving circuit 120 and the gate driving circuit GD.

[0051] For example, the controller 130 may output various data control signals for controlling the data driving circuit 120 including a source start pulse, a source sampling clock, and a source output enable signal. The source start pulse may control the data sampling start timing of one or more data signal generation circuits constituting the data driving circuit 120. The source sampling clock may be a clock signal for controlling the sampling timing of data in each data signal generation circuit. The source output enable signal may control the output timing of the data driving circuit 120.

[0052] In addition, the controller 130 may output gate control signals for controlling the gate driving circuit GD including a gate start pulse, a gate shift clock, and a gate output enable signal. The gate start pulse may control the operation start timing of one or more gate signal generation circuits constituting the gate driving circuit GD. The gate shift clock may be a clock signal commonly input to one or more gate signal generation circuits and may control the shift timing of the scan signal. The gate output enable signal may specify the timing information regarding one or more gate signal generation circuits.

[0053] The controller 130 may be a timing controller used in general display device technologies, or may be a control device that performs additional control functions in addition to the timing controller.

[0054] The controller 130 may be implemented as a separate element independent of the data driving circuit 120, or the controller 130 and the data driving circuit 120 may be integrated and implemented as an integrated circuit (IC).

[0055] The data driving circuit 120 can be implemented to include one or more data signal generating circuits. The data signal generating circuit may include a shift register, a latch circuit, a digital-to-analog converter, and an output buffer. Optionally, the data signal generating circuit may further include an analog-to-digital converter.

[0056] The data signal generating circuit can be connected to the bonding pads of the display panel 110 by using tape automated bonding (TAB) type, chip on glass (COG) type, or chip on panel (COP) type, or can be directly disposed in the display panel 110 and can be integrated and disposed in the display panel 110. In addition, multiple data signal generating circuits can be implemented as a chip on film (COF) type in which the data signal generating circuit is mounted on a source circuit film connected to the display panel 110.

[0057] The gate driving circuit GD can sequentially supply gate signals to a plurality of gate lines GL to drive a plurality of pixels PX connected to the plurality of gate lines GL. The gate driving circuit GD may include a shift register and a level shifter.

[0058] The gate driving circuit GD can be connected to the bonding pads of the display panel 110 by using TAB type, COG type, or COP type, or can be implemented as a gate in panel (GIP) type and can be directly disposed in the display panel 110. In addition, multiple gate signal generating circuits can be implemented as a COF type in which the gate signal generating circuit is mounted on a gate circuit film connected to the display panel 110. The gate driving circuit GD may include a plurality of gate signal generating circuits, and the plurality of gate signal generating circuits can be implemented as GIP type and can be disposed in the non-display area NDA of the display panel 110.

[0059] The gate driving circuit GD can sequentially supply gate signals to a plurality of gate lines GL based on the control of the controller 130. The gate signals have a gate high voltage VGH of a first voltage level for turning on / off the transistor or a gate low voltage VGL of a second voltage level for turning on / off the transistor. When a signal is supplied to a specific gate line through the gate driving circuit GD, the data driving circuit 120 can convert the image data received from the controller 130 into an analog data signal, and can supply the analog data signal to a plurality of data lines DL.

[0060] The data driving circuit 120 can be disposed on one side of the display panel 110. For example, the data driving circuit 120 can be disposed on the upper side, lower side, left side, or right side of the display panel 110. In addition, the data driving circuit 120 can be disposed on both sides of the display panel 110 based on the driving type or panel design type. For example, the data driving circuit 120 can be disposed on the upper side and lower side, or left side and right side of the display panel 110.

[0061] The gate driving circuit GD can be disposed on one side of the display panel 110. For example, the gate driving circuit GD can be disposed on the upper side, lower side, left side, or right side of the display panel 110. In addition, the gate driving circuit GD can be disposed on both sides of the display panel 110 based on the driving type or the panel design type. For example, the gate driving circuit GD can be disposed on the upper side and the lower side, or the left side and the right side of the display panel 110. The gate driving circuit GD can be formed in the non-display area NDA on the left side and / or the right side of the substrate together with the process of manufacturing the thin film transistor (TFT) of the pixel PX, and can provide a gate signal to each of the plurality of gate lines GL based on the single-feed type operation. Alternatively, the gate driving circuit GD can be formed in each of the left and right non-display areas NDA of the substrate, and can provide a gate signal to each of the plurality of gate lines GL based on the dual-feed type operation. Alternatively, the gate driving circuit GD can be formed in each of the left and right non-display areas NDA of the substrate, and can operate based on the interlaced type to provide a gate signal to each of the plurality of gate lines GL.

[0062] An example is described in which a plurality of gate lines GL are arranged in a first direction (or row direction) in the display panel 110 and a plurality of pixels PX are arranged in a second direction (or column direction) intersecting the first direction. Therefore, it is assumed that the data driving circuit 120 is disposed on the upper side of the display panel 110 and the gate driving circuit GD is disposed on the left side and the right side of the display panel 110 to describe the present disclosure.

[0063] The plurality of gate lines GL disposed in the display panel 110 can include a plurality of first gate control lines, a plurality of second gate control lines, and a plurality of third gate control lines. The first gate control line, the second gate control line, and the third gate control line can be lines that transmit different types of gate signals to the gates of different transistors. For example, the first gate control line can be a line that transmits a first light emission control signal, the second gate control line can be a line that transmits a second light emission control signal, and the third gate control line can be a line that transmits a scan signal.

[0064] Therefore, the gate driving circuit GD can include a plurality of first light emission control driving circuits that output a first light emission control signal to the first gate control line of the gate line GL, a plurality of second light emission control driving circuits that output a second light emission control signal to the second gate control line, and a plurality of scan driving circuits that output a scan signal to the third gate control line.

[0065] A period during which all pixels PX arranged in the second direction (or column direction) in the display area DA are scanned by a gate signal including a first light emission control signal, a second light emission control signal, and a scan signal and a data signal is applied once may be referred to as one frame period. One frame period may be divided into a scan period and a light emission period after the scan period. In the scan period, data of an input image is applied to the pixels PX through gate lines GL connected to the pixels PX, and in the light emission period, the pixels PX emit light based on the first light emission control signal and the second light emission control signal. The scan period may include an initialization period and a sampling period. In addition, the sampling period may include a programming period. During the scan period, nodes included in the pixel circuit may be initialized, the threshold voltage of the driving transistor may be compensated, and a data voltage may be charged; during the light emission period, a light emission operation may be performed. The scan period may be only about several horizontal scan periods, and most of one frame period may be occupied by the light emission period.

[0066] Figure 2 is a circuit diagram of a pixel circuit and a light emitting device according to an embodiment of the present disclosure. Figure 2 The pixel circuit and the light emitting device shown in Figure 1 represent one pixel shown, and pixels arranged in the nth horizontal row will be described below.

[0067] Referring to Figure 2 , the pixel circuit for transmitting a driving current to the light emitting device ED may include a plurality of transistors and capacitors and may be electrically connected to a first driving voltage VDD line, a second driving voltage VSS line, an initialization voltage VINI line, a first gate control line GL1, a second gate control line GL2, a third gate control line GL3, and a data line DL. The pixel circuit according to an embodiment of the present disclosure may be an internal compensation circuit for compensating the threshold voltage of the driving transistor DT.

[0068] The light emitting device ED may be disposed between a first electrode (or anode electrode) connected to the pixel circuit and a second electrode (or cathode electrode) connected to the second driving voltage VSS line. The light emitting device ED according to an embodiment may include an organic light emitting unit, a quantum dot light emitting unit, or an inorganic light emitting unit, or may include a micro light emitting diode device. The light emitting device ED may emit light using a data voltage provided from the pixel circuit.

[0069] The pixel circuit may include a driving transistor DT, five switching transistors T1 to T5, and a storage capacitor C. The pixel circuit may be provided with a first driving voltage VDD as a high-level voltage, a second driving voltage VSS as a low-level voltage, and an initialization voltage VINI as a source voltage. The pixel circuit may be provided with a gate signal as a first light emission control signal EM1(n), a second light emission control signal EM2(n), and a scan signal Scan(n) through a gate driving circuit GD, and the pixel circuit may be provided with a data voltage Vdata through a data driving circuit 120. The first light emission control signal EM1(n), the second light emission control signal EM2(n), and the scan signal Scan(n) may be gate signals applied to the pixels arranged in the n-th horizontal row.

[0070] The driving transistor DT may be a driving element that adjusts the current flowing through the light-emitting device ED based on its gate-source voltage Vgs, and may include a first node N1 connected to one side of the capacitor C, a second node N2 connected to the first transistor T1 and the second transistor T2, and a third node N3 connected to the third transistor T3 and the fifth transistor T5. The driving transistor DT may include a gate electrode connected to the first node N1, a drain electrode connected to the second node N2, and a source electrode connected to the third node N3.

[0071] When the first transistor Tl and the second transistor T2 are turned on, the driving transistor DT may store the first driving voltage VDD in the first node N1 as its gate electrode. In addition, when the data voltage Vdata is provided in a state where the first transistor T1 is turned on, the data voltage Vdata may be applied to the first node N1 through a diode connection. In addition, the driving transistor DT may provide a driving current to the light-emitting device ED based on the first light emission control signal EM1(n) and the second light emission control signal EM2(n), thereby adjusting the brightness of the light-emitting device ED based on the amount of current.

[0072] The first transistor Tl may be connected to the first gate control line GL1, the first node N1, and the second node N2 and may be turned on or off by the first light emission control signal EM1(n) via the first gate control line GL1. For example, the first transistor T1 may be a TFT having a first conductivity type (or N-type). When the first light emission control signal EM1(n) is a gate high voltage VGH having a first voltage level, the first transistor T1 may be turned on. In addition, when the first light emission control signal EM1(n) is a gate low voltage VGL having a second voltage level, the first transistor T1 may be turned off.

[0073] Therefore, when the first light emission control signal EM1(n) is the gate high voltage VGH, the first transistor Tl can be turned on and can transfer the sampling voltage of the driving transistor DT or the first driving voltage VDD, which is the high-level voltage of the second node N2, to the first node N1. Thus, the data voltage Vdata applied to the light-emitting device ED can be initialized or the data voltage Vdata can be applied to sample the threshold voltage Vth of the driving transistor DT.

[0074] The second transistor T2 can be connected to the second gate control line GL2, the second node N2, and the first driving voltage VDD line, and can be turned on or off by the second light emission control signal EM2(n) via the second gate control line GL2. For example, the second transistor T2 can be a TFT having a second conductivity type (or P-type). When the second light emission control signal EM2(n) is the gate low voltage VGL having a second voltage level, the second transistor T2 can be turned on. In addition, when the second light emission control signal EM2(n) is the gate high voltage VGH having a first voltage level, the second transistor T2 can be turned off.

[0075] Therefore, when the second light emission control signal EM2(n) is the gate low voltage VGL, the second transistor T2 can be turned on and can electrically connect the first driving voltage VDD line to the second node N2. Thus, the first driving voltage VDD can be supplied to the second node N2. Therefore, the second transistor T2 can adjust the current amount of the light-emitting device ED based on the data voltage Vdata.

[0076] The third transistor T3 can be connected to the first gate control line GL1, the third node N3, and the fourth node N4 connected to the anode electrode of the light-emitting device ED, and can be turned on or off by the first light emission control signal EM1(n) via the first gate control line GL1. For example, the third transistor T3 can be a TFT having a second conductivity type (or P-type). When the first light emission control signal EM1(n) is the gate low voltage VGL having a second voltage level, the third transistor T3 can be turned on. In addition, when the first light emission control signal EM1(n) is the gate high voltage VGH having a first voltage level, the third transistor T3 can be turned off.

[0077] Therefore, when the first light emission control signal EM1(n) is the gate low voltage VGL, the third transistor T3 can be turned on and can electrically connect the third node N3 to the fourth node N4. Thus, the voltage of the third node N3 can be supplied to the fourth node N4. Therefore, when the third transistor T3, the driving transistor DT, and the second transistor T2 are turned on, the first driving voltage VDD can be supplied to the driving transistor DT and the driving current can be supplied to the light-emitting device ED. Thus, the light-emitting device ED can emit light.

[0078] The fourth transistor T4 can be connected to the first gate control line GL1, the fourth node N4, and the initialization voltage VINI line, and can be turned on or off via the first gate control line GL1 by the first light emission control signal EM1(n). For example, the fourth transistor T4 can be a TFT having a first conductivity type (or N-type). When the first light emission control signal EM1(n) is a gate high voltage VGH having a first voltage level, the fourth transistor T4 can be turned on. In addition, when the first light emission control signal EM1(n) is a gate low voltage VGL having a second voltage level lower than the first voltage level, the fourth transistor T4 can be turned off.

[0079] Therefore, when the first light emission control signal EM1(n) is the gate high voltage VGH, the fourth transistor T4 can be turned on and can electrically connect the initialization voltage VINI line to the fourth node N4, and thus the initialization voltage VINI can be transmitted to the fourth node N4 to initialize the data voltage Vdata applied to the light emitting device ED.

[0080] The fifth transistor T5 can be connected to the third gate control line GL3, the third node N3, and the data line DL, and can be turned on or off via the third gate control line GL3 by the scan signal Scan(n). For example, the fifth transistor T5 can be a TFT having a second conductivity type (or P-type). When the scan signal Scan(n) is a gate low voltage VGL having a second voltage level, the fifth transistor T5 can be turned on. In addition, when the scan signal Scan(n) is a gate high voltage VGH having a first voltage level, the fifth transistor T5 can be turned off.

[0081] Therefore, when the scan signal Scan(n) is the gate low voltage VGL, the fifth transistor T5 can be turned on and can electrically connect the data line DL to the third node N3, and thus the data voltage Vdata can be provided to the third node N3.

[0082] The capacitor C can be a storage capacitor C that stores the voltage applied to the first node N1 connected to the gate electrode of the driving transistor DT, and can be disposed between the second node N1 and the fourth node N4 connected to the anode electrode of the light emitting device ED. The capacitor C can be connected to the first node N1 and the fourth node N4, and can store the voltage difference between the voltage at the gate electrode of the driving transistor DT and the voltage provided to the anode electrode of the light emitting device ED.

[0083] The pixel circuit according to an embodiment of the present disclosure can be configured with various types of transistors in which the semiconductor layers included in the driving transistor DT and the first to fifth transistors T1 to T5 include different materials.

[0084] For example, in a pixel circuit including multiple types of transistors, a TFT including a semiconductor layer of crystalline silicon may include a low-temperature polycrystalline silicon (LTPS) TFT including LTPS, and a TFT including a semiconductor layer of an oxide may include an oxide semiconductor TFT including low-temperature polycrystalline oxide (LTPO).

[0085] In a pixel circuit according to an embodiment of the present disclosure, the driving transistor DT and the driving transistor DT, the first transistor T1, and the fourth transistor T4 among the first transistor T1 to the fifth transistor T5 may each be configured as a TFT having a first conductivity type (or N-type), and the second transistor T2, the third transistor T3, and the fifth transistor T5 may each be configured as a TFT having a second conductivity type (or P-type). For example, the driving transistor DT may be configured as an oxide semiconductor TFT having a first conductivity type (or N-type), the first transistor T1 and the fourth transistor T4 may each be configured as an LTPS TFT or an oxide semiconductor TFT having a first conductivity type (or N-type), and the second transistor T2, the third transistor T3, and the fifth transistor T5 may each be configured as an LTPS TFT having a second conductivity type (or P-type).

[0086] The polysilicon semiconductor material may have a relatively high electron mobility (100 cm 2 / Vs or higher), and thus may have low power consumption and excellent reliability. The oxide semiconductor material may have a relatively low off-current, and thus has a short on-time and can maintain a long off-time. Therefore, in a pixel circuit according to an embodiment of the present disclosure, the driving transistor DT, the first transistor T1, and the fourth transistor T4, which require precise current control and low leakage current in low-frequency driving for low-power driving, may each be implemented as an oxide semiconductor TFT having a first conductivity type (or N-type), and the second transistor T2, the third transistor T3, and the fifth transistor T5, which are disposed in the current supply path and require fast and stable driving characteristics, may each be implemented as an LTPS TFT having a second conductivity type (or P-type). In addition, the first transistor T1 and the fourth transistor T4 connected to the same first gate control line GL1 may each be implemented as a TFT having a first conductivity type (or N-type), and the third transistor T3 may be implemented as a TFT having a second conductivity type (or P-type), thereby minimizing the structure of the gate driving circuit and the gate line.

[0087] Therefore, in a display device according to an embodiment of the present disclosure, TFTs having characteristics suitable for the required performance of transistors for constructing a pixel circuit may be arranged to share a gate control signal, thereby enabling low-frequency driving for low-power driving and minimizing the structure of the gate driving circuit and the gate line, thus achieving a narrow bezel and improving power consumption.

[0088] Figure 3 is a waveform diagram of the voltage of a specific node and the gate signal input to the pixel circuit according to an embodiment of the present disclosure, Figures 4 to 8 and is a diagram for describing a driving method of a pixel circuit according to an embodiment of the present disclosure. Figure 3 The waveform diagram shown in Figure 2 relates to the pixel shown in

[0089] Referring to Figure 3 and Figures 4 to 8 , the pixel circuit according to an embodiment of the present disclosure can be driven separately in a first interval ①, a second interval ②, a third interval ③, a fourth interval ④, and a fifth interval ⑤. For example, each pixel arranged in the n-th horizontal row can be provided with a data voltage Vdata through the first to fifth intervals ①, ②, ③, ④, and ⑤ and can emit light. According to an embodiment, the time of each of the first to fifth intervals ①, ②, ③, ④, and ⑤ can be changed differently.

[0090] The gate signal input to the pixel circuit may include a first light emission control signal EM1(n) applied via a first gate control line GL1, a second light emission control signal EM2(n) applied via a second gate control line GL2, and a scan signal Scan(n) applied via a third gate control line GL3.

[0091] The first light emission control signal EM1(n) may have a gate high voltage VGH of a first voltage level in the first to third intervals ①, ②, and ③, and may have a gate low voltage VGL of a second voltage level different from the first voltage level in the fourth interval ④ and the fifth interval ⑤.

[0092] The second light emission control signal EM2(n) may have the same time period as the first light emission control signal EM1(n), have a phase overlapping with the phase of the first light emission control signal EM1(n), have a gate high voltage VGH of a first voltage level in the second to fourth intervals ②, ③, and ④, and have a gate low voltage VGL of a second voltage level in the first interval ① and the fifth interval ⑤.

[0093] The scan signal Scan(n) may have a gate high voltage VGH of a first voltage level in the first interval ① and the third to fifth intervals ③, ④, and ⑤, and may have a gate low voltage VGL of a second voltage level in the second interval ②. In the interval where the phase of the first light emission control signal EM1(n) overlaps with the phase of the second light emission control signal EM2(n), the pulse of the scan signal Scan(n) having a gate low voltage VGL may have a time period of one horizontal period 1H in one frame. According to an embodiment, the pulse period of the scan signal Scan(n) can be changed differently.

[0094] Hereinafter, reference will be made to Figures 4 to 8 describe the operation of the pixel circuit in each driving period.

[0095] First, at the time when the first interval ① starts, the first light emission control signal EM1(n) may rise and may have a gate high voltage VGH, the second light emission control signal EM2(n) may maintain a gate low voltage VGL, and the scan signal Scan(n) may maintain a gate high voltage VGH. As Figure 4 shown, during the first interval ①, based on the gate high voltage VGH of the first light emission control signal EM1(n), the first transistor T1 and the fourth transistor T4 may be turned on and the third transistor T3 may be turned off; based on the gate low voltage VGL of the second light emission control signal EM2(n), the second transistor T2 may be turned on; and based on the gate high voltage VGH of the scan signal Scan(n), the fifth transistor T5 may be turned off.

[0096] Therefore, the initialization voltage VINI may be supplied to the fourth node N4 through the fourth transistor T4, and the first driving voltage VDD applied to the second node N2 through the second transistor T2 may be supplied to the first node N1 through the first transistor T1. That is to say, when the initialization voltage VINI is supplied to the fourth node N4 connected to the anode electrode of the light emitting device ED, the data voltage Vdata applied to the light emitting device ED may be initialized, and the first driving voltage VDD may be supplied to the first node N1 connected to the gate electrode of the driving transistor DT.

[0097] At the time when the second interval ② starts, the scan signal Scan(n) may fall and may have a gate low voltage VGL, the first light emission control signal EM1(n) may maintain a gate high voltage VGH, and the second light emission control signal EM2(n) may rise to a gate high voltage VGH and may maintain a gate high voltage VGH. At this time, the second light emission control signal EM2(n) may first rise to a gate high voltage VGH before the second interval ② starts, so that the second light emission control signal EM2(n) and the scan signal Scan(n) may not be mixed. The period during which the second light emission control signal EM2(n) first rises may be about one horizontal period 1H, but the embodiments of the present disclosure are not limited thereto. As Figure 5 shown, during the second interval ②, based on the gate high voltage VGH of the first light emission control signal EM1(n), the first transistor T1 and the fourth transistor T4 may be turned on and the third transistor T3 may be turned off; based on the gate high voltage VGH of the second light emission control signal EM2(n), the second transistor T2 may be turned off; and based on the gate low voltage VGL of the scan signal Scan(n), the fifth transistor T5 may be turned on.

[0098] Therefore, the data voltage Vdata can be provided to the third node N3 through the fifth transistor T5. In addition, when the second transistor T2 is turned off and the first transistor T1 is turned on, the first node N1 and the second node N2 of the driving transistor DT can be connected to each other, so that the gate-source voltage Vgs of the driving transistor DT can be sampled as the threshold voltage Vth of the driving transistor DT through diode connection. In addition, as the fourth transistor T4 is turned on, the initialization voltage VINI can be provided to the fourth node N4, and the voltage difference "Vdata + Vth - VINI" between the sum of the data voltage Vdata and the threshold voltage Vth of the driving transistor DT and the initialization voltage VINI can be stored in the capacitor C. Therefore, during the second period ②, the voltage of each of the first node N1 and the second node N2 can converge to the voltage that is the sum of the data voltage Vdata and the threshold voltage Vth of the driving transistor DT, the voltage of the third node N3 can be the data voltage Vdata, and the voltage of the fourth node N4 can be the initialization voltage VINI.

[0099] At the time when the third period ③ starts, the scan signal Scan(n) can rise and can have a gate high voltage VGH, the first emission control signal EM1(n) can maintain the gate high voltage VGH, and the second emission control signal EM2(n) can maintain the gate high voltage VGH. As Figure 6 shown, during the third period ③, based on the gate high voltage VGH of the first emission control signal EM1(n), the first transistor T1 and the fourth transistor T4 can be turned on and the third transistor T3 can be turned off; based on the gate high voltage VGH of the second emission control signal EM2(n), the second transistor T2 can be turned off; and based on the gate high voltage VGH of the scan signal Scan(n), the fifth transistor T5 can be turned off.

[0100] Therefore, when the second transistor T2, the third transistor T3, and the fifth transistor T5 are turned off, each of the first node N1, the second node N2, the third node N3, and the fourth node N4 that is sampled or has a voltage applied thereto can float in the second period ② and can maintain the voltage of each node.

[0101] At the time when the fourth period ④ starts, the first emission control signal EM1(n) can fall and can have a gate low voltage VGL, the second emission control signal EM2(n) can maintain the gate high voltage VGH, and the scan signal Scan(n) can maintain the gate high voltage VGH. As Figure 7As shown, during the fourth period ④, only the third transistor T3 can be turned on, and the first, second, fourth, and fifth transistors T1, T2, T4, and T5 can be turned off. Therefore, the third transistor T3 can be turned on and connected to the third node N3 and the fourth node N4, and the data voltage Vdata held by the third node N3 can be provided to the fourth node N4.

[0102] At the time when the fifth interval ⑤ starts, the second light emission control signal EM2(n) can fall and have a gate low voltage VGL, the first light emission control signal EM1(n) can maintain the gate low voltage VGL, and the scan signal Scan(n) can maintain the gate high voltage VGH. As Figure 8 shown, during the fifth interval ⑤, the first, fourth, and fifth transistors T1, T4, and T5 can be turned off, and the second transistor T2 and the third transistor T3 can be turned on. In addition, the driving transistor DT can be turned on by the sum of the threshold voltage Vth of the driving transistor DT and the data voltage Vdata stored in the first node N1, and thus a path for the driving current to flow from the first driving voltage VDD line to the light emitting device ED can be formed. That is to say, the driving current can flow to the light emitting device ED through the driving transistor DT, the second transistor T2, and the third transistor T3 that are turned on during the fifth interval ⑤. In addition, in the fifth interval ⑤, the gate-source voltage Vgs of the driving transistor DT can be referred to as the data voltage Vdata, and the threshold voltage Vth of the driving transistor DT can be compensated, and thus the level of the driving current can be adjusted based on the level of the data voltage Vdata of the driving transistor DT, and the light emitting device ED can emit light using the driving current, thereby increasing the brightness.

[0103] Figure 9 is a block diagram illustrating a part of a gate driving circuit according to an embodiment of the present disclosure. Figure 9 The gate driving circuit shown in Figure 1 represents a part of the gate driving circuit GD shown in

[0104] Combined with Figure 1 for reference Figure 9, according to an embodiment of the present disclosure, the gate driving circuit GD may include a plurality of gate signal generating circuits, and the plurality of gate signal generating circuits include stages ST corresponding to pixels PX arranged in each horizontal row. For example, the gate driving circuit GD may include a plurality of first light emission control driving circuits EM1 ST(n / n+1) and EM1 ST(n+2 / n+3) that output a plurality of first light emission control signals EM1, a plurality of second light emission control driving circuits EM2 ST(n / n+1) and EM2 ST(n+2 / n+3) that output a plurality of second light emission control signals EM2, and a plurality of scan driving circuits Scan ST(n), Scan ST(n+1), Scan ST(n+2), Scan ST(n+3) that output a plurality of scan signals Scan.

[0105] As Figure 9 shown, the gate driving circuit GD may be separately disposed in a left non-display area NDA and a right non-display area NDA divided based on the display area DA of the display panel 110. For example, the gate driving circuit GD may include a first gate driving circuit GD_R disposed in the left non-display area NDA and a second gate driving circuit GD_L disposed in the right non-display area NDA.

[0106] The first gate driving circuit GD_R and the second gate driving circuit GD_L may be configured to output gate signals with different timings, and may be circuits with the same structure or different circuits that output different gate signals.

[0107] Each of the first gate driving circuit GD_R and the second gate driving circuit GD_L may include a plurality of first light emission control driving circuits EM1 ST(n / n+1) and EM1 ST(n+2 / n+3), a plurality of second light emission control driving circuits EM2 ST(n / n+1) and EM2 ST(n+2 / n+3), and a plurality of scan driving circuits Scan ST(n), Scan ST(n+1), Scan ST(n+2), and Scan ST(n+3). For example, the first gate driving circuit GD_R may include the second light emission control driving circuits EM2 ST(n / n+1) and EM2 ST(n+2 / n+3) and some of the scan driving circuits Scan ST(n) and Scan ST(n+2), and the second gate driving circuit GD_L may include the first light emission control driving circuits EM1 ST(n / n+1) and EM1 ST(n+2 / n+3) and some of the scan driving circuits Scan ST(n+1) and Scan ST(n+3).

[0108] The first light emission control driving circuits EM1 ST(n / n+1) and EM1 ST(n+2 / n+3) can be arranged in the non-display area on the right side and can have a slave connection structure. In addition, each of the first light emission control driving circuits EM1 ST(n / n+1) and EM1 ST(n+2 / n+3) can receive at least one output signal from a previous stage or a next stage as an input signal. The first light emission control driving circuits EM1 ST(n / n+1) and EM1 ST(n+2 / n+3) can share the clock signals EM1 CLK1 and EM1 CLK2, as well as the driving voltages VGH and VGL, and the start signal EM1 VST can be applied to the first light emission control driving circuit EM1 ST(n / n+1) of the previous stage. Each of the first light emission control driving circuits EM1 ST(n / n+1) and EM1 ST(n+2 / n+3) can provide a first light emission control signal shared by the pixels arranged in the horizontal rows adjacent to each other vertically. For example, the first light emission control driving circuit EM1 ST(n / n+1) can provide the first light emission control signal to the pixels Line(n)PX arranged in the n-th horizontal row and the pixels Line(n+1)PX arranged in the (n+1)-th horizontal row, and the other first light emission control driving circuit EM1 ST(n+2 / n+3) can provide the first light emission control signal to the pixels Line(n+2)PX arranged in the (n+2)-th horizontal row and the pixels Line(n+3)PX arranged in the (n+3)-th horizontal row. That is to say, each of the first light emission control driving circuits EM1 ST(n / n+1) and EM1 ST(n+2 / n+3) can be configured to provide the first light emission control signal shared by the pixels arranged in two adjacent horizontal rows, and thus can be designed into a structure in which the width of each circuit stage in the horizontal direction is smaller than the width of each circuit stage in the vertical direction, thereby reducing the border area of the display panel.

[0109] The second light emission control driving circuits EM2 ST(n / n+1) and EM2 ST(n+2 / n+3) can be disposed in the left non-display area and can have a slave connection structure. In addition, each of the second light emission control driving circuits EM2 ST(n / n+1) and EM2 ST(n+2 / n+3) can receive at least one output signal of a previous stage or a next stage as an input signal. The second light emission control driving circuits EM2 ST(n / n+1) and EM2 ST(n+2 / n+3) can share clock signals EM2 CLK1 and EM2 CLK2, and driving voltages VGH and VGL, and a start signal EM2 VST can be applied to the second light emission control driving circuit EM2 ST(n / n+1) of the previous stage. Each of the second light emission control driving circuits EM2 ST(n / n+1) and EM2 ST(n+2 / n+3) can provide a second light emission control signal shared by pixels arranged in horizontal rows vertically adjacent to each other. For example, the second light emission control driving circuit EM2 ST(n / n+1) can provide the second light emission control signal to pixels Line(n)PX arranged in the n-th horizontal row and pixels Line(n+1)PX arranged in the (n+1)-th horizontal row, and the other second light emission control driving circuit EM2 ST(n+2 / n+3) can provide the second light emission control signal to pixels Line(n+2)PX arranged in the (n+2)-th horizontal row and pixels Line(n+3)PX arranged in the (n+3)-th horizontal row. That is to say, each of the second light emission control driving circuits EM2 ST(n / n+1) and EM2 ST(n+2 / n+3) can be configured to provide a first light emission control signal shared by pixels arranged in two adjacent horizontal rows, and thus can be designed into a structure in which the width of each circuit stage in the horizontal direction is smaller than the width of each circuit stage in the vertical direction, thereby reducing the border area of the display panel.

[0110] The scan driving circuits Scan ST(n), Scan ST(n+1), Scan ST(n+2), and Scan ST(n+3) can be separately arranged in the left non-display area and the right non-display area, and can have a structure of subordinate connection in each area. In addition, each scan driving circuit can receive at least the output signal of the previous stage or the next stage as an input signal. The scan driving circuits Scan ST(n), Scan ST(n+1), Scan ST(n+2), and Scan ST(n+3) can share the clock signals Scan CLK1 and Scan CLK2, as well as the driving voltages VGH and VGL, and the start signal Scan VST can be applied to the previous-stage scan driving circuit Scan ST(n). The scan driving circuits Scan ST(n), Scan ST(n+1), Scan ST(n+2), and Scan ST(n+3) can sequentially provide scan signals to the pixels arranged in each horizontal row. The scan driving circuits Scan ST(n), Scan ST(n+1), Scan ST(n+2), and Scan ST(n+3) can be alternately arranged in the left non-display area and the right non-display area. For example, the scan driving circuit Scan ST(n) corresponding to the pixel Line(n)PX arranged in the n-th horizontal row can be arranged in the left non-display area, the scan driving circuit Scan ST(n+1) corresponding to the pixel Line(n+1)PX arranged in the (n+1)-th horizontal row can be arranged in the right non-display area, the scan driving circuit Scan ST(n+2) corresponding to the pixel Line(n+2)PX arranged in the (n+2)-th horizontal row can be arranged in the left non-display area, and the scan driving circuit Scan ST(n+3) corresponding to the pixel Line(n+3)PX arranged in the (n+3)-th horizontal row can be arranged in the right non-display area. That is to say, the scan driving circuits Scan ST(n), Scan ST(n+1), Scan ST(n+2), and Scan ST(n+3) can be separately arranged in the left non-display area and the left non-display area, and thus can be designed into a structure in which the width of each circuit stage in the horizontal direction is smaller than the width of each circuit stage in the vertical direction, thereby reducing the border area of the display panel.

[0111] Figure 10 It is a waveform diagram of the voltage of a specific node according to an embodiment of the present disclosure and the gate signal of each pixel circuit input to the vertically adjacent pixels. Figure 10 The waveform diagram shown in [the figure] relates to pixels vertically adjacent to each other and is used to describe the pixel arranged in the n-th horizontal row and the pixel arranged in the (n+1)-th horizontal row.

[0112] Refer to Figure 10, the pixel circuit of each of the vertically adjacent pixels according to an embodiment of the present disclosure can be driven separately in a first interval ①, second intervals ②' and ②", third intervals ③' and ③", fourth interval ④, and fifth interval ⑤. For example, each pixel arranged in the n-th horizontal row can be provided with a data voltage Vdata through the first to fifth intervals ①, ②', ③', ④, and ⑤ and can emit light, and each pixel arranged in the (n + 1)-th horizontal row can be provided with a data voltage Vdata through the first to fifth intervals ①, ②", ③", ④, and ⑤ and can emit light. Here, each pixel arranged in the n-th horizontal row can be referred to as the n-th pixel, and each pixel arranged in the (n + 1)-th horizontal row can be referred to as the (n + 1)-th pixel. Each of the n-th pixel and the (n + 1)-th pixel can be driven identically in the first interval ①, fourth interval ④, and fifth interval ⑤ among the first interval ①, second intervals ②' and ②", third intervals ③' and ③", fourth interval ④, and fifth interval ⑤, and can be driven differently in the second intervals ②' and ②" and the third intervals ③' and ③". For example, compared with the second interval ②' and the third interval ③' of the n-th pixel, the second interval ②" and the third interval ③" of the (n + 1)-th pixel can be driven in the reverse order. That is, the n-th pixel can be driven first in the second interval ②' and then in the third interval ③', and the (n + 1)-th pixel can be driven first in the third interval ③" and then in the second interval ②". According to an embodiment, the times of the first to fifth intervals ①, ②', ③', ④, and ⑤ of the n-th pixel and the first to fifth intervals ①, ②", ③", ④, and ⑤ of the (n + 1)-th pixel can be changed differently.

[0113] The gate signals input to the pixel circuits of the n-th pixel and the (n + 1)-th pixel adjacent to each other vertically can include a first light emission control signal EM1(n / n + 1) applied via a first gate control line GL1, a light emission control signal EM2(n / n + 1) applied via a second gate control line GL2, and scan signals Scan(n) and Scan(n + 1) applied via a third gate control line GL3.

[0114] The first light emission control signal EM1(n / n + 1) can be shared by the n-th pixel and the (n + 1)-th pixel and applied. For the driving period of the n-th pixel, the first light emission control signal EM1(n / n + 1) can have a gate high voltage VGH of the first voltage level in the first to third periods ①, ②' and ③', and can have a gate low voltage VGL of a second voltage level different from the first voltage level in the fourth period ④ and the fifth period ⑤. In addition, for the driving period of the (n + 1)-th pixel, the first light emission control signal EM1(n / n + 1) can have a gate high voltage VGH of the first voltage level in the first, third and second periods ①, ③" and ②", and can have a gate low voltage VGL of a second voltage level different from the first voltage level in the fourth period ④ and the fifth period ⑤.

[0115] The second light emission control signal EM2(n / n + 1) can be shared by the n-th pixel and the (n + 1)-th pixel and applied, and can have the same time period as the first light emission control signal EM1(n / n + 1) and a phase overlapping with the phase of the first light emission control signal EM1(n / n + 1). In addition, for the driving period of the n-th pixel, the second light emission control signal EM2(n / n + 1) can have a gate high voltage VGH of the first voltage level in the second to fourth periods ②', ③' and ④, and can have a gate low voltage VGL of the second voltage level in the first period ① and the fifth period ⑤. In addition, for the driving period of the (n + 1)-th pixel, the second light emission control signal EM2(n / n + 1) can have a gate high voltage VGH of the first voltage level in the third, second and fourth periods ③", ②" and ④, and can have a gate low voltage VGL of the second voltage level in the first period ① and the fifth period ⑤.

[0116] The scan signals Scan(n) and Scan(n + 1) can include the n-th scan signal Scan(n) corresponding to the n-th pixel and the (n + 1)-th scan signal Scan(n + 1) corresponding to the (n + 1)-th pixel. In the period where the first light emission control signal EM1(n / n + 1) and the second light emission control signal EM2(n / n + 1) overlap with each other in the gate high voltage VGH, the n-th scan signal Scan(n) and the (n + 1)-th scan signal Scan(n + 1) may not overlap with each other. The n-th scan signal Scan(n) can have a gate high voltage VGH of the first voltage level in the first period ① and the third to fifth periods ③', ④ and ⑤ of the n-th pixel, and can have a gate low voltage VGL of the second voltage level in the second period ②'. In addition, the (n + 1)-th scan signal Scan(n + 1) can have a gate high voltage VGH of the first voltage level in the first period ① and the third to fifth periods ③", ④ and ⑤ of the (n + 1)-th pixel, and can have a gate low voltage VGL of the second voltage level in the second period ②".

[0117] Therefore, in an interval where the first emission control signal EM1(n / n + 1) and the second emission control signal EM2(n / n + 1) overlap each other in the gate high voltage VGH having a first voltage level, the second intervals ②' and ②" and the third intervals ③' and ③" of each of the n-th pixel and the (n + 1)-th pixel may overlap. In addition, the second intervals ②' and ②" of each of the n-th pixel and the (n + 1)-th pixel may be an interval where each of the scan signals Scan(n) and Scan(n + 1) has a gate low voltage VGL having a second voltage level in an interval where the first emission control signal EM1(n / n + 1) and the second emission control signal EM2(n / n + 1) overlap each other in the gate high voltage VGH having a first voltage level, and the third intervals ③' and ③" of each of the n-th pixel and the (n + 1)-th pixel may be an interval other than the second intervals ②' and ②" in an interval where the first emission control signal EM1(n / n + 1) and the second emission control signal EM2(n / n + 1) overlap each other in the gate high voltage VGH having a first voltage level.

[0118] Hereinafter, reference will be made to Figures 4 to 8 Describe the operation of the pixel circuit in the driving interval of each of the n-th pixel and the (n + 1)-th pixel. The operation of the pixel circuit of the n-th pixel may be the same as the description given above with reference to Figure 3 Therefore, only the operation of the pixel circuit of the (n + 1)-th pixel will be described below and the repeated description will be omitted.

[0119] First, at the time when the first interval ① of the (n + 1)-th pixel starts, the first emission control signal EM1(n / n + 1) may rise and may have the gate high voltage VGH, the second emission control signal EM2(n / n + 1) may maintain the gate low voltage VGL, and the scan signal Scan(n + 1) may maintain the gate high voltage VGH. As Figure 4 shown, during the first interval ①, based on the gate high voltage VGH of the first emission control signal EM1(n / n + 1), the first transistor T1 and the fourth transistor T4 may be turned on and the third transistor T3 may be turned off; based on the gate low voltage VGL of the second emission control signal EM2(n / n + 1), the second transistor T2 may be turned on; based on the gate high voltage VGH of the scan signal Scan(n) + 1, the fifth transistor T5 may be turned off.

[0120] Therefore, the initialization voltage VINI can be supplied to the fourth node N4 through the fourth transistor T4, and the first driving voltage VDD applied to the second node N2 through the second transistor T2 can be supplied to the first node N1 through the first transistor T1. That is to say, when the initialization voltage VINI is supplied to the fourth node N4 connected to the anode electrode of the light-emitting device ED, the data voltage Vdata applied to the light-emitting device ED can be initialized, and the first driving voltage VDD can be supplied to the first node N1 connected to the gate electrode of the driving transistor DT.

[0121] Different from the n-th pixel, in the (n + 1)-th pixel, the third period ③" can be executed first, and the second period ②" can be executed subsequently. During the third period ③" of the (n + 1)-th pixel, the scan signal Scan(n + 1) can maintain the gate high voltage VGH, the first light emission control signal EM1(n / n + 1) can maintain the gate high voltage VGH, and the second light emission control signal EM2(n / n + 1) can rise to the gate high voltage VGH and can maintain the gate high voltage VGH. As Figure 6 shown, during the third period ③", based on the gate high voltage VGH of the first light emission control signal EM1(n / n + 1), the first transistor T1 and the fourth transistor T4 can be turned on and the third transistor T3 can be turned off; based on the gate high voltage VGH of the second light emission control signal EM2(n / n + 1), the second transistor T2 can be turned off; and based on the gate high voltage VGH of the scan signal Scan(n + 1), the fifth transistor T5 can be turned off.

[0122] Therefore, the second transistor T2, the third transistor T3, and the fifth transistor T5 can be turned off, so that the voltages of the first node N1, the second node N2, the third node N3, and the fourth node N4 initialized in the first period ① can be maintained.

[0123] At the time when the second period ②" of the (n + 1)-th pixel starts, the scan signal Scan(n + 1) can drop and can have the gate low voltage VGL, the first light emission control signal EM1(n / +1) can maintain the gate high voltage VGH, and the second light emission control signal EM2(n / n + 1) can maintain the gate high voltage VGH. At this time, the time of the scan signal Scan(n + 1) of the (n + 1)-th pixel can have a specific period after the time when the scan signal Scan(n) of the n-th pixel rises again, so that the scan signals Scan(n) and Scan(n + 1) can be non-overlapping. The period between the scan signals Scan(n) and Scan(n + 1) can be within about one horizontal period 1H, but embodiments of the present disclosure are not limited thereto. As Figure 5As shown, during the second period ②", based on the gate high voltage VGH of the first emission control signal EM1(n / n+1), the first transistor T1 and the fourth transistor T4 can be turned on and the third transistor T3 can be turned off; based on the gate high voltage VGH of the second emission control signal EM2(n / n+1), the second transistor T2 can be turned off; based on the gate low voltage VGL of the scan signal Scan(n+1), the fifth transistor T5 can be turned on.

[0124] Therefore, the data voltage Vdata can be supplied to the third node N3 through the fifth transistor T5. In addition, when the second transistor T2 is turned off and the first transistor T1 is turned on, the first node N1 and the second node N2 of the driving transistor DT can be connected to each other, so that the gate-source voltage Vgs of the driving transistor DT can be sampled as the threshold voltage Vth of the driving transistor DT through diode connection. In addition, as the fourth transistor T4 is turned on, the initialization voltage VINI can be supplied to the fourth node N4, and the voltage difference "Vdata + Vth - VINI" between the sum of the data voltage Vdata and the threshold voltage Vth of the driving transistor DT and the initialization voltage VINI can be stored in the capacitor C. Therefore, during the second period ②", the voltage of each of the first node N1 and the second node N2 can converge to the voltage that is the sum of the data voltage Vdata and the threshold voltage Vth of the driving transistor DT, the voltage of the third node N3 can be the data voltage Vdata, and the voltage of the fourth node N4 can be the initialization voltage VINI.

[0125] At the time when the fourth period ④ of the (n + 1)-th pixel starts, the scan signal Scan(n+1) can rise and can have the gate high voltage VGH, the first emission control signal EM1(n / n+1) can fall and can have the gate low voltage VGL, and the second emission control signal EM2(n / n+1) can maintain the gate high voltage VGH. As Figure 7 shown, during the fourth period ④, only the third transistor T3 can be turned on, and the first, second, fourth, and fifth transistors T1, T2, T4, and T5 can be turned off. Therefore, the third transistor T3 can be turned on and can be connected to the third node N3 and the fourth node N4, and the data voltage Vdata held by the third node N3 can be supplied to the fourth node N4.

[0126] At the time when the fifth period ⑤ starts, the second emission control signal EM1(n / n+1) can fall and can have the gate low voltage VGL, the first emission control signal EM1(n / n+1) can maintain the gate low voltage VGL, and the scan signal Scan(n+1) can maintain the gate high voltage VGH. As Figure 8As shown, during the fifth interval ⑤, the first, fourth, and fifth transistors T1, T4, and T5 may be turned off, and the second transistor T2 and the third transistor T3 may be turned on. In addition, the driving transistor DT may be turned on by the sum of the threshold voltage Vth of the driving transistor DT and the data voltage Vdata stored in the first node N1, so that a path for the driving current to flow from the first driving voltage VDD line to the light-emitting device ED may be formed. That is, the driving current may flow to the light-emitting device ED through the driving transistor DT, the second transistor T2, and the third transistor T3 that are turned on during the fifth interval ⑤. In addition, in the fifth interval ⑤, the gate-source voltage Vgs of the driving transistor DT may be referred to as the data voltage Vdata, and the threshold voltage Vth of the driving transistor DT may be compensated, so that the level of the driving current may be adjusted based on the level of the data voltage Vdata of the driving transistor DT, and the light-emitting device ED may emit light using the driving current, thereby increasing the brightness.

[0127] Therefore, in the display device according to an embodiment of the present disclosure, TFTs having characteristics suitable for the required performance of the transistors constituting the pixel circuit may be arranged, so that the pixels arranged in the vertically adjacent horizontal rows may share the first light emission control signal and the second light emission control signal. Therefore, low-frequency driving for low-power consumption driving may be performed, and the configuration of the gate driving circuit and the gate lines may be minimized, thereby achieving a narrow bezel and improving power consumption.

[0128] The pixel according to an embodiment of the present disclosure and the display device including the pixel may be described as follows.

[0129] The pixel according to an embodiment of the present disclosure may include: a light-emitting device; and a pixel circuit connected to a first gate control line, a second gate control line, a third gate control line, and the light-emitting device, the pixel circuit including a first node, a second node, a third node, and a fourth node, wherein the pixel circuit includes: a driving transistor connected to the first node to the third node; a first transistor connected to the first gate control line and the first node and the second node; a second transistor connected to the second gate control line, the second node, and a first driving voltage line; a third transistor connected to the first gate control line, the third node, and the fourth node; a fourth transistor connected to the first gate control line, the fourth node, and an initialization voltage line; a fifth transistor connected to the third gate control line, the third node, and a data line; and a storage capacitor provided between the first node and the fourth node.

[0130] In a pixel according to an embodiment of the present disclosure, some of the driving transistor and the first to fifth transistors may have a first conductivity type, and other transistors may have a second conductivity type different from the first conductivity type.

[0131] In a pixel according to an embodiment of the present disclosure, the driving transistor, and the first and fourth transistors may have the first conductivity type, and the second, third, and fifth transistors may have the second conductivity type.

[0132] In a pixel according to an embodiment of the present disclosure, some of the driving transistor and the first to fifth transistors may include an oxide semiconductor layer containing an oxide, and other transistors may include a silicon semiconductor layer containing crystalline silicon.

[0133] In a pixel according to an embodiment of the present disclosure, the driving transistor may include an oxide semiconductor layer having the first conductivity type.

[0134] In a pixel according to an embodiment of the present disclosure, the first and fourth transistors may include an oxide semiconductor layer having the first conductivity type.

[0135] In a pixel according to an embodiment of the present disclosure, the second, third, and fifth transistors may include a silicon semiconductor layer having the second conductivity type.

[0136] In a pixel according to an embodiment of the present disclosure, the pixel circuit may be driven in a first interval, a second interval, a third interval, a fourth interval, and a fifth interval. A signal of the first gate control line may have a first voltage level in the first to third intervals and may have a second voltage level different from the first voltage level in the fourth and fifth intervals. A signal of the second gate control line may have the first voltage level in the second to fourth intervals and may have the second voltage level in the first and fifth intervals. And a signal of the third gate control line may have the first voltage level in the first interval and the third to fifth intervals and may have the second voltage level in the second interval.

[0137] In a pixel according to an embodiment of the present disclosure, the first transistor may be turned on only in the first to third intervals among the first to fifth intervals, the second transistor may be turned on only in the first and fifth intervals among the first to fifth intervals, the third transistor may be turned on only in the fourth and fifth intervals among the first to fifth intervals, the fourth transistor may be turned on only in the first to third intervals among the first to fifth intervals, and the fifth transistor may be turned on only in the second interval among the first to fifth intervals.

[0138] In a pixel according to an embodiment of the present disclosure, the first conductivity type is N-type, and the second conductivity type is P-type.

[0139] A display device according to an embodiment of the present disclosure may include: a display panel including a display area and a non-display area provided near the display area, in which a plurality of pixels are arranged in a first direction and a second direction intersecting the first direction in the display area; and a gate driver provided in the non-display area to provide a scan signal, a first light emission control signal, and a second light emission control signal to each of the plurality of pixels, wherein one or more of the first light emission control signal and the second light emission control signal are shared by two pixels adjacent to each other in the second direction among the plurality of pixels.

[0140] In a display device according to an embodiment of the present disclosure, each of the plurality of pixels may include a pixel circuit including a light emitting device, a driving transistor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a storage capacitor, and some of the driving transistor and the first to fifth transistors may have a first conductivity type, and other transistors may have a second conductivity type different from the first conductivity type.

[0141] In a display device according to an embodiment of the present disclosure, some of the driving transistor and the first to fifth transistors may include an oxide semiconductor layer including an oxide, and other transistors may include a silicon semiconductor layer including crystalline silicon.

[0142] In a display device according to an embodiment of the present disclosure, the driving transistor among the driving transistor and the first to fifth transistors may include an oxide semiconductor layer having the first conductivity type, the first transistor and the fourth transistor may include an oxide semiconductor layer or a silicon semiconductor layer having the first conductivity type, and the second transistor, the third transistor, and the fifth transistor may include a silicon semiconductor layer having the second conductivity type.

[0143] In a display device according to an embodiment of the present disclosure, the gate driver may provide a first light emission control signal, a second light emission control signal, and a scan signal having a first voltage level and a second voltage level different from the first voltage level to each of the plurality of pixels, may provide the shared first light emission control signal and the second light emission control signal to two pixels adjacent to each other in the second direction, and may provide different scan signals to the two pixels.

[0144] In a display device according to an embodiment of the present disclosure, the first light emission control signal and the second light emission control signal may partially overlap in an interval having the first voltage level, and the scan signals provided to the two pixels may not overlap in an interval having the second voltage level.

[0145] In a display device according to an embodiment of the present disclosure, a pixel circuit of each of the plurality of pixels may be driven in a first interval, a second interval, a third interval, a fourth interval, and a fifth interval, and a pixel circuit of each of the two pixels may be driven identically in the first interval, the fourth interval, and the fifth interval among the first interval to the fifth interval, and may be driven differently in the second interval and the third interval.

[0146] In a display device according to an embodiment of the present disclosure, the second interval and the third interval of each of the two pixels may overlap with an interval in which the first light emission control signal and the second light emission control signal have the first voltage level, the second interval of each of the two pixels may be an interval in which each scan signal has the second voltage level in an interval in which the first light emission control signal and the second light emission control signal have the first voltage level, and the third interval of each of the two pixels may be an interval other than the second interval in an interval in which the first light emission control signal and the second light emission control signal have the first voltage level.

[0147] In a display device according to an embodiment of the present disclosure, the first conductivity type is N-type, and the second conductivity type is P-type.

[0148] A display device according to an embodiment of the present disclosure may include: a display panel including a display area and a first non-display area and a second non-display area that are parallel to each other with the display area therebetween, in the display area, an nth pixel and an (n + 1)th pixel are vertically adjacent to each other, where n is an odd number of 1 or greater; a first gate driver that provides a first light emission control signal to the nth pixel and the (n + 1)th pixel in the first non-display area; and a second gate driver that provides a second light emission control signal to the nth pixel and the (n + 1)th pixel in the second non-display area, wherein each of the nth pixel and the (n + 1)th pixel emits light based on the first light emission control signal and the second light emission control signal.

[0149] In a display device according to an embodiment of the present disclosure, the first gate driver may include a first light emission control driving circuit and an nth scan driving circuit, the first light emission control driving circuit provides the first light emission control signal shared by the nth pixel and the (n + 1)th pixel, the nth scan driving circuit provides an nth scan signal to the nth pixel, and the second gate driver may include a second light emission control driving circuit and an (n + 1)th scan driving circuit, the second light emission control driving circuit provides the second light emission control signal shared by the nth pixel and the (n + 1)th pixel, and the (n + 1)th scan driving circuit provides an (n + 1)th scan signal to the (n + 1)th pixel.

[0150] In a display device according to an embodiment of the present disclosure, the first light emission control signal, the second light emission control signal, the nth scan signal, and the (n + 1)th scan signal may have a first voltage level and a second voltage level different from the first voltage level, the first light emission control signal and the second light emission control signal may partially overlap in an interval having the first voltage level, and in an interval where the first light emission control signal and the second light emission control signal overlap in the first voltage level, the nth scan signal and the (n + 1)th scan signal may have non-overlapping second voltage levels.

[0151] In a pixel according to an embodiment of the present disclosure and a display device including the pixel, the number of gate control signals required for a pixel driving circuit may be reduced by sharing gate control signals in adjacent horizontal rows. Therefore, a narrow bezel may be achieved and power consumption may be reduced.

[0152] It will be apparent to those skilled in the art that the above disclosure is not limited by the above embodiments and drawings, and various substitutions, modifications and changes can be made in the disclosure without departing from the spirit and scope of the disclosure. Therefore, the scope of the disclosure is defined by the appended claims, and all variations or modifications derived from the meaning, scope and equivalent concepts of the claims fall within the scope of the disclosure.

Claims

1. A display device, comprising: a display panel, the display panel including a display area and a non-display area disposed near the display area, the display area including a plurality of pixels arranged along a first direction and a second direction intersecting the first direction; and a gate driver, the gate driver being disposed in the non-display area, the gate driver including: a scan driving circuit disposed adjacent to the display area; and a light emission control driving circuit disposed farther from the display area than the scan driving circuit, wherein the scan driving circuit is configured to receive at least one first clock signal and provide scan signals to the pixels arranged in at least one horizontal row parallel to the first direction among the plurality of pixels, and wherein the light emission control driving circuit is configured to receive at least one second clock signal different from the at least one first clock signal and provide light emission control signals to the pixels in one or more horizontal rows parallel to the first direction among the plurality of pixels.

2. The display device according to claim 1, wherein the scan driving circuit is disposed between the display area and the light emission control driving circuit.

3. The display device according to claim 1, wherein the scan driving circuit and the light emission control driving circuit share the same driving voltage.

4. The display device according to claim 1, wherein the light emission control driving circuit is configured to provide the light emission control signal to two adjacent pixels among the plurality of pixels in the second direction.

5. The display device according to claim 1, wherein the light emission control driving circuit is configured to provide the shared light emission control signal to two adjacent pixels among the plurality of pixels in the second direction.

6. The display device according to claim 1, wherein each of the plurality of pixels includes: a light emitting device; and a pixel circuit, the pixel circuit being connected to a first gate control line, a second gate control line, a third gate control line, and the light emitting device, wherein the pixel circuit of each of the plurality of pixels is driven in a first interval, a second interval, a third interval, a fourth interval, and a fifth interval, and wherein the pixel circuits of two adjacent pixels among the plurality of pixels in the second direction are driven identically in the first interval, the fourth interval, and the fifth interval among the first interval to the fifth interval, and are driven differently in the second interval and the third interval.

7. The display device according to claim 6, wherein: the pixel circuit includes a driving transistor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a storage capacitor, some of the driving transistor and the first transistor to the fifth transistor have a first conductivity type, and other transistors have a second conductivity type different from the first conductivity type.

8. The display device according to claim 7, wherein some of the driving transistor and the first to fifth transistors include an oxide semiconductor layer containing an oxide, and the other transistors include a silicon semiconductor layer containing crystalline silicon.

9. The display device according to claim 8, wherein: the driving transistor among the driving transistor and the first to fifth transistors includes an oxide semiconductor layer of a first conductivity type; the first transistor and the fourth transistor include an oxide semiconductor layer or a silicon semiconductor layer of the first conductivity type; and the second transistor, the third transistor, and the fifth transistor include a silicon semiconductor layer of a second conductivity type.

10. The display device according to claim 6, wherein the scan signal and the light emission control signal have a first voltage level and a second voltage level different from the first voltage level.

11. The display device according to claim 10, wherein: the second interval and the third interval of each of the two pixels overlap with an interval in which a first light emission control signal and a second light emission control signal have the first voltage level; the second interval of each of the two pixels is an interval in which each scan signal has the second voltage level in the interval in which the first light emission control signal and the second light emission control signal have the first voltage level; and the third interval of each of the two pixels is an interval other than the second interval in the interval in which the first light emission control signal and the second light emission control signal have the first voltage level.

12. The display device according to claim 6, wherein the pixel circuit includes a first node, a second node, a third node, and a fourth node, and the pixel circuit includes: a driving transistor connected to the first to third nodes; a first transistor connected to the first gate control line and the first and second nodes; a second transistor connected to the second gate control line, the second node, and a first driving voltage line; a third transistor connected to the first gate control line, the third node, and the fourth node; a fourth transistor connected to the first gate control line, the fourth node, and an initialization voltage line; a fifth transistor connected to the third gate control line, the third node, and a data line; and a storage capacitor between the first node and the fourth node.

13. The display device according to claim 12, wherein: the signal of the first gate control line has a first voltage level in the first to third intervals and a second voltage level different from the first voltage level in the fourth and fifth intervals, The signal of the second gate control line has the first voltage level in the second interval to the fourth interval and has the second voltage level in the first interval and the fifth interval, and the signal of the third gate control line has the first voltage level in the first interval and the third interval to the fifth interval, and has the second voltage level in the second interval.

14. The display device according to claim 13, wherein: The first transistor is turned on only in the first interval to the third interval among the first interval to the fifth interval; The second transistor is turned on only in the first interval and the fifth interval among the first interval to the fifth interval; The third transistor is turned on only in the fourth interval and the fifth interval among the first interval to the fifth interval; The fourth transistor is turned on only in the first interval to the third interval among the first interval to the fifth interval; and The fifth transistor is turned on only in the second interval among the first interval to the fifth interval.

15. The display device according to claim 1, wherein: The non-display area includes a first non-display area and a second non-display area that are parallel to each other with the display area therebetween; and The gate driver includes a first gate driver and a second gate driver that are symmetric to each other with the display area therebetween.

16. The display device according to claim 15, wherein: The first gate driver is disposed in the first non-display area, and the first gate driver includes a first scan driving circuit and a first light emission control driving circuit. The first scan driving circuit is connected to the pixels arranged in the odd horizontal rows, and the first light emission control driving circuit provides a first light emission control signal to the pixels arranged in the odd horizontal rows and the even horizontal rows adjacent to each other; and The second gate driver is disposed in the second non-display area, and the second gate driver includes a second scan driving circuit and a second light emission control driving circuit. The second scan driving circuit is connected to the pixels arranged in the even horizontal rows, and the second light emission control driving circuit provides a second light emission control signal different from the first light emission control signal to the pixels arranged in the odd horizontal rows and the even horizontal rows adjacent to each other.

17. The display device according to claim 16, wherein the first scan driving circuit and the second scan driving circuit are alternately disposed in the first non-display area and the second non-display area.

18. The display device according to claim 16, wherein the first scan driving circuit and the second scan driving circuit are alternately driven in the odd horizontal rows and the even horizontal rows.

19. The display device according to claim 16, wherein: The first light emission control signal and the second light emission control signal have a first voltage level and a second voltage level different from the first voltage level; and The first light emission control signal and the second light emission control signal partially overlap in an interval having the first voltage level.

20. The display device according to claim 19, wherein: different scan signals output from each of the first scan driving circuit and the second scan driving circuit have the first voltage level and the second voltage level; and in an interval in which the first light emission control signal and the second light emission control signal overlap in the first voltage level, the different scan signals have non-overlapping second voltage levels.

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