Noise reduction circuit, gate drive circuit and display panel

Abstract

The present application belongs to the field of display drive technology, and specifically relates to a noise reduction circuit, a gate drive circuit and a display panel. The noise reduction circuit includes: a noise reduction control unit, a threshold compensation unit and a noise reduction execution unit; the noise reduction control unit is used to output a noise reduction signal during the non-scanning time of the scanning phase of the current-level gate drive module under the action of the noise reduction control signal output by the noise reduction control end and the voltage on the drive control node; the threshold compensation unit is used to compensate the noise reduction signal according to the threshold voltage of the transistor in the noise reduction execution unit to obtain a noise reduction compensation signal; the present application compensates the noise reduction control signal according to the threshold voltage of the transistor in the noise reduction execution unit through the threshold compensation unit, thereby improving the problem of unstable noise reduction caused by the threshold voltage drift of the noise reduction transistor and improving the noise reduction stability of the noise reduction circuit.

Description

Technical Field

[0001] The present disclosure belongs to the field of display drive technology, and particularly relates to a noise reduction circuit, a gate drive circuit, and a display panel. Background Art

[0002] TFT-LCDs (Thin-Film Transistor Liquid Crystal Displays) display images by controlling the transmittance of pixels in the display area. Specifically, under the action of an applied voltage, the liquid crystal molecules within a single pixel deflect, thereby changing the transmittance and displaying color. The display area is composed of pixels arranged in an array, and dynamic display is achieved by switching the pixel state frame by frame.

[0003] The Gate Driver on Array (GOA) is a key circuit for TFT-LCDs to achieve progressive scanning. The noise reduction circuit, which performs noise reduction on key nodes, is the core module for the reliable operation of the GOA. However, the noise reduction transistors in the noise reduction circuit are often biased at a positive gate-source voltage (Vgs) for a long time during operation, which can easily cause the threshold voltage (Vth) of the noise reduction transistor to drift. This leads to unstable noise reduction and abnormal GOA output signals, affecting the display quality of the display panel.

[0004] Therefore, how to improve the threshold voltage drift of the noise reduction transistor that causes noise reduction instability is a problem that the current baseband needs to solve. Summary of the Invention

[0005] An embodiment of the present application provides a noise reduction circuit, a gate drive circuit, and a display panel, wherein a threshold compensation unit compensates a noise reduction control signal according to the threshold voltage of a transistor in a noise reduction execution unit, thereby improving the problem of unstable noise reduction caused by threshold voltage drift of the noise reduction transistor and improving the noise reduction stability of the noise reduction circuit.

[0006] In a first aspect, an embodiment of the present application provides a noise reduction circuit, which is applied to a gate drive circuit, wherein the gate drive circuit includes N cascaded gate drive modules, and the n-th level gate drive module includes at least a drive control node, a drive output terminal, a level transmission output terminal and a noise reduction circuit, and the noise reduction circuit includes: a noise reduction control unit, a threshold compensation unit and a noise reduction execution unit; the first control terminal of the noise reduction control unit is connected to the noise reduction control terminal, and the second control terminal of the noise reduction control unit is connected to the drive control node, and the noise reduction control unit is used to output the noise reduction control signal from the noise reduction control terminal and the voltage on the drive control node under the action of the noise reduction control signal. , outputting a noise reduction signal during the non-scanning time of the scanning phase of the current-level gate driving module; the threshold compensation unit is respectively connected to the output end of the noise reduction control unit and the noise reduction execution unit, and the threshold compensation unit is used to compensate the noise reduction signal according to the threshold voltage of the transistor in the noise reduction execution unit to obtain a noise reduction compensation signal; the output end of the noise reduction execution unit is respectively connected to the drive control node, the drive output end and the stage transmission output end, and the noise reduction execution unit is used to perform noise reduction processing on the voltages on the drive control node, the drive output end and the stage transmission output end according to the noise reduction compensation signal.

[0007] Optionally, the noise reduction control unit includes: a first transistor, the control end of the first transistor is connected to the noise reduction control end, and the first end of the first transistor is connected to the control end of the first transistor; a second transistor, the control end of the second transistor is connected to the second end of the first transistor, and the first end of the second transistor is connected to the first end of the first transistor; a third transistor, the control end of the third transistor is connected to the drive control node of the n-th level gate drive module, the first end of the third transistor is connected to the second end of the first transistor, and the second end of the third transistor is connected to the first low-level end; and a fourth transistor, the control end of the fourth transistor is connected to the control end of the third transistor, the first end of the fourth transistor is connected to the second end of the second transistor, and the second end of the fourth transistor is connected to the first low-level end.

[0008] Optionally, the noise reduction control unit further includes: a fifth transistor, the control end of the fifth transistor being connected to the drive control node of the n+h-th level gate drive module, the first end of the fifth transistor being connected to the second end of the first transistor, and the second end of the fifth transistor being connected to the first low-level end; and a sixth transistor, the control end of the sixth transistor being connected to the control end of the fifth transistor, the first end of the sixth transistor being connected to the second end of the second transistor, and the second end of the sixth transistor being connected to the first low-level end.

[0009] Optionally, the noise reduction execution unit includes: a seventh transistor, the control end of the seventh transistor is connected to the threshold compensation unit, the first end of the seventh transistor is connected to the drive output end, and the second end of the seventh transistor is connected to the first low-level end; an eighth transistor, the control end of the eighth transistor is connected to the control end of the seventh transistor, the first end of the eighth transistor is connected to the drive control node, and the second end of the eighth transistor is connected to the first low-level end; a ninth transistor, the control end of the ninth transistor is connected to the control end of the seventh transistor, the first end of the seventh transistor is connected to the stage transmission output end, and the second end of the seventh transistor is connected to the second low-level end.

[0010] Optionally, the threshold compensation unit includes: a storage capacitor, a first end of the storage capacitor is connected to the output end of the noise reduction control unit, and is used to couple the noise reduction signal; a compensation subunit, the compensation subunit is respectively connected to the second end of the storage capacitor and the noise reduction execution unit, and is used to compensate the noise reduction signal according to the threshold voltage of the transistor in the noise reduction execution unit.

[0011] Optionally, the compensation subunit includes: a tenth transistor, the control end of the tenth transistor is connected to the level transmission output end of the n+j-th level gate driving module, and the first end of the tenth transistor is connected to the level transmission output end of the n+k-th level gate driving module; an eleventh transistor, the control end of the eleventh transistor is connected to the second end of the tenth transistor, the first end of the eleventh transistor is connected to the control end of the eleventh transistor, and the second end of the eleventh transistor is connected to the second end of the storage capacitor; a twelfth transistor, the control end of the twelfth transistor is connected to the control end of the tenth transistor, and the first end of the twelfth transistor is connected to the level transmission output end of the n+1-th level gate driving module; a thirteenth transistor, the control end of the thirteenth transistor is connected to the second end of the twelfth transistor, the first end of the thirteenth transistor is connected to the second end of the eleventh transistor, and the second end of the thirteenth transistor is connected to the first end of the seventh transistor.

[0012] Optionally, a size of the eleventh transistor is larger than a size of the thirteenth transistor.

[0013] Optionally, a first low level output by the first low level end is smaller than or greater than a second low level output by the second low level end.

[0014] In a second aspect, an embodiment of the present application provides a gate drive circuit, comprising N cascaded gate drive modules, the nth-level gate drive module comprising: a pull-up unit, the pull-up unit being respectively connected to the drive output terminal of the ni-th-level gate drive module and the level transmission output terminal of the ni-th-level gate drive module; a pull-down unit, the pull-down unit being connected to the level transmission output terminal of the n+j-th-level gate drive module, and the pull-down unit being further connected to the pull-up unit through a drive control node; an output unit, the output unit being respectively connected to the clock signal terminal and the drive control node; and a noise reduction circuit, the noise reduction circuit being respectively connected to the drive control node, the drive output terminal and the level transmission output terminal of the current-level gate drive module.

[0015] In a third aspect, an embodiment of the present application provides a display panel comprising a display area and a non-display area, wherein the display area comprises a plurality of scan lines; the non-display area comprises a gate drive circuit, and a drive output end of a circuit unit in the gate drive circuit is electrically connected to at least one scan line.

[0016] The technical solutions provided in the embodiments of the present application have at least the following beneficial effects:

[0017] In the embodiment of the present application, a threshold compensation unit is used to compensate the noise reduction signal output by the noise reduction control unit according to the threshold voltage of the transistor in the noise reduction execution unit, so that the noise reduction compensation signal includes the threshold voltage of the noise reduction transistor. Even if the threshold voltage drifts severely, the noise reduction compensation signal can still turn on the transistor in the noise reduction execution unit, so that the noise reduction circuit can still maintain normal operation, thereby avoiding the problem of the gate drive circuit failing due to the threshold voltage drift. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0019] Figure 1 Shown is a structural schematic diagram of a gate drive module provided in an embodiment of the present application.

[0020] Figure 2 FIG. 1 is a circuit diagram of a noise reduction circuit in related art.

[0021] Figure 3 Shown Figure 2 Driving timing diagram of the noise reduction circuit.

[0022] Figure 4Shown is a structural schematic diagram of a noise reduction circuit provided in an embodiment of the present application.

[0023] Figure 5 Shown is a circuit schematic diagram of a noise reduction circuit provided in an embodiment of the present application.

[0024] Figure 6 The figure shows a driving timing diagram provided in an embodiment of the present application.

[0025] Figure 7 Shown Figure 6 A partial enlarged view of point A in the middle.

[0026] Description of reference numerals:

[0027] 100, noise reduction circuit; 110, noise reduction control unit; 120, threshold compensation unit; 121, compensation subunit; 130, noise reduction execution unit;

[0028] T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; T10, tenth transistor; T11, eleventh transistor; T12, twelfth transistor; T13, thirteenth transistor; C, storage capacitor;

[0029] Qn, drive control node; P1n, first noise reduction control node; P2n, second noise reduction control node; Fn, stage transmission output terminal; Gn, drive output terminal; LC, noise reduction control terminal; VSS1, first low level terminal; VSS2, second low level terminal. DETAILED DESCRIPTION

[0030] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art.

[0031] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner.In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps etc. can be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0032] The present application is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0033] The inventors of this application have found that the gate drive circuit includes N cascaded gate drive modules, such as Figure 1 As shown, the n-th level gate driving module mainly includes a pull-up unit, a pull-down unit, an output unit, a reset unit and a noise reduction circuit. The pull-up unit and the pull-down unit output a Q-point voltage. The pull-up unit and the pull-down unit need to obtain multiple level transmission signals from the upper and lower gate driving modules. The Q-point voltage is the turn-on voltage of the output unit, so that the output unit outputs a gate driving signal to provide a turn-on voltage for the display area. The reset unit is used to avoid the influence between frames. The noise reduction circuit performs noise reduction processing on the signals at each key node; wherein Qn represents the driving control node of the n-th level gate driving module, Gn represents the driving output terminal of the n-th level gate driving module, Fn represents the level transmission output terminal of the n-th level gate driving module, CKn represents the clock signal terminal of the n-th level gate driving module, Reset represents the reset signal terminal, LC represents the noise reduction control terminal, Gn-3 represents the driving output terminal of the n-3-th level gate driving module, Fn-3 represents the level transmission output terminal of the n-3-th level gate driving module and Fn+4 represents the level transmission output terminal of the n+4-th level gate driving module.

[0034] The normal output of the gate drive module is a necessary condition to ensure the normal display of the picture, so the noise reduction circuit is particularly important for suppressing the noise of the signal. Figure 2 FIG. 1 is a circuit diagram of a noise reduction circuit in the related art. Figure 3 for Figure 2 Driving timing diagram of the noise reduction circuit; Figure 2 The first transistor T1 and the second transistor T2 are control transistors, and the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are noise reduction transistors; Figure 2 and Figure 3 As shown, the unit composed of the first transistor T1 and the second transistor T2 mainly inverts the potential of the driving control node Qn to obtain the potential of the noise reduction control node Pn. The voltage on the noise reduction control node Pn turns on the third transistor T3, the fourth transistor T4, and the fifth transistor T5 to perform noise reduction processing on the driving output terminal Gn, the driving control node Qn, and the stage transmission output terminal Fn, respectively. The specific working process is as follows:

[0035] When the drive control node Qn (i.e., point Q) in the n-th stage gate driver module is at a low level, the noise reduction control terminal LC continuously outputs a high level. At this time, the first transistor T1 is turned on and the second transistor T2 is turned off, causing the noise reduction control node Pn to be at a high level. The third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned on respectively, thereby continuously pulling down the signals on the drive output terminal Gn, the drive control node Qn, and the stage transmission output terminal Fn, thereby achieving noise reduction processing for each important node in the gate driver module. Since the drive output terminal, the drive control node, and the stage transmission output terminal in each stage gate driver module do not perform noise reduction only during the scanning time of the current stage, and all other times are noise reduction processing time periods, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 in the noise reduction circuit need to be in a positive gate-source voltage bias state for a long time, which can easily cause the threshold voltage (Vth) of the noise reduction transistor to drift, thereby causing the output signal of the GOA circuit to be abnormal, affecting the display effect of the display panel.

[0036] In order to improve the threshold voltage drift problem of the noise reduction transistor, the present application provides a noise reduction circuit, which specifically includes the following embodiments:

[0037] Figure 4 FIG. 1 is a schematic structural diagram of a noise reduction circuit provided in an embodiment of the present application; the noise reduction circuit 100 of this embodiment is applied to a gate drive circuit, and the gate drive circuit includes N cascaded gate drive modules; Figure 1 As shown, each gate driving module at least includes a driving control node Qn, a driving output terminal Gn, a stage transmission output terminal Fn and a noise reduction circuit 100; Figure 4 As shown, the noise reduction circuit 100 includes a noise reduction control unit 110 , a threshold compensation unit 120 and a noise reduction execution unit 130 .

[0038] In this embodiment, the first control end of the noise reduction control unit 110 is connected to the noise reduction control end LC, and the second control end of the noise reduction control unit 110 is connected to the drive control node Qn, and is configured to output a noise reduction signal during the non-scanning time of the scanning phase of the current-level gate drive module under the action of the noise reduction control signal output by the noise reduction control end LC and the voltage on the drive control node Qn.

[0039] It should be noted that in the driving technology of display panels, the scanning stage and the blanking stage are key points in timing control. The two together ensure that pixel data is correctly updated and the display is stable. The scanning stage is the stage in which the gate drive circuit activates pixels row by row and writes data. For example, in a display that scans row by row, the gate drive signal selects each row of pixels from top to bottom in turn, and writes the voltage signal to the pixel unit of that row through the data line. The blanking stage is the "interval period" between scans, when the drive circuit stops writing data to switch rows or frames to prevent signal overlap and display distortion.

[0040] In this embodiment, the non-scanning time of the current-stage gate driving module represents the non-scanning time of the current stage in the scanning phase; that is, under the combined action of the noise reduction control signal output by the noise reduction control terminal LC and the voltage on the drive control node Qn, the noise reduction control unit 110 in the n-stage gate driving module outputs the noise reduction signal in the non-scanning time period in the scanning phase of the n-stage gate driving module, and does not output the noise reduction signal in the scanning time period of the n-stage gate driving module.

[0041] In this embodiment, the threshold compensation unit 120 is connected to the output end of the noise reduction control unit 110 and the noise reduction execution unit 130 respectively. The threshold compensation unit 120 is used to compensate the noise reduction signal according to the threshold voltage of the transistor in the noise reduction execution unit 130 to obtain a noise reduction compensation signal.

[0042] In this embodiment, the output end of the noise reduction execution unit 130 is connected to the driving control node Qn, the driving output end Gn and the stage transmission output end Fn, respectively, and is used to perform noise reduction processing on the voltages on the driving control node Qn, the driving output end Gn and the stage transmission output end Fn according to the noise reduction compensation signal.

[0043] It should be noted that, in this embodiment, noise reduction processing is performed on the voltages on the drive control node Qn, the drive output terminal Gn, and the stage transmission output terminal Fn according to the noise reduction compensation signal. That is, the noise reduction execution unit 130 continuously pulls down the signals on the drive output terminal Gn, the drive control node Qn, and the stage transmission output terminal Fn, thereby preventing leakage current in the circuit or other transistor abnormalities from causing the voltages on the drive output terminal Gn, the drive control node Qn, and / or the stage transmission output terminal Fn to be at a high level, thereby causing display abnormalities such as pixel mischarging.

[0044] The present application uses a threshold compensation unit to compensate the noise reduction signal output by the noise reduction control unit according to the threshold voltage of the transistor in the noise reduction execution unit, so that the noise reduction compensation signal includes the threshold voltage of the noise reduction transistor. Even if the threshold voltage drifts severely, the noise reduction compensation signal can still turn on the transistor in the noise reduction execution unit, so that the noise reduction circuit can still maintain normal operation, improving the problem of unstable noise reduction caused by the threshold voltage drift of the noise reduction transistor, and improving the noise reduction stability of the noise reduction circuit.

[0045] Figure 5 FIG. 1 is a circuit diagram of a noise reduction circuit provided in an embodiment of the present application, as shown in FIG. Figure 5 As shown, the noise reduction control unit 110 includes a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4; wherein the control end of the first transistor T1 is connected to the noise reduction control end LC, and the first end of the first transistor T1 is connected to the control end of the first transistor T1; the control end of the second transistor T2 is connected to the second end of the first transistor T1, and the first end of the second transistor T2 is connected to the first end of the first transistor T1; the control end of the third transistor T3 is connected to the driving control node Qn of the current-stage gate driving module, the first end of the third transistor T3 is connected to the second end of the first transistor T1, and the second end of the third transistor T3 is connected to the first low-level end VSS1; the control end of the fourth transistor T4 is connected to the control end of the third transistor T3, the first end of the fourth transistor T4 is connected to the second end of the second transistor T2, and the second end of the fourth transistor T4 is connected to the first low-level end VSS1.

[0046] It should be noted that the main purpose of the noise reduction control unit 110 of this embodiment is to invert the voltage on the current stage driving control node Qn, that is, when the voltage on the driving control node Qn is high, the noise reduction control unit 110 outputs a low-level voltage, and when the voltage on the driving control node Qn is low, the noise reduction control unit 110 outputs a high-level voltage; Figure 6 The timing diagram of the noise reduction control unit 110 is used to illustrate the specific working principle of the noise reduction control unit 110:

[0047] (1) When the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 are all N-type MOS transistors, the noise reduction control terminal LC always outputs a high level in the scanning phase, and the first transistor T1 is continuously turned on.

[0048] (2) During the scanning time of the current-stage gate driving module, the voltage on the driving control node Qn is at a high level, and the third transistor T3 and the fourth transistor T4 are turned on at the same time, so that the voltages on the node An and the first noise reduction control node P1n are both at the first low level output by the first low-level terminal VSS1, thereby turning off the second transistor T2 and the noise reduction control unit 110 outputting the first low level, that is, the voltage on the first noise reduction control node P1n is at the first low level, as shown in FIG. Figure 6 The Gn waveform and P1n waveform in .

[0049] (3) During the non-scanning time of the scanning phase of the current-stage gate driving module, the voltage on the current-stage driving control node Qn is at a low level, and the third transistor T3 and the fourth transistor T4 are turned off at the same time. Then, the voltage on the node An is at a high level, thereby turning on the second transistor T2. The noise reduction control unit 110 outputs a high level, which is the noise reduction signal. That is, at this time, the voltage on the first noise reduction control node P1n is at a high level.

[0050] In another embodiment, Figure 5 As shown, the noise reduction control unit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6; wherein, the control end of the first transistor T1 is connected to the noise reduction control end LC, and the first end of the first transistor T1 is connected to the control end of the first transistor T1; the control end of the second transistor T2 is connected to the second end of the first transistor T1, and the first end of the second transistor T2 is connected to the first end of the first transistor T1; the control end of the third transistor T3 is connected to the driving control node Qn of the current-stage gate driving module, the first end of the third transistor T3 is connected to the second end of the first transistor T1, and the second end of the third transistor T3 is connected to the first low-level end VSS1; the control end of the fourth transistor T4 is connected to the control end of the third transistor T3, the first end of the fourth transistor T4 is connected to the second end of the second transistor T2, and the second end of the fourth transistor T4 is connected to the first low-level end VSS1.

[0051] In this embodiment, the control end of the fifth transistor T5 is connected to the drive control node of the n+h-th level gate drive module, the first end of the fifth transistor T5 is connected to the second end of the first transistor T1, and the second end of the fifth transistor T5 is connected to the first low-level end VSS1; the control end of the sixth transistor T6 is connected to the control end of the fifth transistor T5, the first end of the sixth transistor T6 is connected to the second end of the second transistor T2, and the second end of the sixth transistor T6 is connected to the first low-level end VSS1.

[0052] It should be noted that the main purpose of the noise reduction control unit 110 provided in this embodiment is to invert the voltage on the drive control node Qn of the current-stage gate drive module and the voltage on the drive control node of the n+h-stage gate drive module. That is to say, if the voltage on either the current-stage drive control node Qn or the n+h-stage drive control node Qn+h is high, the noise reduction control unit 110 outputs a low level; if the voltage on the current-stage drive control node Qn and the n+h-stage drive control node Qn+h are both low, the noise reduction control unit 110 outputs a high level. Therefore, the voltage inversion method of the two-stage drive control nodes adopted in this embodiment can extend the time period during which the first noise reduction control node P1n is at a low potential, thereby delaying its pull-up, thereby gaining sufficient time for the threshold voltage extraction process and improving the accuracy of compensation.

[0053] Here, combined Figure 6 The specific working principle of the noise reduction control unit 110 of this embodiment is described as follows:

[0054] (1) When the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are all N-type MOS transistors, the noise reduction control terminal LC always outputs a high level in the scanning phase, and the first transistor T1 is continuously turned on.

[0055] (2) During the scanning time of the current-stage gate driving module (i.e., the n-th-stage gate driving module), the voltage on the driving control node Qn is at a high level, and the third transistor T3 and the fourth transistor T4 are turned on at the same time, so that the voltages on the node An and the first noise reduction control node P1n are both at the first low level output by the first low-level terminal VSS1, thereby turning off the second transistor T2, and the noise reduction control unit 110 outputs the first low level, that is, the voltage on the first noise reduction control node P1n is at the first low level, as shown in FIG. Figure 6 The Gn waveform and P1n waveform in .

[0056] (3) During the scanning time of the n+h-th gate driving module, the voltage on the n+h-th driving control node Qn+h is at a high level, and the fifth transistor T5 and the sixth transistor T6 are turned on at the same time, so that the voltages on the node An and the first noise reduction control node P1n are both at the first low level output by the first low level terminal VSS1, thereby turning off the second transistor T2, and the noise reduction control unit 110 outputs the first low level, that is, the voltage on the first noise reduction control node P1n is at the first low level, as shown in FIG. Figure 6 The Gn+h waveform and P1n waveform in .

[0057] (4) During the non-scanning time shared by the current-stage gate driving module and the n+h-stage gate driving module, the voltages on the current-stage driving control node Qn and the n+h-stage driving control node Qn+h are both low. At this time, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off, and the voltage on the node An is high, thereby turning on the second transistor T2. The noise reduction control unit 110 outputs a high level, which is a noise reduction signal. That is, at this time, the voltage on the first noise reduction control node P1n is high.

[0058] It should also be noted that the above working principle is described using the example where the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are all N-type MOS transistors. When the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are P-type transistors, the working principle is the same but the driving timing is opposite, which will not be repeated here.

[0059] like Figure 5 As shown, the noise reduction execution unit 130 of this embodiment includes a seventh transistor T7, an eighth transistor T8 and a ninth transistor T9; specifically, the control end of the seventh transistor T7 is connected to the threshold compensation unit 120, the first end of the seventh transistor T7 is connected to the driving output end Gn, and the second end of the seventh transistor T7 is connected to the first low-level end VSS1; the control end of the eighth transistor T8 is connected to the control end of the seventh transistor T7, the first end of the eighth transistor T8 is connected to the driving control node Qn, and the second end of the eighth transistor T8 is connected to the first low-level end VSS1; the control end of the ninth transistor T9 is connected to the control end of the seventh transistor T7, the first end of the seventh transistor T7 is connected to the stage transmission output end Fn, and the second end of the seventh transistor T7 is connected to the second low-level end VSS2.

[0060] It should be noted that, taking the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 as N-type MOS transistors as an example, the working principle of the noise reduction execution unit 130 is described in detail:

[0061] (1) When the threshold compensation unit 120 outputs the noise reduction compensation signal, that is, the voltage on the second noise reduction control node P2n is at a high level, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned on at the same time, so that the voltage on the driving output terminal Gn is pulled down to a first low level through the turned-on seventh transistor T7, the voltage on the driving control node Qn of the current stage is pulled down to the first low level through the turned-on eighth transistor T8, and the voltage on the stage transmission output terminal Fn of the current stage is pulled down to a second low level through the turned-on ninth transistor T9; optionally, by adjusting the voltage values of the first low level and the second low level respectively, the leakage current of the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 can be reduced, thereby improving the stability of the voltage on the second noise reduction control node P2n.

[0062] (2) When the threshold compensation unit 120 does not output the noise reduction compensation signal, that is, the voltage on the second noise reduction control node P2n is at a low level, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned off at the same time, and the noise reduction processing of the voltages on the current stage driving control node Qn, the driving output terminal Gn, and the stage transmission output terminal Fn is stopped.

[0063] like Figure 5 As shown, the threshold compensation unit 120 provided in this embodiment includes a storage capacitor C and a compensation sub-unit 121; wherein, the first end of the storage capacitor C is connected to the output end of the noise reduction control unit 110 for coupling the noise reduction signal; the compensation sub-unit 121 is respectively connected to the second end of the storage capacitor C and the noise reduction execution unit 130 for compensating the noise reduction control signal according to the threshold voltage of the transistor in the noise reduction execution unit 130.

[0064] It should be noted that, in this embodiment, the first end of the storage capacitor C is defined as the first noise reduction control node P1n, and the second end of the storage capacitor C is defined as the second noise reduction control node P2n. The noise reduction control unit 110 and the noise reduction execution unit 130 are connected in series through the storage capacitor C, so that the noise reduction signal on the first noise reduction control node P1n is coupled to the second noise reduction control node P2n through the storage capacitor C.

[0065] In this embodiment, the compensation subunit 121 includes a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13. The control end of the tenth transistor T10 is connected to the stage transmission output end of the (n+j)-th stage gate driving module, and the first end of the tenth transistor T10 is connected to the stage transmission output end of the (n+k)-th stage gate driving module; the control end of the eleventh transistor T11 is connected to the second end of the tenth transistor T10, the first end of the eleventh transistor T11 is connected to the control end of the eleventh transistor T11, and the second end of the eleventh transistor T11 is connected to the second end of the storage capacitor C; the control end of the twelfth transistor T12 is connected to the control end of the tenth transistor T10, and the first end of the twelfth transistor T12 is connected to the stage transmission output end of the (n+1)-th stage gate driving module; the control end of the thirteenth transistor T13 is connected to the second end of the twelfth transistor T12, the first end of the thirteenth transistor T13 is connected to the second end of the eleventh transistor T11, and the second end of the thirteenth transistor T13 is connected to the first end of the seventh transistor T7.

[0066] It should be noted that Figure 5 Where Qn+h represents the driving control node of the n+h-th gate driving module, Fn+j represents the level transmission output terminal of the n+j-th gate driving module, Fn+k represents the level transmission output terminal of the n+k-th gate driving module, and Fn+l represents the level transmission output terminal of the n+l-th gate driving module. According to the connection mode of the tenth transistor T10 and the eleventh transistor T11, when the level transmission output terminal of the n+j-th gate driving module and the level transmission output terminal of the n+k-th gate driving module simultaneously output a high level, the potential of the node Bn is pulled high by the turned-on tenth transistor T10, and the potential of the second noise reduction control node P2n is then pulled high by the turned-on eleventh transistor T11. Because the eleventh transistor T11 is unidirectionally connected, the charge on the second noise reduction control node P2n will not be discharged through the eleventh transistor T11.

[0067] In addition, according to the connection method of the twelfth transistor T12 and the thirteenth transistor T13, when the stage transmission output terminal of the n+j-th stage gate driving module and the stage transmission output terminal of the n+1-th stage gate driving module simultaneously output a high level, the potential of the node Cn is pulled high by the turned-on twelfth transistor T12, and then the second noise reduction control node P2n and the driving output terminal Gn of the current stage are connected through the turned-on thirteenth transistor T13.

[0068] It can be seen that this embodiment requires the use of timing coordination control on Qn+h, Fn+j, Fn+k and Fn+l. Here, taking the driving mechanism of 12CK, -6+6 stage transmission, and 5.5hCK width as an example, i=6, j=6, and according to the logic definition of h=3, k=2 and l=3 in this embodiment, the following is obtained: Figure 6 The timing diagram shown; combined with Figure 6 Timing diagram and Figure 7 The working principle of the noise reduction circuit of this embodiment is explained as follows:

[0069] (1) If Figure 6 and Figure 7 It can be seen that the potential on the first noise reduction control node P1n is controlled by the potentials on the nodes Qn and Qn+3 at the same time, so that the low potential on the first noise reduction control node P1n lasts until Figure 7 Start pulling up after the t3 period;

[0070] (2) The potentials on Fn+6 and Fn+2 jointly determine the potential of node Bn at time t1 to be high through the tenth transistor T10. Then, the high level of node Bn turns on the eleventh transistor T11, thereby raising the potential of the second noise reduction control node P2n.

[0071] (3) The potentials on Fn+6 and Fn+3 jointly determine the potential of the node Cn at times t1 and t2 to be high through the twelfth transistor T12, and to be low at time t3; when the node Cn is at a high level, the thirteenth transistor T13 is turned on, so that the control terminal of the seventh transistor T7 and the first terminal of the seventh transistor T7 are turned on, and discharge is directed to the first low-level terminal VSS1;

[0072] (4) At time t1, the eleventh transistor T11 charges the second noise reduction control node P2n, and at times t1 and t2, the second noise reduction control node P2n is discharged through the seventh transistor T7. Since the size of the eleventh transistor T11 is smaller than the tenth transistor T10, at time t1, although the second noise reduction control node P2n is undergoing both charging and discharging processes, the potential of the second noise reduction control node P2n is gradually increased. After time t1, at time t2, the second noise reduction control node P2n only retains the discharge path of the eleventh transistor T11 and the seventh transistor T7. At this time, the final discharged voltage is the threshold voltage of the seventh transistor T7 plus the first low level (i.e., Vss1+Vth). At time t3, the potential of the node Cn is pulled down, turning off the thirteenth transistor T13, so that the voltage of the second noise reduction control node P2n is in a floating state after the t3 period.

[0073] (5) After the period t3, the potential of the first noise reduction control node P1n rises (the rising potential is ΔV). Under the influence of the coupling of the storage capacitor C, the potential of the second control node P2n also rises by ΔV, so that the potential of the second noise reduction control node P2n after coupling is the noise reduction compensation signal (i.e., Vss1+Vth+ΔV). At this time, the potential of the second noise reduction control node P2n includes the threshold voltage Vth of the seventh transistor T7. Even if the threshold voltage Vth of the seventh transistor T7 drifts, the potential of the second noise reduction control node P2n will be compensated accordingly, so that the noise reduction capability is not affected by the drift of the threshold voltage Vth.

[0074] (6) The discharge of the second noise reduction control node P2n is terminated in advance after the t2 period, and coupling is performed after the t3 period. The discharge end time and the coupling time are staggered to be performed at the same time, thereby avoiding the potential drop of the second noise reduction control node P2n caused by the untimely termination of the discharge process during the coupling process.

[0075] Among them, Figure 6 and Figure 7 In the figure, the start time of the t1 period corresponds to the rising edge of Fn+6, the end time of the t1 period (i.e. the start time of the t2 period) corresponds to the falling edge of Fn+2, the end time of the t2 period (i.e. the start time of the t3 period) corresponds to the falling edge of Fn+3, and the end time of the t3 period corresponds to the rising edge of P1n.

[0076] It should also be noted that, since the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 have the same function, model, and forward bias state, the drift states of their threshold voltages can also be considered to be the same. Therefore, compensating the voltage on the second noise reduction control node P2n by the threshold voltage of the seventh transistor T7 is equivalent to compensating for the threshold voltage drift of the eighth transistor T8 and the ninth transistor T9, thereby achieving the purpose of compensating for the threshold voltage drift of the transistors in the noise reduction execution unit (hereinafter referred to as the noise reduction transistors).

[0077] The above description only uses 12CK and -6+6 level transmission as an example. The same is applicable to this application with any CK number and any level transmission mode. The same threshold voltage compensation capability can be achieved by simply making adaptive selection of the logic control signal.

[0078] In summary, the noise reduction circuit provided in this application has at least the following beneficial effects:

[0079] (1) This application performs compensation by extracting the threshold voltage of the transistor (i.e., the seventh transistor) that implements the noise reduction processing, which can better represent the change of the noise reduction capability drift, ensures the compensation accuracy, and improves the noise reduction precision.

[0080] (2) The present application adopts a two-stage drive control node voltage inversion method to extend the time that the first noise reduction control node P1n is at a low potential, delaying its pull-up, thereby gaining enough time for the threshold voltage extraction process and improving the accuracy of compensation.

[0081] (3) This application uses a logical combination of the output signals of the stage transmission output end to extract the threshold voltage, avoiding the addition of additional control signals and reducing the complexity of the noise reduction circuit.

[0082] (4) This application is applicable to display devices with any CK number and CK width, so that the device has threshold voltage compensation capability. Even after the threshold voltage has seriously drifted, the noise reduction circuit can still maintain normal operation, thereby improving the problem of unstable noise reduction caused by the threshold voltage drift of the noise reduction transistor and improving the noise reduction stability of the noise reduction circuit.

[0083] In one embodiment, the embodiment of the present application provides a gate drive circuit, comprising N cascaded gate drive modules, the nth-level gate drive module comprising: a pull-up unit, a pull-down unit, an output unit and a noise reduction circuit, the pull-up unit being respectively connected to the drive output terminal of the ni-th-level gate drive module and the level transmission output terminal of the ni-th-level gate drive module; the pull-down unit being connected to the level transmission output terminal of the n+j-th-level gate drive module, and the pull-down unit being further connected to the pull-up unit through a drive control node; the output unit being respectively connected to the clock signal terminal and the drive control node; and the noise reduction circuit being respectively connected to the drive control node, the drive output terminal and the level transmission output terminal of the current-level gate drive module.

[0084] It should be noted that the specific structure of the gate drive module provided in this embodiment is as follows Figure 1 As shown, the working principle of the gate drive module is described above using i=3, j=4 as an example, which will not be repeated here.

[0085] In one embodiment, the embodiment of the present application provides a display panel, including a display area and a non-display area, the display area including multiple scan lines; the non-display area includes a gate drive circuit, and the drive output end of the circuit unit in the gate drive circuit is electrically connected to at least one scan line.

[0086] Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first," "second," or "third" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0087] In the description of this specification, the reference terms "some embodiments", "exemplarily", etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0088] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent application.

Claims

1. A noise reduction circuit, characterized in that: Applied to a gate drive circuit, the gate drive circuit includes N cascaded gate drive modules, the n-th level gate drive module includes at least a drive control node, a drive output terminal, a level transmission output terminal and a noise reduction circuit, the noise reduction circuit includes: Noise reduction control unit, threshold compensation unit and noise reduction execution unit; The first control terminal of the noise reduction control unit is connected to the noise reduction control terminal, and the second control terminal of the noise reduction control unit is connected to the drive control node. The noise reduction control unit is configured to output a noise reduction signal during a non-scanning time of a scanning phase of a current-stage gate drive module under the action of a noise reduction control signal output by the noise reduction control terminal and a voltage on the drive control node. The threshold compensation unit is connected to the output end of the noise reduction control unit and the noise reduction execution unit respectively, and the threshold compensation unit is used to compensate the noise reduction signal according to the threshold voltage of the transistor in the noise reduction execution unit to obtain a noise reduction compensation signal; The output end of the noise reduction execution unit is connected to the drive control node, the drive output end and the stage transmission output end respectively, and the noise reduction execution unit is used to perform noise reduction processing on the voltages on the drive control node, the drive output end and the stage transmission output end according to the noise reduction compensation signal; The threshold compensation unit includes a storage capacitor and a compensation subunit, wherein the first end of the storage capacitor is connected to the output end of the noise reduction control unit for coupling the noise reduction signal; the compensation subunit is respectively connected to the second end of the storage capacitor and the noise reduction execution unit for compensating the noise reduction signal according to the threshold voltage of the transistor in the noise reduction execution unit; The compensation subunit includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor, wherein the control terminal of the tenth transistor is connected to the stage transmission output terminal of the n+j-th stage gate driving module, and the first terminal of the tenth transistor is connected to the stage transmission output terminal of the n+k-th stage gate driving module; the control terminal of the eleventh transistor is connected to the second terminal of the tenth transistor, the first terminal of the eleventh transistor is connected to the control terminal of the eleventh transistor, and the second terminal of the eleventh transistor is connected to the second terminal of the storage capacitor; the control terminal of the twelfth transistor is connected to the control terminal of the tenth transistor, and the first terminal of the twelfth transistor is connected to the stage transmission output terminal of the n+1-th stage gate driving module; the control terminal of the thirteenth transistor is connected to the second terminal of the twelfth transistor, the first terminal of the thirteenth transistor is connected to the second terminal of the eleventh transistor, and the second terminal of the thirteenth transistor is connected to the first terminal of the seventh transistor of the noise reduction execution unit; wherein the first terminal of the seventh transistor is connected to the driving output terminal.

2. The noise reduction circuit according to claim 1, wherein: The noise reduction control unit includes: a first transistor, wherein a control terminal of the first transistor is connected to the noise reduction control terminal, and a first terminal of the first transistor is connected to the control terminal of the first transistor; a second transistor, wherein a control terminal of the second transistor is connected to the second terminal of the first transistor, and a first terminal of the second transistor is connected to the first terminal of the first transistor; a third transistor, wherein a control end of the third transistor is connected to the driving control node of the n-th stage gate driving module, a first end of the third transistor is connected to the second end of the first transistor, and a second end of the third transistor is connected to the first low level end; a fourth transistor, wherein a control end of the fourth transistor is connected to the control end of the third transistor, a first end of the fourth transistor is connected to the second end of the second transistor, and a second end of the fourth transistor is connected to the first low-level end.

3. The noise reduction circuit according to claim 2, wherein: The noise reduction control unit further includes: a fifth transistor, wherein a control end of the fifth transistor is connected to the drive control node of the (n+h)th stage gate drive module, a first end of the fifth transistor is connected to the second end of the first transistor, and a second end of the fifth transistor is connected to the first low-level end; a sixth transistor, wherein a control end of the sixth transistor is connected to the control end of the fifth transistor, a first end of the sixth transistor is connected to the second end of the second transistor, and a second end of the sixth transistor is connected to the first low-level end.

4. The noise reduction circuit according to claim 1, wherein: The noise reduction execution unit includes: a seventh transistor, wherein a control terminal of the seventh transistor is connected to the threshold compensation unit, a first terminal of the seventh transistor is connected to the driving output terminal, and a second terminal of the seventh transistor is connected to the first low level terminal; an eighth transistor, wherein a control terminal of the eighth transistor is connected to the control terminal of the seventh transistor, a first terminal of the eighth transistor is connected to the drive control node, and a second terminal of the eighth transistor is connected to the first low-level terminal; A ninth transistor, wherein the control end of the ninth transistor is connected to the control end of the seventh transistor, the first end of the seventh transistor is connected to the stage transmission output end, and the second end of the seventh transistor is connected to the second low level end.

5. The noise reduction circuit according to claim 1, wherein: The size of the eleventh transistor is larger than that of the thirteenth transistor.

6. The noise reduction circuit according to claim 4, wherein: A first low level output by the first low level terminal is smaller than or larger than a second low level output by the second low level terminal.

7. A gate drive circuit comprising N cascaded gate drive modules, characterized in that: The n-th level gate driver module includes: A pull-up unit, wherein the pull-up unit is respectively connected to the driving output terminal of the n-th level gate driving module and the level transmission output terminal of the n-th level gate driving module; A pull-down unit, the pull-down unit being connected to the stage transmission output terminal of the n+j-th stage gate driving module, and the pull-down unit being further connected to the pull-up unit via a driving control node; an output unit, the output unit being connected to the clock signal terminal and the drive control node respectively; The noise reduction circuit according to any one of claims 1 to 6, wherein the noise reduction circuit is respectively connected to the drive control node, the drive output terminal and the stage transmission output terminal of the current stage gate drive module.

8. A display panel comprising a display area and a non-display area, wherein the display area comprises a plurality of scan lines; The non-display area includes the gate driving circuit according to claim 7 , and a driving output terminal of a circuit unit in the gate driving circuit is electrically connected to at least one scan line.

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