Error checking and correction circuit and memory

Abstract

The application provides an error checking and correction circuit and a memory, which comprises a first timing control circuit, a second timing control circuit, a reading amplification circuit, an operation circuit, a timing matching circuit and a latch circuit. The circuit matches the delay of the first timing control circuit, the reading amplification circuit and the operation circuit and the wiring delay through the second timing control circuit and the timing matching circuit, realizes that the delay of the control signal and the operation time in the circuit is basically close under different process angles, voltage and temperature conditions, can reduce the waiting time, improves the reading correction efficiency of the circuit while completing the asynchronous collection of data signals, and has simple circuit structure, small circuit area, and the timing matching circuit does not involve wiring on the circuit layout, so that the delay effect close to the circuit itself can be obtained without wiring matching, and a part of the area is saved, and the flexibility is improved.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to an error checking and correction circuit and a memory. Background Technology

[0002] Error checking and correcting (ECC) circuits are widely used in memory. They not only detect memory errors but also pinpoint the location (bit) of the error in the data and correct it to the correct value. Specifically, when writing data, the ECC circuit calculates information called the "error correction code (ECC)" for the data being written, and the calculated ECC is stored in the memory's storage space. When reading data, the ECC circuit refers to the pre-calculated ECC to check and correct errors in the read data. Since ECC computation time is generally long, accurately matching the ECC control signals and ECC results to reduce waiting time is a key factor in improving the efficiency of ECC circuits and is one of the hot issues that urgently need to be addressed by those skilled in the art. Summary of the Invention

[0003] The purpose of this invention is to provide an error checking and correction circuit and a memory that can improve circuit efficiency.

[0004] To achieve the above objectives, the present invention provides an error checking and correction circuit, comprising:

[0005] The first timing control circuit has an input terminal coupled to a first reading signal and an output terminal outputting a second reading signal that is delayed relative to the first reading signal.

[0006] The reading amplifier circuit has its input terminal coupled to the output terminal of the first timing control circuit, its first output terminal outputs the read data signal, and its second output terminal outputs the corresponding error correction code signal.

[0007] The second timing control circuit has its input terminal coupled to the first reading signal or the second reading signal, and its output terminal outputs a first control signal. The first control signal is delayed relative to the first reading signal and matches the output time of the reading amplifier circuit.

[0008] The arithmetic circuit has a first input terminal coupled to the first output terminal of the reading amplifier circuit, a second input terminal coupled to the second output terminal of the reading amplifier circuit, and an output terminal that outputs the data signal after being checked and corrected by the error correction code.

[0009] A timing matching circuit, the input of which is coupled to the output of the second timing control circuit, and the output of which outputs a second control signal, the second control signal being delayed relative to the first control signal and matching the operation time of the arithmetic circuit;

[0010] The latch circuit has its data input terminal coupled to the output terminal of the arithmetic circuit, its clock input terminal coupled to the output terminal of the timing matching circuit, and its output terminal outputs the data signal after being checked and corrected by the error correction code signal under the control of the second control signal.

[0011] Optionally, the first timing control circuit includes at least two cascaded first timing control units. Each first timing control unit includes a first 2-to-1 logic selector and a first delay chain. The input of the first delay chain is the input of the first timing control unit and is coupled to the first input of the first 2-to-1 logic selector. The output of the first delay chain is coupled to the second input of the first 2-to-1 logic selector. The output of the first 2-to-1 logic selector is the output of the first timing control unit.

[0012] Optionally, the second timing control circuit includes a third delay chain and at least two cascaded second timing control units. The second timing control unit includes a second 2-to-1 logic selector and a second delay chain. The input of the second delay chain is the input of the second timing control unit and is coupled to the first input of the second 2-to-1 logic selector. The output of the second delay chain is coupled to the second input of the second 2-to-1 logic selector. The output of the second 2-to-1 logic selector is the output of the second timing control unit. The output of the last stage of the second timing control unit is also coupled to the input of the third delay chain. The output of the third delay chain is the output of the second timing control circuit.

[0013] Optionally, the arithmetic circuit includes an encoding circuit and a decoding circuit. The input terminal of the encoding circuit is coupled to the first output terminal of the reading amplification circuit, the output terminal of the encoding circuit is coupled to the second input terminal of the decoding circuit, the first input terminal of the decoding circuit is coupled to the second output terminal of the reading amplification circuit, and the output terminal of the decoding circuit is the output terminal of the arithmetic circuit.

[0014] Optionally, the encoding circuit and / or the decoding circuit are composed of at least one XOR gate.

[0015] Optionally, the encoding circuit includes a first to a sixth XOR gate. The two inputs of the first to third XOR gates are both coupled to the first output of the reading amplifier circuit. The output of the first XOR gate is coupled to the first input of the fourth XOR gate. The output of the second XOR gate is coupled to the second input of the fourth XOR gate and the first input of the fifth XOR gate. The output of the third XOR gate is coupled to the second input of the fifth XOR gate. The output of the fourth XOR gate is coupled to the first input of the sixth XOR gate. The output of the fifth XOR gate is coupled to the second input of the sixth XOR gate. The output of the sixth XOR gate is coupled to the second input of the decoding circuit.

[0016] Optionally, the decoding circuit includes a seventh XOR gate, the first input terminal of the seventh XOR gate is the first input terminal of the decoding circuit, the second input terminal of the seventh XOR gate is the second input terminal of the decoding circuit, and the output terminal of the seventh XOR gate is the output terminal of the decoding circuit.

[0017] Optionally, the timing matching circuit includes a fourth delay chain whose delay matches the operation time of the arithmetic circuit.

[0018] Optionally, the first timing control circuit, the second timing control circuit, the reading amplification circuit, the arithmetic circuit, and the timing matching circuit are all constructed using MOSFETs, and the MOSFETs in the first timing control circuit and the second timing control circuit have a first threshold voltage, while the MOSFETs in the timing matching circuit and the arithmetic circuit have a second threshold voltage, wherein the first threshold voltage is higher than the second threshold voltage.

[0019] Optionally, the MOS transistor in the operational circuit has a first transistor length, and the MOS transistor in the timing matching circuit has a second transistor length, wherein the first transistor length is shorter than the second transistor length.

[0020] Based on the same inventive concept, the present invention also provides a memory comprising a memory array and an error checking and correction circuit coupled thereto as described in the present invention.

[0021] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0022] 1. Using less circuit area and a simpler circuit structure, a better match can be achieved between the second control signal (i.e., an ECC control signal) and the output of the arithmetic circuit (i.e., the ECC result), thereby reducing waiting time and improving circuit efficiency.

[0023] 2. By using a timing matching circuit, the delay of the signal traces and the operation delay in the reading amplifier circuit and the operation circuit can be matched. Moreover, the timing matching circuit does not involve winding in the circuit layout. Therefore, a delay effect close to that of the circuit itself can be obtained without wiring matching. At the same time, it saves some area and improves flexibility.

[0024] 3. For the sake of processing speed, the ECC's operational circuit uses MOSFETs with low threshold voltage. Therefore, the timing matching circuit used to match its delay also uses the same type of MOSFET.

[0025] 4. The corresponding circuit is equipped with a delay chain, and the delay length of the delay chain can be adjusted by adjusting the number of MOS transistors connected to it, so as to achieve convenient adjustment and have good flexibility.

[0026] 5. Under the premise of equal delay, the length of the MOS transistor in the timing matching circuit is relatively larger than that in the operational circuit. This requires less circuit area than increasing the number of MOS transistors, and the convergence of different process corners is also better. In addition, choosing a longer MOS transistor to implement the delay chain has the following advantages: (1) The convergence of the delay chain is close to the convergence of the ECC calculation + routing as a whole; (2) It is relatively easy to construct delay modules that are multiples of 100ps, which is convenient for circuit design. Attached Figure Description

[0027] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0028] Figure 1 This is a schematic diagram of an example architecture of an error checking and correction circuit according to a specific embodiment of the present invention.

[0029] Figure 2 This is a schematic diagram of an example circuit structure of the first timing control circuit in the error checking and correction circuit of a specific embodiment of the present invention.

[0030] Figure 3A and Figure 3B These are schematic diagrams of two example circuit structures of the second timing control circuit in the error checking and correction circuit of a specific embodiment of the present invention.

[0031] Figure 4 This is a schematic diagram of an example circuit structure of the operational circuit in the error checking and correction circuit of a specific embodiment of the present invention.

[0032] Figure 5 This is a schematic diagram of an example circuit structure of the timing matching circuit in the error checking and correction circuit of a specific embodiment of the present invention.

[0033] Figure 6 This is a schematic diagram of an example circuit structure of the latch circuit in the error checking and correction circuit of a specific embodiment of the present invention.

[0034] Figure 7 This is a signal timing diagram of an error checking and correction circuit according to a specific embodiment of the present invention.

[0035] Figure 8 This is a schematic diagram of another example architecture of the error checking and correction circuit in a specific embodiment of the present invention.

[0036] Figure 9 This is a schematic diagram of an example architecture of a memory according to a specific embodiment of the present invention. Detailed Implementation

[0037] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" other elements, it may be directly connected to other elements, or there may be intervening elements. Conversely, when an element is referred to as "directly connected to" other elements, there are no intervening elements. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0038] Please refer to Figure 1 An embodiment of the present invention provides an error checking and correction circuit, which includes a first timing control circuit 11, a second timing control circuit 12, a reading amplification circuit (hereinafter referred to as "SSA") 13, an arithmetic circuit 14, a timing matching circuit 15, and a latching circuit 16. The arithmetic circuit 14 includes an encoding circuit 141 and a decoding circuit 142.

[0039] In this regard, please combine Figure 1The input terminal of the first timing control circuit 11 is coupled to the first reading signal DPAPB, and the output terminal of the first timing control circuit 11 is coupled to the input terminal of the reading amplification circuit 13. The first timing control circuit 11 is used to generate and output a second reading signal RDSSA based on the received first reading signal DPAPB. The second reading signal RDSSA has a delay relative to the first reading signal DPAPB. Please refer to [reference needed]. Figure 7 In one example, the rising edge of the second reading signal RDSSA is delayed by t1 compared to the falling edge of the first reading signal DPAPB.

[0040] Please combine Figure 1 The readout amplifier circuit 13 has a first output terminal and a second output terminal. The first output terminal of the readout amplifier circuit 13 is coupled to the input terminal of the encoding circuit 141 in the operational circuit 14, and the second output terminal of the readout amplifier circuit 13 is coupled to the input terminal of the decoding circuit 141 in the operational circuit 14. In one example, the information stored in the memory includes data bits and error correction code bits. The readout amplifier circuit 13 can be a series of sense amplifiers (SA), which generally includes a sense amplifier (not shown) capable of outputting a data signal DATA (i.e., the value on the data bits) based on the second readout signal RDSSA and a sense amplifier (not shown) capable of outputting an error correction code signal DATA_ECC_RD (i.e., the value on the error correction code bits) based on the second readout signal RDSSA. Thus, the readout amplifier circuit 13 can output the data signal DATA it has read from its first output terminal and the error correction code signal DATA_ECC_RD it has read from its second output terminal based on the second readout signal RDSSA. It should be understood that the readout amplifier circuit 13 itself will produce a delay effect, that is, the signal it outputs will have a certain delay relative to the signal it receives. Please refer to... Figure 7 The data signal DATA and the error correction code signal DATA_ECC_RD output by the reading amplifier circuit 13 are output synchronously, and both are delayed by t2 compared to the rising edge of the second reading signal RDSSA.

[0041] The input terminal of the second timing control circuit 12 is coupled to the output terminal of the first timing control circuit 11, and the output terminal of the second timing control circuit 12 is coupled to the output terminal of the timing matching circuit 15. The second timing control circuit 12 is used to match the delay differences of the readout amplifier circuit 13 itself during chip manufacturing and the delay generated during the operation of the readout amplifier circuit 13. It is also used to generate and output a first control signal RDECC based on the received second readout signal RDSSA. Therefore, the first control signal RDECC has a delay compared to the first readout signal DPAPB, and this delay matches the output time of the readout amplifier circuit 13. Please refer to [reference needed]. Figure 7The rising edge of the first control signal RDECC is delayed by t5 relative to the falling edge of the first reading signal DPAPB, that is, the rising edge of the first control signal RDECC is earlier or delayed by |t5-t1| relative to the rising edge of the second reading signal RDSSA. For other embodiments of the present invention, please refer to... Figure 8 The input terminal of the second timing control circuit 12 can be directly coupled to the first reading signal DPAPB, thereby directly generating the first control signal RDECC based on the first reading signal DPAPB.

[0042] The input terminal of the encoding circuit 141 in the arithmetic circuit 14 serves as the first input terminal of the arithmetic circuit 14 and is coupled to the first output terminal of the reading amplifier circuit 13. The output terminal of the encoding circuit 141 is coupled to the second input terminal of the decoding circuit 142 in the arithmetic circuit 14. The encoding circuit 141 is used to generate an error correction code encoding signal ECC_ENCODE based on the data signal DATA read from the reading amplifier circuit 13. This error correction code encoding signal ECC_ENCODE has a delay relative to the data signal DATA. Please refer to [reference needed]. Figure 7 The rising edge of the error correction code signal ECC_ENCODE is delayed by t3 relative to the data signal DATA.

[0043] The first input terminal of the decoding circuit 142 serves as the second input terminal of the arithmetic circuit 14 and is coupled to the second output terminal of the readout amplifier circuit 13. The output terminal of the decoding circuit 142 serves as the output terminal of the arithmetic circuit 14 and is coupled to the data input terminal of the latch circuit 16. The decoding circuit 142 uses the error correction code signal DATA_ECC_RD read from the readout amplifier circuit 13 to check and correct the error correction code encoding signal ECC_ENCODE output by the encoding circuit 141, thereby completing the checking and correction of errors in the data signal DATA read by the readout amplifier circuit 13, and then generating and outputting the data signal ECC_FLX after being checked and corrected by the error correction code signal DATA_ECC_RD. Please refer to [reference needed]. Figure 7 The data signal ECC_FLX output by the decoding circuit 142 has a delay of t4 relative to the error correction code encoding signal ECC_ENCODE.

[0044] The output of timing matching circuit 15 is coupled to the clock input of latch circuit 16. The arithmetic circuit 14 typically involves long traces, resulting in delays in both computation time and signal trace time. The main purpose of timing matching circuit 15 is to match the computation time of arithmetic circuit 14. Specifically, timing matching circuit 15 generates and outputs a second control signal RD_ECC_DONE based on the received first control signal RDECC. This second control signal RD_ECC_DONE has a delay compared to the first control signal RDECC, and this delay matches the computation time of arithmetic circuit 14. Please refer to [reference needed]. Figure 7The rising edge of the second control signal RD_ECC_DONE is delayed by t6 compared to the rising edge of the first control signal RDECC. Ensuring that t5+t6 is slightly greater than t1+t2+t3+t4 maximizes the efficiency of the error checking and correction circuit, reduces the time gap between the end of the operation of the arithmetic circuit 14 and the start of the second control signal RD_ECC_DONE, and thus allows for better matching between the second control signal RD_ECC_DONE and the output result (ECC_FLX) of the arithmetic circuit 14 under different process angles, voltages, and temperatures, reducing the waiting time of the error checking and correction circuit and improving its efficiency.

[0045] The latch circuit 16 is used to release the data signal ECC_FLX under the control of the second control signal RD_ECC_DONE.

[0046] Please combine Figures 1 to 6 as well as Figure 7 The working principle of the error checking and correction circuit in this embodiment is as follows: When the reading signal DRAPB is issued from the first timing control circuit 11, one path passes through the reading amplification circuit 13 and the arithmetic circuit 14 for data checking and error correction. The total time for this path is t1+t2+t3+t4. The other path passes through the second timing control circuit 12 and the timing matching circuit 15 for timing matching. The second timing control circuit 12 can match the output time of the reading amplification circuit 13, and the timing matching circuit 15 can match the calculation time of the XOR gate in the arithmetic circuit 14. The total time for this path is t5+t6. By ensuring that t5+t6 is slightly greater than t1+t2+t3+t4, the second control signal RD_ECC_DONE received by the clock input terminal of the latch circuit 16 can stably acquire the correct data. This maximizes the working efficiency of the error checking and correction circuit and reduces the blank time between the end of the arithmetic circuit 14 and the start of the second control signal (i.e., reduces the waiting time of the error checking and correction circuit).

[0047] It should be understood that, in this embodiment, the first timing control circuit 11, the second timing control circuit 12, the reading amplification circuit 13, the encoding circuit 141, the decoding circuit 142, the timing matching circuit 15, and the latching circuit 16 can adopt any suitable circuit design, and the present invention does not impose any specific limitations on them.

[0048] Preferably, the first timing control circuit 11, the second timing control circuit 12, the reading amplification circuit 13, the encoding circuit 141, the decoding circuit 142, the timing matching circuit 15, and the latch circuit 16 all use MOS transistors to construct logic gates, thereby realizing their corresponding functions and delays.

[0049] In one example, the widths of the MOS transistors in each circuit are the same. The MOS transistors in the first timing control circuit 11 and the second timing control circuit 12 have a high threshold voltage, slow response but low leakage. The MOS transistors in the arithmetic circuit 14 and the timing matching circuit 15 have a low threshold voltage. That is, the MOS transistors used in the first timing control circuit 11 and the second timing control circuit 12 are high-threshold-voltage MOS transistors (i.e., ntnm transistors), which have a first threshold voltage VTH1. The MOS transistors used in the timing matching circuit 15 and the arithmetic circuit 14 are low-threshold-voltage MOS transistors (i.e., ntnlv transistors), which have a second threshold voltage VTH2, and VTH1 > VTH2. That is, for the consideration of arithmetic speed, all the MOS transistors used in the arithmetic circuit 14 are low-threshold-voltage MOS transistors. Therefore, the timing matching circuit 15 used to match its delay also uses the same type of MOS transistors. Thus, the arithmetic speed of the arithmetic circuit 14 can be ensured, and on the path from the first reading signal DPAPB to the output of the second control signal RD_ECC_DONE, a part of high-threshold-voltage MOS transistors are mixed to trim the overall delay of the error checking and correcting circuit, and a delay amount close to the gate-level delay and routing delay of the mixed devices can be obtained under different process corners, voltages and temperatures. Furthermore, the latch circuit in the error checking and correcting circuit can accurately collect the target data under the control of the second control signal RD_ECC_DONE, improving the working efficiency of the error checking and correcting circuit.

[0050] Furthermore, the MOS transistors in the arithmetic circuit 14 have a first channel length L1 (for example, 200 nm), and the MOS transistors in the timing matching circuit 15 have a second channel length L2 (for example, 380 nm), and L1 < L2. Thus, on the premise of equal delay, the channel length of the MOS transistors in the timing matching circuit 15 is relatively increased compared with that of the arithmetic circuit 14, which requires a smaller circuit area than increasing the number of MOS transistors, and the convergence of different process corners is also better. In addition, the timing matching circuit 15 selects MOS transistors with a longer length to implement the delay chain, and it also has the following advantages: (1) The convergence of the delay chain composed of MOS transistors in the timing matching circuit 15 is close to the convergence of the arithmetic circuit 14 and the overall routing; (2) It is relatively easy to construct a delay chain that is an integer multiple of 100 ps, which is convenient for circuit design.

[0051] In other words, by using longer, low-threshold-voltage MOSFETs (i.e., NTNVL transistors) to construct delay chains in the timing matching circuit 15, the timing matching circuit 15 does not involve wiring in its overall circuit layout. Furthermore, it can use gate-level delays to match the computation time and wiring delays in the arithmetic circuit 14. This allows for delay effects close to those of the circuit itself without wiring matching, while also improving convergence across different process corners. In addition, under the premise of equal delay, increasing the length of the MOSFET requires less circuit area than increasing the number of MOSFETs, thus saving circuit area and improving flexibility.

[0052] Alternatively, please refer to Figure 2 The first timing control circuit 11 includes at least two cascaded first timing control units 11a. Each first timing control unit 11a includes a first 2-to-1 logic selector Mux1 and a first delay chain 110. The input terminal of the first delay chain 110 is the input terminal of the first timing control unit 11a and is coupled to the first input terminal "0" of the first 2-to-1 logic selector Mux1 in the first timing control unit 11a. The output terminal of the first delay chain 110 is coupled to the second input terminal "1" of the first 2-to-1 logic selector Mux1 in the first timing control unit 11a. The output terminal of the first 2-to-1 logic selector Mux1 is the output terminal of the first timing control unit 11a. The first delay chain 110 may include at least two cascaded delay circuits ta.

[0053] Optionally, each delay circuit ta is a CMOS logic gate (e.g., a NOT gate) constructed from MOS transistors with high threshold voltage, slow response, and low leakage current. Thus, by adjusting the number of MOS transistors connected in the first delay chain 110, different delay values ​​can be obtained for the first delay chain 110. In one example, the first timing control circuit 11 includes at least two cascaded first timing control units 11a, and the first delay chain 110 in each first timing control unit 11a also includes at least two delay circuits ta.

[0054] Further optionally, the first two-to-one logic selector Mux1 is a CMOS logic gate constructed from MOS transistors with high threshold voltage, slow response and low leakage current. It can be an AND gate, OR gate, NAND gate, NOR gate, XOR gate and XNOR gate, etc.

[0055] Alternatively, in one example, please refer to Figure 3AThe second timing control circuit 12 includes a third delay chain 121 and at least two cascaded second timing control units 12a. Each second timing control unit 12a includes a second 2-to-1 logic selector Mux2 and a second delay chain 120. The input of the second delay chain 120 is the input of the second timing control unit 12a and is coupled to the first input "0" of the second 2-to-1 logic selector Mux2 in the second timing control unit 12a. The output of the second delay chain 120 is coupled to the second 2-to-1 logic selector of the second timing control unit 12a. The second input terminal "1" of the selector Mux2 is the output terminal of the second timing control unit 12a, which is also coupled to the input terminal of the third delay chain 121. The output terminal of the third delay chain 121 is the output terminal of the second timing control circuit 12. The input terminal of the second delay chain 120 in the first-stage second timing control unit 12a is the input terminal of the second timing control circuit 12 (this input terminal is connected to a reading signal, such as the first reading signal DPAPB or the second reading signal RDSSA mentioned above). Both the second delay chain 120 and the third delay chain 121 can include at least two cascaded delay circuits tb; the number of stages of the delay circuits tb in the third delay chain 121 matches the delay of the reading amplification circuit 13.

[0056] Further optionally, each delay circuit tb is a CMOS logic gate (e.g., a NOT gate) constructed from MOSFETs with high threshold voltage, slow response, and low leakage current. Therefore, by adjusting the number of MOSFETs connected in the second delay chain 120, different delay sizes can be obtained for the second delay chain 120; similarly, by adjusting the number of MOSFETs connected in the third delay chain 121, different delay sizes can be obtained for the third delay chain 121. In one example, the second timing control circuit 12 includes at least two cascaded second timing control units 12a. Each second delay chain 120 in each second timing control unit 12a also includes at least two delay circuits tb, and the third delay chain 121 also includes at least two delay circuits tb. In one example, the delay circuit tb has the same circuit design as the aforementioned delay circuit ta. Further, in Figure 8 In the embodiment shown where the input terminal of the second timing control circuit 12 is connected to the first reading signal DPAPB, the delay design of the second timing control unit 12a is to match the delay of the first timing control circuit 11 and the delay difference of the reading amplification circuit 13 itself during the chip manufacturing process. Figure 3A In the embodiment where the input terminal of the second timing control circuit 12 is connected to the second reading signal RDSSA, the delay design of the second timing control unit 12a is only required to match the delay difference of the reading amplifier circuit 13 itself during the chip manufacturing process.

[0057] Further optionally, the second 2-to-1 logic selector Mux2 can be a CMOS logic gate constructed from MOS transistors with high threshold voltage, slow response, and low leakage current. It can be an AND gate, OR gate, NAND gate, NOR gate, XOR gate, and XNOR gate, etc. In one example, the second 2-to-1 logic selector Mux2 and the aforementioned first 2-to-1 logic selector Mux1 employ the same circuit design.

[0058] In another example, please refer to Figure 3B Alternatively, depending on the delay matching requirements, the second timing control unit 12a can be omitted from the second timing control circuit 12, and only the third delay chain 121 can be set. In this example, the length of the third delay chain 121 needs to match the delay generated from the input of the first reading signal to the first timing control circuit 11 to the output of the data signal DATA from the reading amplifier circuit 13 (i.e., the delay of the first timing control circuit 11, the delay difference of the reading amplifier circuit 13 itself in the chip manufacturing process, and the sum of the delay of the reading amplifier circuit 13). That is, the third delay chain 121 can contain at least two stages of delay circuits tb. The number of stages of the delay circuits tb in the third delay chain 121 matches the delay generated from the input of the first reading signal to the first timing control circuit 11 to the output of the data signal DATA from the reading amplifier circuit 13 (i.e., the delay of the first timing control circuit 11, the delay difference of the reading amplifier circuit 13 itself in the chip manufacturing process, and the sum of the delay of the reading amplifier circuit 13).

[0059] In one example, please refer to Figure 4 The encoding circuit 141 includes first to sixth XOR gates XOR1 to XOR6, and the decoding circuit 142 includes a seventh XOR gate XOR7. In this circuit, the two input terminals of the first to third XOR gates XOR1 to XOR3 are both coupled to the first output terminal of the reading amplifier circuit 13. The output terminal of the first XOR gate XOR1 is coupled to the first input terminal of the fourth XOR gate XOR4. The output terminal of the second XOR gate XOR2 is coupled to the second input terminal of the fourth XOR gate XOR4 and the first input terminal of the fifth XOR gate XOR5. The output terminal of the third XOR gate XOR3 is coupled to the second input terminal of the fifth XOR gate XOR5. The output terminal of the fourth XOR gate XOR4 is coupled to the first input terminal of the sixth XOR gate XOR6. The output terminal of the fifth XOR gate XOR5 is coupled to the second input terminal of the sixth XOR gate XOR6. The output terminal of the sixth XOR gate XOR6 is coupled to the second input terminal of the seventh XOR gate XOR7. The first input terminal of the seventh XOR gate XOR7 is the first input terminal of the decoding circuit 141. The second input terminal of the seventh XOR gate XOR7 is the second input terminal of the decoding circuit 142. The output terminal of the seventh XOR gate XOR7 is the output terminal of the decoding circuit 142 (which is also the output terminal of the operational circuit 14).

[0060] Optionally, the first to seventh XOR gates XOR1 to XOR7 are all constructed from the same MOS transistor with low threshold voltage and small length (e.g., 200nm).

[0061] Alternatively, please refer to Figure 5 The timing matching circuit 15 includes a fourth delay chain 15a. This fourth delay chain 15a may include at least two cascaded delay circuits tc. The length of the fourth delay chain 15a needs to match the delay of the operational circuit 15 (including the delay generated by its signal traces and its operation time). Further optionally, each delay circuit tc is a CMOS logic gate (e.g., a NOT gate) constructed from MOS transistors with low threshold voltages and long transistor lengths. Therefore, by adjusting the number of MOS transistors connected in the fourth delay chain 15a, different delay values ​​can be obtained for the fourth delay chain 15a. In one example, the fourth delay chain 15a includes four cascaded delay circuits tc.

[0062] In the operational circuit 14, the encoding circuit 141 and decoding circuit 142 involve relatively long traces. When using MOSFETs with low threshold voltages, the overall convergence is better than that of the high threshold voltage MOSFETs in the first timing control circuit 11, and the operation speed is also better. In the timing matching circuit 15, using MOSFETs with low threshold voltages and longer lengths (L) to construct the delay chain can achieve a delay effect close to that of the circuit itself without trace matching, while also saving area and improving flexibility. Furthermore, the timing matching circuit 15 does not involve traces in its overall layout, thus requiring less area to increase the MOSFET length compared to increasing the number of MOSFETs, while maintaining the same delay. Verification also shows that when the timing matching circuit 15 is constructed using MOSFETs with longer lengths and lower threshold voltages, its delay convergence under different process angles (P), voltages (V), and temperatures (T) is very close to the delay of the operational circuit 14, effectively matching the operation time of the operational circuit 15.

[0063] Alternatively, please refer to Figure 6 The latch circuit 16 includes a D flip-flop.

[0064] Optionally, some of the MOSFETs in the reading amplifier circuit 13 are the same as those in the first timing control circuit 11, while the other part of the MOSFETs are the same as those in the operational circuit 14.

[0065] In summary, the error checking and correction circuit of this invention can match the delays and wiring delays of the first timing control circuit, the reading amplification circuit, and the arithmetic circuit through the second timing control circuit and the timing matching circuit. This ensures that the delays of the output of the timing matching circuit (i.e., the second control signal) and the output of the arithmetic circuit (i.e., the calculation result of the arithmetic circuit, or the data signal after error checking and correction) are basically similar under different process corners, voltages, and temperature conditions. This reduces waiting time and improves the readout error correction efficiency of the circuit while completing asynchronous data signal acquisition. Moreover, the circuit structure is simple, uses less circuit area, and the timing matching circuit does not involve wiring in the circuit layout. Therefore, a delay effect close to that of the circuit itself can be obtained without wiring matching, while also saving some area and improving flexibility. In addition, the corresponding circuit has a delay chain, and the delay length of the delay chain can be adjusted by adjusting the number of MOS transistors connected to it, which allows for convenient adjustment and provides good flexibility.

[0066] Based on the same inventive concept, please refer to Figure 9 An embodiment of the present invention also provides a memory including a memory array 2 and an error checking and correction circuit 1 coupled thereto as described in the present invention.

[0067] The memory of the present invention has improved circuit efficiency because it employs the error checking and correction circuit described in the present invention.

[0068] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. An error checking and correction circuit, characterized in that, include: The first timing control circuit has an input terminal coupled to a first reading signal and an output terminal outputting a second reading signal that is delayed relative to the first reading signal. The reading amplifier circuit has its input terminal coupled to the output terminal of the first timing control circuit, its first output terminal outputs the read data signal, and its second output terminal outputs the corresponding error correction code signal. The second timing control circuit has its input terminal coupled to the first reading signal or the second reading signal, and its output terminal outputs a first control signal. The first control signal is delayed relative to the first reading signal and matches the output time of the reading amplifier circuit. The arithmetic circuit has a first input terminal coupled to the first output terminal of the reading amplifier circuit, a second input terminal coupled to the second output terminal of the reading amplifier circuit, and an output terminal that outputs the data signal after being checked and corrected by the error correction code signal. A timing matching circuit, the input of which is coupled to the output of the second timing control circuit, and the output of which outputs a second control signal, the second control signal being delayed relative to the first control signal and matching the operation time of the arithmetic circuit; The latch circuit has its data input terminal coupled to the output terminal of the arithmetic circuit, its clock input terminal coupled to the output terminal of the timing matching circuit, and its output terminal outputs the data signal after being checked and corrected by the error correction code under the control of the second control signal.

2. The error checking and correction circuit as described in claim 1, characterized in that, The first timing control circuit includes at least two cascaded first timing control units. Each first timing control unit includes a first 2-to-1 logic selector and a first delay chain. The input of the first delay chain is the input of the first timing control unit and is coupled to the first input of the first 2-to-1 logic selector. The output of the first delay chain is coupled to the second input of the first 2-to-1 logic selector. The output of the first 2-to-1 logic selector is the output of the first timing control unit.

3. The error checking and correction circuit as described in claim 1, characterized in that, The second timing control circuit includes a third delay chain and at least two cascaded second timing control units. The second timing control unit includes a second 2-to-1 logic selector and a second delay chain. The input of the second delay chain is the input of the second timing control unit and is coupled to the first input of the second 2-to-1 logic selector. The output of the second delay chain is coupled to the second input of the second 2-to-1 logic selector. The output of the second 2-to-1 logic selector is the output of the second timing control unit. The output of the last stage of the second timing control unit is also coupled to the input of the third delay chain. The output of the third delay chain is the output of the second timing control circuit.

4. The error checking and correction circuit as described in claim 1, characterized in that, The arithmetic circuit includes an encoding circuit and a decoding circuit. The input terminal of the encoding circuit is coupled to the first output terminal of the reading amplification circuit, the output terminal of the encoding circuit is coupled to the second input terminal of the decoding circuit, the first input terminal of the decoding circuit is coupled to the second output terminal of the reading amplification circuit, and the output terminal of the decoding circuit is the output terminal of the arithmetic circuit.

5. The error checking and correction circuit as described in claim 4, characterized in that, The encoding circuit and / or the decoding circuit are composed of at least one XOR gate.

6. The error checking and correction circuit as described in claim 5, characterized in that, The encoding circuit includes a first to a sixth XOR gate. The two inputs of the first to third XOR gates are both coupled to the first output of the reading amplifier circuit. The output of the first XOR gate is coupled to the first input of the fourth XOR gate. The output of the second XOR gate is coupled to the second input of the fourth XOR gate and the first input of the fifth XOR gate. The output of the third XOR gate is coupled to the second input of the fifth XOR gate. The output of the fourth XOR gate is coupled to the first input of the sixth XOR gate. The output of the fifth XOR gate is coupled to the second input of the sixth XOR gate. The output of the sixth XOR gate is coupled to the second input of the decoding circuit.

7. The error checking and correction circuit as described in claim 5, characterized in that, The decoding circuit includes a seventh XOR gate, the first input terminal of the seventh XOR gate is the first input terminal of the decoding circuit, the second input terminal of the seventh XOR gate is the second input terminal of the decoding circuit, and the output terminal of the seventh XOR gate is the output terminal of the decoding circuit.

8. The error checking and correction circuit as described in claim 1, characterized in that, The timing matching circuit includes a fourth delay chain, the delay of which is matched with the operation time of the arithmetic circuit.

9. The error checking and correction circuit as described in any one of claims 1-8, characterized in that, The first timing control circuit, the second timing control circuit, the reading amplification circuit, the arithmetic circuit, and the timing matching circuit all use MOS transistors to construct logic gates. The MOS transistors in the first timing control circuit and the second timing control circuit have a first threshold voltage, and the MOS transistors in the timing matching circuit and the arithmetic circuit have a second threshold voltage. The first threshold voltage is higher than the second threshold voltage.

10. The error checking and correction circuit as described in any one of claims 1-8, characterized in that, The MOS transistor in the operational circuit has a first transistor length, and the MOS transistor in the timing matching circuit has a second transistor length, wherein the first transistor length is less than the second transistor length.

11. A memory, characterized in that, Includes a storage array and the error checking and correction circuitry coupled thereto as described in any one of claims 1-10.

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