A method for preparing silicon oxide insulating layer by atmospheric pressure chemical vapor deposition

Abstract

The present invention provides a method for preparing a silicon oxide insulating layer by atmospheric pressure chemical vapor deposition, comprising: step S10, etching a blind hole with a certain aspect ratio on a silicon substrate using a photoresist as a mask; wherein the blind hole with a certain aspect ratio can be configured as a plurality of blind holes with different aspect ratios; step S20, humidifying oxygen by passing deionized water through oxygen, then introducing the humidified oxygen into a CVD reaction chamber, wherein the pressure in the CVD chamber is atmospheric pressure, heating the CVD chamber to 1000°C, maintaining the temperature for 3-5 hours to allow the silicon substrate to fully react with the humidified oxygen, and then removing the silicon substrate after natural cooling to room temperature. The technical solution of the present invention simplifies the growth steps and requires simple reactants and equipment. Using the silicon substrate itself, oxygen, and water as reactants, a uniform and high-quality silicon oxide insulating layer can be formed on the sidewalls of the blind holes, ensuring that the TSV device has excellent insulation properties.

Description

Technical Field

[0001] The present invention relates to the technical field of advanced chip packaging, and in particular to a method for preparing a silicon oxide insulating layer by atmospheric pressure chemical vapor deposition. Background Art

[0002] 2.5D / 3D packaging and chiplets are currently advanced packaging technologies. Their core lies in achieving planar or vertical interconnection between chips through a silicon substrate (TSV interposer), thereby building a high-density, short-path interconnection solution. The TSV manufacturing process mainly includes the following steps: first, the circuit and device are prepared on the wafer surface, followed by through-hole etching; then, an insulating layer is deposited on the inner wall of the etched through-hole, and the insulating layer is filled with conductive metal; finally, the processing is completed by polishing. It is worth noting that the thickness, uniformity, and step coverage of the insulating layer on the TSV through-hole sidewall directly affect the device performance, and the surface roughness of the through-hole sidewall after etching has a significant impact on the quality of subsequent metal coating.

[0003] The current mainstream methods for depositing silicon oxide sidewall insulating layers include magnetron sputtering to deposit silicon oxide insulating layers, and using PECVD (plasma-enhanced chemical vapor deposition) with TEOS (ethyl silicate) as a source to grow silicon oxide sidewall insulating layers. However, both methods require relatively complex equipment and reaction sources, and the use of the above two methods requires the preparation of other reactants. Specifically: (1) The disadvantage of using PECVD with TEOS as a source to grow silicon oxide sidewall insulating layers is that the reactants and reaction conditions used are relatively complex, requiring the use of a radio frequency source and liquid TEOS as the source reactant. (2) The disadvantage of magnetron sputtering is that it requires the preparation of corresponding silicon oxide targets, and magnetron sputtering is relatively poor for growing blind holes with high aspect ratios. It is difficult to ensure uniformity and film quality, which is not conducive to subsequent TSV coating. Summary of the Invention

[0004] In response to the above technical problems, the present invention discloses a method for preparing a silicon oxide insulating layer by atmospheric pressure chemical vapor deposition, aiming to solve the problem of complex equipment and reactants used in the prior art.

[0005] To this end, the technical solution adopted in the present invention is:

[0006] A method for preparing a silicon oxide insulating layer by atmospheric pressure chemical vapor deposition comprises the following steps:

[0007] Step S10, etching a blind hole with a certain aspect ratio on a silicon substrate using a photoresist as a mask; wherein the blind hole with a certain aspect ratio can be set as a plurality of blind holes with different aspect ratios;

[0008] In step S20, deionized water is introduced into the oxygen for humidification treatment, and then the humidified oxygen is introduced into the CVD reaction chamber. The pressure of the CVD reaction chamber is atmospheric pressure. The CVD is heated to 900-1100°C and kept at this temperature for 3-5 hours to allow the silicon substrate to fully react with the humidified oxygen. The silicon substrate is then taken out after natural cooling to room temperature.

[0009] This technical solution introduces the reaction of wet oxygen and silicon at high temperature to form silicon oxide and water into CVD, resulting in a method for growing a TSV silicon oxide insulating layer using CVD at normal pressure. Other methods for growing TSV silicon oxide sidewall insulating layers, such as PECVD and magnetron sputtering, have the disadvantages of complex equipment and reactants, and it is difficult to ensure the uniformity of the growth of the sidewall insulating layer. The method of the technical solution of the present invention uses silicon, oxygen, and water from the silicon substrate itself as reactants, and uses simple CVD equipment to grow a uniform and high-quality sidewall insulating layer on the TSV sidewall. This method can be widely used in the design and production of TSVs, and is used to grow TSV sidewall insulating layers using simple equipment and reactants.

[0010] As a further improvement of the present invention, in step S10, the photoresist is AZ4620, which has a very high etching selectivity ratio under a photolithography machine; further, the speed ratio of etching the photoresist and etching the silicon substrate is 1:10.

[0011] As a further improvement of the present invention, in step S20, the oxygen flow rate is 280-320 sccm. Further, the oxygen flow rate is 300 sccm.

[0012] As a further improvement of the present invention, in step S20, when heating the CVD, it is first heated to 700°C at a heating rate of 20-30°C / min, and then heated to 1000°C at a heating rate of 5-15°C / min.

[0013] As a further improvement of the present invention, in step S20, when heating the CVD, it is first heated to 700°C at a heating rate of 25°C / min, and then heated to 1000°C at a heating rate of 10°C / min.

[0014] As a further improvement of the present invention, in step S20, oxygen is provided by an oxygen cylinder, and an anti-backflow oil bubbler is connected between the oxygen cylinder and the CVD. Deionized water is contained in the anti-backflow oil bubbler, and the oxygen enters the anti-backflow oil bubbler for humidification before entering the CVD.

[0015] As a further improvement of the present invention, in step S10, the diameter of the blind hole is not less than 3 μm. Furthermore, the diameter of the blind hole is 10-25 μm and the depth is 80-110 μm.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] The technical solution of the present invention has simple growth steps, simple required reactants and equipment conditions, and uses the silicon wafer, oxygen and water of the silicon substrate itself as reactants to generate a uniform and high-quality silicon oxide insulating layer on the side wall of the blind hole, ensuring that the TSV device has good insulation properties and guaranteeing the reliability of subsequent coating. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a diagram of the internal structure of a blind hole with a diameter of 11.35 μm and a depth of 82.06 μm in Example 1 of the present invention observed under a scanning electron microscope after CVD growth for 3 hours and laser cutting; (a), (b), and (c) are scanning electron microscope images of different parts, respectively.

[0019] Figure 2 This is a diagram of the internal structure of a blind hole with a diameter of 15.82 μm and a depth of 94.16 μm in Example 2 of the present invention observed under a scanning electron microscope after CVD growth for 3 hours and laser cutting; (a), (b), and (c) are scanning electron microscope images of different parts, respectively.

[0020] Figure 3 This is a diagram of the internal structure of a blind hole with a diameter of 20.47 μm and a depth of 101.0 μm in Example 3 of the present invention observed under a scanning electron microscope after cutting after CVD growth for 3 hours; (a), (b), and (c) are scanning electron microscope images of different parts, respectively.

[0021] Figure 4 This is a diagram of the internal structure of a blind hole with a diameter of 11.35 μm and a depth of 82.06 μm in Example 4 of the present invention observed under a scanning electron microscope after CVD growth for 4 hours and laser cutting; (a), (b), and (c) are scanning electron microscope images of different parts, respectively.

[0022] Figure 5 This is a diagram of the internal structure of a blind hole with a diameter of 15.82 μm and a depth of 94.16 μm in Example 5 of the present invention observed under a scanning electron microscope after CVD growth for 4 hours and laser cutting; (a), (b), and (c) are scanning electron microscope images of different parts, respectively.

[0023] Figure 6 This is a diagram of the internal structure of a blind hole with a diameter of 20.47 μm and a depth of 101.0 μm in Example 6 of the present invention observed under a scanning electron microscope after being cut after CVD growth for 4 hours; (a), (b), and (c) are scanning electron microscope images of different parts, respectively. DETAILED DESCRIPTION

[0024] The preferred embodiments of the present invention are described in further detail below.

[0025] A method for preparing a silicon oxide insulating layer by atmospheric pressure chemical vapor deposition, wherein the chip includes a wafer (silicon substrate) having a through hole therein, and the method for preparing the silicon oxide insulating layer by atmospheric pressure chemical vapor deposition comprises the following steps:

[0026] S10, etching blind holes with a certain aspect ratio on the silicon substrate using a photoresist as a mask, wherein the blind holes with a certain aspect ratio can be provided as multiple blind holes with different aspect ratios;

[0027] S20: First, oxygen is humidified by passing it through deionized water at a constant flow rate. The humidified oxygen is then introduced into the CVD reaction chamber. The CVD reaction chamber is maintained at atmospheric pressure. Regarding temperature control, the temperature is first raised to 700°C over a 30-minute period, followed by a further 30 minutes of heating to a target temperature of 1000°C. The temperature is maintained at 1000°C to allow the silicon substrate to fully react with the humidified oxygen. Upon completion of the reaction, heating is stopped, and the sample is removed after naturally cooling to room temperature within the chamber.

[0028] S30, cutting the wafer along the diameter of the blind hole to obtain a cut wafer;

[0029] S40, observing the internal structure of the blind hole in the cut silicon substrate.

[0030] Furthermore, step S10 includes: using AZ4620 high selectivity photoresist as an etching mask (the speed ratio of etching the photoresist to etching the silicon substrate is 1:10).

[0031] Furthermore, the oxygen flow rate in step S20 is 300 sccm.

[0032] Furthermore, the diameter of the grown blind hole is not less than 3 μm.

[0033] Furthermore, in step S20, the reaction occurring in the CVD is that the silicon wafer and wet oxygen react at high temperature to generate silicon oxide and water.

[0034] Furthermore, in step S20, an anti-backflow oil bubble generator is used to introduce a certain amount of deionized water into the container.

[0035] Furthermore, in step S20, an anti-backflow oil bubbler is connected between the oxygen cylinder and the CVD, and the oxygen enters the anti-backflow oil bubbler for humidification before entering the CVD.

[0036] Furthermore, in step S30, the wafer cutting method used is laser blind cutting.

[0037] Furthermore, in step S40, the internal structure of the blind vias in the cut wafer is observed by a scanning electron microscope.

[0038] The technical solutions of the present invention are further described in detail below in conjunction with specific embodiments and drawings. It should be understood that the following embodiments are only used to explain the present invention and are not used to limit the present invention. Example 1

[0039] A method for growing a TSV silicon oxide insulating layer in a chip by CVD at normal pressure, wherein the wafer material is a silicon substrate, comprises the following steps:

[0040] S10, providing a wafer, and etching a blind hole with a diameter of 11.35 μm and a depth of 82.06 μm on the wafer using ultraviolet photoresist (AZ4620) as a mask;

[0041] S20, continuously introduce a certain flow of oxygen into the CVD reaction chamber, and before the oxygen enters the chamber, introduce it into deionized water for wet treatment, then heat the CVD to 700 degrees for 30 minutes, and then heat the CVD to 1000 degrees for 30 minutes, and maintain 1000 degrees to allow the wafer to react with wet oxygen for 3 hours, and finally cool it naturally and remove the sample;

[0042] S30, cutting the wafer along the diameter of the blind hole to obtain a cut wafer; further, the wafer cutting method used is laser blind cutting.

[0043] S40. The cut surface of the wafer is glued to a glass slide with conductive glue and moved to a scanning electron microscope (FESEM (field emission scanning electron microscope)) to observe the internal structure of the through hole. The internal characterization content includes the silicon oxide sidewall insulation layer at the TSV opening, the silicon oxide sidewall insulation layer in the middle of the TSV, and the silicon oxide sidewall insulation layer at the bottom of the TSV. Example 2

[0044] The chip of this embodiment is a silicon substrate with TSVs. A silicon oxide film is grown inside the TSVs as an insulating layer. The steps are different from those of Example 1 in that:

[0045] The TSV has a diameter of 15.82 μm and a depth of 94.16 μm. Example 3

[0046] The chip of this embodiment is a silicon substrate with TSVs. A silicon oxide film is grown inside the TSVs as an insulating layer. The steps are different from those of Example 1 in that:

[0047] The TSV diameter is 20.47 μm and the depth is 101.0 μm. Example 4

[0048] The chip of this embodiment is a silicon substrate with TSVs. A silicon oxide film is grown inside the TSVs as an insulating layer. The difference from the first embodiment is that:

[0049] In step S20 , the reaction time between the wafer and the silicon slice is 4 hours. Example 5

[0050] The chip of this embodiment is a silicon substrate with TSVs. A silicon oxide film is grown inside the TSVs as an insulating layer. The difference between this embodiment and embodiment 2 is that:

[0051] In step S20 , the reaction time between the wafer and the silicon slice is 4 hours. Example 6

[0052] The chip of this embodiment is a silicon substrate with TSVs. A silicon oxide film is grown inside the TSVs as an insulating layer. The difference between this embodiment and embodiment 3 is that:

[0053] In step S20 , the reaction time between the wafer and the silicon slice is 4 hours.

[0054] The internal structures observed in Examples 1 to 6 are shown in FIG. Figure 1 、 Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 shown.

[0055] Depend on Figure 1 It can be seen that the cut sample is a silicon substrate with a TSV with a diameter of 11.35um and a depth of 82.06um, and a layer of silicon oxide film is grown as an insulating layer. The CVD growth time is 3 hours. The blind hole is first cut by laser hidden cutting and the side wall morphology of the sample is observed by FESEM. It can be seen that a well-uniform and thick silicon oxide insulating layer is obtained.

[0056] Depend on Figure 2 It can be seen that the cut sample is a silicon substrate with a TSV with a diameter of 15.82um and a depth of 94.16um, and a layer of silicon oxide film is grown as an insulating layer. The CVD growth time is 3 hours. The blind hole is first cut by laser hidden cutting and the side wall morphology of the sample is observed by FESEM. It can be seen that a well-uniform and thick silicon oxide insulating layer is obtained.

[0057] Depend on Figure 3 It can be seen that the cut sample is a silicon substrate with a TSV with a diameter of 20.47um and a depth of 101.0um, and a layer of silicon oxide film is grown as an insulating layer. The CVD growth time is 3 hours. The blind hole is first cut by laser hidden cutting and the side wall morphology of the sample is observed by FESEM. It can be seen that a well-uniform and thick silicon oxide insulating layer is obtained.

[0058] Depend on Figure 4It can be seen that the cut sample is a silicon substrate with a TSV with a diameter of 11.35um and a depth of 82.06um, and a layer of silicon oxide film is grown as an insulating layer. The CVD growth time is 4 hours. The blind hole is first cut by laser hidden cutting and the side wall morphology of the sample is observed by FESEM. It can be seen that a well-uniform and thick silicon oxide insulating layer is obtained.

[0059] Depend on Figure 5 It can be seen that the cut sample is a silicon substrate with a TSV with a diameter of 15.82um and a depth of 94.16um, and a layer of silicon oxide film is grown as an insulating layer. The CVD growth time is 4 hours. The blind hole is first cut by laser hidden cutting and the side wall morphology of the sample is observed by FESEM. It can be seen that a well-uniform and thick silicon oxide insulating layer is obtained.

[0060] Depend on Figure 6 It can be seen that the cut sample is a silicon substrate with a TSV with a diameter of 20.47um and a depth of 101.0um, and a layer of silicon oxide film is grown as an insulating layer. The CVD growth time is 4 hours. The blind hole is first cut by laser hidden cutting and the side wall morphology of the sample is observed by FESEM. It can be seen that a silicon oxide insulating layer with good uniformity and thickness is obtained.

[0061] In summary, the technical solution of the present invention introduces the reaction principle of wet oxygen and silicon to form silicon oxide and water into the chemical vapor deposition (CVD) process, and develops a method for growing the silicon oxide insulating layer of through-silicon vias (TSVs) using CVD under atmospheric pressure conditions. The resulting insulating layer has good uniformity and high quality.

[0062] Existing TSV silicon oxide sidewall insulation growth technologies, such as plasma-enhanced chemical vapor deposition (PECVD) and magnetron sputtering, suffer from complex equipment structures and a wide variety of reactants. Furthermore, ensuring uniform growth of the sidewall insulation layer presents challenges. In stark contrast, the method proposed in this invention cleverly utilizes silicon, oxygen, and water from the silicon substrate itself as reactants. The equipment requires only a CVD unit and an anti-backflow oil bubble generator, significantly simplifying the equipment. This method enables the growth of a uniform, high-quality insulation layer on the TSV sidewalls. This method offers significant advantages and broad application prospects, and can be widely applied in the design and fabrication of TSVs, providing an effective approach for growing TSV sidewall insulation layers using simple equipment and reactants.

[0063] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A method for preparing a silicon oxide insulating layer by atmospheric pressure chemical vapor deposition, characterized in that: include: Step S10, etching a blind hole with a certain aspect ratio on a silicon substrate using a photoresist as a mask; wherein the blind hole with a certain aspect ratio is provided as a plurality of blind holes with different aspect ratios; In step S20, deionized water is introduced into the oxygen for humidification treatment, and then the humidified oxygen is introduced into the CVD reaction chamber. The pressure of the CVD reaction chamber is atmospheric pressure, and the CVD is heated to 900-1100°C and kept at this temperature for 3-5 hours to allow the silicon substrate to fully react with the humidified oxygen. The silicon substrate is naturally cooled to room temperature and then removed. In step S20, when heating the CVD, the temperature is first increased to 700°C at a rate of 20-30°C / min, and then increased to 1000°C at a rate of 5-15°C / min. In step S20, oxygen is provided by an oxygen cylinder, and an anti-backflow oil bubbler is connected between the oxygen cylinder and the CVD. The anti-backflow oil bubbler contains deionized water, and the oxygen enters the anti-backflow oil bubbler for humidification before entering the CVD. In step S20, the oxygen flow rate is 280-320 sccm.

2. The method for preparing a silicon oxide insulating layer by atmospheric pressure chemical vapor deposition according to claim 1, characterized in that: In step S10, the photoresist is AZ4620.

3. The method for preparing a silicon oxide insulating layer by atmospheric pressure chemical vapor deposition according to claim 1, wherein: In step S20 , when heating the CVD, the temperature is firstly heated to 700° C. at a heating rate of 25° C. / min, and then heated to 1000° C. at a heating rate of 10° C. / min.

4. The method for preparing a silicon oxide insulating layer by atmospheric pressure chemical vapor deposition according to any one of claims 1 to 3, characterized in that: In step S10, the diameter of the blind hole is 10-25 μm and the depth is 80-110 μm.

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