Fan-out type packaging structure with high heat dissipation performance and packaging method

Abstract

The invention discloses a fan-out type packaging structure with high heat dissipation performance, which greatly improves the volume ratio of silicon in a packaging body, meanwhile, the silicon is exposed on the side of the structure, the heat dissipation performance of a product can be remarkably improved, and the finished product is higher in strength and better in reliability. The device comprises at least one chip; a plurality of dummy chip mechanisms, wherein each group of dummy chip mechanism comprises a silicon layer and a surface insulating layer; a plastic package layer; the mixing layer is formed by arranging a plurality of RDLs and PAs; and an I / O export structure; a chip and fake chip mechanisms are arranged on the surface of the plastic package layer, the chip and the fake chip mechanisms are connected into a whole in a plastic package mode through the plastic package layer, the chip is located in a center position area formed by the multiple fake chip mechanisms in a surrounding mode, and at least one vertical face of the fake chip mechanisms arranged on the periphery is exposed. The surface insulating layer of the dummy chip mechanism and the surface layer of the chip are arranged in parallel and level, and the mixed layer covers the surface insulating layer of the dummy chip mechanism, the surface layer of the chip and the surface layer of the corresponding surface of the plastic package layer.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor chip packaging, and in particular to a fan-out packaging structure with high heat dissipation performance. The present invention also provides a packaging method corresponding to the packaging structure. Background Art

[0002] With the development of electronic technology, the rapid rise of high-performance computing, big data, 5G communications and artificial intelligence applications, the scale and complexity of corresponding semiconductor technology integrated circuits are increasing, and the density of transistors is greatly improved. The original fan-in package can no longer meet the demand, and the fan-out package came into being. The biggest difference of fan-out packaging is that the customer's incoming wafers need to be reconstructed first, and the wiring area is increased by increasing the chip spacing, and then the redistribution layer (RDL) and passivation layer (PA) are alternately prepared on the reconstructed "wafer". It is the reconstruction process that makes heterogeneous integration possible in fan-out packaging. According to the size and shape of the "reconstructed wafer", it can be divided into wafer-level fan-out packaging (FOWLP) and panel-level fan-out packaging (FOPLP). According to the different processes and materials used for reconstruction, it can be divided into two categories: plastic-encapsulated fan-out and embedded silicon-based fan-out, which are represented by Infineon's eWLB technology and Huatian Technology's eSiFO technology.

[0003] As transistor density increases, the power consumption and heat density of chip products also increase greatly, so fan-out packaging places higher demands on the heat dissipation performance of products. In plastic-encapsulated fan-out packaging products represented by eWLB, the customer chip (the main heat source) is wrapped with a large amount of epoxy molding compound (EMC) with low thermal conductivity, and its heat dissipation problem needs to be solved urgently. At the same time, the wafer / large board warping problem caused by the obvious mismatch of thermal expansion coefficient (CTE) between EMC and materials such as silicon and metal directly affects the process accuracy and production yield. Summary of the invention

[0004] In response to the above problems, the present invention provides a fan-out packaging structure with high heat dissipation performance, which greatly increases the volume proportion of silicon in the package body. At the same time, the silicon is exposed on the side of the structure, which can significantly improve the heat dissipation performance of the product, and the finished product has higher strength and better reliability. In addition, the warping of the finished product is also significantly improved.

[0005] A fan-out packaging structure with high heat dissipation performance, characterized in that it includes:

[0006] At least one chip;

[0007] A plurality of dummy chip mechanisms, each set of dummy chip mechanisms comprising a silicon layer and a surface insulating layer;

[0008] Plastic sealing layer;

[0009] A mixed layer formed by arranging a plurality of RDLs and PAs;

[0010] And an I / O lead-out structure;

[0011] The surface of the encapsulation layer is arranged with chips and the dummy chip mechanism. The encapsulation layer encapsulates and connects the chips and the dummy chip mechanism into one body. The chip is located in the central position area formed by being surrounded by a plurality of dummy chip mechanisms. At least one vertical surface of the dummy chip mechanism arranged on the periphery is exposed. The surface insulating layer of the dummy chip mechanism is arranged flush with the surface layer of the chip. The mixed layer covers the surface insulating layer of the dummy chip mechanism, the surface layer of the chip, and the corresponding surface layer of the encapsulation layer. An I / O lead-out structure is arranged on the mixed layer, and the I / O lead-out structure is connected to the chip through the RDL in the mixed layer.

[0012] It is further characterized in that:

[0013] The I / O lead-out structure is a UBM structure or a BGA structure;

[0014] The mixed layer is prepared with multiple alternating RDL and PA layers according to product requirements;

[0015] The silicon layer of the dummy chip mechanism is as thick as possible, so as to increase the volume ratio of silicon in the dummy chip mechanism as an encapsulation body.

[0016] A fan-out packaging method with high heat dissipation performance, characterized in that:

[0017] Before chip packaging, the chips and the dummy chip mechanism are typeset and arranged on the temporary bonding layer of the carrier board, so that the dummy chip mechanism is arranged between adjacent chips, and the chip is located in the central position area formed by being surrounded by a plurality of dummy chip mechanisms. Then, the surface area where the chips and the dummy chip mechanism are combined is encapsulated. After that, the carrier board and the temporary bonding layer are removed, so that the surface layer of the chip is exposed and at the same time the insulating layer of the dummy chip mechanism is exposed. A mixed layer is arranged on the surface layer formed by the chip, the dummy chip mechanism, and the encapsulation body. Then, the I / O lead-out structure is prepared. After that, cutting is performed so that the area of the dummy chip mechanism covers the cutting channel, and the silicon layer of the dummy chip mechanism on the corresponding part of the cut packaging product is partially exposed.

[0018] It is further characterized in that it includes the following steps:

[0019] S1. Pretreatment of incoming wafers. The chip wafer and the dummy chip mechanism wafer are ground and cut to obtain chips and dummy chip mechanisms of a preset size. The surface insulating layer is prepared on the surface of the dummy chip mechanism.

[0020] S2. Prepare a temporary bonding layer on the carrier board;

[0021] S3. Die bonding, to complete the mounting of the chip and the dummy chip mechanism, requiring that the surface insulation layer of the dummy chip mechanism and the functional layer of the chip are on the same side, and the spacing between chips and the spacing between the chip and the dummy chip mechanism are arranged according to the layout settings;

[0022] S4. Encapsulation, encapsulating the product formed by the chips and the dummy chip mechanism mounted in step S3 with encapsulant;

[0023] S5. Debonding, removing the carrier board and the temporary bonding layer from the product;

[0024] S6. Additive manufacturing of the hybrid layer, preparing multiple alternating RDL and PA layers according to the product requirements to form a hybrid layer;

[0025] S7. Complete the preparation of the I / O lead-out structure;

[0026] S8. Perform testing, marking, cutting and packaging for shipment as required. The area of the dummy chip mechanism straddles the cutting lane between two groups of chips, so the side-exposed silicon of the encapsulated product is directly achieved after cutting.

[0027] Its further features are as follows:

[0028] In step S1, the incoming wafer is tested, polished and cut, and at the same time, a redistribution layer (RDL) or a passivation layer (PA), or an alternating structure of multiple RDL and PA layers is prepared on the surface of the incoming wafer according to the actual needs of the product; the wafer of the dummy chip mechanism is also ground and cut in this stage. On the premise that it does not conflict with the product requirements for thickness and process capabilities, the wafer of the dummy chip mechanism is as thick as possible, and a surface insulation layer needs to be prepared on the front side of the wafer of the dummy chip mechanism before cutting;

[0029] The material of the surface insulation layer is an insulating polymer material such as polyimide or epoxy resin, and its thickness is 5 - 30 μm, preferably 5 - 10 μm;

[0030] Or the surface insulation layer is an insulating inorganic coating such as deposited silicon nitride, silicon oxide, or aluminum oxide, and its thickness is 0.5 - 10 μm, preferably 1 - 3 μm;

[0031] The layout requirements in step S3 are as follows. The maximum size c of the dummy chip structure in the x direction can be set as the minimum chip pitch a between two adjacent units in the x direction on the reconstructed wafer / large board minus 2 times the minimum allowable chip pitch b in the x direction of the product, that is, c max = a - 2b. To avoid voids in the encapsulation due to too small chip gaps, it is recommended that the value of b is not less than 2 times the maximum size of the filler particles in the encapsulant; the size d of the dummy chip mechanism in the y direction is set as the minimum chip pitch e between two adjacent units in the y direction on the reconstructed wafer / large board minus 2 times the minimum allowable chip pitch f in the y direction of the product, that is, d max= e - 2f. To avoid molding voids caused by too small chip gaps, it is recommended that the value of f be not less than 2 times the maximum size of the filler particles in the molding compound.

[0032] In step S2, the function of the temporary bonding layer is to fix the mounted integrated circuit devices during subsequent wafer reconstruction. Its structure is one or more layers of composites, its material is liquid slurry or solid adhesive film, and its curing form is thermal curing or UV curing, or a combination of both; the surface of the temporary bonding layer needs to have a certain adhesiveness to ensure that the chip components mounted on it do not slip or fall off during the transfer of the carrier board.

[0033] In step S4, the molding compound is a polymer molding material in the form of powder, liquid or dry film, etc. The operation form is film pressing molding or vacuum laminating. It is recommended that the molding thickness of the molding layer be set so that the value of the Overmold thickness g is not less than 2 times the maximum size of the filler particles in the molding compound.

[0034] In step S5, the debonding is carried out by means of thermal foaming to reduce adhesion, UV reduction of adhesion, and laser ablation of the interface layer.

[0035] Advantages of the present invention:

[0036] 1) Significantly increase the volume ratio of silicon (high thermal conductivity) in the package, and at the same time expose silicon on the structure side, which can significantly improve the heat dissipation performance of the product;

[0037] 2) Significantly increase the volume ratio of silicon (high strength) in the package, resulting in higher finished product strength and better reliability;

[0038] 3) Can effectively reduce the warping of the wafer or large board during the packaging process, which is beneficial to improving the process accuracy and production yield, and the warping of the finished product can also be significantly improved;

[0039] 4) Compared with the solutions for improving heat dissipation by increasing the silicon thickness ratio of the customer's chip (requiring cutting thick wafers), exposing silicon by back grinding after molding (requiring a grinding machine), and using high thermal conductivity EMC materials (material price more than 2 times), this structure has obvious cost advantages in terms of equipment, process and materials;

[0040] 5) The present invention is applicable to both wafer-level fan-out (FOWLP) and board-level fan-out packaging (FOPLP). Description of the Drawings

[0041] Figure 1 Schematic diagram of the packaging structure of the specific embodiment of the present invention;

[0042] Figure 2 Process flow chart of the packaging method of the present invention (step S1 is not shown);

[0043] Figure 3 Schematic layout diagram of the chip and dummy chip structure of the present invention;

[0044] Figure 4 Schematic diagram of the thickness of the plastic encapsulation layer of the present invention;

[0045] The names corresponding to the serial numbers in the figure are as follows:

[0046] Encapsulated product 100;

[0047] Chip 10, dummy chip mechanism 20, silicon layer 21, surface insulation layer 22, plastic encapsulation layer 30, hybrid layer 40, first layer of PA 41, RDL 42, second layer of PA 43, I / O lead-out structure 50, UBM-CU layer 51, UBM-SN layer 52, carrier board 60, temporary bonding layer 61, saw street 70. Detailed implementation mode

[0048] A fan-out package structure with high heat dissipation performance, as shown in Figure 1 , which includes at least one chip 10, a plurality of dummy chip mechanisms 20, a plastic encapsulation layer 30, a hybrid layer 40, and an I / O lead-out structure 50;

[0049] Each group of dummy chip mechanisms 20 includes a silicon layer 21 and a surface insulation layer 22.

[0050] In a specific embodiment, a group of dummy chip mechanisms 20 are respectively arranged at intervals around the chip 10. The hybrid layer 40 includes a first layer of PA 41, RDL 42, and a second layer of PA 43.

[0051] The I / O lead-out structure 50 is specifically a UBM-CU layer 51 and a UBM-SN layer 52;

[0052] The chip 10 and the dummy chip mechanisms 20 are arranged on the surface of the plastic encapsulation layer 30. The plastic encapsulation layer 30 encapsulates and connects the chip 10 and the dummy chip mechanisms 20 into one body. The chip 10 is located in the central position area formed by the surrounding of the four groups of dummy chip mechanisms 20. At least one facade of the four groups of surrounding dummy chip mechanisms 20 is exposed. The surface insulation layer 22 of the dummy chip mechanism 20 is arranged flush with the functional layer of the chip 10. The hybrid layer 40 covers the surface insulation layer 22 of the dummy chip mechanism 20, the functional layer of the chip 10, and the corresponding surface of the plastic encapsulation layer 30. An I / O lead-out structure 50 is arranged on the hybrid layer 40. The I / O lead-out structure 50 is connected to the chip 10 through the RDL 42 in the hybrid layer 40.

[0053] During specific implementation, the silicon layer 21 of the dummy chip mechanism 20 is as thick as possible, so as to increase the volume ratio of silicon in the dummy chip mechanism as an encapsulation body.

[0054] A fan-out packaging method with high heat dissipation performance, as shown in Figures 2 - 4 :

[0055] Before the encapsulation of the chip 10, the chip 10 and the dummy chip mechanism 20 are typeset and arranged on the temporary bonding layer of the carrier board 60, such that the dummy chip mechanism 20 is arranged between adjacent chips 10, and the chip 10 is located in the central position area surrounded by a plurality of dummy chip mechanisms 20. Then, the surface area of the combination of the chip 10 and the dummy chip mechanism 20 is encapsulated to form the plastic encapsulation layer 30. After that, the carrier board 60 and the temporary bonding layer 61 are removed, such that the surface of the chip 10 is exposed, and at the same time, the insulating layer 22 of the dummy chip mechanism 20 is exposed. A hybrid layer 40 is arranged on the surface formed by the chip 10, the dummy chip mechanism 20, and the plastic encapsulation layer 30. Then, the preparation of the I / O lead-out structure 50 is completed. After that, dicing is performed, such that the surface area of the dummy chip mechanism 20 covers the dicing lane, and the side of the encapsulated product 100 corresponding to the dummy chip mechanism 20 partially exposes the silicon layer 21 of the dummy chip mechanism 20.

[0056] It includes the following steps:

[0057] S1. Pretreatment of the incoming wafers. The chip wafer and the dummy chip mechanism wafer are ground and diced to obtain the chips 10 and the dummy chip mechanisms 20 of preset sizes. A surface insulating layer 22 is prepared on the surface of the dummy chip mechanism 20.

[0058] The incoming wafers are tested, ground, and diced. At the same time, according to the actual requirements of the product, a redistribution layer (RDL) or a passivation layer (PA), or an alternating structure of multiple layers of RDL and PA is prepared on the surface of the incoming wafers. The wafers of the dummy chip mechanisms are also ground and diced in this stage. On the premise that there is no conflict with the product required thickness and process capabilities, the wafers of the dummy chip mechanisms 20 are as thick as possible. A surface insulating layer 22 needs to be prepared on the front side of the wafers of the dummy chip mechanisms 20 before dicing.

[0059] Specifically in implementation, the material of the surface insulating layer 22 is an insulating polymer material such as polyimide or epoxy resin, and its thickness is 5 - 30 μm, preferably 5 - 10 μm.

[0060] Or the surface insulating layer 22 is a deposited insulating inorganic coating such as silicon nitride, silicon oxide, or aluminum oxide, and its thickness is 0.5 - 10 μm, preferably 1 - 3 μm.

[0061] S2. Prepare the temporary bonding layer 61 on the carrier board 60.

[0062] The function of the temporary bonding layer 61 is to fix the mounted integrated circuit devices during subsequent wafer reconstruction. Its structure is one layer or multiple layers of composite, its material is a liquid slurry or a solid adhesive film, and its curing form is thermal curing or UV curing, or a combination of the two. The surface of the temporary bonding layer needs to have a certain adhesiveness to ensure that the chip components mounted on it do not slip or fall off during the transfer of the carrier board.

[0063] S3. Die bonding is performed to complete the mounting of the chip 10 and the dummy chip mechanism 20. It is required that the surface insulation layer 22 of the dummy chip mechanism 20 and the functional layer of the chip 10 are on the same side. The spacing between chips 10 and the spacing between the chip 10 and the dummy chip mechanism 20 are arranged according to the layout settings.

[0064] The layout requirements are as follows. The maximum size c of the dummy chip structure 20 in the x direction can be set to the minimum chip spacing a between two adjacent units in the x direction on the reconstructed wafer / large board minus twice the minimum allowable chip spacing b in the x direction of the product, that is, c max = a - 2b. To avoid plastic encapsulation voids caused by too small a gap between chips 10, it is recommended that b be not less than twice the maximum size of the filler particles in the plastic encapsulation material. The size d of the dummy chip mechanism 20 in the y direction is set to the minimum chip spacing e between two adjacent units in the y direction on the reconstructed wafer / large board minus twice the minimum allowable chip spacing f in the y direction of the product, that is, d max = e - 2f. To avoid plastic encapsulation voids caused by too small a gap between chips 10, it is recommended that f be not less than twice the maximum size of the filler particles in the plastic encapsulation material.

[0065] S4. Plastic encapsulation: The product formed by the chip 10 and the dummy chip mechanism 20 mounted in step S3 is encapsulated with a plastic encapsulation material.

[0066] S5. Debonding: The carrier plate 60 and the temporary bonding layer 61 are removed from the product.

[0067] The plastic encapsulation material is a polymer plastic encapsulation material in the form of powder, liquid or dry film, etc. The operation form is film pressing plastic encapsulation or vacuum film laminating. It is recommended that the set plastic encapsulation thickness of the plastic encapsulation layer 30 satisfy that the Overmold thickness value g is not less than twice the maximum size of the filler particles in the plastic encapsulation material.

[0068] S6. Additive manufacturing of the hybrid layer 40: Multilayer alternating RDL and PA layers are prepared according to product requirements to form the hybrid layer.

[0069] Specifically, when implementing, the first layer of PA 41 is prepared first, then the RDL 42 is prepared, and finally the second layer of PA 43 is prepared.

[0070] S7. Complete the preparation of the I / O lead-out structure.

[0071] Specifically, when implementing, the I / O lead-out structure 50 is a UBM, and the UBM includes a UBM-CU layer 51 and a UBM-SN layer 52.

[0072] S8. Perform testing, marking, cutting and packaging for shipment as required. The area of the dummy chip mechanism 20 straddles the cutting channel 70 between two groups of chips. Therefore, the side silicon of the encapsulated product is directly exposed after cutting. Preferably, the cutting channel 70 is located at the center position in the x or y direction of the area of the dummy chip mechanism 20.

[0073] The beneficial effects are as follows:

[0074] 1) Significantly increase the volume ratio of silicon (high thermal conductivity) in the package, and expose silicon on the structural side, which can significantly improve the heat dissipation performance of the product;

[0075] 2) Significantly increase the volume ratio of silicon (high strength) in the package, resulting in higher finished product strength and better reliability;

[0076] 3) Can effectively reduce the warping of the wafer or large board in the packaging process, which is beneficial to improving the process accuracy and production yield, and the warping of the finished product can also be significantly improved;

[0077] 4) Compared with the solutions for improving heat dissipation by increasing the silicon thickness ratio of the customer chip (requiring cutting thick wafers), exposing silicon by back grinding after plastic packaging (requiring a grinding machine), and using high thermal conductivity EMC materials (material price more than twice as high), this structure has obvious cost advantages in terms of equipment, process, and materials;

[0078] 5) The present invention is applicable to both wafer-level fan-out (FOWLP) and board-level fan-out package (FOPLP).

[0079] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and without departing from the spirit or basic characteristics of the present invention, the present invention can be implemented in other specific forms. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-restrictive. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present invention. Any reference signs in the claims should not be regarded as limiting the claimed invention.

[0080] In addition, it should be understood that although this specification is described according to embodiments, not every embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A fan-out package structure and packaging method with high heat dissipation performance, characterized in that It includes: At least one chip; A number of dummy chip mechanisms, each group of dummy chip mechanisms including a silicon layer and a surface insulation layer; A molding compound layer; A hybrid layer formed by arranging a number of RDLs and PAs; And an I / O lead-out structure; On the surface of the molding compound layer, chips and the dummy chip mechanisms are arranged. The molding compound layer encapsulates the chips and the dummy chip mechanisms into one body. The chip is located in the central position area surrounded by a number of dummy chip mechanisms. At least one facade of the dummy chip mechanisms arranged on the periphery is exposed. The surface insulation layer of the dummy chip mechanism and the surface layer of the chip are arranged flush. The hybrid layer covers the surface insulation layer of the dummy chip mechanism, the surface layer of the chip, and the corresponding surface layer of the molding compound layer. An I / O lead-out structure is provided on the hybrid layer, and the I / O lead-out structure is connected to the chip through the RDL in the hybrid layer.

2. The fan-out package structure with high heat dissipation performance according to claim 1, characterized in that: The I / O lead-out structure is a UBM structure or a BGA structure.

3. The fan-out package structure with high heat dissipation performance according to claim 1, characterized in that: The hybrid layer is prepared with multiple alternating layers of RDL and PA according to product requirements.

4. The fan-out package structure with high heat dissipation performance according to claim 1, characterized in that: The silicon layer of the dummy chip mechanism is as thick as possible, so as to increase the volume ratio of silicon in the package body of the dummy chip mechanism.

5. A fan-out packaging method with high heat dissipation performance, which is used to fabricate a fan-out packaging structure with high heat dissipation performance as described in any one of claims 1-4, characterized in that: Before chip packaging, the chips and the dummy chip mechanisms are typeset and set on the temporary bonding layer of the carrier board, so that the dummy chip mechanisms are arranged between adjacent chips, and the chips are located in the central position area surrounded by a number of dummy chip mechanisms. Then, the surface area where the chips and the dummy chip mechanisms are combined is encapsulated. After that, the carrier board and the temporary bonding layer are removed, so that the surface layer of the chip is exposed and at the same time the insulation layer of the dummy chip mechanism is exposed. A hybrid layer is arranged on the surface layer formed by the chips, the dummy chip mechanisms and the package body. Then, the preparation of the I / O lead-out structure is completed. After that, cutting is carried out so that the area of the dummy chip mechanism covers the cutting channel, and the part of the packaged product corresponding to the dummy chip mechanism laterally exposes the silicon layer of the dummy chip mechanism.

6. The fan-out packaging method with high heat dissipation performance according to claim 5, characterized in that, It includes the following steps: S1. Pretreatment of the incoming wafers. The chip wafers and the dummy chip mechanism wafers are ground and cut to obtain chips and dummy chip mechanisms of preset sizes. Among them, a surface insulation layer is prepared on the surface of the dummy chip mechanism. S2. Prepare a temporary bonding layer on the carrier board. S3. Die bonding. The chip and the dummy chip mechanism are mounted. It is required that the surface insulation layer of the dummy chip mechanism and the functional layer of the chip are on the same side, and the spacing between chips and the spacing between the chip and the dummy chip mechanism are arranged according to the typesetting setting. S4. Molding. The product formed by the chips and the dummy chip mechanisms mounted in step S3 is encapsulated with a molding compound. S5. Debonding. The carrier board and the temporary bonding layer are removed from the product. S6. Build-up manufacturing of the hybrid layer. Multiple alternating layers of RDL and PA are prepared according to product requirements to form the hybrid layer. S7. Complete the preparation of the I / O lead-out structure. S8. Complete testing, marking, cutting and packaging for shipment as required. The area of the dummy chip mechanism straddles the cutting channel between two groups of chips, so the lateral exposure of silicon of the packaged product is directly achieved after cutting.

7. A fan-out packaging method with high heat dissipation performance according to claim 6, characterized in that: In step S1, the incoming wafers are tested, polished, and diced. Meanwhile, according to the actual requirements of the product, a redistribution layer (RDL) or a passivation layer (PA), or an alternating structure of multiple layers of RDL and PA is prepared on the surface of the incoming wafers; the wafers of the dummy chip mechanism are also polished and diced in this stage. On the premise that it does not conflict with the product demand thickness and process capabilities, the wafers of the dummy chip mechanism are as thick as possible. A surface insulation layer needs to be prepared on the front side of the wafers of the dummy chip mechanism before dicing.

8. A fan-out packaging method with high heat dissipation performance according to claim 6, characterized in that: The material of the surface insulation layer is an insulating polymer material such as polyimide or epoxy resin, and its thickness is 5 - 30 μm; Or the surface insulation layer is a deposited insulating inorganic coating such as silicon nitride, silicon oxide, or aluminum oxide, and its thickness is 0.5 - 10 μm.

9. The fan-out packaging method with high heat dissipation performance according to claim 6, characterized in that: The layout requirements in step S3 are as follows. The maximum value of the size c of the dummy chip structure in the x direction can be set to the minimum chip pitch a between two adjacent units in the x direction on the reconstructed wafer / substrate minus twice the minimum chip pitch b allowed for the product in the x direction, that is, c max = a - 2b. To avoid molding voids caused by too small chip gaps, the value of b should not be less than twice the maximum size of the filler particles in the molding compound; the size d of the dummy chip structure in the y direction is set to the minimum chip pitch e between two adjacent units in the y direction on the reconstructed wafer / substrate minus twice the minimum chip pitch f allowed for the product in the y direction, that is, d max = e - 2f. To avoid molding voids caused by too small chip gaps, the value of f should not be less than twice the maximum size of the filler particles in the molding compound.

10. A fan-out packaging method with high heat dissipation performance according to claim 6, characterized in that: The function of the temporary bonding layer is to fix the mounted integrated circuit devices during subsequent wafer reconstruction. Its structure is one layer or multiple layers of composite. The material of the temporary bonding layer is a liquid slurry or a solid adhesive film. The curing form of the temporary bonding layer is thermal curing or UV curing, or a combination of both; the surface of the temporary bonding layer needs to have adhesiveness to ensure that the chip components mounted on it do not slip or fall off during the transfer of the carrier board.

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