Semiconductor device and manufacturing method, power module, power conversion circuit and vehicle

Abstract

The present invention discloses a semiconductor device and manufacturing method, a power module, a power conversion circuit, and a vehicle. The semiconductor device comprises: a semiconductor structure; wherein the semiconductor structure comprises a semiconductor body and a first dielectric layer, the first dielectric layer being located on one side of the semiconductor body; the first dielectric layer comprising a first conductive via and a second conductive via; a first conductive layer located in the first conductive via and electrically connected to the semiconductor body; a second conductive layer located in the second conductive via and electrically connected to the semiconductor structure; and the material of the first conductive layer and the material of the second conductive layer being different. The present invention provides a semiconductor device and manufacturing method, a power module, a power conversion circuit, and a vehicle, which can improve the reliability of semiconductor devices and reduce the manufacturing cost of semiconductor devices.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] In semiconductor devices of integrated circuits, the conductive layer in the semiconductor device is prone to problems such as voids during the process of filling conductive through-holes, resulting in poor filling quality of the conductive layer in the conductive through-holes, and further resulting in low reliability of the semiconductor device. Summary of the Invention

[0003] The present invention provides a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle, which can improve the reliability of the semiconductor device and reduce the manufacturing cost of the semiconductor device.

[0004] According to one aspect of the present invention, there is provided a semiconductor device, comprising:

[0005] A semiconductor structure; wherein the semiconductor structure comprises a semiconductor body and a first dielectric layer, wherein the first dielectric layer is located on one side of the semiconductor body; the first dielectric layer comprises a first conductive hole and a second conductive hole;

[0006] a first conductive layer located in the first conductive hole, wherein the first conductive layer is electrically connected to the semiconductor body;

[0007] A second conductive layer is located in the second conductive hole, wherein the second conductive layer is electrically connected to the semiconductor structure; and a material of the first conductive layer is different from a material of the second conductive layer.

[0008] Optionally, the semiconductor device provided in this embodiment further includes a third conductive layer and a fourth conductive layer;

[0009] The third conductive layer is located on a side of the first conductive layer away from the semiconductor body and is electrically connected to the first conductive layer;

[0010] The fourth conductive layer is located on a side of the second conductive layer away from the semiconductor body and is electrically connected to the second conductive layer.

[0011] Optionally, the semiconductor body includes a first surface and a second surface arranged opposite to each other;

[0012] The semiconductor body further includes a well region, a first region, and a second region, wherein the first region is configured to be of a first conductivity type and is disposed on the first surface; the well region is configured to be of the first conductivity type and is disposed on a side of the first region away from the first surface; the second region is configured to be of a second conductivity type and is disposed on the first surface, the second region being in contact with the first region; the first conductive layer is in contact with the first region and the second region, and the second conductive layer is in contact with the gate;

[0013] The semiconductor body further includes a gate structure; wherein the gate structure is disposed on the first surface or the gate structure extends from the first surface into the semiconductor body; the gate structure includes a second dielectric layer and a gate, wherein the second dielectric layer is used for insulating and spacing the gate and the semiconductor body;

[0014] The semiconductor device further includes a drain located on the second surface.

[0015] Optionally, the gate is made of polysilicon;

[0016] The material of the first conductive layer includes a compound produced by the reaction of nickel and the material of the second region or a compound produced by the reaction of aluminum and the material of the second region;

[0017] The material of the second conductive layer includes titanium and titanium nitride.

[0018] Optionally, the semiconductor structure includes an edge region and a central region, and the edge region surrounds the central region;

[0019] The thickness of the second dielectric layer located in the edge region is greater than the thickness of the second dielectric layer located in the central region.

[0020] Optionally, the semiconductor body comprises a silicon carbide semiconductor body or a gallium nitride semiconductor body. According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, the method comprising:

[0021] forming a semiconductor structure; wherein the semiconductor structure comprises a semiconductor body and a first dielectric layer, the first dielectric layer being located on one side of the semiconductor body; the first dielectric layer comprising a first conductive via and a second conductive via;

[0022] A first conductive layer is formed in the first conductive hole and a second conductive layer is formed in the second conductive hole, wherein the first conductive layer is electrically connected to the semiconductor body; the second conductive layer is electrically connected to the semiconductor structure; and the material of the first conductive layer is different from the material of the second conductive layer.

[0023] Optionally, forming a semiconductor structure includes:

[0024] forming a semiconductor body;

[0025] forming a first dielectric layer on one side of the semiconductor body;

[0026] forming a first conductive hole and a second conductive hole simultaneously in the first dielectric layer;

[0027] The forming of the first conductive layer in the first conductive hole and the forming of the second conductive layer in the second conductive hole comprises:

[0028] forming an isolation layer in the second conductive hole;

[0029] Depositing a first conductive material on a side of the first dielectric layer away from the semiconductor body to form a first conductive layer in the first conductive hole;

[0030] removing the isolation layer and the first conductive material outside the first conductive hole;

[0031] A second conductive layer is formed in the second conductive hole.

[0032] Optionally, the simultaneously forming a first conductive via and a second conductive via in the first dielectric layer includes:

[0033] forming a mask layer on a side of the first dielectric layer away from the semiconductor body; wherein the mask layer comprises a through hole, and the through hole exposes the first dielectric layer;

[0034] The first dielectric layer is etched using the mask layer as a mask to simultaneously form the first conductive via and the second conductive via.

[0035] Optionally, forming an isolation layer in the second conductive hole includes:

[0036] A sacrificial layer is formed on a side of the first dielectric layer away from the semiconductor body, wherein the sacrificial layer covers a surface of the first dielectric layer and fills the first conductive via and the second conductive via; a first thickness is greater than a second thickness, the first thickness being a vertical distance from the surface of the sacrificial layer away from the semiconductor structure to the surface of the semiconductor structure exposed by the first conductive via, and the second thickness being a vertical distance from the surface of the sacrificial layer away from the semiconductor structure to the surface of the semiconductor structure exposed by the second conductive via;

[0037] removing the sacrificial layer in the second conductive hole, and partially retaining the sacrificial layer in the first conductive hole;

[0038] forming an isolation transition layer on a side of the first dielectric layer away from the semiconductor structure, wherein the isolation transition layer is located in the second conductive hole and the first conductive hole and covers the sacrificial layer in the first conductive hole;

[0039] The sacrificial layer and the isolation transition layer in the first conductive hole are removed, and the isolation transition layer retained in the second conductive hole is used as the isolation layer.

[0040] Optionally, forming a semiconductor structure includes:

[0041] A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface disposed opposite to each other; the semiconductor body further comprising a well region, a first region, and a second region, wherein the first region is configured to be of a first conductivity type and disposed on the first surface; the well region is configured to be of the first conductivity type and disposed on a side of the first region away from the first surface; the second region is configured to be of a second conductivity type and disposed on the first surface, the second region being in contact with the first region;

[0042] forming a gate structure on the first surface; wherein the gate structure is disposed on the first surface or the gate structure extends from the first surface into the semiconductor body; the gate structure comprises a second dielectric layer and a gate, the second dielectric layer being used for insulating and spacing the gate from the semiconductor body;

[0043] forming the first dielectric layer on a side of the gate structure away from the second dielectric layer;

[0044] After forming the second conductive layer in the second conductive hole, the method further includes:

[0045] forming a third conductive layer located on a side of the first conductive layer away from the semiconductor body and electrically connected to the first conductive layer, and a fourth conductive layer located on a side of the second conductive layer away from the semiconductor body and electrically connected to the second conductive layer;

[0046] A drain electrode is formed on the second surface.

[0047] According to another aspect of the present invention, a power module is provided. The power module includes a substrate and at least one semiconductor device provided by an embodiment of the present invention. The substrate is used to support the semiconductor device.

[0048] According to another aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0049] The power conversion circuit includes a circuit board and at least one semiconductor device provided by an embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0050] According to another aspect of the present invention, a vehicle is provided, comprising a load and a power conversion circuit provided by any embodiment of the present invention, wherein the power conversion circuit is configured to convert alternating current (AC) into direct current (DC), convert AC into AC, convert DC into DC, or convert DC into AC, and then input the converted DC into the load.

[0051] An embodiment of the present invention provides a semiconductor device, which includes: a semiconductor structure, a first conductive layer and a second conductive layer. The semiconductor structure includes a semiconductor body and a first dielectric layer, and the first dielectric layer includes a first conductive hole and a second conductive hole. The first conductive layer is located in the first conductive hole, and the second conductive layer is located in the second conductive hole. The first conductive layer is electrically connected to the semiconductor body, and the second conductive layer is electrically connected to the semiconductor structure. In the embodiment of the present invention, the material of the first conductive layer is different from the material of the second conductive layer. Even when metals such as nickel and aluminum are deposited in the process of forming the first conductive layer, since the material of the second conductive layer is different from the material of the first conductive layer, the second conductive layer will not be nickel and aluminum, thereby avoiding the second conductive layer from violently reacting with the semiconductor structure to produce voids and other problems. In summary, the semiconductor device provided by the embodiment of the present invention can improve the reliability of the semiconductor device.

[0052] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0054] Figure 1 and Figure 2 It is a structural diagram of the manufacturing process of a semiconductor device provided in the related technology of the present invention.

[0055] Figure 3 3 is a schematic structural diagram of a semiconductor device provided according to an embodiment of the present invention.

[0056] Figure 4 3 is a schematic structural diagram of a semiconductor structure provided according to an embodiment of the present invention.

[0057] Figure 5 3 is a schematic structural diagram of another semiconductor device provided according to an embodiment of the present invention.

[0058] Figure 6 The figure is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0059] Figure 7 This is a schematic diagram of the semiconductor structure when the first dielectric layer is not formed.

[0060] Figure 8 It is a flowchart of another method for manufacturing a semiconductor device provided according to an embodiment of the present invention.

[0061] Figure 9 It is a schematic diagram of the structure after a first dielectric layer is formed on one side of the semiconductor body.

[0062] Figure 10 Schematic diagram of the structure of forming an isolation layer in the second conductive hole.

[0063] Figure 11 Schematic diagram of the structure after the first conductive layer is formed.

[0064] Figure 12 It is a schematic diagram of the structure after removing the isolation layer and the material of the first conductive layer outside the first conductive hole.

[0065] Figure 13 It is a flowchart of another method for manufacturing a semiconductor device provided according to an embodiment of the present invention.

[0066] Figure 14 Schematic diagram of the structure after forming the sacrificial layer.

[0067] Figure 15 This is a schematic diagram of the structure after removing the sacrificial layer located in the second conductive hole.

[0068] Figure 16 Schematic diagram of the structure after the isolation transition layer is formed.

[0069] Figure 17 3 is a schematic structural diagram of a semiconductor body provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0070] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0071] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0072] The inventors have studied and analyzed that the reasons for the generation of voids and other problems in the conductive layer during the process of filling the conductive through-holes are: Figure 1 and Figure 2 This is a schematic diagram of the manufacturing process of a semiconductor device provided in the related technology of the present invention, with reference to Figure 1 and Figure 2 Before forming the conductive layer, a first conductive hole 101 and a second conductive hole 102 are formed in the first dielectric layer 110 (refer to Figure 1 ), and then depositing a metal such as nickel or aluminum with low contact resistance into the first conductive via 101 and the second conductive via 102 simultaneously to form a conductive layer 130. Because the gate 120 is exposed in the second conductive via 102, during the formation of the conductive layer 130, the metals such as nickel and aluminum react violently with the gate 120 to form an alloy, thereby causing voids and other problems.

[0073] In order to improve the reliability of a semiconductor device, this embodiment provides a semiconductor device.

[0074] Figure 3 is a schematic structural diagram of a semiconductor device provided according to an embodiment of the present invention. Figure 4 is a schematic diagram of a semiconductor structure provided according to an embodiment of the present invention, with reference to Figure 3 and Figure 4 The semiconductor device provided in this embodiment includes: a semiconductor structure 100, a first conductive layer 150 and a second conductive layer 160; the semiconductor structure 100 includes a semiconductor body 210 and a first dielectric layer 110, the first dielectric layer 110 is located on one side of the semiconductor body 210; the first dielectric layer 110 includes a first conductive via 101 and a second conductive via 102 (refer to Figure 4); the first conductive layer 150 is located in the first conductive via 101, and the first conductive layer 150 is electrically connected to the semiconductor body 210; the second conductive layer 160 is located in the second conductive via 102, wherein the second conductive layer 160 is electrically connected to the semiconductor structure 100; the material of the first conductive layer 150 is different from the material of the second conductive layer 160.

[0075] Specifically, when manufacturing a semiconductor device, the first conductive via 101 and the second conductive via 102 in the first dielectric layer 110 can be formed simultaneously, thereby reducing the number of manufacturing steps of the semiconductor device and lowering the manufacturing cost of the semiconductor device.

[0076] In this embodiment, the material of the first conductive layer 150 is different from the material of the second conductive layer 160 . This can prevent the second conductive layer 160 , which is the same as the material of the first conductive layer 150 , from reacting with the gate electrode in the semiconductor structure 100 exposed by the second conductive via 102 to produce voids, thereby improving the reliability of the semiconductor device.

[0077] This embodiment provides a semiconductor device, which includes: a semiconductor structure, a first conductive layer, and a second conductive layer. The semiconductor structure includes a semiconductor body and a first dielectric layer, and the first dielectric layer includes a first conductive hole and a second conductive hole. The first conductive layer is located in the first conductive hole, and the second conductive layer is located in the second conductive hole. The first conductive layer is electrically connected to the semiconductor body, and the second conductive layer is electrically connected to the semiconductor structure. In this embodiment, the material of the first conductive layer is different from the material of the second conductive layer. When metals such as nickel and aluminum are deposited in the process of forming the first conductive layer, since the material of the second conductive layer is different from the material of the first conductive layer, the second conductive layer will not be nickel and aluminum, thereby avoiding the second conductive layer from violently reacting with the semiconductor structure to produce voids and other problems. In summary, the semiconductor device provided by this embodiment can improve the reliability of the semiconductor device.

[0078] Optional, Figure 5 is a schematic structural diagram of another semiconductor device provided according to an embodiment of the present invention, with reference to Figure 5 The semiconductor device provided in this embodiment also includes a third conductive layer 170 and a fourth conductive layer 180; the third conductive layer 170 is located on the side of the first conductive layer 150 away from the semiconductor body 210, and is electrically connected to the first conductive layer 150; the fourth conductive layer 180 is located on the side of the second conductive layer 160 away from the semiconductor body 210, and is electrically connected to the second conductive layer 160.

[0079] Specifically, the third conductive layer 170 is the source conductive layer of the semiconductor device, and the fourth conductive layer 180 can be the gate conductive layer of the semiconductor device. The third conductive layer 170 and the fourth conductive layer 180 can be electrically connected to external devices, thereby achieving electrical connection between the semiconductor device provided in this embodiment and the external device.

[0080] The material of the third conductive layer 170 may include aluminum, copper, tungsten, or Ti / Al / Ti, etc. The material of the fourth conductive layer 180 may include titanium nitride, molybdenum, or TiN / Al / TiN, etc.

[0081] Optional, continue to refer to Figure 5 The semiconductor body 210 includes a first surface S1 and a second surface S2 arranged opposite to each other; the semiconductor body 210 also includes a well region 211, a first region 212 and a second region 213, the first region 212 is set to the first conductivity type and is arranged on the first surface S1, and the well region 211 is set to the first conductivity type and is arranged on the side of the first region 212 away from the first surface S1. The second region 213 is set to the second conductivity type and is arranged on the first surface S1, and the second region 213 is in contact with the first region 212; the first conductive layer 150 is in contact with the first region 212 and the second region 213, and the second conductive layer 160 is in contact with the gate 120; the semiconductor body 210 also includes a gate structure 220; wherein the gate structure 220 is arranged on the first surface S1 or the gate structure 220 extends from the first surface S1 into the semiconductor body 210; the gate structure 220 includes a second dielectric layer 221 and the gate 120, and the second dielectric layer 221 is used to insulate the gate 120 and the semiconductor body 210; the semiconductor device also includes a drain 190; the drain 190 is located on the second surface S2.

[0082] Specifically, the first conductive layer 150 may be an ohmic contact layer, and the second conductive layer 160 may be another ohmic contact layer. The semiconductor body 210 may further include a substrate 215 and an epitaxial layer 216. The epitaxial layer 216 is located on one side of the substrate 215. The active region 214 and the well region 211 are both located on a side of the epitaxial layer 216 away from the substrate 215. The active region 214 may include a first region 212 and a second region 213, or may include only the second region 213.

[0083] In some embodiments of the present invention, the semiconductor body 210 may include only the epitaxial layer 216. The epitaxial layer 216 is a semiconductor layer formed on the substrate 215 through a single epitaxial growth process. Epitaxial growth processes include chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0084] A second dielectric layer 221 can be formed on the side of the epitaxial layer 216 away from the substrate 215 by a film forming process. The second dielectric layer 221 can be made of silicon oxide or a dielectric layer with a higher dielectric constant. The gate 120 is formed on the side of the second dielectric layer 221 away from the epitaxial layer 216.

[0085] Optionally, the material of the gate includes polysilicon; the material of the first conductive layer includes a compound produced by the reaction of nickel and the material of the second region or a compound produced by the reaction of aluminum and the material of the second region; and the material of the second conductive layer includes titanium and titanium nitride.

[0086] Specifically, the material of the first conductive layer includes a compound formed by the reaction of nickel with the material of the second region, or a compound formed by the reaction of aluminum with the material of the second region. This allows nickel or aluminum to be deposited during the formation of the first conductive layer, reducing the cost of manufacturing the first conductive layer and lowering the resistivity of the formed first conductive layer, thereby improving the reliability of the semiconductor device. Furthermore, nickel or aluminum can be deposited in the first conductive via. During the annealing process, the deposited metal reacts with the material of the second region to form a compound. This allows the first conductive layer within the first conductive via to be removed during the fabrication of the semiconductor structure, while the first conductive material outside the first conductive via is removed.

[0087] The second conductive layer can be made of titanium or titanium nitride to avoid problems such as voids caused by reactions between the second conductive layer and the gate material, which is polysilicon. This can also reduce the ohmic resistance of the second conductive layer and the manufacturing cost. Alternatively, the second conductive layer can be made of a relatively stable metal such as silver or gold.

[0088] Optional, continue to refer to Figure 5 The semiconductor structure includes an edge region 100b and a central region 100a, and the edge region 100b surrounds the central region 100a; the thickness of the second dielectric layer 221 in the edge region 100b is greater than the thickness of the second dielectric layer 221 in the central region 100a.

[0089] Specifically, the thicker second dielectric layer 221 in the edge region 100b imparts a good stress to the second dielectric layer 221 in the edge region 100b, thereby providing protection during semiconductor device packaging. Furthermore, the thicker second dielectric layer 221 in the edge region 100b allows the second conductive via to be positioned higher than the first conductive via along the thickness of the semiconductor body 210. This allows the second conductive via to be located on a side of the first conductive via that is further away from the semiconductor body 210. This facilitates semiconductor device fabrication, as detailed in the subsequent fabrication method.

[0090] Optionally, the semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0091] Specifically, the MOSFET power device corresponding to the silicon carbide semiconductor body is a silicon carbide MOSFET power device. The MOSFET power device corresponding to the gallium nitride semiconductor body is a gallium nitride MOSFET power device. Silicon carbide MOSFET power devices or gallium nitride MOSFET power devices have the advantages of high withstand voltage, low on-resistance, and high frequency, which can further improve the performance of semiconductor devices. Specifically, when silicon carbide or gallium nitride material is used as the semiconductor body 210, due to the high temperature resistance of silicon carbide or gallium nitride material, it can also prevent particles in the semiconductor body 210 from dissolving in the first conductive layer 150 and the second conductive layer 160 when the conductive material contacts the semiconductor body 210, thereby further improving the filling quality of the first conductive layer 150 and the second conductive layer 160.

[0092] Figure 6 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, with reference to Figure 6 The method for manufacturing a semiconductor device provided in this embodiment includes the following steps:

[0093] S110 , forming a semiconductor structure.

[0094] in, Figure 4 This is a schematic diagram of a semiconductor structure provided by an embodiment of the present invention, with reference to Figure 4 The semiconductor structure 100 provided in this embodiment includes a semiconductor body 210 and a first dielectric layer 110 , wherein the first dielectric layer 110 is located on one side of the semiconductor body 210 . The first dielectric layer 110 includes a first conductive via 101 and a second conductive via 102 .

[0095] Specifically, the semiconductor device provided in this embodiment may be a metal-oxide field-effect transistor (MOSFET). The semiconductor structure provided in this embodiment may be a structure that realizes the semiconductor function of a MOSFET power device. Figure 7 , Figure 7 This is a schematic diagram of a semiconductor structure before the first dielectric layer is formed. The semiconductor structure 100 further includes a gate structure 220, which includes a second dielectric layer 221 and a gate 120. The gate structure 220 can be located on one side of the semiconductor body 210. The first dielectric layer can be formed on the side of the gate structure 220 away from the semiconductor body 210 to complete the semiconductor structure 100.

[0096] S120 , forming a first conductive layer in the first conductive hole and forming a second conductive layer in the second conductive hole.

[0097] Among them, continue to refer to Figure 3 The first conductive layer 150 is electrically connected to the semiconductor body 210 ; the second conductive layer 160 is electrically connected to the semiconductor structure 100 ; and the material of the first conductive layer 150 is different from the material of the second conductive layer 160 .

[0098] The present embodiment provides a method for manufacturing a semiconductor device, which includes: first forming a semiconductor structure. The semiconductor structure includes a semiconductor body and a first dielectric layer, and the first dielectric layer includes a first conductive hole and a second conductive hole. Then, a first conductive layer is formed in the first conductive hole and a second conductive layer is formed in the second conductive hole. The formed first conductive layer is electrically connected to the semiconductor body, and the second conductive layer is electrically connected to the semiconductor structure. In this embodiment, the material of the first conductive layer is different from the material of the second conductive layer. When the conductive material deposited when manufacturing the first conductive layer is a metal such as nickel and aluminum, since the material of the second conductive layer is different from the material of the first conductive layer, the second conductive layer will not be nickel and aluminum, thereby avoiding the second conductive layer from violently reacting with the semiconductor structure to produce voids and other problems. In summary, the method for manufacturing a semiconductor device provided by this embodiment can improve the reliability of semiconductor devices.

[0099] Figure 8 is a flow chart of another method for manufacturing a semiconductor device according to an embodiment of the present invention, with reference to Figure 8 The method for manufacturing a semiconductor device provided in this embodiment includes the following steps:

[0100] S210 , forming a semiconductor body.

[0101] S220 , forming a first dielectric layer on one side of the semiconductor body.

[0102] Specifically, Figure 9 This is a schematic diagram of the structure after the first dielectric layer is formed on one side of the semiconductor body. Figure 9 A first dielectric layer may be formed on one side of the semiconductor body through a deposition process, and the first dielectric layer may cover the gate.

[0103] S230 , simultaneously forming a first conductive via and a second conductive via in the first dielectric layer.

[0104] For details, please refer to Figure 4 , Figure 4 In the structure formed in step S230, the first conductive via 101 exposes a portion of the semiconductor body 210, and the second conductive via 102 exposes a portion of the gate 120. There can be multiple first conductive vias 101.

[0105] The first dielectric layer 110 can be photolithographically formed simultaneously with the first conductive via 101 and the second conductive via 102. Simultaneous formation of the first conductive via 101 and the second conductive via 102 can reduce the number of steps required to manufacture the semiconductor device. Furthermore, simultaneous formation of the first conductive via 101 and the second conductive via 102 avoids the need for two photolithography processes, reducing the number of photolithography steps and preventing an increase in the number of photolithography steps that would increase the manufacturing cost of the semiconductor device and reduce the manufacturing yield of the semiconductor device.

[0106] S240 , forming an isolation layer in the second conductive hole.

[0107] Specifically, Figure 10 For a schematic diagram of a structure in which an isolation layer is formed in the second conductive hole, refer to Figure 10 After step S240, the isolation layer 140 is removed from the first conductive via 101, and the semiconductor body 210 is still exposed in the first conductive via 101. The isolation layer 140 in the second conductive via covers the gate 120 exposed by the second conductive via. The isolation layer 140 can be made of titanium or silicon nitride.

[0108] S250 , depositing a first conductive material on a side of the first dielectric layer away from the semiconductor body to form a first conductive layer in the first conductive hole.

[0109] Specifically, Figure 11 This is a schematic diagram of the structure after the first conductive layer is formed, refer to Figure 11 During the formation of the first conductive layer 150, since the isolation layer 140 is disposed within the second conductive via, the first conductive material only covers the isolation layer 140 and does not directly contact and react with the gate electrode 120 exposed by the second conductive via, thereby generating voids and other problems. Forming the first conductive layer using a deposition process can reduce the manufacturing cost of semiconductor devices. The first conductive material can be nickel or aluminum.

[0110] S260 , removing the isolation layer and the first conductive material outside the first conductive hole.

[0111] Specifically, Figure 12 This is a schematic diagram of the structure after removing the isolation layer and the first conductive material outside the first conductive hole, refer to Figure 12 The isolation layer and the first conductive material outside the first conductive via can be removed by wet etching. After the isolation layer is removed, the first conductive material covering the isolation layer is also removed. At this point, the isolation layer and the first conductive material are no longer inside the second conductive via 102, and the gate 120 is exposed in the second conductive via 102.

[0112] S270 , forming a second conductive layer in the second conductive hole.

[0113] For details, please refer to Figure 3 , Figure 3FIG. 1 is a schematic diagram of the structure after the second conductive layer 160 is formed.

[0114] This embodiment provides a method for fabricating a semiconductor device. The method comprises: first, simultaneously forming a first conductive via and a second conductive via in a first dielectric layer within a semiconductor structure. The simultaneous formation of the first and second conductive vias reduces the number of photolithography steps, thereby reducing manufacturing costs and avoiding problems such as misalignment that may arise during the two photolithography steps. Then, forming an isolation layer within the second conductive via, such that the isolation layer covers the second conductive via while leaving the semiconductor body exposed within the first conductive via. Next, forming a first conductive layer within the first conductive via. Because the second conductive via is covered by the isolation layer, the first conductive material cannot fall into the second conductive via during the formation of the first conductive layer. Even if the contact metal within the first conductive via is nickel, aluminum, or the like, the first conductive material is prevented from reacting with the semiconductor structure exposed by the second conductive via, thereby preventing problems such as voids. Next, removing the isolation layer and the first conductive material outside the first conductive via, and forming a second conductive layer electrically connected to the semiconductor structure within the second conductive via, thereby forming a semiconductor device. In summary, the method for fabricating a semiconductor device provided by this embodiment can improve the reliability of the semiconductor device and reduce its manufacturing costs.

[0115] Optionally, forming the first conductive via and the second conductive via simultaneously in the first dielectric layer includes the following steps:

[0116] S231 , forming a mask layer on a side of the first dielectric layer away from the semiconductor body; wherein the mask layer includes a through hole, and the through hole exposes the first dielectric layer.

[0117] S232 , etching the first dielectric layer using the mask layer as a mask to simultaneously form a first conductive via and a second conductive via.

[0118] For details, please refer to Figure 9 , available in Figure 9 As shown, a mask layer is formed on a side of the first dielectric layer 110 away from the semiconductor body 210 . The mask layer may be a photoresist layer.

[0119] Optional, Figure 13 is a flow chart of another method for manufacturing a semiconductor device according to an embodiment of the present invention, with reference to Figure 13 The method for manufacturing a semiconductor device provided in this embodiment includes the following steps:

[0120] S310 , forming a semiconductor body.

[0121] The content of step S310 is the same as that of step S210. For the description of step S310, please refer to the description of step S210, which will not be repeated here.

[0122] S320 , forming a first dielectric layer on one side of the semiconductor body.

[0123] The content of step S320 is the same as that of step S220. For the description of step S320, please refer to the description of step S220, which will not be repeated here.

[0124] S330 , simultaneously forming a first conductive via and a second conductive via in the first dielectric layer.

[0125] The content of step S330 is the same as that of step S230. For the description of step S330, please refer to the description of step S230, which will not be repeated here.

[0126] S340 , forming a sacrificial layer on a side of the first dielectric layer away from the semiconductor body.

[0127] Among them, reference Figure 14 , Figure 14 This is a schematic diagram of the structure after the sacrificial layer is formed. The sacrificial layer 310 covers the surface of the first dielectric layer 110 and fills the first conductive via 101 and the second conductive via 102. The first thickness h1 is greater than the second thickness h2. The first thickness h1 is the vertical distance from the surface of the sacrificial layer 310 away from the semiconductor structure 100 to the surface of the semiconductor structure 100 exposed by the first conductive via 101, and the second thickness h2 is the vertical distance from the surface of the sacrificial layer 310 away from the semiconductor structure 100 to the surface of the semiconductor structure 100 exposed by the second conductive via 102. The material of the sacrificial layer 310 can be photoresist. The photoresist is applied to the side of the first dielectric layer 110 away from the semiconductor body 210 and cured to form the sacrificial layer 310. The photoresist can be either positive or negative photoresist.

[0128] Specifically, the surface of the sacrificial layer 310 away from the semiconductor structure 100 can be flush. The first thickness h1 is greater than the second thickness h2, indicating that the thickness of the sacrificial layer 310 on the side of the first conductive via 101 away from the semiconductor body 210 is greater than the thickness of the sacrificial layer 310 on the side of the second conductive via 102 away from the semiconductor body 210. This configuration allows for etching of the sacrificial layer 310, allowing a portion of the sacrificial layer 310 to remain in the first conductive via 101 after the sacrificial layer 310 in the second conductive via 102 is completely etched.

[0129] S350 , removing the sacrificial layer in the second conductive via, and partially retaining the sacrificial layer in the first conductive via.

[0130] Specifically, refer to Figure 15 , Figure 15This is a schematic diagram of the structure after removing the sacrificial layer located in the second conductive hole. The sacrificial layer 310 on the side of the second conductive hole 102 away from the semiconductor body 210 and the sacrificial layer 310 on the side of the first conductive hole 101 away from the semiconductor body 210 can be etched synchronously. Since the first thickness is greater than the second thickness, after the sacrificial layer in the second conductive hole is completely removed, some sacrificial layer 310 will still remain in the first conductive hole to cover the first conductive hole.

[0131] S360 , forming an isolation transition layer on a side of the first dielectric layer away from the semiconductor structure.

[0132] Among them, reference Figure 16 , Figure 16 This is a schematic diagram of the structure after the isolation transition layer is formed. The isolation transition layer 320 is located in the second conductive hole and the first conductive hole, and covers the sacrificial layer 310 in the first conductive hole.

[0133] Specifically, because the first conductive via is filled with the sacrificial layer 310, the isolation transition layer 320 does not directly contact the semiconductor body 210 exposed by the first conductive via. Since the second conductive via is unfilled, the isolation transition layer 320 fills the second conductive via. A deposition process can be used to form the isolation transition layer 320. In addition to being located within the second conductive via and on the surface of the sacrificial layer 310, the isolation transition layer 320 also covers the surface of the first dielectric layer 110 away from the semiconductor body 210.

[0134] S370 , removing the sacrificial layer and the isolation transition layer in the first conductive hole, and retaining the isolation transition layer in the second conductive hole as an isolation layer.

[0135] Specifically, since the isolation transition layer in the first conductive hole is attached to one side of the sacrificial layer, when removing the isolation transition layer on one side of the sacrificial layer, only the sacrificial layer needs to be removed. After the sacrificial layer is removed, the isolation transition layer attached to one side of the sacrificial layer will be removed. A wet etching process can be used to remove the sacrificial layer in the first conductive hole and thereby simultaneously remove the isolation transition layer on the side of the sacrificial layer. The isolation transition layer in the second conductive hole is in direct contact with the semiconductor structure. During the process of removing the sacrificial layer, the isolation transition layer in the second conductive hole does not react with the solution for removing the sacrificial layer. Continue to refer to Figure 10 The isolation transition layer retained in the second conductive hole is the isolation layer 140. If the isolation transition layer 320 covers the surface of the first dielectric layer 110 away from the semiconductor body 210, after step S360, the isolation transition layer 320 located on the surface of the first dielectric layer 110 away from the semiconductor body 210 may still exist. However, in step S390, the isolation transition layer 320 located on the surface of the first dielectric layer 110 will be removed.

[0136] S380 , depositing a first conductive material on a side of the first dielectric layer away from the semiconductor body to form a first conductive layer in the first conductive hole.

[0137] The content of step S380 is the same as that of step S250. For the description of step S380, please refer to the description of step S250, which will not be repeated here.

[0138] S390 , removing the isolation layer and the first conductive material outside the first conductive hole.

[0139] Among them, the content of step S390 is the same as that of step S260. For the description of step S390, please refer to the description of step S260, which will not be repeated here.

[0140] S391. Form a second conductive layer in the second conductive hole.

[0141] Among them, the content of step S391 is the same as that of step S270. For the description of step S391, please refer to the description of step S270, which will not be repeated here.

[0142] Optional, continue to refer to Figure 10 , the thickness of the isolation layer 140 is greater than or equal to the depth of the second conductive hole.

[0143] Specifically, setting the thickness of the isolation layer 140 greater than the depth of the second conductive hole can prevent the first conductive material from being deposited into the second conductive hole during the formation of the first conductive layer and reacting with the gate in the second conductive hole to cause voids and other problems.

[0144] Optionally, the semiconductor structure further includes a gate structure, and forming the semiconductor structure includes the following steps:

[0145] S111. Provide a semiconductor body.

[0146] Among them, reference Figure 17 , Figure 17 It is a structural schematic diagram of a semiconductor body provided according to an embodiment of the present invention, wherein the semiconductor body 210 includes a first surface S1 and a second surface S2 arranged opposite to each other; the semiconductor body 210 also includes a well region 211 and a first region 212, wherein the first region 212 is arranged on the first surface S1, and the well region 211 is arranged on a side of the first region 212 away from the first surface S1.

[0147] Specifically, the semiconductor body 210 may further include a second region 213, a substrate 215, and an epitaxial layer 216. The epitaxial layer 216 is located on one side of the substrate 215, and the active region 214 and the well region 211 are both located on a side of the epitaxial layer 216 away from the substrate 215. The active region 214 may include the first region 212 and the second region 213, or may include only the second region 213.

[0148] In some embodiments of the present invention, the semiconductor body 210 may include only the epitaxial layer 216. The epitaxial layer 216 is a semiconductor layer formed on the substrate 215 through a single epitaxial growth process. Epitaxial growth processes include chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0149] S112 , forming a gate structure on the first surface.

[0150] Among them, continue to refer to Figure 7 The gate structure 220 is disposed on the first surface S1 or the gate structure 220 extends from the first surface S1 into the semiconductor body 210 ; the gate structure 220 includes a second dielectric layer 221 and the gate 120 , and the second dielectric layer 221 is used for insulating the gate 120 and the semiconductor body 210 ;

[0151] Specifically, a second dielectric layer 221 can be formed on the side of the epitaxial layer 216 away from the substrate 215 through a film forming process. The second dielectric layer 221 can be made of silicon oxide or a dielectric layer with a higher dielectric constant. The gate 120 is formed on the side of the second dielectric layer 221 away from the epitaxial layer 216.

[0152] S113 , forming a first dielectric layer on a side of the gate structure away from the second dielectric layer.

[0153] For details, please refer to Figure 9 A first dielectric layer 110 is formed on the side of the gate 120 away from the second dielectric layer 221 through a film formation process. The first dielectric layer 110 is used to insulate the gate 120 from the subsequently formed first and second conductive layers. The present embodiment does not impose any particular restrictions on the material of the first dielectric layer 110; any dielectric layer with insulating properties may be selected.

[0154] Optionally, the material of the gate includes polysilicon; the first conductive material includes nickel or aluminum; and the material of the second conductive layer includes titanium and titanium nitride.

[0155] Optionally, providing a semiconductor body includes providing a silicon carbide semiconductor body or providing a gallium nitride semiconductor body.

[0156] Specifically, the MOSFET power device corresponding to the silicon carbide semiconductor body is a silicon carbide MOSFET power device. The MOSFET power device corresponding to the gallium nitride semiconductor body is a gallium nitride MOSFET power device. Silicon carbide MOSFET power devices or gallium nitride MOSFET power devices have the advantages of high withstand voltage, low on-resistance, and high frequency, which can further improve the performance of semiconductor devices. Specifically, when silicon carbide or gallium nitride material is used as the semiconductor body 210, due to the high temperature resistance of silicon carbide or gallium nitride material, it can also prevent particles in the semiconductor body 210 from dissolving in the first conductive layer 150 and the second conductive layer 160 when the conductive material contacts the semiconductor body 210, thereby further improving the filling quality of the first conductive layer 150 and the second conductive layer 160.

[0157] It should be noted that the semiconductor device provided by the embodiment of the present invention can be manufactured by the method for manufacturing the semiconductor device provided by the embodiment of the present invention.

[0158] The method for manufacturing a semiconductor device provided in this embodiment has corresponding beneficial effects as the semiconductor device provided in any embodiment of the present invention. For technical details not detailed in this embodiment, please refer to the semiconductor device provided in any embodiment of the present invention.

[0159] An embodiment of the present invention provides a power module comprising a substrate and at least one semiconductor device according to any embodiment of the present invention, wherein the substrate is used to support the semiconductor device. Therefore, the beneficial effects of the power module including any semiconductor device according to any embodiment of the present invention are not further described here.

[0160] An embodiment of the present invention provides a power conversion circuit for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of the present invention, the semiconductor device being electrically connected to the circuit board. Therefore, the beneficial effects of including the semiconductor device as described in any embodiment of the present invention in the power conversion circuit are not further elaborated here.

[0161] An embodiment of the present invention further provides a vehicle including a load and a power conversion circuit according to any embodiment of the present invention. The power conversion circuit is configured to convert AC power to DC power, AC power to AC power, DC power to DC power, or DC power to AC power, and then input the converted power to the load. Therefore, the beneficial effects of including the power conversion circuit according to any embodiment of the present invention in the vehicle are not further elaborated here.

[0162] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0163] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor structure comprising a semiconductor body and a first dielectric layer, wherein the first dielectric layer is located on one side of the semiconductor body; The first dielectric layer includes a first conductive hole and a second conductive hole; a first conductive layer located in the first conductive hole, wherein the first conductive layer is electrically connected to the semiconductor body; a second conductive layer located in the second conductive hole, wherein the second conductive layer is electrically connected to the semiconductor structure, and a material of the second conductive layer includes any one of titanium and titanium nitride, gold, and silver, or a combination thereof; and a material of the first conductive layer is different from a material of the second conductive layer; The semiconductor body includes a first surface and a second surface disposed opposite to each other; the semiconductor body further includes a gate structure; wherein the gate structure is disposed on the first surface or the gate structure extends from the first surface into the semiconductor body; the gate structure includes a second dielectric layer and a gate, the gate material includes polysilicon, the second dielectric layer is used for insulating and spacing the gate from the semiconductor body; the second conductive layer is in contact with the gate; The semiconductor device further includes a third conductive layer and a fourth conductive layer; The third conductive layer is located on a side of the first conductive layer away from the semiconductor body and is electrically connected to the first conductive layer; The fourth conductive layer is located on a side of the second conductive layer away from the semiconductor body and is electrically connected to the second conductive layer; The third conductive layer is a source conductive layer of the semiconductor device, and the fourth conductive layer is a gate conductive layer of the semiconductor device.

2. The semiconductor device according to claim 1, wherein The semiconductor body further includes a well region, a first region, and a second region. The first region is configured to be of a first conductivity type and is disposed on the first surface. The well region is configured to be of the first conductivity type and is disposed on a side of the first region away from the first surface. The second region is configured to be of a second conductivity type and is disposed on the first surface, and the second region is in contact with the first region. The first conductive layer is in contact with the first region and the second region, and the second conductive layer is in contact with the gate; The semiconductor device further includes a drain located on the second surface.

3. The semiconductor device according to claim 2, wherein The material of the first conductive layer includes a compound generated by the reaction of nickel and the material of the second region or a compound generated by the reaction of aluminum and the material of the second region.

4. The semiconductor device according to claim 3, wherein The semiconductor structure includes an edge region and a central region, wherein the edge region surrounds the central region; The thickness of the second dielectric layer located in the edge region is greater than the thickness of the second dielectric layer located in the central region.

5. The semiconductor device according to claim 1, wherein The semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

6. A method for manufacturing a semiconductor device, characterized in that: include: forming a semiconductor structure; wherein the semiconductor structure comprises a semiconductor body and a first dielectric layer, the first dielectric layer being located on one side of the semiconductor body; the first dielectric layer comprising a first conductive via and a second conductive via; forming a first conductive layer in the first conductive hole and forming a second conductive layer in the second conductive hole, wherein the first conductive layer is electrically connected to the semiconductor body; the second conductive layer is electrically connected to the semiconductor structure; a material of the second conductive layer includes any one of titanium and titanium nitride, gold, and silver, or a combination thereof; and the material of the first conductive layer is different from the material of the second conductive layer; The semiconductor body includes a first surface and a second surface disposed opposite to each other; the semiconductor body further includes a gate structure; wherein the gate structure is disposed on the first surface or the gate structure extends from the first surface into the semiconductor body; the gate structure includes a second dielectric layer and a gate, the gate material includes polysilicon, the second dielectric layer is used for insulating and spacing the gate from the semiconductor body; the second conductive layer is in contact with the gate; The semiconductor device further includes a third conductive layer and a fourth conductive layer; The third conductive layer is located on a side of the first conductive layer away from the semiconductor body and is electrically connected to the first conductive layer; The fourth conductive layer is located on a side of the second conductive layer away from the semiconductor body and is electrically connected to the second conductive layer; The third conductive layer is a source conductive layer of the semiconductor device, and the fourth conductive layer is a gate conductive layer of the semiconductor device.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The forming of the semiconductor structure comprises: forming a semiconductor body; forming a first dielectric layer on one side of the semiconductor body; forming a first conductive hole and a second conductive hole simultaneously in the first dielectric layer; The forming of the first conductive layer in the first conductive hole and the forming of the second conductive layer in the second conductive hole comprises: forming an isolation layer in the second conductive hole; Depositing a first conductive material on a side of the first dielectric layer away from the semiconductor body to form a first conductive layer in the first conductive hole; removing the isolation layer and the first conductive material outside the first conductive hole; A second conductive layer is formed in the second conductive hole.

8. The production method according to claim 7, characterized in that: The step of simultaneously forming a first conductive hole and a second conductive hole in the first dielectric layer includes: forming a mask layer on a side of the first dielectric layer away from the semiconductor body; wherein the mask layer comprises a through hole, and the through hole exposes the first dielectric layer; The first dielectric layer is etched using the mask layer as a mask to simultaneously form the first conductive via and the second conductive via.

9. The production method according to claim 7, characterized in that: The forming of the isolation layer in the second conductive hole includes: A sacrificial layer is formed on a side of the first dielectric layer away from the semiconductor body, wherein the sacrificial layer covers a surface of the first dielectric layer and fills the first conductive via and the second conductive via; a first thickness is greater than a second thickness, the first thickness being a vertical distance from the surface of the sacrificial layer away from the semiconductor structure to the surface of the semiconductor structure exposed by the first conductive via, and the second thickness being a vertical distance from the surface of the sacrificial layer away from the semiconductor structure to the surface of the semiconductor structure exposed by the second conductive via; removing the sacrificial layer in the second conductive hole, and partially retaining the sacrificial layer in the first conductive hole; forming an isolation transition layer on a side of the first dielectric layer away from the semiconductor structure, wherein the isolation transition layer is located in the second conductive hole and the first conductive hole and covers the sacrificial layer in the first conductive hole; The sacrificial layer and the isolation transition layer in the first conductive hole are removed, and the isolation transition layer retained in the second conductive hole is used as the isolation layer.

10. The manufacturing method according to claim 7, characterized in that: The forming of the semiconductor structure comprises: A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface disposed opposite to each other; the semiconductor body further comprising a well region, a first region, and a second region, wherein the first region is configured to be of a first conductivity type and disposed on the first surface; the well region is configured to be of the first conductivity type and disposed on a side of the first region away from the first surface; the second region is configured to be of a second conductivity type and disposed on the first surface, the second region being in contact with the first region; forming a gate structure on the first surface; wherein the gate structure is disposed on the first surface or the gate structure extends from the first surface into the semiconductor body; the gate structure comprises a second dielectric layer and a gate, the second dielectric layer being used for insulating and spacing the gate and the semiconductor body; forming the first dielectric layer on a side of the gate structure away from the second dielectric layer; After forming the second conductive layer in the second conductive hole, the method further includes: forming a third conductive layer located on a side of the first conductive layer away from the semiconductor body and electrically connected to the first conductive layer, and a fourth conductive layer located on a side of the second conductive layer away from the semiconductor body and electrically connected to the second conductive layer; A drain electrode is formed on the second surface.

11. A power module, characterized in that: The invention comprises a substrate and at least one semiconductor device according to any one of claims 1 to 5, wherein the substrate is used for carrying the semiconductor device.

12. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of claims 1 to 5, wherein the semiconductor device is electrically connected to the circuit board.

13. A vehicle, characterized in that: It includes a load and the power conversion circuit as claimed in claim 12, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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