A wide-area power waveform synchronous monitoring system and synchronous monitoring method

Abstract

The present invention provides a wide-area power waveform synchronization monitoring system and a synchronization monitoring method. In the synchronization monitoring system, first, the terminal layer nodes adopt multi-channel synchronization sampling technology combined with cross-calibration, phase error detection and correction filtering to ensure that data from different signal sources can be collected at the same time, and eliminate the delay caused by hardware differences and different transmission paths, so that the data synchronization accuracy uploaded to the edge layer nodes is high and the accuracy is also high. Then, the edge layer nodes can maintain the time synchronization accuracy at a high level by executing a cross-level clock synchronization mechanism. Finally, synchronization analysis is performed through the master station layer nodes to ensure the reliability of the monitoring results. It can be seen that in the present invention, the terminal layer nodes, edge layer nodes and master station layer nodes perform corresponding synchronization monitoring tasks at different levels, which can improve the synchronization accuracy and reduce the synchronization error, thereby meeting the stringent requirements of high-precision time synchronization and improving the reliability of the synchronization monitoring results.

Description

Technical Field

[0001] The present invention relates to the technical field of smart grid monitoring, and in particular to a wide-area power waveform synchronous monitoring system and a synchronous monitoring method. Background Art

[0002] Wide-area power waveform synchronization monitoring mainly uses time synchronization technology to monitor and analyze the waveforms of various electrical quantities in the power grid, such as voltage and current. In this way, the operating status of the power grid can be grasped in real time, potential problems can be discovered in time, and the safe and stable operation of the power system can be guaranteed.

[0003] In traditional time synchronization technologies, GPS (Global Positioning System) satellite timing, NTP (Network Time Protocol), and Precision Time Protocol constitute the main solution system.

[0004] GPS satellite timing solutions primarily achieve μs-level synchronization through satellite signals. However, satellite signals are susceptible to environmental factors such as building obstruction and electromagnetic interference, resulting in synchronization errors often exceeding 1 μs indoors or in complex terrain. NTP primarily uses a network-based software protocol stack for time synchronization. While this solution is simple to deploy, it is limited by operating system scheduling and network jitter, resulting in synchronization accuracy limited to milliseconds. Precision time protocols, including IEEE 1588v2 / PTP (Precision Time Synchronization Protocol), are primarily based on hardware timestamping. While they can achieve sub-microsecond accuracy in local area networks (LANs), when deployed in complex network topologies with multi-hop switching, asymmetric routing, or bursty traffic, path delay uncertainty and the nonlinear response of the clock servo system can significantly increase cumulative clock drift. This is especially true when synchronizing across heterogeneous network domains. Frequency offset compensation errors between master and slave clocks grow exponentially, ultimately degrading synchronization accuracy to tens of microseconds.

[0005] In summary, traditional time synchronization technology has too large synchronization errors and insufficient synchronization accuracy, making it difficult to meet the stringent requirements of high-precision time synchronization at the hundred-nanosecond level in emerging fields such as power distribution system operation regulation and massive source and load control. Summary of the Invention

[0006] In order to overcome the defects of the above-mentioned traditional time synchronization technology, such as large synchronization error and insufficient synchronization accuracy, the present invention provides a wide-area power waveform synchronization monitoring system, comprising: a master layer node, an edge layer node and a plurality of terminal layer nodes that are communicatively connected to each other;

[0007] Each of the terminal layer nodes is configured to perform multi-channel synchronous sampling based on a reference clock to obtain multiple sampling results; perform cross-calibration and phase error detection on the multiple sampling results to obtain multiple error feedback sampling results; perform correction filtering and delay compensation on the multiple error feedback sampling results to obtain an initial power waveform and upload it to the edge layer node;

[0008] The edge layer node is configured to perform cross-layer clock synchronization on the received initial power waveform based on the reference clock, obtain a synchronized power waveform and upload it to the master layer node;

[0009] The master station layer node is used to perform synchronization analysis on the synchronous power waveform based on the reference clock according to the set time synchronization accuracy to obtain the synchronization monitoring result of the power waveform.

[0010] Optionally, the terminal layer node is specifically used to obtain the reference clock provided by the GPS / PTP clock source, use the DPLL digital phase-locked loop to lock the local clock with the reference clock to obtain a clock signal; use the calibration clock distributor to adjust the clock signal to obtain a unified time reference; perform multi-channel synchronous sampling under the unified time reference to obtain multiple sampling results.

[0011] Optionally, the terminal layer node is specifically used to calculate the correlation between the multiple sampling results using a cross-correlator; based on the correlation between the multiple sampling results, a phase error detection unit is used to analyze the phase deviation between different channels to obtain multiple error feedback sampling results.

[0012] Optionally, the terminal layer node is specifically used to read the filter coefficients corresponding to the multiple error feedback sampling results in the coefficient memory; use the shift register chain to pass the multiple error feedback sampling results to the MAC operation unit array in a set order; based on the filter coefficients, use the MAC operation unit array to perform filtering to obtain a corrected filtering result; and perform delay compensation on the corrected filtering result to obtain an initial power waveform.

[0013] Optionally, the terminal layer node is specifically used to perform error calculation based on the multiple sampling results to obtain an error calculation result; if the error calculation result is greater than a preset error threshold, the delay line is adjusted to perform delay compensation on the correction filtering result until the error calculation result after delay compensation is no greater than the preset error threshold, and the correction filtering result after delay compensation at this time is used as the initial power waveform.

[0014] Optionally, the terminal layer node is specifically used to adjust the delay amount of the initial delay value based on a proportional integral algorithm to generate a new delay value, and update the new delay value to the delay register to achieve dynamic calibration of the delay line.

[0015] Optionally, the edge layer nodes are configured in the substation and interconnected with the master layer nodes via a 5G network, and the terminal layer nodes in the substation are interconnected with the edge layer nodes via optical fibers or network cables; and / or

[0016] The edge layer nodes are configured in the distribution station area and are interconnected with the master station layer nodes through optical fibers. The terminal layer nodes in the distribution station area are interconnected with the edge layer nodes through power line carriers PLC and optical fibers.

[0017] Optionally, the initial power waveform incorporates energy flow and information flow.

[0018] On the other hand, the present invention also provides a method for synchronously monitoring wide-area power waveforms, comprising:

[0019] Perform multi-channel synchronous sampling based on the reference clock to obtain multiple sampling results;

[0020] performing cross calibration and phase error detection on the multiple sampling results to obtain multiple error feedback sampling results;

[0021] Correction filtering and delay compensation are performed on the multiple error feedback sampling results to obtain an initial power waveform which is uploaded to the edge layer node. The edge layer node is used to perform cross-level clock synchronization on the received initial power waveform based on the reference clock to obtain a synchronized power waveform, and the master layer node performs synchronization analysis on the synchronized power waveform according to the set time synchronization accuracy based on the reference clock to obtain a synchronized monitoring result of the power waveform.

[0022] Optionally, performing multi-channel synchronous sampling based on a reference clock to obtain multiple sampling results includes:

[0023] Obtain the reference clock provided by the GPS / PTP clock source, and use the DPLL digital phase-locked loop to lock the local clock with the reference clock to obtain a clock signal;

[0024] Adjusting the clock signal using a calibration clock distributor to obtain a unified time reference;

[0025] Multi-channel synchronous sampling is performed under the unified time base to obtain multiple sampling results.

[0026] Optionally, performing cross-calibration and phase error detection on the multiple sampling results to obtain multiple error feedback sampling results includes:

[0027] Calculating correlations between the plurality of sampling results using a cross-correlator;

[0028] Based on the correlation between the multiple sampling results, a phase error detection unit is used to analyze the phase deviations between different channels to obtain multiple error feedback sampling results.

[0029] Optionally, performing correction filtering and delay compensation on the multiple error feedback sampling results to obtain an initial power waveform includes:

[0030] Reading filter coefficients corresponding to the plurality of error feedback sampling results in a coefficient memory;

[0031] Using a shift register chain, the plurality of error feedback sampling results are transferred to a MAC operation unit array in a set order;

[0032] Based on the filter coefficient, the MAC operation unit array is used to perform filtering to obtain a corrected filtering result; and delay compensation is performed on the corrected filtering result to obtain an initial power waveform.

[0033] Optionally, performing delay compensation on the correction filtering result to obtain an initial power waveform includes:

[0034] Perform error calculation based on the multiple sampling results to obtain an error calculation result;

[0035] If the error calculation result is greater than the preset error threshold, the delay line is adjusted to perform delay compensation on the correction filtering result until the error calculation result after delay compensation is no greater than the preset error threshold, and the correction filtering result after delay compensation at this time is used as the initial power waveform.

[0036] Optionally, adjusting the delay line includes:

[0037] The initial delay value is adjusted by the delay amount based on the proportional integral algorithm to generate a new delay value, and the new delay value is updated to the delay register to realize dynamic calibration of the delay line.

[0038] Optionally, the edge layer nodes are configured in the substation and interconnected with the master layer nodes via a 5G network, and the terminal layer nodes in the substation are interconnected with the edge layer nodes via optical fibers or network cables; and / or

[0039] The edge layer nodes are configured in the distribution station area and are interconnected with the master station layer nodes through optical fibers. The terminal layer nodes in the distribution station area are interconnected with the edge layer nodes through power line carriers PLC and optical fibers.

[0040] Optionally, the initial power waveform incorporates energy flow and information flow, and the information flow is a multi-dimensional time-frequency domain characteristic quantity of the energy flow that reflects the operating status of the system.

[0041] On the other hand, the present invention also provides a wide-area power waveform synchronous monitoring system, comprising:

[0042] A multi-channel synchronous sampling module is used to perform multi-channel synchronous sampling based on a reference clock to obtain multiple sampling results;

[0043] an error feedback module, configured to perform cross-calibration and phase error detection on the plurality of sampling results to obtain a plurality of error feedback sampling results;

[0044] The power waveform generation module is used to perform correction filtering and delay compensation on the multiple error feedback sampling results to obtain an initial power waveform and upload it to the edge layer node. The edge layer node is used to perform cross-level clock synchronization on the received initial power waveform based on the reference clock to obtain a synchronized power waveform, and the master station layer node is used to perform synchronization analysis on the synchronized power waveform according to the set time synchronization accuracy based on the reference clock to obtain a synchronized monitoring result of the power waveform.

[0045] Optional, multi-channel simultaneous sampling module includes:

[0046] A clock locking unit is used to obtain a reference clock provided by a GPS / PTP clock source, and to lock a local clock with the reference clock using a DPLL digital phase-locked loop to obtain a clock signal;

[0047] A clock synchronization unit, configured to adjust the clock signal using a calibration clock distributor to obtain a unified time reference;

[0048] The multi-channel sampling unit is used to perform multi-channel synchronous sampling under the unified time reference to obtain multiple sampling results.

[0049] Optionally, the error feedback module includes:

[0050] a cross-correlation calculation unit, configured to calculate the correlation between the plurality of sampling results using a cross-correlator;

[0051] The error feedback unit is used to analyze the phase deviation between different channels based on the correlation between the multiple sampling results using the phase error detection unit to obtain multiple error feedback sampling results.

[0052] Optionally, the power waveform generation module includes:

[0053] A coefficient reading unit, configured to read filter coefficients corresponding to the plurality of error feedback sampling results from a coefficient memory;

[0054] an error transmission unit, configured to transmit the plurality of error feedback sampling results to the MAC operation unit array in a set order by using a shift register chain;

[0055] The filtering compensation unit is used to perform filtering based on the filter coefficient using the MAC operation unit array to obtain a corrected filtering result; and perform delay compensation on the corrected filtering result to obtain an initial power waveform.

[0056] Optionally, the filter compensation unit is specifically used to:

[0057] Perform error calculation based on the multiple sampling results to obtain an error calculation result;

[0058] If the error calculation result is greater than the preset error threshold, the delay line is adjusted to perform delay compensation on the correction filtering result until the error calculation result after delay compensation is no greater than the preset error threshold, and the correction filtering result after delay compensation at this time is used as the initial power waveform.

[0059] Optionally, the filter compensation unit is specifically used to:

[0060] The initial delay value is adjusted by the delay amount based on the proportional integral algorithm to generate a new delay value, and the new delay value is updated to the delay register to realize dynamic calibration of the delay line.

[0061] Optionally, the edge layer nodes are configured in the substation and interconnected with the master layer nodes via a 5G network, and the terminal layer nodes in the substation are interconnected with the edge layer nodes via optical fibers or network cables; and / or

[0062] The edge layer nodes are configured in the distribution station area and are interconnected with the master station layer nodes through optical fibers. The terminal layer nodes in the distribution station area are interconnected with the edge layer nodes through power line carriers PLC and optical fibers.

[0063] Optionally, the initial power waveform incorporates energy flow and information flow, and the information flow is a multi-dimensional time-frequency domain characteristic quantity of the energy flow that reflects the operating status of the system.

[0064] On the other hand, the present invention also provides an electronic device, comprising: at least one processor and a memory; the memory and the processor are connected via a bus;

[0065] The memory is used to store one or more programs;

[0066] When the one or more programs are executed by the at least one processor, the above-mentioned wide-area power waveform synchronous monitoring method is implemented.

[0067] On the other hand, the present invention also provides a readable storage medium having an execution program stored thereon, which, when executed, implements the above-mentioned wide-area power waveform synchronous monitoring method.

[0068] Compared with the prior art, the present invention has the following beneficial effects:

[0069] The present invention provides a wide-area power waveform synchronization monitoring system and synchronization monitoring method. In this synchronization monitoring system, each terminal layer node is used to perform multi-channel synchronous sampling based on a reference clock to obtain multiple sampling results; the multiple sampling results are cross-calibrated and phase error detected to obtain multiple error feedback sampling results; the multiple error feedback sampling results are corrected, filtered, and delayed compensated to obtain an initial power waveform and upload it to the edge layer node; the edge layer node is used to perform cross-level clock synchronization on the received initial power waveform based on the reference clock to obtain a synchronized power waveform and upload it to the master layer node; the master layer node is used to perform synchronization analysis on the synchronized power waveform according to a set time synchronization accuracy based on the reference clock to obtain a synchronized monitoring result of the power waveform. First, the terminal layer node uses multi-channel synchronous sampling technology combined with cross-calibration, phase error detection, and correction filtering to ensure that data from different signal sources can be collected simultaneously and eliminate delays caused by hardware differences and different transmission paths. This ensures that the data synchronization accuracy and accuracy of the data uploaded to the edge layer node are high. Then, the edge layer node maintains a high level of time synchronization accuracy by executing a cross-level clock synchronization mechanism. Finally, synchronization analysis is performed by the master layer node to ensure the reliability of the monitoring results. It can be seen that in the present invention, the terminal layer nodes, edge layer nodes and master station layer nodes perform corresponding synchronization monitoring tasks at different levels, which can improve the synchronization accuracy and reduce the synchronization error, thereby meeting the stringent requirements of emerging fields such as power distribution system operation regulation and massive source and load regulation for high-precision time synchronization at the hundred-nanosecond level, and improving the reliability of wide-area power waveform synchronization monitoring results. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] Figure 1 Schematic diagram of the architecture of the wide-area power waveform synchronous monitoring system of the present invention;

[0071] Figure 2 Schematic diagram of the architecture of the wide-area power waveform synchronous monitoring system of the present invention;

[0072] Figure 3 This is a schematic structural diagram of a clock module of the present invention;

[0073] Figure 4 Schematic diagram of the ADC calibration module structure of the present invention;

[0074] Figure 5 Schematic diagram of the correction filter structure of the present invention;

[0075] Figure 6 This is a schematic diagram of the delay compensation module structure of the present invention;

[0076] Figure 7 This is a schematic diagram of the synchronous sampling process of the present invention;

[0077] Figure 8 Schematic diagram of the flow of the method for synchronous monitoring of wide-area power disturbance fluctuations of the present invention;

[0078] Figure 9 This is a schematic structural diagram of the wide-area power disturbance fluctuation synchronous monitoring system of the present invention;

[0079] Figure 10 Schematic diagram of the structure of the electronic device of the present invention. DETAILED DESCRIPTION

[0080] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0081] Example 1:

[0082] The present invention provides a wide-area power waveform synchronous monitoring system, such as Figure 1 As shown, the synchronous monitoring system includes a master layer node, an edge layer node and a plurality of terminal layer nodes that are communicatively connected to each other.

[0083] An embodiment of the present invention provides a layered system architecture, including a master station layer, an edge layer, and a terminal layer. The master station layer is configured with master station layer nodes, and can also integrate one or more control platforms in a dispatching automation system, a distribution automation system, or a power quality monitoring system. The master station layer nodes can be deployed in the form of a master station server. The master station layer can rely on a dispatching automation system, a distribution automation system, or a power quality monitoring system. The edge layer is configured with edge layer nodes, and the terminal layer is configured with terminal layer nodes. The edge layer can be configured in a substation and / or a distribution substation area, and is responsible for node coordination and data feature analysis in the area under its jurisdiction. The edge layer nodes can include edge computing gateways and / or intelligent fusion terminals. The terminal layer is configured in the substation bus / user outlet and distribution substation area. The terminal layer nodes can include bus monitoring terminals, feeder monitoring terminals, user outlet terminals, distributed power supply terminals, etc.

[0084] In one possible scenario, when the edge layer and terminal layer are configured in a substation, the edge layer nodes are interconnected with the main station layer nodes via a 5G network, and the terminal layer nodes in the substation are interconnected with the edge layer nodes via optical fiber and network cables. When the edge layer and terminal layer are configured in a distribution substation, the edge layer nodes are interconnected with the main station layer nodes via optical fiber, and the terminal layer nodes in the distribution substation are interconnected with the edge layer nodes via PLC (Power Line Carrier) / HPLC (High-speed Power Line Carrier) and optical fiber. Through the hierarchical system architecture provided by the embodiment of the present invention, the terminal layer nodes can include multiple types of terminals and adopt multiple communication methods to realize multi-scenario monitoring node clock synchronization technology.

[0085] A specific system architecture such as Figure 2 As shown, at the master station layer, the master station server is interconnected with the dispatching automation system via the IEC (International Electro Technical Commission) 61970 protocol, with the distribution automation system via IEC 61850, and with the power quality monitoring platform via PQDIF (Power Quality Data Interchange Format). The master station server is interconnected with the edge computing gateway deployed in the substation via a fiber-optic private network. The edge computing gateway is interconnected with the busbar monitoring terminal via fiber and with the feeder monitoring terminal via network cables. The master station server is interconnected with the intelligent fusion node deployed in the distribution area via 5G SA. The intelligent fusion node is interconnected with the user outgoing line terminal via PLC / HPLC and with the distributed power supply terminal via fiber. The intelligent fusion node is also interconnected with the edge computing gateway via IEEE 1588v2. In this system architecture, the substation and distribution area adopt a hybrid fiber / 5G heterogeneous networking method, and a cross-layer clock synchronization path is provided between edge devices (see Figure 2 (dashed line in ).

[0086] In an embodiment of the present invention, each terminal layer node is configured to perform multi-channel synchronous sampling based on a reference clock to obtain multiple sampling results; perform cross-calibration and phase error detection on the multiple sampling results to obtain multiple error feedback sampling results; perform correction filtering and delay compensation on the multiple error feedback sampling results to obtain an initial power waveform and upload it to the edge layer node;

[0087] The edge layer node is used to synchronize the received initial power waveform across different layers based on the reference clock, and obtain the synchronized power waveform and upload it to the master layer node;

[0088] The master station layer node is used to perform synchronous analysis on the synchronous power waveform based on the reference clock and in accordance with the set time synchronization accuracy to obtain the synchronous monitoring result of the power waveform.

[0089] In an embodiment of the present invention, first, the terminal layer node adopts multi-channel synchronous sampling technology combined with cross-calibration, phase error detection and correction filtering to ensure that data from different signal sources can be collected at the same time, and to eliminate delays caused by hardware differences and different transmission paths, so that the data synchronization accuracy uploaded to the edge layer node is high and the accuracy is also high. Then, the edge layer node can maintain the time synchronization accuracy at a high level by executing a cross-level clock synchronization mechanism, and finally perform synchronization analysis through the master station layer node to ensure the reliability of the monitoring results. It can be seen that in the present invention, the terminal layer nodes, edge layer nodes and master station layer nodes perform different synchronization monitoring tasks at different levels, which can improve synchronization accuracy and reduce synchronization errors, thereby meeting the stringent requirements for high-precision time synchronization at the hundred-nanosecond level in emerging fields such as power distribution system operation regulation and massive source and load regulation, and improving the reliability of wide-area power waveform synchronization monitoring results.

[0090] The terminal layer nodes are equipped with clock synchronization modules, such as Figure 3 As shown in the figure, the clock synchronization module integrates a GPS / PTP clock source, a DPLL (Digital Phase-Locked Loop), and a calibration clock distributor. When performing multi-channel synchronous sampling based on a reference clock and obtaining multiple sampling results, the terminal layer node obtains the reference clock provided by the GPS / PTP clock source and uses the DPLL digital phase-locked loop to lock the local clock to the reference clock to obtain a clock signal. The calibration clock distributor then adjusts the clock signal to obtain a unified time reference. Multi-channel synchronous sampling is then performed under this unified time reference to obtain multiple sampling results.

[0091] A GPS / PTP clock source provides a highly accurate time reference. For example, the reference clock provided by the GPS / PTP clock source can be used by master-layer nodes for time synchronization. The DPLL digital phase-locked loop (DPLL) ensures the stability and accuracy of the local clocks of end-layer nodes by locking them to the reference clock provided by the GPS / PTP clock source. The calibrated clock distributor synchronizes the precise clock signal adjusted by the DPLL, ensuring that end-layer nodes can simultaneously sample multiple data channels using a unified time reference and generate multiple sampling results.

[0092] The terminal layer node also deploys an ADC (analog to digital converter) calibration module, such as Figure 4As shown in the figure, the ADC calibration module integrates a cross-correlator and a phase error detection unit. When the terminal layer node performs cross-calibration and phase error detection on multiple sampling results to obtain multiple error feedback sampling results, it can use the cross-correlator to calculate the correlation between the multiple sampling results. Based on this correlation, the phase error detection unit can analyze the phase deviation between different channels to obtain multiple error feedback sampling results.

[0093] In a possible implementation, Figure 4 For example, the terminal layer node samples and performs analog-to-digital conversion on the voltage signal through the voltage channel ADC, and samples and performs analog-to-digital conversion on the current signal through the current channel ADC, to obtain the original data input to the cross-correlator, that is, multiple sampling results. Since the sampling is performed under the precise time reference provided by the clock synchronization module, the synchronization of multi-channel sampling is ensured. By processing the two sets of original data using a cross-correlator and calculating the temporal correlation between the two sets of original data, possible phase differences or other errors can be identified. The phase error detection unit can then be used to further analyze the phase error between the quantized voltage signal and the current signal, accurately determine the phase deviation between data from different channels, and determine the error feedback sampling result based on the phase deviation, thereby ensuring the accuracy and reliability of the voltage and current waveforms based on error feedback.

[0094] The terminal layer nodes are also equipped with correction filters and clock delay compensation modules. The error feedback results are used as error inputs to the correction filters and clock delay compensation modules for processing, which can effectively eliminate various errors introduced during the sampling process and ensure the high quality and reliability of the power waveform. Figure 5 As shown, the correction filter integrates a coefficient memory, a shift register chain, and a MAC (Multiply-Accumulate) operation unit array. When the terminal layer node performs correction filtering and delay compensation on multiple error feedback sampling results to obtain the initial power waveform and upload it to the edge layer node, it can read the filter coefficients corresponding to the multiple error feedback sampling results from the coefficient memory. Using the shift register chain, the multiple error feedback sampling results are passed to the MAC operation unit array in a set order. Based on the filter coefficients, the MAC operation unit array performs filtering to obtain the correction filtering result. Delay compensation is performed on the correction filtering result to obtain the initial power waveform.

[0095] The correction filter can employ a symmetric FIR (Finite Impulse Response) structure, such as a 17th-order linear phase FIR filter. The coefficient memory stores the filter coefficients used for the correction filter. These coefficients are pre-calculated and stored based on a specific filtering algorithm and determine the filter's characteristics, such as frequency response and phase response. For example, the filter coefficients can be dynamically updated using an LSM (Log-Structured Merge) algorithm. When the correction filter receives an error input, it reads the corresponding filter coefficients from the coefficient memory to prepare for subsequent filtering operations. The shift register chain, a digital circuit structure used for temporary data storage and transmission, is responsible for passing the error input data to the MAC operation unit array in a specific order. The shift register chain also implements data delay, enabling filter timing control and ensuring that data is processed at the correct time. Each MAC unit in the MAC operation unit array is responsible for performing a multiplication-add operation: multiplying a filter coefficient by an error input data and adding the resulting product to the previously calculated result. Through this series of operations, the error input data can be corrected and filtered, and the noise and interference components therein can be eliminated or reduced, ensuring that the final output power waveform is accurate in time and phase.

[0096] A possible implementation is Figure 6 As shown, when the terminal layer node performs delay compensation on the correction filtering result to obtain the initial power waveform, it can perform error calculation based on multiple sampling results to obtain an error calculation result; if the error calculation result is greater than the preset error threshold, the delay line is adjusted to perform delay compensation on the correction filtering result until the error calculation result after delay compensation is no greater than the preset error threshold, and the correction filtering result after delay compensation at this time is used as the initial power waveform.

[0097] When the error calculation result is not greater than the preset error threshold, the delay value of the current delay line may be saved as the current parameter.

[0098] To eliminate inter-channel timing skew and suppress high-frequency phase noise, when adjusting the delay line, the terminal node can adjust the initial delay value using a proportional-integral algorithm to generate a new delay value. This new delay value is then updated to the delay register, enabling dynamic calibration of the delay line. The terminal node uses a programmable delay line to fine-tune the sampling clock phase at sub-nanosecond levels, eliminating timing skew caused by inter-channel transmission path differences. In implementation, the terminal node can configure a programmable delay line structure within an FPGA (Field Programmable Gate Array), supporting clock phase adjustments as small as 10ps.

[0099] By adjusting the delay line, the terminal layer node can solve the problem of asynchronous sampling time caused by differences in data transmission paths after voltage and current absorption, thereby eliminating the time deviation between channels. It also improves the accuracy of harmonic measurement and suppresses high-frequency phase noise by compensating for ADC clock tree jitter, and adapts to dynamic environmental changes by automatically correcting delay fluctuations caused by temperature drift and device aging.

[0100] Figure 7 A block diagram of the principle of a multi-channel high-precision synchronous sampling process for voltage and current based on sampling error feedback is proposed. Terminal nodes use a GPS / PTP clock source to provide a reference clock. A DPLL digital phase-locked loop (DPL) locks the local clock to the reference clock. A calibration clock distributor synchronizes the DPLL-adjusted clock signal. An ADC-driven clock generator then drives the voltage and current channel ADCs to acquire voltage and current signals. The acquired voltage and current signals are synchronized and output as data. A cross-correlator calculates the temporal correlation between the two sets of signals. A phase error detection unit then identifies the phase deviation between the data from different channels to obtain the error feedback sampling results. The error feedback sampling results are then corrected and filtered using an FIR correction filter, and delay compensation is performed using a clock delay compensation module to obtain the initial power waveform. During the real-time sampling process, feedback control can be performed based on the initial power waveform, with the ADC-driven clock generator continuing the synchronous sampling process.

[0101] In one implementation, the initial power waveform output by the terminal node incorporates energy flow and information flow. The information flow is the multidimensional time-frequency domain characteristic of the energy flow that reflects the system's operating status. In some implementations, dual-flow coupling of "energy and information" can be achieved through multidimensional waveform feature extraction and information fusion technology. Multidimensional waveform feature extraction can capture waveform details and establish a mapping relationship with the system's operating status. Analysis after coupling the energy and information flows can then reflect the overall system performance.

[0102] Combined with the above Figure 2In one specific embodiment, when the master layer nodes are deployed as servers, the hardware configuration can be dual hot-standby servers with a time synchronization accuracy of ≤±100ns. When the edge layer is deployed in a substation, the edge layer nodes can be edge computing gateways, whose core functions include transient event detection and communication interfaces include four fiber optic ports. When the edge layer is deployed in a distribution area, the edge layer nodes can be IFUs (Intelligent Fusion Units), whose core functions include harmonic responsibility partitioning and communication interfaces include HPLC + 5G modules. When the terminal layer is deployed in a substation, the terminal layer nodes are substation terminals, including busbar monitoring terminals and feeder monitoring terminals. The sampling rate can be 256kS / s, and the synchronization method can be IRIG-B code + fiber B code. When the terminal layer is deployed in a distribution area, the terminal layer nodes are distribution area terminals, including user outgoing line terminals and distributed power supply terminals. The sampling rate can be 64kS / s, and carrier communication can comply with the Q / GDW11627-2016 standard.

[0103] The time monitoring system proposed in the embodiment of the present application is multi-level, bidirectional feedback, and has fault tolerance, achieving high-precision and high-reliability time alignment from the master station to the terminal.

[0104] First, cross-layer synchronization logic can be implemented:

[0105] 1. Top-down calibration:

[0106] Master layer -> edge layer: The master layer nodes provide nanosecond-level reference clocks through GNSS+atomic clocks, and the edge nodes receive and synchronize to the reference clocks.

[0107] Edge layer -> terminal layer: The edge node further distributes the time signal to the terminal device to achieve μs-level alignment, and the terminal layer hardware is self-maintained.

[0108] 2. Bottom-up feedback:

[0109] Terminal layer feedback: Each terminal reports the health status of its local clock (such as crystal oscillator drift, error statistics, etc.).

[0110] Edge layer response: Dynamically adjust the time synchronization window and calibration strategy based on terminal feedback.

[0111] Master station layer optimization: The master station layer integrates feedback information from the entire network, optimizes timing strategies, and improves overall synchronization performance.

[0112] Secondly, a failover mode is provided:

[0113] 1. Master station failure: When the master station timing source fails, the edge node automatically switches to a local high-stability atomic clock (such as a rubidium clock) to keep time and maintain system operation.

[0114] 2. Communication interruption: If the communication link between the edge layer and the terminal is interrupted, the terminal enters a short-term autonomous mode and relies on its local hardware clock to continue working for a period of time to ensure that the sampling is not offset.

[0115] Finally, different levels of clock mechanisms are provided:

[0116] 1. Terminal layer (μs-level hardware synchronization)

[0117] Clock drive: The hardware timer is driven by a local high-stability crystal oscillator, which directly controls the ADC sampling pulse.

[0118] Time stamping: FPGA is used to implement nanosecond-level time stamping to accurately lock each sampling moment.

[0119] Power-off retention capability: After losing the external clock input, it can still maintain self-synchronization capability with μs level accuracy for several minutes.

[0120] 2. Edge layer (sub-ms collaborative synchronization):

[0121] Clock source: Based on the PTP timing signal sent by the master station (can be transmitted wirelessly or optically).

[0122] Synchronization mechanism: Multi-node data alignment adopts the "sliding time window + confidence interval verification" method; dynamic identification and elimination of abnormal time points to ensure data consistency among multiple nodes.

[0123] 3. Master station layer (ns-level global timing):

[0124] Clock source configuration: Dual redundant atomic clocks (cesium clock + rubidium clock) as the core reference; synchronously combined with GNSS satellite signals to tame the clock, improving long-term stability and reliability.

[0125] Timing architecture: A hierarchical timing system is adopted to support efficient time synchronization management of large-scale systems.

[0126] In one possible implementation, edge-layer nodes synchronize the received initial power waveform across multiple layers using a reference clock. Once the synchronized power waveform is obtained, the reference clock signal provided by the master layer is used as a parameter to adjust its internal clock, resulting in a synchronized local clock. Using this synchronized local clock, edge-layer nodes realign the received initial power waveform with a precise timestamp, eliminating errors caused by differences in acquisition time. A "sliding time window + confidence interval check" technique can also be used to identify and correct data inconsistencies across multiple nodes.

[0127] In one possible implementation, the master-layer nodes perform synchronous analysis of the synchronous power waveform based on the reference clock and in accordance with the set time synchronization accuracy. When obtaining the synchronous monitoring results of the power waveform, the master-layer usually has the highest-level reference clock source and can provide global timing services. Based on this clock, the data of the edge-layer nodes can be fine-tuned to achieve higher time synchronization accuracy requirements. In addition, the master-layer nodes can execute specific synchronization analysis algorithms, such as harmonic analysis and spectrum analysis, based on the preset time synchronization accuracy standards to evaluate the quality of the power waveform and detect abnormalities such as harmonic distortion and frequency offset. Based on the analysis results, the master-layer nodes can also generate detailed power waveform synchronization monitoring reports, including but not limited to key indicators such as voltage and current values, power factor, and harmonic components, providing a scientific basis for grid operation status monitoring and fault diagnosis.

[0128] This layered architecture not only improves the overall synchronization accuracy of the system, but also enhances the ability to cope with local failures. When a problem occurs at one layer, the next layer can temporarily maintain basic functions until the problem is resolved.

[0129] Example 2:

[0130] Based on the same inventive concept, the present invention provides a method for synchronously monitoring wide-area power disturbance fluctuations, the flow chart of which is as follows: Figure 8 Shown, including:

[0131] Step 801: Perform multi-channel synchronous sampling based on a reference clock to obtain multiple sampling results;

[0132] Step 802: performing cross calibration and phase error detection on the multiple sampling results to obtain multiple error feedback sampling results;

[0133] Step 803: Correction filtering and delay compensation are performed on multiple error feedback sampling results to obtain an initial power waveform and upload it to the edge layer node. The edge layer node is used to synchronize the received initial power waveform across levels based on the reference clock to obtain a synchronized power waveform, and the master station layer node is used to synchronize the synchronized power waveform according to the set time synchronization accuracy based on the reference clock to obtain a synchronized monitoring result of the power waveform.

[0134] Optionally, performing multi-channel synchronous sampling based on a reference clock to obtain multiple sampling results includes:

[0135] Obtain the reference clock provided by the GPS / PTP clock source, and use the DPLL digital phase-locked loop to lock the local clock with the reference clock to obtain a clock signal;

[0136] Adjusting the clock signal using a calibration clock distributor to obtain a unified time reference;

[0137] Multi-channel synchronous sampling is performed under the unified time base to obtain multiple sampling results.

[0138] Optionally, performing cross-calibration and phase error detection on the multiple sampling results to obtain multiple error feedback sampling results includes:

[0139] Calculating correlations between the plurality of sampling results using a cross-correlator;

[0140] Based on the correlation between the multiple sampling results, a phase error detection unit is used to analyze the phase deviations between different channels to obtain multiple error feedback sampling results.

[0141] Optionally, performing correction filtering and delay compensation on the multiple error feedback sampling results to obtain an initial power waveform includes:

[0142] Reading filter coefficients corresponding to the plurality of error feedback sampling results in a coefficient memory;

[0143] Using a shift register chain, the plurality of error feedback sampling results are transferred to a MAC operation unit array in a set order;

[0144] Based on the filter coefficient, the MAC operation unit array is used to perform filtering to obtain a corrected filtering result; and delay compensation is performed on the corrected filtering result to obtain an initial power waveform.

[0145] Optionally, performing delay compensation on the correction filtering result to obtain an initial power waveform includes:

[0146] Perform error calculation based on the multiple sampling results to obtain an error calculation result;

[0147] If the error calculation result is greater than the preset error threshold, the delay line is adjusted to perform delay compensation on the correction filtering result until the error calculation result after delay compensation is no greater than the preset error threshold, and the correction filtering result after delay compensation at this time is used as the initial power waveform.

[0148] Optionally, adjusting the delay line includes:

[0149] The initial delay value is adjusted by the delay amount based on the proportional integral algorithm to generate a new delay value, and the new delay value is updated to the delay register to realize dynamic calibration of the delay line.

[0150] Optionally, the edge layer nodes are configured in the substation and interconnected with the master layer nodes via a 5G network, and the terminal layer nodes in the substation are interconnected with the edge layer nodes via optical fibers or network cables; and / or

[0151] The edge layer nodes are configured in the distribution station area and are interconnected with the master station layer nodes through optical fibers. The terminal layer nodes in the distribution station area are interconnected with the edge layer nodes through power line carriers PLC and optical fibers.

[0152] Optionally, the initial power waveform incorporates energy flow and information flow, and the information flow is a multi-dimensional time-frequency domain characteristic quantity of the energy flow that reflects the operating status of the system.

[0153] Example 3:

[0154] Based on the same inventive concept, the present invention also provides a wide-area power disturbance fluctuation synchronous monitoring system, such as Figure 9 Shown, including:

[0155] A multi-channel synchronous sampling module is used to perform multi-channel synchronous sampling based on a reference clock to obtain multiple sampling results;

[0156] An error feedback module is used to perform cross-calibration and phase error detection on multiple sampling results to obtain multiple error feedback sampling results;

[0157] The power waveform generation module is used to perform correction filtering and delay compensation on multiple error feedback sampling results, obtain the initial power waveform and upload it to the edge layer node. The edge layer node is used to synchronize the received initial power waveform across layers based on the reference clock to obtain a synchronized power waveform, and the master station layer node is used to synchronize the synchronized power waveform according to the set time synchronization accuracy based on the reference clock to obtain the synchronized monitoring result of the power waveform.

[0158] Optional, multi-channel simultaneous sampling module includes:

[0159] A clock locking unit is used to obtain a reference clock provided by a GPS / PTP clock source, and to lock a local clock with the reference clock using a DPLL digital phase-locked loop to obtain a clock signal;

[0160] A clock synchronization unit, configured to adjust the clock signal using a calibration clock distributor to obtain a unified time reference;

[0161] The multi-channel sampling unit is used to perform multi-channel synchronous sampling under the unified time reference to obtain multiple sampling results.

[0162] Optionally, the error feedback module includes:

[0163] a cross-correlation calculation unit, configured to calculate the correlation between the plurality of sampling results using a cross-correlator;

[0164] The error feedback unit is used to analyze the phase deviation between different channels based on the correlation between the multiple sampling results using the phase error detection unit to obtain multiple error feedback sampling results.

[0165] Optionally, the power waveform generation module includes:

[0166] A coefficient reading unit, configured to read filter coefficients corresponding to the plurality of error feedback sampling results from a coefficient memory;

[0167] an error transmission unit, configured to transmit the plurality of error feedback sampling results to the MAC operation unit array in a set order by using a shift register chain;

[0168] The filtering compensation unit is used to perform filtering based on the filter coefficient using the MAC operation unit array to obtain a corrected filtering result; and perform delay compensation on the corrected filtering result to obtain an initial power waveform.

[0169] Optionally, the filter compensation unit is specifically used to:

[0170] Perform error calculation based on the multiple sampling results to obtain an error calculation result;

[0171] If the error calculation result is greater than the preset error threshold, the delay line is adjusted to perform delay compensation on the correction filtering result until the error calculation result after delay compensation is no greater than the preset error threshold, and the correction filtering result after delay compensation at this time is used as the initial power waveform.

[0172] Optionally, the filter compensation unit is specifically used to:

[0173] The initial delay value is adjusted by the delay amount based on the proportional integral algorithm to generate a new delay value, and the new delay value is updated to the delay register to realize dynamic calibration of the delay line.

[0174] Optionally, the edge layer nodes are configured in the substation and interconnected with the master layer nodes via a 5G network, and the terminal layer nodes in the substation are interconnected with the edge layer nodes via optical fibers or network cables; and / or

[0175] The edge layer nodes are configured in the distribution station area and are interconnected with the master station layer nodes through optical fibers. The terminal layer nodes in the distribution station area are interconnected with the edge layer nodes through power line carriers PLC and optical fibers.

[0176] Optionally, the initial power waveform incorporates energy flow and information flow, and the information flow is a multi-dimensional time-frequency domain characteristic quantity of the energy flow that reflects the operating status of the system.

[0177] Example 4:

[0178] like Figure 10 As shown, the present invention also provides an electronic device, which may be a computer, a single-chip microcomputer, a smart mobile device, or the like. The electronic device in this embodiment may include a processor, a memory, a transceiver component, and the like. The memory, processor, and transceiver component are connected via a bus; the memory may be used to store an execution program, which may include instructions; and the processor may be used to execute the instructions stored in the memory. The memory may also be used to store data, which may be accessed and / or modified during the execution of the instructions.

[0179] The processor may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. It is the computing core and control core of the terminal, which is suitable for implementing one or more instructions, specifically suitable for loading and executing one or more instructions in the storage medium to implement the corresponding method flow or corresponding function, so as to realize the steps of a wide-area power disturbance fluctuation synchronous monitoring method in the above embodiment.

[0180] Example 5:

[0181] Based on the same inventive concept, the present invention also provides a readable storage medium, specifically an electronic device-readable storage medium (Memory). This electronic device-readable storage medium is a memory device within the electronic device, used to store programs and data. It is understood that the storage medium herein may include both built-in storage media within the electronic device and, of course, extended storage media supported by the electronic device. The storage medium provides storage space, which stores the terminal's operating system. Furthermore, this storage space also stores one or more instructions suitable for being loaded and executed by a processor. These instructions may be one or more executable programs (including program code). It should be noted that the storage medium herein may be high-speed RAM memory or non-volatile memory, such as at least one disk drive. The processor loading and executing one or more instructions stored in the storage medium can implement the steps of the method for synchronously monitoring wide-area power disturbance fluctuations described in the above-mentioned embodiment.

[0182] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Thus, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0183] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0184] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0185] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0186] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit its scope of protection. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the field should understand that after reading the present invention, those skilled in the art may still make various changes, modifications or equivalent substitutions to the specific implementation methods of the invention, but these changes, modifications or equivalent substitutions are all within the scope of protection of the pending claims of the invention.

Claims

1. A wide-area power waveform synchronous monitoring system, characterized in that: It includes a master layer node, an edge layer node and multiple terminal layer nodes that are connected to each other for communication; Each of the terminal layer nodes is configured to perform multi-channel synchronous sampling based on a reference clock to obtain multiple sampling results; performing cross calibration and phase error detection on the multiple sampling results to obtain multiple error feedback sampling results; Performing correction filtering and delay compensation on the multiple error feedback sampling results to obtain an initial power waveform and uploading it to the edge layer node; The edge layer node is configured to perform cross-layer clock synchronization on the received initial power waveform based on the reference clock, obtain a synchronized power waveform and upload it to the master layer node; The master station layer node is used to perform synchronization analysis on the synchronous power waveform based on the reference clock according to the set time synchronization accuracy to obtain a synchronization monitoring result of the power waveform; The terminal layer node is specifically configured to read filter coefficients corresponding to the plurality of error feedback sampling results from a coefficient memory; and transmit the plurality of error feedback sampling results to a multiplier-accumulator (MAC) operation unit array in a set order using a shift register chain; Based on the filter coefficient, the MAC operation unit array is used to perform filtering to obtain a corrected filtering result; and delay compensation is performed on the corrected filtering result to obtain an initial power waveform.

2. The system according to claim 1, wherein The terminal layer node is specifically used to obtain a reference clock provided by a global positioning system GPS / precision time synchronization protocol PTP clock source, and use a digital phase-locked loop DPLL to lock the local clock with the reference clock to obtain a clock signal; The clock signal is adjusted by using a calibration clock distributor to obtain a unified time base; multi-channel synchronous sampling is performed under the unified time base to obtain multiple sampling results.

3. The system according to claim 1, wherein: The terminal layer node is specifically used to calculate the correlation between the multiple sampling results using a cross-correlator; based on the correlation between the multiple sampling results, a phase error detection unit is used to analyze the phase deviation between different channels to obtain multiple error feedback sampling results.

4. The system according to claim 1, wherein: The terminal layer node is specifically used to perform error calculation based on the multiple sampling results to obtain an error calculation result; if the error calculation result is greater than a preset error threshold, the delay line is adjusted to perform delay compensation on the correction filtering result until the error calculation result after delay compensation is no greater than the preset error threshold, and the correction filtering result after delay compensation at this time is used as the initial power waveform.

5. The system according to claim 4, wherein: The terminal layer node is specifically used to adjust the delay amount of the initial delay value based on the proportional integral algorithm to generate a new delay value, and update the new delay value to the delay register to achieve dynamic calibration of the delay line.

6. The system according to claim 1, wherein: The edge layer nodes are configured in the substation and interconnected with the master layer nodes via a 5G network, and the terminal layer nodes in the substation are interconnected with the edge layer nodes via optical fibers and network cables; and / or The edge layer nodes are configured in the distribution station area and are interconnected with the master station layer nodes through optical fibers. The terminal layer nodes in the distribution station area are interconnected with the edge layer nodes through power line carriers PLC and optical fibers.

7. The system according to claim 1, wherein: The initial power waveform integrates energy flow and information flow, and the information flow is a multi-dimensional time-frequency domain characteristic quantity of the energy flow that reflects the operating status of the system.

8. A method for synchronous monitoring of wide-area power waveforms, characterized in that: include: Perform multi-channel synchronous sampling based on the reference clock to obtain multiple sampling results; performing cross calibration and phase error detection on the multiple sampling results to obtain multiple error feedback sampling results; Performing correction filtering and delay compensation on the multiple error feedback sampling results to obtain an initial power waveform and uploading it to the edge layer node, so that the edge layer node performs cross-level clock synchronization on the received initial power waveform based on the reference clock to obtain a synchronized power waveform, and the master layer node performs synchronization analysis on the synchronized power waveform based on the reference clock according to a set time synchronization accuracy to obtain a synchronized monitoring result of the power waveform; The performing correction filtering and delay compensation on the plurality of error feedback sampling results to obtain an initial power waveform includes: Reading filter coefficients corresponding to the plurality of error feedback sampling results in a coefficient memory; Using a shift register chain, the plurality of error feedback sampling results are transferred to a multiplier-accumulator (MAC) operation unit array in a set order; Based on the filter coefficient, the MAC operation unit array is used to perform filtering to obtain a corrected filtering result; and delay compensation is performed on the corrected filtering result to obtain an initial power waveform.

9. The method according to claim 8, wherein The performing multi-channel synchronous sampling based on the reference clock to obtain multiple sampling results includes: Obtain a reference clock provided by a Global Positioning System (GPS) / Precision Time Protocol (PTP) clock source, and use a digital phase-locked loop (DPLL) to lock the local clock to the reference clock to obtain a clock signal. Adjusting the clock signal using a calibration clock distributor to obtain a unified time reference; Multi-channel synchronous sampling is performed under the unified time base to obtain multiple sampling results.

10. The method according to claim 8, wherein The performing cross-calibration and phase error detection on the multiple sampling results to obtain multiple error feedback sampling results includes: Calculating correlations between the plurality of sampling results using a cross-correlator; Based on the correlation between the multiple sampling results, a phase error detection unit is used to analyze the phase deviations between different channels to obtain multiple error feedback sampling results.

11. The method according to claim 8, wherein The delay compensation of the correction filtering result to obtain the initial power waveform includes: Perform error calculation based on the multiple sampling results to obtain an error calculation result; If the error calculation result is greater than the preset error threshold, the delay line is adjusted to perform delay compensation on the correction filtering result until the error calculation result after delay compensation is no greater than the preset error threshold, and the correction filtering result after delay compensation at this time is used as the initial power waveform.

12. The method according to claim 11, wherein The adjusting the delay line comprises: The initial delay value is adjusted by the delay amount based on the proportional integral algorithm to generate a new delay value, and the new delay value is updated to the delay register to realize dynamic calibration of the delay line.

13. The method according to claim 8, wherein The edge layer nodes are configured in the substation and interconnected with the master layer nodes via a 5G network, and the terminal layer nodes in the substation are interconnected with the edge layer nodes via optical fibers and network cables; and / or The edge layer nodes are configured in the distribution station area and are interconnected with the master station layer nodes through optical fibers. The terminal layer nodes in the distribution station area are interconnected with the edge layer nodes through power line carriers PLC and optical fibers.

14. The method according to claim 8, wherein The initial power waveform integrates energy flow and information flow, and the information flow is a multi-dimensional time-frequency domain characteristic quantity of the energy flow that reflects the operating status of the system.

15. A wide-area power waveform synchronous monitoring system, characterized in that include: A multi-channel synchronous sampling module is used to perform multi-channel synchronous sampling based on a reference clock to obtain multiple sampling results; an error feedback module, configured to perform cross-calibration and phase error detection on the plurality of sampling results to obtain a plurality of error feedback sampling results; a power waveform generation module, configured to perform correction filtering and delay compensation on the multiple error feedback sampling results to obtain an initial power waveform and upload it to the edge layer node; the edge layer node is configured to perform cross-layer clock synchronization on the received initial power waveform based on the reference clock to obtain a synchronized power waveform; and the master layer node is configured to perform synchronization analysis on the synchronized power waveform based on the reference clock according to a set time synchronization accuracy to obtain a synchronized monitoring result of the power waveform; The power waveform generation module includes: A coefficient reading unit, configured to read filter coefficients corresponding to the plurality of error feedback sampling results from a coefficient memory; an error transfer unit, configured to transfer the plurality of error feedback sampling results to a multiplier-accumulator (MAC) operation unit array in a set order using a shift register chain; The filtering compensation unit is used to perform filtering based on the filter coefficient using the MAC operation unit array to obtain a corrected filtering result; and perform delay compensation on the corrected filtering result to obtain an initial power waveform.

16. The system according to claim 15, wherein: The multi-channel synchronous sampling module includes: A clock locking unit is used to obtain a reference clock provided by a GPS / PTP clock source, and to lock a local clock with the reference clock using a DPLL digital phase-locked loop to obtain a clock signal; A clock synchronization unit, configured to adjust the clock signal using a calibration clock distributor to obtain a unified time reference; The multi-channel sampling unit is used to perform multi-channel synchronous sampling under the unified time reference to obtain multiple sampling results.

17. The system according to claim 15, wherein: The error feedback module includes: a cross-correlation calculation unit, configured to calculate the correlation between the plurality of sampling results using a cross-correlator; The error feedback unit is used to analyze the phase deviation between different channels based on the correlation between the multiple sampling results using the phase error detection unit to obtain multiple error feedback sampling results.

18. The system of claim 15, wherein: The filtering compensation unit is specifically used to: Perform error calculation based on the multiple sampling results to obtain an error calculation result; If the error calculation result is greater than the preset error threshold, the delay line is adjusted to perform delay compensation on the correction filtering result until the error calculation result after delay compensation is no greater than the preset error threshold, and the correction filtering result after delay compensation at this time is used as the initial power waveform.

19. The system of claim 18, wherein: The filtering compensation unit is specifically used to: The initial delay value is adjusted by the delay amount based on the proportional integral algorithm to generate a new delay value, and the new delay value is updated to the delay register to realize dynamic calibration of the delay line.

20. The system of claim 15, wherein: The edge layer nodes are configured in the substation and interconnected with the master layer nodes via a 5G network, and the terminal layer nodes in the substation are interconnected with the edge layer nodes via optical fibers and network cables; and / or The edge layer nodes are configured in the distribution station area and are interconnected with the master station layer nodes through optical fibers. The terminal layer nodes in the distribution station area are interconnected with the edge layer nodes through power line carriers PLC and optical fibers.

21. The system of claim 15, wherein: The initial power waveform integrates energy flow and information flow, and the information flow is a multi-dimensional time-frequency domain characteristic quantity of the energy flow that reflects the operating status of the system.

22. An electronic device, characterized in that: include: at least one processor and memory; The memory and the processor are connected via a bus; The memory is used to store one or more programs; When the one or more programs are executed by the at least one processor, the wide-area power waveform synchronous monitoring method according to any one of claims 8 to 14 is implemented.

23. A readable storage medium, characterized in that An execution program is stored thereon, and when the execution program is executed, the wide-area power waveform synchronous monitoring method according to any one of claims 8 to 14 is implemented.

Images