Implementation Method of a Chaotic Signal Generator Based on FPGA Technology with Hybrid Fitting

Abstract

A hybrid fitting FPGA chaotic signal generator implementation method can efficiently generate memristive chaotic systems with complex nonlinear characteristics such as hyperbolic functions and natural logarithms on resource-constrained FPGAs. This approach analyzes the slope distribution of the target function, employs binomial fitting for steep slope intervals, and optimizes the hardware architecture to reduce resource usage. For smoother slope intervals, linear fitting simplifies the implementation logic. A memristive chaotic system model constructed based on this hybrid strategy has an on-chip iterative computation module integrated. Experimental verification demonstrates that this method significantly reduces storage resource consumption while maintaining high accuracy, making it particularly suitable for chaotic signal generation scenarios requiring low power consumption and high real-time performance.

Description

Technical Field

[0001] The invention belongs to the field of nonlinear dynamics, and in particular relates to a method for realizing a chaotic signal generator using FPGA technology of hybrid fitting. Background Art

[0002] FPGAs (Field Programmable Gate Arrays), currently a key tool for hardware-based information encryption, have been widely researched and applied both domestically and internationally. Many international research institutions and scholars have used FPGAs to model, simulate, and implement encryption algorithms for memristive chaotic systems. By combining chaotic systems with traditional encryption algorithms, they have improved the security and efficiency of information encryption. FPGA applications in chaotic encryption include key generation based on chaotic maps, chaotic sequence generation, and chaotic scrambling. Meanwhile, many domestic research institutions and scholars are also studying chaotic systems and implementing information encryption on FPGAs. Specifically, they are designing and implementing nonlinear chaotic digital circuits, developing hardware implementation platforms for chaotic systems, and further studying chaotic encryption algorithms and chaotic sequence generators. Furthermore, some researchers have combined memristive chaotic systems with other encryption algorithms, such as AES and DES, to enhance the effectiveness and security of information encryption. These systems exhibit not only rich dynamic characteristics but also excellent stability and high repeatability.

[0003] As research on memristive chaotic systems deepens, the key challenge facing researchers is how to implement their mathematical models with high precision using existing electronic circuit technology. While analog circuits can implement memristive chaotic systems, they suffer from inherent drawbacks such as long development cycles and poor reproducibility, often due to transistor mismatch and process variations. Digital platforms such as ASICs, FPGAs, and single-chip microcontrollers can effectively circumvent component matching issues. FPGAs, with their parallel computing capabilities, hardware reconfigurability, and real-time performance, are a particularly attractive option.

[0004] However, existing FPGA-based implementations of memristive chaotic systems suffer from insufficient computational precision for nonlinear functions (such as tanh, cosh, and ln), leading to significant deviations between hardware implementation results and simulation models. This is especially true when the system contains multiple nonlinear functions and runs for extended periods of time, as accumulated errors can cause iterative value divergence. To address this issue, existing FPGA technology suffers from insufficient computational precision when implementing memristive chaotic systems containing multiple nonlinear functions (such as tanhx, coshx, and lnx). This paper proposes an FPGA-based memristive chaotic circuit implementation method with lower resource usage, improved real-time performance, and higher computational precision.

[0005] Technical comparison with the published application CN119272828B "Implementation method of fractional-order memristor Hopfield neural network circuit based on FPGA";

[0006] The application CN119272828B adopts the GL fractional-order derivative definition and the short-term memory principle, and completes the FPGA circuit implementation of the fractional-order memristor Hopfield model only through multi-segment linear fitting of the hyperbolic tangent function.

[0007] This application analyzes the slope characteristics of the hyperbolic tangent function, hyperbolic cotangent function, and natural logarithm, and combines FPGA resources and precision requirements. It chooses to use binomial curve fitting in the range with larger slopes and optimize the hardware architecture to reduce resource consumption. In the range with smaller slopes, straight line fitting is used to simplify the implementation of the objective function.

[0008] The application CN119272828B uses a 64-bit RAM IP core to store the slope and intercept coefficients of a linear function, and implements a nonlinear function through fitting through a multiplier and an adder. However, when applied to the natural logarithmic function ln(x), since the straight line cannot fit the function value at ln(0+) well, the closer x approaches 0+, the greater the error will be. In order to compensate for this error, a large number of segmented intervals need to be added.

[0009] This application uses a 96-bit RAM IP core to store the three coefficients of the quadratic function, and uses three multipliers and two adders to fit the nonlinear function. Using the slope as the dividing point between straight-line and curve fitting, curve fitting near ln(0+) can better approximate the curve characteristics of ln(x), reducing the number of segments and fitting errors.

[0010] The application CN119272828B does not adopt Euler iteration for design, the overall module structure is different from that of the present application, and the iteration process is more complicated than that of the present application, requiring more iteration time.

[0011] There are essential differences between the two in terms of their technical implementation solutions.

[0012] The application CN119272828B adopts the GL fractional-order derivative definition and the short-term memory principle to be applicable to the design of fractional-order memristor neural networks, but is not applicable to conventional integer-order memristor chaotic systems.

[0013] This application does not belong to a fractional-order neural network circuit, but to an implementation method of a memristor chaotic circuit.

[0014] There are essential differences between the two in their application scenarios.

[0015] Technical comparison with the published application CN116720554B "A method for realizing a neuron circuit with multi-segment linear fitting based on FPGA technology";

[0016] The application CN116720554B is an improved Fitzhugh-Nagumo neuron model. The mathematical model structure is a two-dimensional differential equation with an external excitation source containing a hyperbolic tangent function and a sine function, and the iteration adopts a second-order Runge-Kutta iteration.

[0017] This application belongs to a memristor chaotic circuit model. In terms of mathematical model structure, it is a three-dimensional differential equation containing hyperbolic tangent function, hyperbolic cotangent function, and natural logarithm. It adopts the Euler iteration method, and the iterative steps are less than the second-order Runge-Kutta iteration.

[0018] Application CN116720554B employs a hardware function fitting method using a 64-bit RAM IP core to design a hyperbolic tangent function. This method stores the slope and intercept coefficients of a linear function and utilizes multipliers and adders to implement piecewise linear fitting of nonlinear functions. However, when applied to the natural logarithm function ln(x), this method exhibits significant limitations near the boundary of the function's domain (x→0+). Because a straight-line fit cannot accurately approximate the asymptotic behavior of ln(x) in this interval, the fitting error exhibits a monotonically increasing trend as x approaches 0+. To meet accuracy requirements, the number of segmented intervals must be significantly increased. Furthermore, patent CN116720554B also implements a piecewise method (non-piecewise linear fitting) for the sine function. This method uses predefined intervals to determine the address of the sine function and performs circular addressing, thereby implementing the sine function.

[0019] This application implements the hyperbolic tangent function, hyperbolic cotangent function, and natural logarithm, all using a 96-bit RAM IP core to store the three coefficients of the quadratic function, and uses three multipliers and two adders for fitting. Using the slope as the dividing point between straight-line and curve fitting, curve fitting near ln(0+) can better approximate the curve characteristics of ln(x), reducing the number of segments and fitting errors.

[0020] There are essential differences between the two in terms of their technical implementation solutions. Summary of the Invention

[0021] To address the above technical problems, the present invention proposes a hybrid fitting FPGA technology chaotic signal generator implementation method to construct a memristor chaotic system with high precision and low resource utilization. Combining FPGA resource and accuracy requirements, the slope of the target nonlinear function is analyzed, and the slope threshold is determined through engineering practice. When the slope of a certain interval of the function is greater than the threshold, binomial curve fitting is used, and the hardware architecture is optimized in the FPGA to reduce resources. When the slope is less than the threshold, straight line fitting is used to simplify the fitting function and implement it using simple logic units. The fitting results are used to construct a memristor chaotic system model, and a memristor chaotic system iteration module is integrated into the FPGA. This allows a memristor chaotic system containing multiple nonlinear functions to be implemented with high precision and low resource utilization.

[0022] To achieve the above object, the technical solution adopted by the present invention is:

[0023] The implementation method of the FPGA technology chaotic signal generator based on hybrid fitting is as follows:

[0024] 1) Analyze the slope of the target nonlinear function based on FPGA resource constraints and accuracy requirements, and determine the slope threshold through engineering experiments;

[0025] 2) Divide the function into intervals based on the slope threshold;

[0026] When the slope of a function interval is greater than a threshold, the binomial curve fitting method is used to design the function fitting module for that interval, and targeted optimization is performed in the FPGA hardware architecture to reduce resource consumption.

[0027] When the slope is less than the threshold, the interval function is simplified using the straight line fitting method, and the fitting function is realized through the simple logic unit in the FPGA;

[0028] 3) Select the fitting module results of each interval to construct a mathematical model of the memristor chaotic system, and integrate the iterative calculation module of the memristor chaotic system on the FPGA;

[0029] 4) Based on the given iterative formula, use the Verilog hardware description language on the Xilinx ISE development platform to build a state machine control module to implement the iterative formula's loop execution. Then, use MATLAB to convert the resulting IEEE754 floating-point format and plot a chart, comparing and analyzing the results with those generated by Visual Studio C++ compilation.

[0030] 5) Finally, the bit file generated after compilation and synthesis is downloaded to the FPGA via the JTAG interface, and the actual output signal is observed with the help of an oscilloscope.

[0031] As a further improvement of the present invention, the binomial curve fitting method in step 2) is used to design a function fitting module function processing for this interval, and the specific processing is as follows:

[0032] 21. Derivative the hyperbolic tangent, hyperbolic cotangent, and natural logarithm functions respectively. First, find the derivatives of these three functions, and then plot the slope graph in the corresponding fitting interval based on the derivative results.

[0033] 22. According to actual engineering requirements, the slope-dominated division intervals for straight-line and curve fitting are determined. When the slope is greater than the set threshold, a quadratic curve is used for fitting. When the slope is less than the set threshold, a straight line is used for fitting. When fitting a straight line or a curve, the least squares method is used in Visual Studio C++ to determine the fitting coefficients of the straight line and curve.

[0034] 23. For a single nonlinear function, there are three coefficients for curve fitting, which need to be encoded into 96-bit data, consisting of three 32-bit IEEE754 floating-point numbers. The upper 32 bits are the quadratic coefficient, the middle 32 bits are the linear coefficient, and the lower 32 bits are the constant. There are two coefficients for linear fitting, which need to be encoded into 64-bit data, consisting of two 32-bit IEEE754 floating-point numbers. The upper 32 bits are the linear coefficient and the lower 32 bits are the constant. This is used to generate COE files and create RAM IP cores in Xilinx.

[0035] 24. When searching for the storage address of the fitting coefficients in the fitting function RAM IP core through independent variables, the search needs to be combined with the partitioning interval.

[0036] As a further improvement of the present invention, the binomial curve fitting method is used to design the function fitting module of this interval. The least squares method is used to determine the fitting coefficients of the straight line and the curve during the function processing process as follows:

[0037] Assume that the data to be fitted is , and these data are passed through To express, is the fitted value, is the independent variable, is a constant, and the fitted value for each data point is , the actual value is , the residual is , No. The input variables for each data point are , is a positive integer, expressed as ;

[0038] The goal of the least squares method is to minimize the sum of squared residuals for all data points:

[0039] ;

[0040] Solve the objective function by the above formula The minimum value of is used to get the estimated value of the parameter. In simple linear regression, the fitting function is assumed to be When , the objective function is:

[0041] ;

[0042] A further fitting function assumption is When , the objective function is:

[0043] ;

[0044] Through 、 and Find the partial derivative and set it equal to zero to get the normal equation, and then solve the constant 、 and The estimated value of , in the above formula, is the intercept, is the linear slope, is the curvature of the curve, is the number of data points.

[0045] As a further improvement of the present invention, in step 3), the memristor chaos model selected in the mathematical model of the memristor chaos system is:

[0046] ;

[0047] ;

[0048] ;

[0049] In the above formula is the voltage value of the resistor device in the memristor circuit, is the voltage value of the memristor device in the memristor circuit, is the voltage value of the capacitor device in the memristor circuit, is a positive system parameter, For time.

[0050] As a further improvement of the present invention, in step 3), an iterative calculation module of the system is integrated on the FPGA, wherein the iterative calculation is specifically as follows;

[0051] The differential equation of the memristor chaotic system uses the Euler iteration formula, and the iterative formula of the memristor chaotic system is obtained as follows:

[0052] ;

[0053] In the above formula is the voltage value at a moment under the resistor in the memristor circuit, is the voltage value of the memristor device in the memristor circuit at the next moment, is the voltage value of the capacitor device in the memristor circuit at the next moment, is the voltage value of the resistor device in the memristor circuit at the current moment, is the voltage value of the memristor device in the memristor circuit at the current moment, is the voltage value of the capacitor device in the memristor circuit at the current moment, is a positive system parameter, is the iteration step size of the system.

[0054] The advantages of the present invention are:

[0055] The hybrid straight line and curve fitting strategy used in the present invention can quickly and accurately match the target nonlinear function. Tests were carried out on the Spartan-6 series FPGA development board, and its data processing delay was significantly reduced compared to traditional solutions. This method first combines FPGA resources and accuracy requirements, analyzes the slope of the nonlinear function and determines a reasonable threshold. When the slope of the function interval exceeds the threshold, binomial curve fitting is used, and when it is below the threshold, straight line fitting is used to achieve efficient simplification of the nonlinear function of the memristor chaotic system in the FPGA. This greatly reduces the resource usage of the iterative solution module of the memristor chaotic system, while improving the calculation accuracy and operating efficiency of the system. This method not only has good fitting effects on common nonlinear functions, but also has good adaptability to complex transcendental functions. It has important application potential and research significance in the fields of chaotic signal generation, secure communication encryption, and memristor neural network construction. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 This is a schematic diagram of least squares fitting;

[0057] Figure 2 It is the hyperbolic tangent function approximation module;

[0058] Figure 3 This is the overall module diagram of the Verilog algorithm;

[0059] Figure 4 This is the schematic diagram of the Euler iteration module;

[0060] Figure 5 This is the overall connection schematic diagram;

[0061] Figure 6 The chaotic phase diagram of zy captured by an oscilloscope with k=2.07. DETAILED DESCRIPTION

[0062] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0063] This paper proposes a hybrid fitting method for implementing a chaotic signal generator on an FPGA, focusing on addressing the accuracy and resource consumption challenges of complex nonlinear functions such as the hyperbolic tangent, hyperbolic cotangent, and natural logarithm in FPGA implementation. This method analyzes the slope characteristics of the function and sets thresholds for partitioning. Binomial curve fitting is used to ensure accuracy in high-slope intervals, while linear fitting is used to optimize resources in low-slope intervals. Ultimately, a high-precision, low-resource memristor chaotic system is implemented on an FPGA, providing an innovative solution for chaotic signal generation.

[0064] The specific steps of the algorithm are:

[0065] 1. First, the processing steps of hyperbolic tangent, hyperbolic cotangent, and natural logarithm functions:

[0066] Step 1) Derivative the hyperbolic tangent, hyperbolic cotangent, and natural logarithm functions. To conveniently plot the slope changes of the hyperbolic tangent, hyperbolic cotangent, and natural logarithm functions within the fitting interval, first find the derivatives of these three functions. Based on the slope plots of the derivatives and the need for engineering simplification, selectively perform curve or line fitting.

[0067] Step 2) According to the actual engineering requirements, determine the slope-dominated division interval for linear fitting and curve fitting. When the slope is greater than the set threshold, a quadratic curve is used for fitting. When the slope is less than the set threshold, a straight line is used for fitting. When the slope is greater than 0.786448, the interval is curve fitting, and the interval is less than 0.786448, the interval is straight line fitting. . Select the independent variable of the hyperbolic cotangent function When the slope is greater than 0.521095, the interval is curve fitting, and the interval is less than 0.521095, the interval is straight line fitting. . Select the independent variable of the natural logarithm function When the slope is greater than 2, the interval is curve fitting, and the interval is less than 2, the interval is straight line fitting. When fitting a straight line or curve, the least squares method is used in Visual Studio C++ to determine the fitting coefficients of the straight line and curve.

[0068] The least squares fitting diagram is as follows Figure 1 As shown, assuming that the data to be fitted is , and these data are passed through To express, is the fitted value, is the independent variable, is a constant, and the fitted value for each data point is , the actual value is , the residual is , No. The input variables for each data point are , is a positive integer, expressed as ;

[0069] The goal of the least squares method is to minimize the sum of squared residuals for all data points:

[0070] ;

[0071] Solve the objective function by the above formula The minimum value of is used to get the estimated value of the parameter. In simple linear regression, the fitting function is assumed to be When , the objective function is:

[0072] ;

[0073] A further fitting function assumption is When , the objective function is:

[0074] ;

[0075] Through 、 and Find the partial derivative and set it equal to zero to get the normal equation, and then solve the constant 、 and The estimated value of , in the above formula, is the intercept, is the linear slope, is the curvature of the curve, is the number of data points.

[0076] Step 3) For a single nonlinear function, there are three curve fitting coefficients. These need to be encoded into 96-bit data, each consisting of three 32-bit IEEE754 floating-point numbers. The upper 32 bits are the quadratic coefficient, the middle 32 bits are the linear coefficient, and the lower 32 bits are the constant. There are two linear fitting coefficients. These need to be encoded into 64-bit data, each consisting of two 32-bit IEEE754 floating-point numbers. The upper 32 bits are the linear coefficient and the lower 32 bits are the constant. This is used to generate the .COE file and create the RAM IP core in Xilinx.

[0077] Step 4), in the present invention, the fitting intervals of the straight line and the curve are divided by the slope value. When the hyperbolic tangent function is in the curve fitting interval When , the interval is divided into 10 segments, and the straight line interval is , the interval is divided into 1250 segments. When the hyperbolic cotangent function is in the curve fitting interval When , the interval is also divided into 10 segments, and the straight line interval is , the interval is divided into 3150 segments. When the natural logarithm function is in the curve fitting interval , divide the interval into 100 segments, especially set the first interval to , the straight line interval is , dividing the interval into 1900 segments. Secondly, by taking advantage of the boundedness of the hyperbolic tangent function, when constructing the hyperbolic tangent function, the function value with an independent variable greater than 3 is forced to be converted to 1. When constructing a negative independent variable, the odd function property is used, and only half of the original RAM IP core resources are consumed. When constructing the hyperbolic cotangent function, the even function property is used, and only half of the original RAM IP core resources are consumed. In practice, the function construction module can be designed as follows Figure 2 As shown in the figure. The independent variable is multiplied by a multiplier to a multiple corresponding to the segmented interval and converted to a decimal fixed point number. The integer is then retained for addressing, and the parameter values for the quadratic curve fit are searched and stored. The multiplier and adder are then called to construct the quadratic curve fit function value. When the expandable module is omitted in the figure, the independent variable is directly multiplied by the slope term through the multiplier, and the intercept term is added to obtain the straight line fit.

[0078] 2. According to the above steps 1), 2), 3), and 4), the memristor chaotic system model is selected as:

[0079] ;

[0080] ;

[0081] ;

[0082] In the above formula is the voltage value of the resistor device in the memristor circuit, is the voltage value of the memristor device in the memristor circuit, is the voltage value of the capacitor device in the memristor circuit, is a positive system parameter, For time, get and set , , .

[0083] 3. Based on the differential equation of the memristor chaotic system mentioned above, the Euler iteration formula is used to obtain the iterative formula of the memristor chaotic system as follows:

[0084] ;

[0085] In the above formula is the voltage value of the resistor, memristor, and capacitor in the memristor circuit at the current moment. When the first iteration is performed, the parameters are selected , and stipulates It is an iterative formula to calculate the voltage values of resistance, memristance and capacitance at the next moment. , , , is the system iteration step.

[0086] 4. Based on the above mathematical iteration formula, the Verilog hardware design is implemented using the state machine architecture in the Xilinx ISE development environment. After completing the RTL coding, the function is verified by writing a testbench in the Xilinx ISE and ModelSim joint simulation environment. The hexadecimal data generated by the simulation is converted into decimal values through MATLAB parsing, and waveform analysis and algorithm verification are performed through plotting. The overall RTL architecture of the system is as follows: Figure 3 The Euler iteration module is constructed by the IEEE754 floating point adder IP core and multiplier IP core, which can generate x n+1 、y n+1 、z n+1 Iteration value, due to the pipeline parallel design of FPGA, while generating the iteration value, the data can be converted into a fixed-point number through the data conversion module and the D / A conversion module can be started, thereby realizing the decimal output of the iteration value.

[0087] Figure 4 This is the schematic diagram of the Euler iteration module, which uses a parallel pipeline design and can generate iterative values in less than microseconds. n and y n The initial value can generate ln(x n +b)、ln(bcosh(y n )) and tanh(y n ) three nonlinear functions. In the multiplier 1 of the first stage pipeline, z n The initial value of is negated to get negative z n And multiply it by 2, y in multiplier 2 n Multiply by k, adder 1 realizes the addition of 2k and 1, and adder 2 realizes the negative ln(x n +b) and ln(bcosh(y n )) Add. Implement negative z in adder 1 of the two-stage pipeline n Add the result of multiplier 2 in the first stage pipeline, and multiplier 1 implements y n Multiply the value of adder 1 of the first stage of the pipeline, multiplier 2 realizes the multiplication of parameter a and the value of adder 2 of the first stage of the pipeline, and multiplier 3 realizes b+x n The value of tanh(y n) is multiplied by the value of . In the three-stage pipeline adder 1, the value of the first-stage pipeline multiplier 1 is added to the value of the second-stage pipeline multiplier 1. In the adder 2, the value of the second-stage pipeline adder 1 is added to the product value obtained by inverting the second-stage pipeline multiplier 3. In the four-stage pipeline, the multiplier 1 realizes the multiplication of the step length h with the three-stage pipeline adder 1, the multiplier 2 realizes the multiplication of the supplement h with the second-stage pipeline multiplier 2, and the multiplier 3 realizes the multiplication of the step length h with the three-stage pipeline adder value. In the five-stage pipeline, adders 1, 2, and 3 are used to add the four-stage pipeline multipliers 1, 2, and 3 to the iteration initial value z n 、x n 、y n Add, and then the output adder value is the next iteration value z n+1 、x n+1 、y n+1 .

[0088] 5. When the simulation results of Modelsim are consistent with the results of the compilation platform Visual studio C++, the bit file generated after compilation and synthesis can be burned into the FPGA through the JTAG interface on the Xilinx ISE platform and observed with an oscilloscope. The connection block diagram is as follows Figure 5 shown.

[0089] 6. The chaotic signal generated by the memristor chaotic system captured by the oscilloscope is as follows: Figure 6 shown.

[0090] In summary, the present invention proposes a method for implementing a chaotic signal generator based on hybrid straight-line and curve fitting FPGA technology. This method achieves high-precision and high-efficiency implementation of a memristive chaotic system containing tanh(x), cosh(x), and ln(x) using limited RAM IP core resources within the limited resources of a Spartan-6 series FPGA. This method combines FPGA resources with precision requirements, analyzes the slope of the target nonlinear function, and determines the slope threshold through engineering practice. When the slope of a certain interval of the function exceeds the threshold, binomial curve fitting is employed, and the hardware architecture is optimized within the FPGA to reduce resources. When the slope is less than the threshold, straight-line fitting is employed to simplify the fitting function and implement it using simple logic units. The fitting results are used to construct a memristive chaotic system model, and a memristive chaotic system iteration module is integrated into the FPGA. The foregoing is only one embodiment of the present invention. Persons skilled in the relevant art may make various improvements and modifications without departing from the principles of the present invention, and such improvements and modifications should be considered within the scope of the present invention.

[0091] The above description is merely a preferred embodiment of the present invention and does not constitute any other form of limitation to the present invention. Any modification or equivalent variation based on the technical essence of the present invention shall still fall within the scope of protection claimed by the present invention.

Claims

1. A method for implementing a chaotic signal generator using FPGA technology based on hybrid fitting, characterized by: The specific steps are as follows: 1) Analyze the slope of the target nonlinear function based on FPGA resource constraints and accuracy requirements, and determine the slope threshold through engineering experiments; 2) Divide the function into intervals based on the slope threshold; When the slope of a function interval is greater than a threshold, the binomial curve fitting method is used to design the function fitting module for that interval, and targeted optimization is performed in the FPGA hardware architecture to reduce resource consumption. The binomial curve fitting method is used to design the function fitting module for this interval. The least squares method is used to determine the fitting coefficients of the straight line and curve during the function processing process. The details are as follows: Assume that the data to be fitted is , and these data are passed through To express, is the fitted value, is the independent variable, is a constant, and the fitted value for each data point is , the actual value is , the residual is , No. The input variables for each data point are , is a positive integer, expressed as ; The goal of the least squares method is to minimize the sum of squared residuals for all data points: ； Solve the objective function by the above formula The minimum value of is used to get the estimated value of the parameter. In simple linear regression, the fitting function is assumed to be When , the objective function is: ； A further fitting function assumption is When , the objective function is: ； Through 、 and Find the partial derivative and set it equal to zero to get the normal equation, and then solve the constant 、 and The estimated value of , in the above formula, is the intercept, is the linear slope, is the curvature of the curve, is the number of data points; When the slope is less than the threshold, the interval function is simplified using the straight line fitting method, and the fitting function is realized through the simple logic unit in the FPGA; 3) Select the fitting module results of each interval to construct a mathematical model of the memristor chaotic system, and integrate the iterative calculation module of the memristor chaotic system on the FPGA; 4) Based on the given iterative formula, use the Verilog hardware description language on the Xilinx ISE development platform to build a state machine control module to implement the iterative formula's loop execution. Then, use MATLAB to convert the resulting IEEE754 floating-point format and plot a chart, comparing and analyzing the results with those generated by Visual Studio C++ compilation. 5) Finally, the bit file generated after compilation and synthesis is downloaded to the FPGA via the JTAG interface, and the actual output signal is observed with the help of an oscilloscope.

2. The method for realizing a chaotic signal generator using FPGA technology based on hybrid fitting according to claim 1, characterized in that: In step 2), the binomial curve fitting method is used to design the function fitting module function processing for this interval, and the specific processing is as follows:

21. Derivative the hyperbolic tangent, hyperbolic cotangent, and natural logarithm functions respectively. First, find the derivatives of these three functions, and then plot the slope graph in the corresponding fitting interval based on the derivative results.

22. According to actual engineering requirements, the slope-dominated division intervals for straight-line and curve fitting are determined. When the slope is greater than the set threshold, a quadratic curve is used for fitting. When the slope is less than the set threshold, a straight line is used for fitting. When fitting a straight line or a curve, the least squares method is used in Visual Studio C++ to determine the fitting coefficients of the straight line and curve.

23. For a single nonlinear function, there are three coefficients for curve fitting, which need to be encoded into 96-bit data, consisting of three 32-bit IEEE754 floating-point numbers. The upper 32 bits are the quadratic coefficient, the middle 32 bits are the linear coefficient, and the lower 32 bits are the constant. There are two coefficients for linear fitting, which need to be encoded into 64-bit data, consisting of two 32-bit IEEE754 floating-point numbers. The upper 32 bits are the linear coefficient and the lower 32 bits are the constant. This is used to generate COE files and create RAM IP cores in Xilinx.

24. When searching for the storage address of the fitting coefficients in the fitting function RAM IP core through independent variables, the search needs to be combined with the partitioning interval.

3. The method for realizing a chaotic signal generator using FPGA technology based on hybrid fitting according to claim 2, characterized in that: In step 3), the memristor chaos model is selected in the mathematical model of the memristor chaos system: ； ； ； In the above formula is the voltage value of the resistor device in the memristor circuit, is the voltage value of the memristor device in the memristor circuit, is the voltage value of the capacitor device in the memristor circuit, is a positive system parameter, For time.

4. The method for realizing a chaotic signal generator using FPGA technology based on hybrid fitting according to claim 3 is characterized in that: In step 3), the iterative calculation module of the system is integrated on the FPGA, wherein the iterative calculation is specifically as follows; The differential equation of the memristor chaotic system uses the Euler iteration formula, and the iteration formula of the memristor chaotic system is obtained as follows: ； In the above formula is the voltage value at a moment under the resistor in the memristor circuit, is the voltage value of the memristor device in the memristor circuit at the next moment, is the voltage value of the capacitor device in the memristor circuit at the next moment, is the voltage value of the resistor device in the memristor circuit at the current moment, is the voltage value of the memristor device in the memristor circuit at the current moment, is the voltage value of the capacitor device in the memristor circuit at the current moment, is a positive system parameter, is the iteration step size of the system.

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