Simulation loop for autonomous time constant state switching and state decision circuit

Abstract

The invention discloses an analog loop for autonomous time constant state switching and a state decision circuit. The analog loop comprises an amplifier AV, a dominant pole loop, a secondary pole loop, a feedback amplifier A2 and a feedback amplifier A1. The output end of the amplifier AV is connected with the input end of the feedback amplifier A1 through a secondary pole loop; the output end of the feedback amplifier A1 is connected with the input end of the feedback amplifier A2 through a dominant pole loop, and the output end of the feedback amplifier A2 is connected with the input end of the amplifier AV; the time constants of the primary pole loop and the secondary pole loop can be automatically switched along with the loop establishment state, and the primary pole voltage and the secondary pole voltage are kept stable in the switching process. The problem of compromise difficulty between baseline drift and response time is solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, and relates to an analog loop with autonomous time constant state switching and a state decision circuit. Background Art

[0002] With the rapid development of Internet technology, Internet traffic has shown an explosive growth trend, which has prompted the fiber access network to usher in a new wave of large-scale installation and upgrade. Among them, the deployment of 10Gb / s-class PON (Passive Optical Network) has gradually become the mainstream and is steadily replacing the traditional GPON (Gigabit PON) to meet the increasing bandwidth requirements.

[0003] In the current time-division multiplexing passive optical network (TDM-PON), how to improve the utilization rate of user-available time resources is one of the key issues in the research of PON systems. The response time and resource allocation of the system, as important research contents, directly affect the overall performance of the network and the user experience.

[0004] At the receiving burst mode front end of the PON upstream network, BM-TIA (Burst Mode-Transimpedance Amplifier) and BM-LA (Burst Mode-Limiting Amplifier) are two commonly used devices that use an analog loop to complete the burst response function. Usually, the specific response time of these analog loop-based burst mode amplifiers is obtained through actual testing. Since it is difficult for the system to clearly define the accurate state of the establishment of the analog loop, in order to ensure the stable operation of the overall system, sufficient margins are usually reserved in advance, which to a certain extent limits the utilization efficiency of the system performance and highlights the restriction of the analog loop design on the system performance optimization.

[0005] In the burst mode TIA of an optical receiver applied to PON, using an analog loop to complete the burst response is a common technical route. The burst mode TIA adopting this technical route performs well in terms of offset cancellation accuracy and circuit structure, and has the advantages of good offset cancellation accuracy and simple circuit structure. However, such TIAs also face the trade-off problem between baseline drift and response time. Specifically, they usually neither can achieve a burst response time below 10 ns nor can ensure a sufficiently small baseline drift, which to a certain extent limits their application in high-speed and high-precision PON systems. Summary of the Invention

[0006] The object of the present invention is to solve the technical problem in the prior art that in a burst-mode TIA, the analog loop faces the difficulty of compromise between baseline drift and response time, and to provide an analog loop and a state decision circuit with autonomous time-constant state switching.

[0007] To achieve the above object, the present invention adopts the following technical solutions: The present invention discloses an analog loop with autonomous time-constant state switching, including: amplifier A V , a main-pole loop, a secondary-pole loop, feedback amplifier A2, and feedback amplifier A1; The output end of the amplifier A V is connected to the input end of the feedback amplifier A1 through the secondary-pole loop; the output end of the feedback amplifier A1 is connected to the input end of the feedback amplifier A2 through the main-pole loop, and the output end of the feedback amplifier A2 is connected to the input end of the amplifier A V . The time constants of the main-pole loop and the secondary-pole loop can be autonomously switched according to the loop establishment state, and the primary and secondary pole voltages are kept stable during the switching process.

[0008] Further, the main-pole loop includes a first variable capacitor and a first variable resistor; one end of the first variable resistor is connected to the output end of the feedback amplifier A1, and the other end is connected to the input end of the feedback amplifier A2 and also connected to one end of the first variable capacitor; the other end of the first variable capacitor is grounded.

[0009] Further, the secondary-pole loop includes a second variable capacitor and a second variable resistor; one end of the second variable resistor is connected to the output end of the amplifier, and the other end is connected to the input end of the feedback amplifier A1 and also connected to one end of the second variable capacitor; the other end of the second variable capacitor is grounded.

[0010] Further, the time-constant switching mechanism includes: During the analog loop establishment stage: accelerate the transient response through a small time constant; after the establishment is completed: increase the primary and secondary pole resistance values through a characteristic signal, and increase the time constant while keeping the voltage stable.

[0011] The present invention discloses a state stability decision circuit, including the above analog loop with autonomous time-constant state switching, a comparator, a first inverter, a flip-flop, and a second inverter; The input end of the comparator is connected to both sides of the resistor on the analog loop; the output end of the comparator is connected to the input end of the first inverter; the output end of the first inverter is connected to the flip-flop.

[0012] Further, the output end of the first inverter is connected to the clock input end of the flip-flop.

[0013] Further, the flip-flop is configured with a reset signal input end.

[0014] Further, the output terminal of the flip-flop is connected to the input terminal of the second inverter.

[0015] Further, the flip-flop is configured with multi-stage hysteresis logic.

[0016] Further, the number of hysteresis bits is adjustable.

[0017] Compared with the prior art, the present invention has the following beneficial effects: The present invention discloses an analog loop with autonomous time constant state switching. Through the series structure of the main pole loop and the secondary pole loop, the system can autonomously adjust the pole distribution in different working stages. In the initial stage of loop establishment, the secondary pole provides high-frequency compensation to suppress transient overshoot; after stabilization, the main pole dominates the low-frequency response, ensuring sufficient phase margin and avoiding high-frequency noise amplification. Automatically adjust the time constant according to the loop establishment state, and can switch between fast response (small time constant) and low noise (large time constant) without external control signals, breaking through the performance bottleneck of traditional fixed compensation networks. During the pole switching process, the dual closed-loop architecture composed of feedback amplifiers A1 and A2 dynamically adjusts the loop gain by real-time monitoring of the node voltage, effectively avoiding the impact of voltage spikes on the subsequent circuit. When the load changes or the input signal frequency suddenly changes, the loop can automatically switch to the optimal time constant combination while maintaining closed-loop stability, and is suitable for high-frequency signal amplification and low-frequency precision measurement scenarios.

[0018] Furthermore, the present invention discloses a state stability judgment circuit. The comparator is directly connected across the analog loop resistance node to monitor the voltage change at the voltage division point in real time, and cooperate with the signal shaping of the first inverter; the output of the first inverter drives the clock terminal of the flip-flop to achieve double-sensitive detection of the rising / falling edge; the flip-flop is built-in with multi-stage hysteresis comparison logic (the number of hysteresis bits is adjustable), which improves the ability to suppress power supply ripple and electromagnetic interference, and reduces the misjudgment rate compared with the single-threshold detection circuit; the comparator adopts a differential input structure to effectively shield common-mode interference. The circuit only activates the comparator and the flip-flop during state switching. When not triggered, the output of the second inverter cuts off the subsequent load through the gating circuit, greatly saving power consumption; forms a closed loop with the autonomous time constant analog loop, automatically triggers the large time constant switching when the steady state is detected, the measured phase margin is improved, and the establishment time is shortened. Through the output feedback of the second inverter, the instability trend of the loop can be predicted in advance, and the protection mechanism can be started in advance to avoid voltage collapse.

[0019] Further, the adjustable function of the number of hysteresis bits realizes dynamic adaptability. Users can adjust the hysteresis depth through configuration according to the noise level and response speed requirements of specific application scenarios, and can complete the adjustment of hysteresis characteristics without interrupting the system operation, meeting the requirements of real-time control systems for dynamic parameter optimization. Description of the Drawings

[0020] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for the embodiments will be briefly introduced below. It should be understood that the following accompanying drawings only show some embodiments of the present invention and should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related accompanying drawings can also be obtained based on these drawings.

[0021] Figure 1 It is a schematic diagram of the self - time - constant switching analog loop topology of the present invention; Figure 2 It is a schematic diagram of the state - stable decision circuit of the present invention; Figure 3 It is a schematic diagram of the working process of the decision circuit of the present invention; Figure 4 It is a performance simulation diagram of the loop signal generation part of the present invention; Figure 5 It is an overall performance simulation diagram of the present invention. Specific embodiments

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, rather than all, of the embodiments of the present invention. Usually, the components of the embodiments of the present invention described and marked in the accompanying drawings here can be arranged and designed in various different configurations.

[0023] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed present invention, but merely represents the selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

[0024] It should be noted that similar reference numerals and letters indicate similar items in the following accompanying drawings. Therefore, once an item is defined in one accompanying drawing, it does not need to be further defined and explained in subsequent accompanying drawings.

[0025] In the description of the embodiments of the present invention, it should be noted that if terms such as "upper", "lower", "horizontal", "inner", etc. are used to indicate the orientation or positional relationship, it is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the invention is usually placed when in use. This is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present invention. In addition, terms such as "first", "second", etc. are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.

[0026] In addition, if the term "horizontal" appears, it does not mean that the component is required to be absolutely horizontal, but it can be slightly inclined. For example, "horizontal" only means that its direction is more horizontal relative to "vertical", and does not mean that the structure must be completely horizontal, but it can be slightly inclined.

[0027] In the description of the embodiments of the present invention, it should also be noted that unless otherwise clearly specified and limited, if terms such as "set", "installed", "connected", "coupled" are used, they should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0028] The following further describes the present invention in detail with reference to the drawings: See Figure 1, the present invention discloses an analog loop with autonomous time constant state switching, which includes an amplifier, a dominant pole loop, a secondary pole loop, a feedback amplifier A2, and a feedback amplifier A1; the output end of the amplifier is connected to the secondary pole loop; the secondary pole loop is connected to the input end of the feedback amplifier A1; the output end of the feedback amplifier A1 is connected to the dominant pole loop; the dominant pole loop is connected to the input end of the feedback amplifier A2, and the output end of the feedback amplifier A2 is connected to the input end of the amplifier; the time constants of the dominant pole loop and the secondary pole loop can be autonomously switched according to the loop establishment state, and the voltages of the dominant and secondary poles are kept stable during the switching process. The dominant pole loop includes a first variable capacitor and a first variable resistor; one end of the first variable resistor is connected to the output end of the feedback amplifier A1, and the other end is connected to the input end of the feedback amplifier A2 and also connected to one end of the first variable capacitor; the other end of the first variable capacitor is grounded. The secondary pole loop includes a second variable capacitor and a second variable resistor; one end of the second variable resistor is connected to the output end of the amplifier, and the other end is connected to the input end of the feedback amplifier A1 and also connected to one end of the second variable capacitor; the other end of the second variable capacitor is grounded. The time constant switching mechanism includes: during the analog loop establishment stage: accelerating the transient response through a small time constant; after establishment: increasing the resistance values of the dominant and secondary poles through a characteristic signal, increasing the time constant while keeping the voltage stable.

[0029] During the initial establishment stage of the loop, through the configuration of a small time constant, after establishment, the time constant is autonomously switched to the large resistance state, reducing the baseline drift of the transfer function of the main path (amplifier path). Through the buffering effect of the feedback amplifiers (A1, A2) and the low-resistance bypass design of the switching circuit, during the resistance switching process, the voltage fluctuations of the dominant and secondary poles are suppressed, avoiding the voltage jump problem caused by impedance mutation in the traditional switching circuit.

[0030] See Figure 2 , the present invention discloses a state stability judgment circuit, which includes a comparator, a double inverter chain (a first inverter and a second inverter), a flip-flop configured with multi-stage hysteresis logic, and a reset signal control module. The specific connection relationship is as follows: The input end of the comparator is connected across both ends of the dominant pole or secondary pole resistor in the analog loop for real-time monitoring of the resistor voltage drop. The output end of the comparator is connected to the input end of the first inverter, and the output of the first inverter is used as the clock signal (CLK) input of the flip-flop, ensuring that the state of the flip-flop is updated only when the resistor voltage changes exceed a preset threshold. The flip-flop integrates multi-stage hysteresis logic units (the number of hysteresis bits can be dynamically adjusted according to system requirements), and its output end is shaped by the second inverter and then fed back to the time constant switching mechanism of the analog loop to form a closed-loop control. In addition, the flip-flop is configured with an external reset signal (RST) input end, supporting manual or automatic reset operations to enhance the flexibility of the system.

[0031] Through the collaborative work of a comparator and a multi-stage hysteresis flip-flop, noise interference is effectively filtered out (the hysteresis logic can set different voltage threshold windows), ensuring that the time constant switching is triggered only after the loop is truly stable. At the same time, the inverter chain is used to optimize the signal edge characteristics, improving the anti-interference ability and response reliability of the decision-making circuit.

[0032] When the analog loop enters the stable state after being established, this state stable decision-making circuit generates a characteristic signal, indicating that the analog loop has been established at this time. This decision-making circuit can be used to detect the state of the analog loop, converting the characteristics of the analog loop itself into digital signals for interaction with the outside world.

[0033] The state stable decision-making circuit of the present invention, the entire state stable decision-making circuit includes four ports, two measurement terminals V A and V G , a reset signal input terminal RESET, and a characteristic signal output terminal. The two measurement terminals are connected to the analog loop to be measured to test the analog loop. The reset signal input terminal can access a pulse signal to complete the circuit reset function. The output signal level of the characteristic signal output terminal represents the decision result of the decision-making circuit.

[0034] The size of the measurement resistor (i.e., the first variable resistor of the main pole loop) needs to be selected according to the detection accuracy. Among them, the comparator needs to have a relatively large (>1G) bandwidth and sufficient (<5mV) relative accuracy. The circuit hysteresis logic has the function of locking the circuit output. At the same time, the number of bits of hysteresis can be selected according to the specific transient characteristics of the circuit. Generally, the output logic of the two-stage hysteresis circuit can be adopted.

[0035] See Figure 3 , the basic circuit principle of the state stable decision-making circuit of the present invention is as follows: For an analog loop, its establishment process can be characterized as a process in which the main pole voltage continuously changes. Since the capacitance at the main pole in the loop is relatively large, a large amount of charge needs to be absorbed or released during the establishment stage, so its voltage change requires an obvious transient current. When there is no longer current injection or extraction at the main pole, it can be considered that the loop establishment is completed. In the actual circuit, the transient voltage when the analog loop is about to be established is related to the phase margin of the analog loop. Usually, when the phase margin is about 60°, there will only be a little overcharge and fluctuation in the final stage of the establishment process of the analog loop. At this time, the direction of the current injected into the main pole will reverse multiple times. The decision-making circuit triggers the characteristic signal by detecting the edge generated by the current reversal. The characteristic signal will increase the resistance at the main pole and secondary pole of the analog loop. On the one hand, it does not change the voltage at the primary and secondary poles, and at the same time, it increases the time constant to reduce the baseline drift when the main path transmits the signal, and also ensures the continuity of the state switching.

[0036] The specific current detection method can be achieved by connecting a resistor in front of the main pole capacitor and detecting the voltage across the resistor.

[0037] For a system with a higher phase margin, the comparator output can be avoided by presetting the reverse offset. Conversely, hysteresis logic can be added, and the second or more inversion edges can be selected to trigger the characteristic signal of the analog circuit.

[0038] The specific method for connecting the access circuit of the state stability judgment circuit is as follows: First, disconnect the analog loop at the main pole, and at the same time, place the capacitor used to form the main pole at the starting end of the disconnected loop. Then, connect the two measurement terminals of the judgment circuit to the loop. Next, when the loop starts to establish or is in the process of establishment, an external input reset signal is applied. Finally, when the loop establishment is completed, the judgment circuit outputs a characteristic signal, indicating that the loop establishment is completed.

[0039] To further illustrate the superiority of the present invention, in this embodiment, a simulation software is used to simulate the state stability judgment circuit, and the results are as Figure 4 shown. After the circuit is reset by the RESET signal, a step signal is input to the analog loop. It can be observed that when the output of the analog loop almost returns to the original DC point of the loop, the comparator output signal reverses, and the loop state stability signal is output.

[0040] The simulation of the analog loop and the overall state stability judgment circuit is carried out, and the results are as Figure 5 shown. After the circuit is reset by the RESET signal, a step signal and a modulation signal are input to the analog loop. It can be observed that the loop establishment is completed within 6 ns. When the output of the analog loop almost returns to the original DC point of the loop, there is almost no baseline drift in the transmission output of the loop state signal.

[0041] The present invention adopts a self-switching mechanism for the time constants of the primary and secondary pole loops. During the analog loop establishment stage, a small time constant is adopted to significantly accelerate the transient response and shorten the loop locking time; while in the stable stage, it automatically switches to a large time constant, effectively suppressing high-frequency noise and improving the phase margin, reducing the steady-state voltage fluctuation. This dynamic adjustment mechanism breaks through the design limitation of the fixed time constant and realizes the intelligent control of "fast start and slow stability". The dual-feedback amplifier architecture (A1 / A2) cooperates with the capacitor-resistor loop to maintain the continuity of the node voltage through the charge conservation mechanism during the time constant switching process. The state judgment circuit integrating multi-stage hysteresis logic realizes noise immunity through the programmable hysteresis bits, and combines the dual-inverting structure of the flip-flop to effectively control the mis-triggering probability. The high sensitivity of the comparator to detect the voltage difference across the resistor, combined with the clock synchronization mechanism, ensures that the state switching is strictly synchronized with the system clock, avoiding the metastability problem.

[0042] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, various modifications and variations can be made to the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. An analog loop with autonomous time constant state switching, characterized in that, Comprising: Amplifier A V , the main pole loop, the secondary pole loop, feedback amplifier A2, and feedback amplifier A1; The amplifier A V The output terminal of which is connected to the input terminal of the feedback amplifier A1 through a sub-pole loop; the output terminal of the feedback amplifier A1 is connected to the input terminal of the feedback amplifier A2 through a main-pole loop, and the output terminal of the feedback amplifier A2 is connected to the input terminal of the amplifier A V The time constants of the main-pole loop and the sub-pole loop can be autonomously switched according to the loop establishment state, and the main and sub-pole voltages are kept stable during the switching process.

2. The analog loop with autonomous time constant state switching according to claim 1, wherein The main pole loop includes a first variable capacitor and a first variable resistor; one end of the first variable resistor is connected to the output end of the feedback amplifier A1, and the other end is connected to the input end of the feedback amplifier A2 and simultaneously connected to one end of the first variable capacitor; the other end of the first variable capacitor is grounded.

3. The analog loop with autonomous time constant state switching according to claim 1, characterized in that, The secondary pole loop includes a second variable capacitor and a second variable resistor; one end of the second variable resistor is connected to the output end of the amplifier, and the other end is connected to the input end of the feedback amplifier A1 and is simultaneously connected to one end of the second variable capacitor; the other end of the second variable capacitor is grounded.

4. The analog loop with autonomous time constant state switching according to claim 1, wherein The time constant switching mechanism includes: Analog loop establishment stage: accelerating the transient response through a small time constant; after establishment: adjusting the main and secondary pole resistance values by a characteristic signal to increase the time constant while maintaining voltage stability.

5. A state stability judgment circuit, characterized in that, Comprising the analog loop with autonomous time constant state switching, comparator, first inverter, flip-flop, and second inverter according to any one of claims 1-4; The input end of the comparator is connected to both sides of the resistor on the analog loop; the output end of the comparator is connected to the input end of the first inverter; the output end of the first inverter is connected to the flip-flop.

6. The state-stable decision circuit according to claim 5, wherein The output end of the first inverter is connected to the clock input end of the flip-flop.

7. The state-stable decision circuit according to claim 5, wherein The flip-flop is configured with a reset signal input end.

8. The state-stable decision circuit according to claim 5, wherein The output end of the flip-flop is connected to the input end of the second inverter.

9. The state-stable decision circuit according to claim 5, wherein The flip-flop is configured with multi-stage hysteresis logic.

10. The state-stable decision circuit according to claim 9, wherein The number of hysteresis bits is adjustable.

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