Semiconductor structure, preparation method thereof and electronic equipment

Abstract

The invention discloses a semiconductor structure, a preparation method thereof and electronic equipment, and relates to the technical field of semiconductors. The preparation method comprises the steps that a substrate is provided, a side wall structure is formed on the substrate, and the side wall structure comprises a bottom face close to the substrate, a top face away from the substrate and a side face connected with the bottom face and the top face; a laminated structure is formed on the substrate on which the side wall structure is formed, the laminated structure comprises isolation layers and conductive layers which are alternately laminated, and the laminated structure is at least distributed on the side surfaces of the substrate and the side wall structure; patterning processing is conducted on the laminated structure to form stacked bit line structures located on different layers, each bit line structure comprises a first bit line and a bit line leading-out structure which make contact with each other, and the bit line leading-out structures extend in the direction away from the substrate and are stacked in the direction away from the side faces of the side wall structures. The bit line leading-out structure is simple in preparation process and low in production cost.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure, a method for manufacturing the same, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking day by day, and the types and quantities of devices included in a single chip are increasing accordingly. As a result, any minor difference in the process production may affect the device performance. In order to reduce the cost of products as much as possible, it is desired to fabricate as many device units as possible on a limited substrate. Since Moore's law came into being, various semiconductor structure designs and process optimizations have been proposed in the industry to meet the requirements of current products. Summary of the Invention

[0003] Embodiments of the present disclosure provide a semiconductor structure, a method for manufacturing the same, and an electronic device, which can optimize the manufacturing process of the bit line structure and reduce the production cost.

[0004] In some embodiments, a method for manufacturing a semiconductor structure is provided, including:

[0005] Providing a substrate, and forming a sidewall structure on the substrate, wherein the sidewall structure includes a bottom surface close to the substrate, a top surface away from the substrate, and a side surface connecting the bottom surface and the top surface;

[0006] Forming a stacked structure on the substrate having the sidewall structure formed thereon, wherein the stacked structure includes alternately stacked isolation layers and conductive layers, and the stacked structure is at least distributed on the substrate and the side surfaces of the sidewall structure;

[0007] Performing a patterning process on the stacked structure to form a bit line structure located in different layer stacks, the bit line structure including a first bit line in contact with a bit line lead-out structure, and each of the bit line lead-out structures extends in a direction away from the substrate and is stacked in a direction away from the side surface of the sidewall structure.

[0008] In some embodiments, it further includes:

[0009] Forming a corresponding bit line contact structure at the top end of each of the bit line lead-out structures.

[0010] In some embodiments, a sidewall structure with a side surface perpendicular to the substrate is formed on the substrate;

[0011] The forming of the stacked structure on the substrate having the sidewall structure formed thereon includes:

[0012] Form the isolation layer and the conductive layer stacked alternately on the substrate, with partial regions of the isolation layer and the conductive layer extending on the side surfaces of the sidewall structure and partial regions of the isolation layer and the conductive layer extending on the substrate.

[0013] In some embodiments, it further includes:

[0014] Form a filling layer on a side of the stacked structure away from the substrate;

[0015] Remove a part of the sidewall structure through a planarization process so that the tops of the bit line lead-out structures are located on the same horizontal plane.

[0016] In some embodiments, patterning the stacked structure to form bit line structures stacked in different layers includes:

[0017] Form a first isolation structure penetrating the stacked structure on the substrate. In a first direction, a bit line preset region and a capacitor connection region are respectively adjacent to opposite sides of the first isolation structure. One end of the bit line preset region is in contact with the sidewall structure. In a second direction, a transistor preset region is adjacent to one side of the first isolation structure, and a word line preset region is provided in the transistor preset region. In the first direction, one side of the transistor preset region is adjacent to the bit line preset region, and the other side of the transistor preset region is adjacent to a capacitor preset region. In the second direction, the capacitor preset region is adjacent to the capacitor connection region;

[0018] Replace at least the isolation layer in partial regions of the capacitor preset region with a capacitor dielectric layer and a first electrode, with the capacitor dielectric layer located between the first electrode and the conductive layer;

[0019] Replace the conductive layer in the transistor preset region with a transistor, and form a word line structure in the word line preset region, obtaining a bit line structure formed by the conductive layer in the bit line preset region and a second electrode formed by the conductive layer in the capacitor preset region. The transistor is electrically connected to the bit line structure and the second electrode respectively;

[0020] Wherein, the storage capacitor includes a first electrode, a second electrode, and a capacitor dielectric layer.

[0021] In some embodiments, the replacing at least the isolation layer in partial regions of the capacitor preset region with the capacitor dielectric layer and the first electrode of the storage capacitor includes:

[0022] Form a first trench penetrating the stacked structure in the capacitor connection region, with the first trench exposing the first isolation structure;

[0023] Laterally etch the isolation layer based on the first trench to form a first filling groove;

[0024] The capacitor dielectric layer and the first electrode are sequentially formed on the inner wall of the first filling groove.

[0025] In some embodiments, the forming of the capacitor dielectric layer and the first electrode on the inner wall of the first filling groove includes:

[0026] The capacitor dielectric layer is formed on the inner wall of the first filling groove, and the capacitor dielectric layer extends to cover the inner wall of the first groove;

[0027] The first electrode is formed on the capacitor dielectric layer, and the first electrode fills the first filling groove and the first groove.

[0028] In some embodiments, the replacing of the conductive layer in the transistor preset area with a transistor and forming a word line structure in the word line preset area includes:

[0029] A word line through hole is formed in the word line preset area;

[0030] Based on the word line through hole, the conductive layer in the transistor preset area is etched laterally to remove it, so as to form a second filling groove, and the bit line structure and the second electrode are obtained;

[0031] The transistor is formed in the second filling groove;

[0032] The word line structure is formed in the word line through hole.

[0033] In some embodiments, a semiconductor structure is further provided, including:

[0034] A substrate;

[0035] A plurality of stacked bit line structures located on the substrate, each of the bit line structures includes an integrally formed first bit line and a bit line lead-out structure, the first bit lines are stacked at intervals in a direction perpendicular to the substrate, the first bit lines extend along a first direction parallel to the substrate, and each of the bit line lead-out structures extends from one end of the corresponding layer of the first bit line in a direction away from the substrate.

[0036] In some embodiments, the tops of the bit line lead-out structures are on the same horizontal plane.

[0037] In some embodiments, it further includes: a sidewall structure located on the substrate, the sidewall structure includes a bottom surface close to the substrate and a top surface away from the substrate, and a side surface connecting the bottom surface and the top surface, and each of the bit line lead-out structures extends in a direction perpendicular to the substrate and is stacked in a direction away from the side surface of the sidewall structure.

[0038] In some embodiments, the side surface of the sidewall structure is perpendicular to the substrate, and the bit line lead-out structure is sequentially formed on the side surface of the sidewall structure.

[0039] In some embodiments, it further includes: a plurality of bit line contact structures, which are respectively and correspondingly connected to the tops of the respective bit line lead-out structures.

[0040] In some embodiments, it further includes a plurality of bit line contact holes. The top of the bit line lead-out structure is exposed in each bit line contact hole, and the bit line contact structure is located in the bit line contact hole.

[0041] In some embodiments, the depths of the bit line contact holes are the same.

[0042] In some embodiments, a plurality of the first bit lines correspond to the stacked multiple layers of memory cells one by one, and the first bit line is a common bit line.

[0043] In some embodiments, an electronic device is further provided, which includes the semiconductor structure as described above. Description of the Drawings

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments or related technologies. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0045] Figure 1 For the manufacturing method of the semiconductor structure in some embodiments;

[0046] Figure 2 For the top view schematic diagram of the semiconductor structure after forming the filling layer in some embodiments;

[0047] Figure 3 For Figure 2 The cross-sectional schematic diagram perpendicular to the substrate of the corresponding semiconductor structure in the EE direction;

[0048] Figure 4 For the top view schematic diagram of the semiconductor structure after forming the bit line structure based on the stacked structure in some embodiments;

[0049] Figure 5 For Figure 4 The cross-sectional schematic diagram perpendicular to the substrate of the corresponding semiconductor structure in the EE direction;

[0050] Figure 6 For the top view schematic diagram of the semiconductor structure after removing a part of the sidewall structure 104 in some embodiments;

[0051] Figure 7is Figure 6 A schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the AA direction;

[0052] Figure 8 is Figure 6 A schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the EE direction;

[0053] Figure 9 A top view schematic of the semiconductor structure after forming the first preset isolation structure in some embodiments;

[0054] Figure 10 is Figure 9 A schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the AA direction;

[0055] Figure 11 is Figure 9 A schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the BB direction;

[0056] Figure 12 is Figure 9 A schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the CC direction;

[0057] Figure 13 is Figure 9 A schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the EE direction;

[0058] Figure 14 A top view schematic of the semiconductor structure after forming the second isolation structure in some embodiments;

[0059] Figure 15 is Figure 14 A schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the AA direction;

[0060] Figure 16 is Figure 14 A schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the BB direction;

[0061] Figure 17 is Figure 14 A schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the CC direction;

[0062] Figure 18 is Figure 14 A schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the EE direction;

[0063] Figure 19 A top view schematic of the semiconductor structure after forming the first trench in some embodiments;

[0064] Figure 20 isFigure 19 Schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the AA direction;

[0065] Figure 21 is Figure 19 Schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the BB direction;

[0066] Figure 22 is Figure 19 Schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the CC direction;

[0067] Figure 23 is Figure 19 Schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the DD direction;

[0068] Figure 24 is Figure 19 Schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the EE direction;

[0069] Figure 25 is a top view schematic of the semiconductor structure after forming the first filling groove in some embodiments;

[0070] Figure 26 is Figure 25 Schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the AA direction;

[0071] Figure 27 is Figure 25 Schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the BB direction;

[0072] Figure 28 is Figure 25 Schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the CC direction;

[0073] Figure 29 is Figure 25 Schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the DD direction;

[0074] Figure 30 is Figure 25 Schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the EE direction;

[0075] Figure 31 is a top view schematic of the semiconductor structure after forming the first electrode in some embodiments;

[0076] Figure 32 is Figure 31 Schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the AA direction;

[0077] Figure 33 isFigure 31 Schematic cross-sectional view perpendicular to the substrate of the corresponding semiconductor structure in the BB direction;

[0078] Figure 34 is Figure 31 Schematic cross-sectional view perpendicular to the substrate of the corresponding semiconductor structure in the CC direction;

[0079] Figure 35 is Figure 31 Schematic cross-sectional view perpendicular to the substrate of the corresponding semiconductor structure in the DD direction;

[0080] Figure 36 is Figure 31 Schematic cross-sectional view perpendicular to the substrate of the corresponding semiconductor structure in the EE direction;

[0081] Figure 37 is a top view schematic of the semiconductor structure before forming the word line vias in some embodiments;

[0082] Figure 38 is Figure 37 Schematic cross-sectional view perpendicular to the substrate of the corresponding semiconductor structure in the AA direction;

[0083] Figure 39 is Figure 37 Schematic cross-sectional view perpendicular to the substrate of the corresponding semiconductor structure in the BB direction;

[0084] Figure 40 is Figure 37 Schematic cross-sectional view perpendicular to the substrate of the corresponding semiconductor structure in the CC direction;

[0085] Figure 41 is Figure 37 Schematic cross-sectional view perpendicular to the substrate of the corresponding semiconductor structure in the DD direction;

[0086] Figure 42 is Figure 37 Schematic cross-sectional view perpendicular to the substrate of the corresponding semiconductor structure in the EE direction;

[0087] Figure 43 is a top view schematic of the semiconductor structure after forming the word line vias in some embodiments;

[0088] Figure 44 is Figure 43 Schematic cross-sectional view perpendicular to the substrate of the corresponding semiconductor structure in the AA direction;

[0089] Figure 45 is Figure 43 Schematic cross-sectional view perpendicular to the substrate of the corresponding semiconductor structure in the BB direction;

[0090] Figure 46 isFigure 43 Schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the CC direction;

[0091] Figure 47 is Figure 43 Schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the DD direction;

[0092] Figure 48 is Figure 43 Schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the EE direction;

[0093] Figure 49 is a top view of the semiconductor structure after forming the word line structure in some embodiments;

[0094] Figure 50 is Figure 49 Schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the AA direction;

[0095] Figure 51 is Figure 49 Schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the BB direction;

[0096] Figure 52 is Figure 49 Schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the CC direction;

[0097] Figure 53 is a top view of the semiconductor structure after forming the bit line contact structure in some embodiments;

[0098] Figure 54 is Figure 53 Schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the AA direction;

[0099] Figure 55 is Figure 53 Schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the BB direction;

[0100] Figure 56 is Figure 53 Schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the CC direction;

[0101] Figure 57 is Figure 53 Schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the DD direction;

[0102] Figure 58 is Figure 53 Schematic cross-sectional view of the corresponding semiconductor structure perpendicular to the substrate in the EE direction.

[0103] Description of reference numerals:

[0104] 102. Substrate; 103. Upper surface layer; 104. Sidewall structure; 105. Bit line structure; 106. Stacked structure; 108. First protective layer; 110. First preset isolation structure; 112. Second isolation structure; 114. First isolation structure; 116. Capacitor dielectric layer; 118. First electrode; 120. Second electrode; 122. Semiconductor layer; 124. Gate dielectric layer; 126. Word line structure; 128. Bit line contact structure; 202. Isolation layer; 203. First bit line; 204. Conductive layer; 205. Bit line lead-out structure; 206. Filling layer; 207. Second bit line; 208. Second protective layer; 210. Capacitor mask pattern layer; 212. First trench; 214. First filling groove; 216. Third protective layer; 218. Second filling layer; 220. Word line through hole; 222. Fourth protective layer; 224. Passivation layer; 1. First isolation part; 2. Second isolation part; 6. Third isolation part; 7. Fourth isolation part. Detailed implementation manners

[0105] To facilitate the understanding of the embodiments of the present disclosure, the embodiments of the present disclosure will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the embodiments of the present disclosure can be implemented in many different forms and are not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the embodiments of the present disclosure more thorough and comprehensive. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the embodiments of the present disclosure belong. The terms used in the description of the embodiments of the present disclosure herein are only for the purpose of describing specific embodiments and are not intended to limit the embodiments of the present disclosure. The term "and / or" used herein includes any and all combinations of one or more of the related listed items. In the description of the embodiments of the present disclosure, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the embodiments of the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the embodiments of the present disclosure. It can be understood that the terms "first", "second", etc. used in the present disclosure can be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, the first electrode can be called the second electrode, and similarly, the second electrode can be called the first electrode. Both the first electrode and the second electrode are electrodes, but they are not the same electrode. In addition, the terms "first", "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present disclosure, "a plurality" means at least two, such as two, three, etc., unless otherwise specifically defined. In the description of the present disclosure, "several" means at least one, such as one, two, etc., unless otherwise specifically defined.

[0106] As used herein, the term "substrate" means and includes the substrate material or structure of the materials of the transistors introduced in the present disclosure. The substrate may be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. The substrate may be a conventional silicon substrate or other bulk substrate including a layer of semiconductor material. The upper surface of the substrate in the present disclosure is the surface on which the stacked structure is formed for the substrate, the lower surface of the substrate is the surface disposed opposite to the upper surface, and for the upper and lower surfaces of other structures or layers, relative to the upper surface of the substrate, for the structures or layers located in the substrate, among the two surfaces parallel to the substrate surface, the one closer to the upper surface of the substrate is the upper surface / top surface / top / top face, and the one away from the upper surface of the substrate is the lower surface / bottom surface / bottom / bottom face. For the structures or layers located on the substrate, on the contrary, among the two surfaces, the one closer to the upper surface of the substrate is the lower surface / bottom surface / bottom / bottom face, and the one away from the upper surface of the substrate is the upper surface / top surface / top / top face. For the structures, trenches, holes, or layers formed in the semiconductor structure in a direction away from the substrate surface, the surface in the third direction is the sidewall of the structure, trench, hole, or layer, and the position where the trench or hole penetrates and stops is the bottom of the trench or hole. The technical solution of the present application is used for semiconductor structures, and may be leads that need to be led out in multiple layers and distributed in a stepped manner in the semiconductor or chip field, such as word lines or bit lines, or common word lines or common bit lines, etc. Taking the bit line as an example, the present application forms a bit line and a lead extending in the vertical direction and connected to the peripheral circuit through a single process. It can be understood that the bit line and the lead are an integrated structure and are formed in the same process. The process is simple and the structural connection performance is good.

[0107] Provided is a method for preparing a semiconductor structure, including:

[0108] Providing a substrate, and forming a sidewall structure on the substrate, wherein the sidewall structure includes a bottom surface close to the substrate, a top surface away from the substrate, and a side surface connecting the bottom surface and the top surface;

[0109] Forming a stacked structure on the substrate formed with the sidewall structure, wherein the stacked structure includes alternately stacked isolation layers and conductive layers, and the stacked structure is at least distributed on the side surfaces of the substrate and the sidewall structure;

[0110] Performing a patterning process on the stacked structure to form bit line structures stacked in different layers, the bit line structures including a first bit line and a bit line lead structure in contact with each other, and each bit line lead structure extends in a direction away from the substrate and is stacked in a direction away from the side surface of the sidewall structure.

[0111] The method will be described in detail below with reference to the drawings. As Figure 1 shown, in this example, it includes:

[0112] S102, Provide a substrate and form a sidewall structure on the substrate.

[0113] Specifically, provide a substrate and form a sidewall structure on the substrate. The sidewall structure is a support structure for a bit line lead-out structure to be formed subsequently. The sidewall structure is located in a preset area of the bit line lead-out structure formed on the substrate subsequently. The sidewall structure includes a bottom surface close to the substrate, a top surface far from the substrate, and a side surface connecting the bottom surface and the top surface.

[0114] The sidewall structure described in this application has at least one sidewall (also called a side surface), and can be a layered, columnar or other shaped structure extending towards the substrate with sidewalls. This application does not specifically limit the shape and structure of the sidewall structure. The sidewall can be a smooth two-dimensional plane or a curved surface. The sidewall can be perpendicular to the substrate or have a non-90-degree angle with the substrate (such as 30 degrees, 60 degrees, etc., which are not limited).

[0115] In some embodiments, the constituent materials of the substrate include but are not limited to undoped single-crystalline silicon, doped single-crystalline silicon, silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), or any combination thereof. As an example, in this embodiment, the constituent material of the substrate is selected as single-crystalline silicon. The substrate has a certain thickness and can be used as a structural support for device structures (such as stacked structures) formed thereon. As an option, the substrate can be removed in some subsequent process steps. In some embodiments, the constituent material of the sidewall structure is an insulating layer, including but not limited to one or more of silicon oxides (such as silicon dioxide), silicon nitrides (silicon oxynitride), nitrides (such as silicon nitride), carbides (silicon carbide), and silicides (germanium silicon). Exemplarily, the constituent material of the sidewall structure is silicon dioxide.

[0116] S104, Form a stacked structure on the substrate formed with the sidewall structure. The stacked structure includes an isolation layer and a conductive layer alternately stacked in a direction away from the substrate, and the stacked structure at least extends to cover the side surface of the sidewall structure.

[0117] The direction away from the substrate in this step can be understood as forming a stacked structure on the upper surface of the substrate formed with the sidewall structure. The stacking directions of the stacked structures are not exactly the same. For example, when stacking on the substrate, it is stacked in a direction away from the substrate, and when stacking on the sidewall of the sidewall structure, it is stacked along a direction away from the side surface.

[0118] A stacked structure is formed on a substrate, and the stacked structure includes an isolation layer and a conductive layer that are alternately stacked in a direction away from the substrate. Exemplarily, in a third direction perpendicular to the substrate, the thickness of the stacked structure is less than or equal to the height of the sidewall structure, and the stacked structure extends along a plane parallel to the substrate to at least cover the side surface of the sidewall structure, or may cover the entire sidewall structure including the top surface, such as the side surface and the top surface of the sidewall structure, that is, each isolation layer and each conductive layer extend to cover the side surface and the top surface of the sidewall structure. The isolation layer and the conductive layer on the side surface of the sidewall structure are alternately stacked in a direction away from the side surface from at least one side surface of the sidewall structure, and the isolation layer and the conductive layer on the side surface of the sidewall structure are alternately stacked to form a stacked structure in the horizontal direction. The number of conductive layers can be set according to the number of bit line structures (the number of memory cells stacked in the third direction Z in the semiconductor structure), and the number of bit line structures (the number of memory cells) stacked in the third direction is the same as the number of conductive layers. In the isolation layer and the conductive layer, either one can be deposited on the substrate first. Exemplarily, the top of the stacked structure can be a conductive layer or an isolation layer; similarly, the bottom of the stacked structure can also be a conductive layer or an isolation layer. Exemplarily, both the top and the bottom of the stacked structure are isolation layers.

[0119] In some embodiments, the bottom of the stacked structure is a conductive layer, and an isolation material layer is formed on the surface of the substrate. By providing the isolation material layer, the memory cells near the substrate in the semiconductor structure are isolated from the device structure in the substrate. In some embodiments, the constituent materials of the isolation layer include, but are not limited to, one or more of silicon oxide (such as silicon dioxide), silicon nitride (silicon oxynitride), nitride (such as silicon nitride), carbide (silicon carbide), silicide (germanium silicide), low-k dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9), and ultra-low-k dielectric material (dielectric constant less than 2.5). Exemplarily, the constituent material of the isolation layer is silicon dioxide, which has a low manufacturing cost and can reduce the parasitic capacitance in the semiconductor structure to a certain extent. In some embodiments, the constituent material of the isolation layer is a low-k dielectric material or an ultra-low-k dielectric material, thereby reducing the capacitance of the parasitic capacitance in the semiconductor structure including the bit line structure provided in the present disclosure, improving the read and write speed of data in the semiconductor structure, and improving the performance of the semiconductor structure. In some embodiments, the constituent material of the isolation layer is silicon nitride. At this time, the isolation layer plays a good supporting role while blocking the diffusion of oxygen atoms.

[0120] The bit line structure described in the embodiments of the present application may be a structure including a bit line. For example, in an application scenario where a multi-layer memory cell array is stacked, each layer has multiple bit lines connected to memory cells in different columns and a common bit line connecting the bit lines in this layer. The bit line structure includes multiple bit lines of multiple columns of stacked memory cells and / or common bit lines respectively connected to multiple columns of stacked bit line structures. The bit line and the common bit line are connected through a switching transistor.

[0121] S106, pattern the stacked structure to form a bit line structure formed by the conductive layer.

[0122] At least pattern the stacked structure on the substrate to obtain a bit line structure formed by the conductive layer in the stacked structure. The bit line structure includes a first bit line and a bit line lead-out structure that are in contact with each other and formed by the same layer of conductive layer. The first bit lines are stacked at intervals in a third direction perpendicular to the substrate and extend in a plane parallel to the substrate. Each of the bit line lead-out structures is stacked at intervals from the side surface of the sidewall structure to the side away from the sidewall structure and extends in a third direction perpendicular to the substrate. One end (the end away from the substrate) of each bit line lead-out structure that is far from the first bit line is in the same plane parallel to the substrate, that is, the lead-out ends of the bit line structure are in the same plane.

[0123] In the preparation method of the above semiconductor structure, the first bit lines in the bit line structure are stacked in a third direction perpendicular to the substrate, and each bit line lead-out structure is stacked at intervals from the side surface of the sidewall structure to the side far from the sidewall structure. This setting can make the lead-out ends (top ends) of the bit line structure located in the same horizontal plane through a top planarization process (such as chemical mechanical polishing process). Subsequently, bit line contact structures corresponding to different layer bit line structures can be formed through the same process step, and the preparation process is simple and the production cost is low. For example, other dielectric layers are formed above the planarized bit line contact structure, and bit line contact holes are formed in the dielectric layer. Each of the bit line contact holes exposes the top end of the bit line lead-out structure, and the bit line contact structure is located in the bit line contact hole. The hole depths of the bit line contact holes are the same. Each bit line contact hole can be obtained through a single-step photolithography and etching process, simplifying the process. The bit line contact structure in the bit line contact hole is used to connect to the peripheral circuit.

[0124] In some embodiments, the sidewall structure may include more than one sidewall. For example, two opposite sidewalls (side surfaces).

[0125] A group of bit line lead-out structures is formed on one sidewall, and another group of bit line lead-out structures is formed on the other sidewall. The two groups of bit line lead-out structures are insulated from each other. The bit line lead-out structure is in the form of a line or a film layer extending in a direction away from the substrate.

[0126] In some embodiments, the sidewall structure is columnar, and a continuous entire surface of bit line lead-out structures is formed on the entire side surface. Different bit line lead-out structures are sequentially formed on the sidewall around the sidewall structure, and the different bit line lead-out structures are insulated from each other by an insulating layer that surrounds the sidewall structure. The cross-section of each bit line lead-out structure is annular.

[0127] The Z direction can be Figure 2 the third direction from the top surface of the substrate 102 to the bottom surface of the substrate 102, such as Figure 2 、Figure 3 As shown, in some embodiments, a substrate 102 is provided, and a sidewall structure 104 is formed on the substrate 102, including: providing the substrate 102, forming a sidewall material layer on the substrate 102 by chemical vapor deposition process or physical vapor deposition process or atomic layer deposition process, and patterning the sidewall material layer through photolithography and etching processes to obtain the sidewall structure 104. The thickness of the sidewall structure 104 is greater than or equal to the thickness of the subsequent formed stacked structure 106, and the direction of the thickness is the direction of the third direction Z. The sidewall structure 104 serves as an induced support layer for the subsequent formed bit line lead-out structure, and the thickness of the sidewall structure can be set according to the thickness of the semiconductor structure in the third direction Z.

[0128] As Figure 2 , Figure 3 shown, in some embodiments, a stacked structure 106 is formed on the substrate 102 on which the sidewall structure 104 is formed, including: forming an alternately stacked isolation layer 202 and a conductive layer 204 on the substrate 102 by using, but not limited to, atomic layer deposition process. Part of the isolation layer 202 and the conductive layer 204 extends in a direction parallel to the side surface of the sidewall structure 104, and part of the isolation layer 202 and the conductive layer 204 extends in a direction parallel to the top surface of the sidewall structure 104. Specifically, both the isolation layer 202 and the conductive layer 204 extend along the side surface of the sidewall structure 104 and cover to the top surface of the sidewall structure 104. The isolation layer 202 and the conductive layer 204 surround all or part of the side surfaces of the sidewall structure 104, and through the sidewall structure 104, the conductive layer 204 is turned from in-plane extension to the third direction Z.

[0129] In some embodiments, when the stacked structure 106 extends and covers to the top surface of the sidewall structure 104, the method for preparing the semiconductor structure further includes: removing a part (the upper surface layer 103) of the sidewall structure 104 and the stacked structure 106 (the stacked structure 106 higher than the upper surface layer 103) in contact with the removed part of the sidewall structure 104. Specifically, by using an etching process or a chemical mechanical polishing process, a part of the sidewall structure and the stacked structure in contact with the removed part of the sidewall structure are removed. The bottom of the removed part of the sidewall structure is higher than or equal to the top of the stacked structure located on the substrate. At this time, the ends of the conductive layer on the sidewall of the sidewall structure facing away from the substrate are in the same plane, and "facing away" means far away. As Figure 2 , Figure 3 shown, in some embodiments, the method for preparing the semiconductor structure further includes step S202 - step S204.

[0130] S202, forming a filling layer 206 on the side of the stacked structure 106 away from the substrate 102.

[0131] In step S204, a part of the sidewall structure 104, a part of the stacked structure 106, and the filling layer 206 are removed, so that the ends of the respective conductive layers away from the substrate are in the same plane.

[0132] Specifically, in steps S202 - S204, a filling layer 206 is formed on the substrate 102 by using a chemical deposition process and a chemical mechanical polishing process. The thickness of the filling layer 206 formed on the stacked structure 106 stacked in the third direction is greater than the thickness of the sidewall structure 104, so as to obtain a substrate 102 with a flat surface. A part (the upper surface layer 103) of the sidewall structure 104 facing away from the substrate 102, a part (the stacked structure 106 higher than the upper surface layer 103) of the stacked structure 106, and the filling layer 206 higher than the upper surface are removed by using a chemical mechanical polishing process or an etching process. At this time, the ends of the respective conductive layers 204 located on the side of the sidewall structure 104 away from the substrate 102 are in the same plane, the ends of the respective isolation layers 202 located on the side of the sidewall structure 104 away from the substrate 102 are in the same plane, and the ends of the conductive layer 204 and the isolation layer 202 located on the sidewall of the sidewall structure 104 away from the substrate 102 are in the same plane. In some embodiments, the bottom of the upper surface layer 103 of the sidewall structure 104 is flush with the top surface of the stacked structure 106 stacked in the third direction on the substrate 102, that is, the filling layer 206 is completely removed. Figure 5 Taking the example that the filling layer 206 on the stacked structure 106 stacked in the third direction after step S204 is removed, in some embodiments, there is a filling layer 206 on the stacked structure 106 stacked in the third direction Z on the substrate 102 after step S204.

[0133] As Figure 4 、 Figure 5 shown, in some embodiments, the stacked structure is patterned to form a bit line structure 105 formed by the conductive layer 204, including: patterning the stacked structure 106 to obtain a bit line structure 105 formed by the remaining conductive layer 204. The bit line structure 105 includes a first bit line 203 stacked at intervals in the third direction Z, and a bit line lead-out structure 205 located on the side of the sidewall structure 104. The bit line lead-out structure 205 extends along the side of the sidewall structure 104 and is in contact with the bit line 203. In the present disclosure, the sidewall of the sidewall structure 104 is equivalent to the side of the sidewall structure 104.

[0134] In some embodiments, each first bit line 203 extends in the same direction. The sidewall structure 104 is located in the extending direction of the first bit line 203, and the bit line lead-out structure 205 is at least located on a partial side surface of the sidewall structure 104. In some embodiments, the bit line structure 105 further includes a second bit line which is subsequently in contact with a transistor. The first bit line 203 is used to connect the second bit line and the bit line lead-out structure 205. Each layer of the first bit line 203 extends in a first direction, and each layer of the second bit line extends in a second direction, and the second direction intersects with the first direction. In some embodiments, the bit line lead-out structures 205 of different bit line structures 105 are covered on different sidewalls of the sidewall structure 104, that is, different bit line structures 105 are formed by the same conductive layer 204 and the same sidewall structure 104, thereby reducing the manufacturing cost of the bit line structure.

[0135] In some embodiments, the method for manufacturing a semiconductor structure further includes: forming a bit line contact structure on a side of the bit line lead-out structure 205 away from the substrate 102. The bit line contact structure is connected to the top end of the bit line lead-out structure 205 in a one-to-one correspondence. The top end of the bit line lead-out structure 205 is the end of the bit line lead-out structure 205 away from the substrate 102, that is, the bit line contact structure is in contact with the end of the bit line lead-out structure 205 facing away from the first bit line 203. The bit line structure 105 can be connected to an external circuit through the bit line contact structure. It can be understood that the ends of the bit line contact structures are on the same plane.

[0136] In some embodiments, patterning the stacked structure 106 to form the bit line structure 105 formed by the conductive layer 204 includes: performing a patterning process on the stacked structure 106 to obtain the bit line structure 105 formed by the remaining conductive layer 204. The bit line structure 105 includes the first bit lines 203 stacked in a third direction and the bit line lead-out structures 205 surrounding the sidewall of the sidewall structure 104. By this setting, the area for arranging the bit line contact structures can be increased, thereby increasing the distance between the subsequently formed bit line contact structures and reducing the interference between adjacent bit line contact structures.

[0137] Figure 6 The schematic cross-sectional views of the corresponding semiconductor structure perpendicular to the substrate in the BB direction, CC direction, and DD direction are the same as Figure 3 Exemplarily, the X direction can be Figure 6 The first direction in the plane parallel to the substrate 102 shown, the Y direction can be Figure 6 The second direction in the plane parallel to the substrate 102 shown, and the Z direction can be Figure 6In a third direction from the top surface to the bottom surface of the substrate 102, within a plane parallel to the substrate 102, the semiconductor structures formed in the first device region 10 and the second device region 20 are mirror-symmetrical about the axis MM. In the first direction X, adjacent semiconductor structures share a bit line structure. Subsequently, an exemplary description will be given of forming a semiconductor structure in the first device region 10.

[0138] In one embodiment, patterning the stacked structure 106 to form a bit line structure formed by the conductive layer 204 includes steps S402 - S406.

[0139] S402, forming a first isolation structure 114 that penetrates the stacked structure 106 on the substrate 102.

[0140] Figure 9 The schematic cross-sectional view perpendicular to the substrate of the corresponding semiconductor structure in the DD direction is the same as Figure 12 the same, Figure 14 The schematic cross-sectional view perpendicular to the substrate of the corresponding semiconductor structure in the DD direction is the same as Figure 17 the same, as Figure 9 - Figure 24 shown. Specifically, a first isolation structure 114 that penetrates the stacked structure 106 is formed on the substrate 102. In the first direction X, a bit line preset region and a capacitor connection region are respectively adjacent to opposite sides of the first isolation structure 114. That is, a bit line preset region, the first isolation structure 114, and a capacitor connection region that are in contact with each other are sequentially arranged in the first direction X. One end of the bit line preset region is in contact with the sidewall structure 104, that is, the sidewall structure 104 is provided in the extending direction of the bit line preset region; in the second direction Y, a transistor preset region is adjacent to one side of the first isolation structure 114, and a word line preset region is provided in the transistor preset region. That is, the transistor preset region completely surrounds or semi-surrounds the word line preset region. In the first direction X, one side of the transistor preset region is adjacent to the bit line preset region, and the other side of the transistor preset region is adjacent to a capacitor preset region. In the second direction Y, the capacitor preset region is adjacent to the capacitor connection region. Here, adjacent means adjacent and in contact.

[0141] As Figure 9 - Figure 24 shown, in some embodiments, forming the first isolation structure 114 that penetrates the stacked structure 106 on the substrate 102 includes steps S502 - S510.

[0142] S502, forming a first preset trench and a second preset trench that are interconnected and penetrate the stacked structure 106 on the substrate 102.

[0143] Specifically, a mask pattern layer is formed on the stacked structure 106. The mask pattern layer covers the bit line preset area, the transistor preset area, the word line preset area, and the capacitor preset area. The stacked structure 106 that is not covered by the mask pattern layer is etched away, and a first preset trench and a second preset trench that communicate with each other are formed on the substrate 102. In the third direction Z, the first preset trench and the second preset trench penetrate the stacked structure 106. The first preset trench extends along the first direction X. In the first direction X, the first preset trench extends from the capacitor connection preset area to the side of the bit line preset area close to the capacitor connection area. The side wall of the first preset trench exposes the stacked structure 106 of the bit line preset area. The second preset trench is located on the side of the capacitor connection area away from the bit line preset area. The second preset trench extends along the second direction Y. In the first direction X, there is a stacked structure 106 between the second preset trench and the capacitor preset area. In the second direction Y, the side wall of the first preset trench exposes the stacked structures 106 of the transistor preset area and the capacitor preset area.

[0144] In some embodiments, in the third direction Z, the bottom of the first preset trench and the bottom of the second preset trench are both flush with the bottom surface of the stacked structure 106. In some embodiments, in the third direction Z, the first preset trench and the second preset trench extend into the substrate 102 (isolation material layer). Through this setting, the influence of process deviation on isolating adjacent memory cells by the subsequently formed first preset isolation structure and the second isolation structure is eliminated. It can be understood that after forming the first preset trench and the second preset trench, the step of removing the mask pattern layer is further included.

[0145] S504, a first protective layer 108 and a first preset isolation structure 110 are sequentially formed on the inner wall of the first preset trench.

[0146] Such as Figure 9 - Figure 13As shown, a first protective layer 108 and a first preset isolation structure 110 are sequentially formed on the inner wall of the first preset trench by a chemical mechanical deposition process, an atomic layer deposition process, or a chemical mechanical polishing process. The first protective layer 108 covers the inner walls of both the first preset trench and the second preset trench. Further, the first protective layer 108 extends to cover the top surface of the stacked structure 106 in the bit line preset area, the transistor preset area, the word line preset area, and the capacitor preset area. The first preset isolation structure 110 fills the first preset trench and the second preset trench. The first preset isolation structure 110 includes a first isolation portion 1 filled in the first preset trench and a second isolation portion 2 filled in the second preset trench. Further, the first preset isolation structure 110 fills the first preset trench and the second preset trench completely. The first protective layer 108 is located on the sidewall of the stacked structure 106 in the bit line preset area, protecting the stacked structure 106 in the bit line preset area and serving as a device support. The first preset isolation structure 110 serves as an isolation later, for example, isolating adjacent semiconductor structures in the second direction and also having a device support function.

[0147] S506, laterally etch the isolation layer 202 between the second preset trench and the capacitor preset area based on the second preset trench to form a third filling groove.

[0148] As Figure 14 - Figure 18 shown, etch and remove the first preset isolation structure 110 filled in the second preset trench and the first protective layer 108 on the inner wall of the second preset trench, and laterally etch the isolation layer 202 and a part of the first preset isolation structure 110 close to the second preset trench in the first preset trench based on the second preset trench to form a third filling groove. The third filling groove communicates with the second preset trench. In the first direction X, the isolation layer 202 in the stacked structure 106 between the second preset trench and the capacitor preset area is removed.

[0149] S508, fill and form a second isolation structure in the third filling groove and the second preset trench.

[0150] As Figure 14 - Figure 18As shown, a second isolation structure 112 is formed by filling a third filling groove and a second preset groove using a chemical vapor deposition process or an atomic layer deposition process. The second isolation structure 112 serves as a support layer for a subsequent formed storage capacitor, preventing the subsequent formed first filling groove from collapsing. The second isolation structure 112 also isolates adjacent storage units arranged in the first direction X. The second isolation structure 112 includes a third isolation portion 6 filled in the third filling groove and a fourth isolation portion 7 filled in the second preset groove. The first protective layer 108 on the top surface of the stacked structure 106, the second isolation structure 112 higher than the top surface of the stacked structure 106, and the first preset isolation structure 110 higher than the top surface of the stacked structure 106 are removed using a chemical mechanical polishing process in a bit line preset area, a transistor preset area, a word line preset area, and a capacitor preset area.

[0151] S510, removing the first preset isolation structure 110 in the capacitor connection area to obtain a first isolation structure 114.

[0152] As Figure 19 - Figure 24 shown, a second protective layer 208 and a capacitor mask pattern layer 210 are sequentially formed on a substrate 102. The second protective layer 208 is in contact with the top surface of the stacked structure 106, and the capacitor mask pattern layer 210 is located on the top surface of the second protective layer 208. Exemplarily, the constituent material of the second protective layer 208 is silicon nitride, and the constituent material of the capacitor mask pattern layer 210 is polysilicon. Then, a patterning process is performed to etch away the second protective layer 208, the capacitor mask pattern layer 210, and the first preset isolation structure 110 in the capacitor connection area to form a first trench 212, obtaining a first isolation structure 114 formed by the remaining first preset isolation structure 110. Among them, in the first direction X, the sidewalls of the first trench 212 expose the second isolation structure 112 and the first isolation structure 114, and in the second direction Y, the first trench 212 exposes the first protective layer 108 on the sidewall of the first preset trench. The first trench 212 extends along the X direction and is arranged at intervals along the Y direction. The first isolation structure 114 is used to isolate adjacent semiconductor structures in the second direction Y. In some embodiments, the first isolation structure 114 is used to isolate a bit line structure and a storage capacitor in the first direction X. In some embodiments, the first trench 212 penetrates through the first preset isolation structure 110 and the first protective layer 108 to expose the substrate 102, facilitating subsequent connection of the structure formed in the first trench 212 to a reference signal line formed in the substrate 102. Further, the first trench 212 extends into the substrate 102 to avoid etching deviation resulting in the bottom of the first trench 212 remaining with the first protective layer 108, which affects the connection between the structure subsequently formed in the first trench 212 and the reference signal line formed in the substrate 102.

[0153] S404. Replace at least a part of the isolation layer in the capacitor preset area with a capacitor dielectric layer and a first electrode, where the capacitor dielectric layer is located between the first electrode and the conductive layer.

[0154] In some embodiments, replacing at least a part of the isolation layer in the capacitor preset area with the capacitor dielectric layer and the first electrode of the storage capacitor includes steps S602 - S606.

[0155] S602. Form a first trench 212 that penetrates the stacked structure in the capacitor connection area, and the first trench 212 exposes the first isolation structure 114.

[0156] S604. Laterally etch the isolation layer based on the first trench 212 to form a first filling groove.

[0157] As Figure 25 - Figure 30 shown, laterally etch the isolation layer 202 in the stacked structure 106 of at least a part or all of the area of the capacitor preset area based on the first trench 212. For example, remove the isolation layer 202 in the stacked structure 106 corresponding to a partial length of the capacitor preset area exposed on the sidewall of the first trench 212 in the second direction Y, or remove the isolation layer 202 in the stacked structure 106 corresponding to a partial length of the capacitor preset area in the first direction X. By adjusting the area of the isolation layer 202 removed by lateral etching in the plane parallel to the substrate 102, the capacitance of the subsequently formed storage capacitor can be adjusted. Further, before laterally etching the isolation layer 202 based on the first trench 212 to form the first filling groove 214, there is also a step of removing the first protective layer 108 (located on the sidewall of the stacked structure 106 in the capacitor preset area) exposed by the first trench 212. In the third direction Z, the first filling groove 214 is located between adjacent conductive layers 204 and between the substrate 102 and adjacent conductive layers 204, and the size of the first filling groove 214 is equal to the thickness of the isolation layer 202. In some embodiments, in the second direction Y, laterally etch the isolation layer 202 between adjacent first trenches 212 through the first trench 212. When there are no adjacent first trenches 212 in the second direction Y for the first trench 212, laterally etch the isolation layer 202 exposed on the sidewall of the first trench 212, and the first filling groove 214 communicates with adjacent first trenches 212 in the second direction Y, thereby increasing the capacitance of the storage capacitor in the semiconductor structure.

[0158] In some embodiments, the isolation layer 202 is removed by lateral etching based on the first trench 212 to form the first filling trench 214, further comprising: removing, by lateral etching based on the first trench 212, a part of the first isolation structure 114 (and the exposed part of the second isolation structure 112) exposed by the first trench 212 in the first direction X, so as to increase the length of the first trench 212 in the first direction X, increase the ability to remove the isolation layer 202 by lateral etching through the first trench 212, and increase the capacitance of the storage capacitor in the semiconductor structure. It can be understood that in the first direction X, there is a first isolation structure 114 between the first trench 212 and the stacked structure 106 of the bit line preset area, so as to isolate the storage capacitor and the bit line structure.

[0159] S606, forming the capacitor dielectric layer 116 and the first electrode 118 on the inner wall of the first filling trench 214 in sequence.

[0160] In some embodiments, before forming the capacitor dielectric layer 116 and the first electrode 118 on the inner wall of the first filling trench 214 in sequence, it further comprises: etching and removing the capacitor mask pattern layer 210 on the substrate 102; etching and removing the second protective layer 208 on the first isolation structure 114, so as to facilitate the uniform deposition of the subsequent capacitor dielectric layer 116.

[0161] As Figure 31 - Figure 36 shown, the capacitor dielectric layer 116 and the first electrode 118 are formed on the inner wall of the first filling trench 214 in sequence by chemical vapor deposition process or / and atomic layer deposition process.

[0162] In some embodiments, the constituent materials of the capacitor dielectric layer 116 include but are not limited to silicon oxides (such as silicon dioxide), silicon nitrides (silicon oxynitrides), nitrides (such as silicon nitride), metal oxides (such as Al2O3), metal oxynitrides (such as AlON), metal silicides, high-K dielectric materials (dielectric constant greater than 3.9), low-k dielectric materials (dielectric constant greater than or equal to 2.5 and less than 3.9), ultra-low-k dielectric materials (dielectric constant less than 2.5), ferroelectric materials, antiferroelectric materials, carbides (silicon carbide) or their combinations. Exemplarily, high-K materials may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5) or strontium titanate (SrTiO3). Exemplarily, the constituent material of the capacitor dielectric layer 116 is a high-K dielectric material, and the capacitor dielectric layer made of the high-K dielectric material can increase the capacitance of the storage capacitor.

[0163] Exemplarily, the constituent material of the first electrode 118 is a stack of titanium nitride and conductive polysilicon. The atomic layer deposition process is used to form titanium nitride, which has a good filling effect. Together with conductive polysilicon (boron-doped polysilicon) that is inexpensive and has good conductivity, they are used as the first electrode 118, which can reduce the process cost.

[0164] In some embodiments, forming the capacitor dielectric layer 116 and the first electrode 118 on the inner wall of the first filling groove 214 in sequence includes step S702 - step S704.

[0165] S702, forming the capacitor dielectric layer 116 on the inner wall of the first filling groove 214, and the capacitor dielectric layer 116 extends to cover the inner wall of the first trench 212.

[0166] Using chemical vapor deposition process or atomic layer deposition process, form the capacitor dielectric layer 116 on the inner wall of the first filling groove 214, and the capacitor dielectric layer 116 extends along the side wall of the first filling groove 214 to cover the inner wall of the first trench 212.

[0167] S704, forming the first electrode 118 on the capacitor dielectric layer 116, and the first electrode 118 fills the first filling groove 214 and the first trench 212.

[0168] Using chemical vapor deposition process or / and atomic layer deposition process, form the first electrode 118 on the capacitor dielectric layer 116, and the first electrode 118 fills the first filling groove 214 and the first trench 212. In some embodiments, the first electrode 118 fills the first filling groove 214 and the first trench 212, and the first electrodes 118 of adjacent storage capacitors in the second direction Y and stacked storage capacitors in the third direction Z share the first electrode 118, so that the first electrode 118 of the storage capacitor can be set to a reference potential, such as zero potential, to reduce the heat dissipated by the storage capacitor during the operation of the semiconductor structure and improve the performance of the semiconductor structure.

[0169] Such as Figure 37 - Figure 42As shown, in some embodiments, the capacitive dielectric layer 116 extends along the sidewalls of the first trench 212 and covers the substrate 102. After forming the first electrode 118 on the capacitive dielectric layer 116, it further includes: removing the capacitive dielectric layer 116 and the first electrode 118 on the stacked structure 106 in the bit line preset area, the stacked structure 106 in the transistor preset area, the stacked structure 106 in the word line preset area, the first isolation structure 114, and the sidewall structure 104. Specifically, the capacitive dielectric layer 116 extends along the sidewalls of the first trench 212 and covers the first isolation structure 114, the second isolation structure 112, and the second protective layer 208. After forming the first electrode 118 on the capacitive dielectric layer 116, the top surface of the first electrode 118 is higher than the top surface of the second protective layer 208; a third protective layer 216 is formed on the substrate 102, and the third protective layer 216 covers the first filling groove 214, the first trench 212, and the second isolation structure 112, that is, the third protective layer 216 covers the capacitive dielectric layer 116 and the first electrode 118 (on the capacitive connection area, the capacitive preset area, and the second isolation structure 112) that are part of the storage capacitor. Using photolithography and etching processes (such as wet etching processes), the capacitive dielectric layer 116 and the first electrode 118 exposed by etching away the third protective layer 216 are removed, that is, the capacitive dielectric layer 116 and the first electrode 118 on the first isolation structure 114, the stacked structure 106 in the transistor preset area, the stacked structure 106 in the word line preset area, the stacked structure 106 in the bit line preset area, and the sidewall structure 104 are removed.

[0170] In some embodiments, after removing the capacitive dielectric layer 116 and the first electrode 118 on the stacked structure 106 in the bit line preset area, the stacked structure 106 in the transistor preset area, the stacked structure 106 in the word line preset area, the first isolation structure 114, and the sidewall structure 104, it further includes: forming a second filling layer 218 on the substrate 102. Specifically, the second filling layer 218 is formed on the substrate 102 using chemical vapor deposition and chemical mechanical polishing processes, and the top surface of the second filling layer 218 is flush with the top surface of the third protective layer 216, and a flat substrate 102 is obtained by forming the second filling layer 218.

[0171] S406, replacing the conductive layer 204 in the transistor preset area with a transistor, and forming a word line structure in the word line preset area.

[0172] Specifically, replace the conductive layer 204 in the transistor preset area with a transistor, and form a word line structure in the word line preset area, obtaining a bit line structure 105 formed by the conductive layer 204 in the bit line preset area and a second electrode 120 formed by the conductive layer 204 in the capacitor preset area, where the transistor is electrically connected to the bit line structure 105 and the second electrode 120 respectively; wherein, the storage capacitor includes a first electrode 118, a second electrode 120, and a capacitor dielectric layer 116.

[0173] In some embodiments, replacing the conductive layer 204 in the transistor preset area with a transistor and forming a word line structure in the word line preset area includes steps S802 - S808.

[0174] S802, form a word line through hole 220 in the word line preset area.

[0175] As Figure 43 - Figure 48 shown, specifically, form a fourth protective layer 222 on the substrate 102, and then through photolithography and etching processes, form a word line through hole 220 that penetrates the fourth protective layer 222 and the stacked structure 106 in the word line preset area. In some embodiments, in the first direction X, at least one of the space between the word line through hole 220 and the bit line preset area and the space between the word line through hole 220 and the adjacent capacitor dielectric layer 116 has the stacked structure 106 of the transistor preset area. In some embodiments, the bottom of the word line through hole 220 is flush with the bottom surface of the stacked structure 106. In some embodiments, in the third direction Z, the word line through hole 220 extends into the substrate 102 (isolation material layer), and through this setting, the influence of process deviation on the isolation between the word line structure and the bit line structure (the conductive layer 204 in the bit line preset area) is eliminated.

[0176] S804, laterally etch the conductive layer 204 in the transistor preset area based on the word line through hole 220 to form a second filling groove, and obtain the bit line structure 105 and the second electrode.

[0177] Figure 49 The schematic cross-sectional view perpendicular to the substrate of the corresponding semiconductor structure in the DD direction is the same as Figure 47 that, Figure 49 The schematic cross-sectional view perpendicular to the substrate of the corresponding semiconductor structure in the EE direction is the same as Figure 48 that, as Figure 49 - Figure 52As shown, the conductive layer 204 in the transistor preset region is laterally etched based on the word line via 220 to form a second filling groove, obtaining a second electrode 120 formed by the conductive layer 204 in the capacitor preset region and a bit line structure 105 formed by the conductive layer 204 in the bit line preset region. Among them, the storage capacitor includes a first electrode 118, a capacitor dielectric layer 116, and a second electrode 120. In the first direction X, the second electrode 120 and the bit line structure 105 are located on opposite sides of the word line via 220. In the third direction Z, the second electrode 120 is located between adjacent capacitor dielectric layers 116. The second filling groove is located between adjacent isolation layers 202 in the stacked structure 106 of the transistor preset region and between the substrate 102 and adjacent isolation layers 202. The size of the second filling groove in the third direction Z is equal to the size of the conductive layer 204. By adjusting the thickness of the conductive layer in the third direction Z and the size of the transistor preset region in the plane parallel to the substrate, the channel length and channel width of the transistor are adjusted.

[0178] S806, form a transistor in the second filling groove.

[0179] In some embodiments, forming a transistor in the second filling groove includes steps S902 - step S906.

[0180] S902, form a semiconductor layer 122 on the inner wall of the second filling groove, and the semiconductor layer 122 is electrically connected to the bit line structure 105 and the second electrode 120 respectively. S904, form a gate dielectric layer 124 on the semiconductor layer 122. S906, form a gate on the gate dielectric layer 124. Among them, the transistor includes a semiconductor layer 122, a gate dielectric layer 124, and a gate.

[0181] Specifically, in steps S902 - S906, an atomic layer deposition process or a chemical vapor deposition process is used to form a semiconductor material layer on the inner wall of the second filling groove. The semiconductor material layer extends along the side wall of the second filling groove and covers the inner wall of the word line via 220. A conformal gate dielectric material layer covering the semiconductor material layer is formed on the semiconductor material layer by an atomic layer deposition process or a chemical vapor deposition process. The gate dielectric material layer and the semiconductor material layer in the word line via 220 (on the inner wall of the word line via) are removed by etching (e.g., a dry etching process) to obtain a semiconductor layer 122 formed by the remaining semiconductor material layer in the second filling groove and a gate dielectric layer 124 formed by the remaining gate dielectric material layer in the second filling groove. In the third direction Z, the semiconductor layers 122 are arranged at intervals. Then, a gate electrode is formed on the gate dielectric layer 124. The gate electrode can fill the second filling groove or be located in the word line via 220 on one side of the second filling groove. Exemplarily, the gate electrode fills the second filling groove. It can be understood that when the gate electrode is located in the word line via 220 on one side of the second filling groove, the conductive layer 204 in the preset region of the transistor is actually replaced by a part of the transistor. The transistor includes a semiconductor layer 122, a gate dielectric layer 124, and a gate electrode; wherein, the semiconductor layer 122 is in contact with the bit line structure 105 and the second electrode 120 at the same time. The part of the semiconductor layer 122 in contact with the bit line structure 105 is the drain region, the part of the semiconductor layer 122 in contact with the second electrode 120 is the source region, and the semiconductor layer 122 between the drain region and the source region is the channel region.

[0182] Exemplarily, the constituent material of the semiconductor layer 122 includes single crystal silicon, polycrystalline silicon, ferroelectric material, antiferroelectric material, IGZO, indium tin oxide (ITO), indium zinc oxide (IZO), IGO, or a combination thereof. When using IGZO as the semiconductor layer, it has the advantages of low leakage current and short refresh time. Exemplarily, the constituent material of the gate dielectric layer 124 includes silicon oxide (e.g., silicon dioxide), silicon nitride (silicon oxynitride), nitride (e.g., silicon nitride), metal oxide (e.g., Al2O3), metal oxynitride (e.g., AlON), metal silicide, high - k dielectric material (dielectric constant greater than 3.9), low - k dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9), ultra - low - k dielectric material (dielectric constant less than 2.5), ferroelectric material, antiferroelectric material, or a combination thereof. Exemplarily, the high - k material can include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanate (SrTiO3).

[0183] S808. A word line structure 126 is formed in the word line via 220.

[0184] Specifically, a word line structure 126 is formed in the word line through hole 220 by using a chemical vapor deposition process and a chemical mechanical polishing process. The word line structure 126 is in contact with the gates of the transistors in each memory cell stacked in the third direction Z, and the top surface of the word line structure 126 is flush with the top surface of the fourth protective layer 222. Exemplarily, the portion of the word line structure 126 opposite to the second filling groove can serve as the gate of the transistor, and by this arrangement, the size of the preset area of the transistor can be further reduced. As Figure 53 - Figure 58 shown, in some embodiments, after forming the word line structure 126 in the word line through hole 220, it further includes: forming a passivation layer 224 on the substrate 102 by using a chemical vapor deposition process and a chemical mechanical polishing process to perform top protection on the semiconductor structure. Exemplarily, the passivation layer 224 includes stacked silicon nitride and silicon dioxide.

[0185] As Figure 53 - Figure 58 shown, in some embodiments, the method for manufacturing the semiconductor structure further includes: forming a bit line contact structure 128 on the bit line lead-out structure 205. The bit line contact structure 128 corresponds to the bit line lead-out structure 205 one by one and is in contact with the bit line lead-out structure 205. Specifically, a plurality of bit line contact holes are formed in the bit line lead-out structure 205 by using a photolithography process and an etching process (such as a wet etching process). The bit line contact holes penetrate through the passivation layer 224, and the bottoms of the bit line contact holes expose the ends of the respective bit line lead-out structures 205. Then, the bit line contact structure 128 is filled in the bit line contact holes.

[0186] In some embodiments, the constituent materials of the conductive layer, the constituent materials of the bit line contact structure 128, the constituent materials of the first electrode 118, the constituent materials of the gate, and the constituent materials of the word line structure 126 include, but are not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. Exemplarily, the metal can be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2), indium tin oxide; the metal silicide includes tungsten silicide (WSi), silicon germanide (SiGe). Exemplarily, the constituent material of the conductive layer is tungsten. In some embodiments, the constituent materials of the isolation material layer, the constituent materials of the filling layer 206, the constituent materials of the first protection layer 108, the constituent materials of the first preset isolation structure 110, the constituent materials of the second isolation structure 112, the constituent materials of the third protection layer 216, the constituent materials of the second filling layer 218, and the constituent materials of the fourth protection layer 222 include, but are not limited to, one or more of silicon oxide (such as silicon dioxide), silicon nitride (silicon oxynitride), nitride (such as silicon nitride), and carbide (silicon carbide). Exemplarily, the constituent materials of the filling layer 206, the first preset isolation structure 110, and the second filling layer 218 are silicon dioxide, and the constituent materials of the first protection layer 108, the second isolation structure 112, the third protection layer 216, and the fourth protection layer 222 are silicon nitride.

[0187] It should be understood that although Figure 1 the steps in the flowchart of Figure 1 are shown sequentially in the direction of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear indication in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover,

[0188] such as Figure 4 , Figure 5As shown, the present disclosure also provides a semiconductor structure. The same or corresponding parts as those in the embodiments of the above-mentioned method for manufacturing a semiconductor structure will not be elaborated below. The semiconductor structure includes: a substrate 102, and a plurality of bit line structures 105 located on the substrate 102; the bit line structure 105 includes a first bit line 203 and a bit line lead-out structure 205 formed integrally. Each of the first bit lines 203 is stacked at intervals in a third direction Z perpendicular to the substrate 102, and the first bit line 203 extends along a first direction X parallel to the substrate 102. Each of the bit line lead-out structures 205 extends from one end of the first bit line 203 of the corresponding layer in a direction away from the substrate 102 to the same plane.

[0189] In the above semiconductor structure, the first bit line and the bit line lead-out structure are formed integrally, and the end of the bit line lead-out structure 205 facing away from the first bit line 203 is in the same plane parallel to the substrate 102. This setting enables the lead-out ends of the bit line structure 105 to be in the same plane, completing the fabrication of the bit line structure for connecting the stepped distributed bit lines or common bit lines to the peripheral circuit. When a bit line contact structure needs to be made subsequently, a consistent hole depth can also be formed through a single drilling process, and a single conductive material filling can form the bit line contact structure, which is in electrical contact with the peripheral circuit. The preparation process of this process is simple and the production cost is low.

[0190] As Figure 4 、 Figure 5 shown, in some embodiments, the semiconductor structure further includes: a sidewall structure 104, the sidewall structure 104 is located on the substrate 102, the sidewall structure 104 includes a bottom surface close to the substrate 102 and a top surface away from the substrate 102, and a side surface connecting the bottom surface and the top surface. The extending direction of the bit line lead-out structure is parallel to the side surface of the sidewall structure 104. As Figure 4 、 Figure 5 shown, in some embodiments, the bit line lead-out structures 205 are stacked at intervals from the side surface of the sidewall structure 104 in a direction away from the sidewall structure 104.

[0191] As Figure 4 、 Figure 5As shown, in some embodiments, the semiconductor structure further includes: a plurality of bit line contact structures, which are respectively connected to the ends of the bit line lead-out structures 205 extending to the same plane and away from the substrate 102. Exemplarily, the bit line contact structure contacts one end of the bit line lead-out structure 205 facing away from the first bit line 203. Through the bit line contact structure, the bit line structure 105 can be connected to the outside for data transmission. In some embodiments, each first bit line 203 extends in the same direction, the sidewall structure 104 is located in the extending direction of the first bit line 203, and the bit line lead-out structure 205 is at least located on a partial sidewall of the sidewall structure 104. In some embodiments, multiple first bit lines 203 correspond to the stacked multiple layers of memory cells one by one. The bit line structure 105 further includes a second bit line, and the second bit line is directly in contact with the transistor subsequently. The first bit line 203 is a common bit line for connecting the second bit line and the bit line lead-out structure 205 through a switching transistor. The transistor is electrically connected through the second bit line and the first bit line 203. Each layer of the first bit line 203 extends in a first direction, and each layer of the second bit line extends in a second direction, and the second direction intersects with the first direction. In some embodiments, the bit line lead-out structures 205 of different bit line structures 105 are covered on different sidewalls of the sidewall structure 104, that is, different bit line structures 105 are formed through the same conductive layer 204 and the same sidewall structure 104, thereby reducing the manufacturing cost of the bit line structure. In some embodiments, the bit line lead-out structure 205 at least partially surrounds the sidewall structure 104. Through this setting, the area for arranging the bit line contact structure can be increased, so as to increase the distance between the subsequently formed bit line contact structures and reduce the interference between adjacent bit line contact structures.

[0192] As Figure 53 - Figure 58 shown, in one of the embodiments, the semiconductor structure further includes: multiple layers of memory cells stacked in a direction perpendicular to the substrate 102, and the memory cells include transistors, and the transistors are electrically connected to the first bit line 203.

[0193] In one of the embodiments, the memory cell further includes: a storage capacitor. The second bit line is located on a side of the transistor facing away from the storage capacitor, and the transistor is electrically connected to the second bit line and the storage capacitor respectively. In one of the embodiments, the semiconductor structure further includes: a word line structure 126, which penetrates through the stacked multiple layers of memory cells in the third direction Z, and the transistors in each layer of the memory cells share the word line structure 126. In some embodiments, the transistor includes a gate and a semiconductor layer 122, the gate contacts the word line structure 126, the semiconductor layer 122 is located on a side of the gate facing away from the word line structure 126, and the semiconductor layers 122 of each layer are spaced apart in the third direction Z, so as to increase the control ability of the transistor.

[0194] In some embodiments, the second bit line 207 extends along the second direction Y. Each layer of memory cells includes a plurality of memory cells arranged in an array. Among the memory cells in the same layer, the memory cells adjacent to each other in the first direction X are mirror-symmetrical with respect to the second bit line 207.

[0195] In some embodiments, in the second direction Y, a first isolation structure 114 that penetrates through the stacked multiple layers of memory cells is disposed between adjacent word line structures 126. In the first direction X, a second isolation structure 112 that penetrates through the stacked multiple layers of memory cells and extends along the second direction Y is disposed between the storage capacitors of adjacent memory cells; the storage capacitor includes a first electrode 118, a capacitive dielectric layer 116, and a second electrode 120. In the third direction Z, the first electrode 118 is located on one side of the second electrode 120, and the capacitive dielectric layer 116 is located between the first electrode 118 and the second electrode 120.

[0196] In some embodiments, the semiconductor structure further includes: a first trench that penetrates through the stacked multiple layers of memory cells, is located between the first isolation structure 114 and the second isolation structure 112, and exposes the first isolation structure 114, the second electrode 120, and the second isolation structure 112; wherein, the capacitive dielectric layer 116 covers the inner wall of the first trench, the side walls of the first isolation structure 114, and the side walls of the second isolation structure 112. The first electrode 118 is filled in the first trench along the capacitive dielectric layer 116, and the storage capacitors of different layers share the first electrode. Further, the storage capacitors adjacent to each other in the second direction Y and the storage capacitors stacked in the third direction Z share the first electrode 118, increasing the electrode area of the storage capacitor, thereby increasing the capacitance of the storage capacitor and improving the reliability of the semiconductor structure.

[0197] In some embodiments, the semiconductor structure further includes: a bit line contact structure 128, the bit line contact structure 128 corresponds to the bit line lead-out structure 205 one by one and is in contact with the bit line lead-out structure 205. The bit line structure 105 can be connected to an external circuit through the bit line contact structure 128.

[0198] The present disclosure also provides an electronic device including the above semiconductor structure. The electronic device may include a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a smart mobile terminal. The embodiments of the present application do not impose any special restrictions on the specific form of the above electronic device.

[0199] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification. The above-described embodiments only represent several implementation manners of the embodiments of the present disclosure, and the description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the embodiments of the present disclosure, several modifications and improvements can still be made, and these all belong to the protection scope of the embodiments of the present disclosure.

Claims

1. A method for preparing a semiconductor structure, characterized in that, Comprising: Providing a substrate, and forming a sidewall structure on the substrate, wherein the sidewall structure includes a bottom surface close to the substrate, a top surface far from the substrate, and a side surface connecting the bottom surface and the top surface; Forming a stacked structure on the substrate formed with the sidewall structure, wherein the stacked structure includes an alternating stack of an isolation layer and a conductive layer, and the stacked structure is at least distributed on the substrate and the side surface of the sidewall structure; Performing a patterning process on the stacked structure to form a bit line structure located in different stacked layers, the bit line structure including a first bit line and a bit line lead-out structure in contact with each other, and each bit line lead-out structure extends in a direction away from the substrate and is stacked in a direction away from the side surface of the sidewall structure.

2. The preparation method according to claim 1, wherein Further comprising: Forming a corresponding bit line contact structure at the top end of each bit line lead-out structure.

3. The preparation method according to claim 1, wherein Forming a sidewall structure on the substrate with the side surface perpendicular to the substrate; The forming a stacked structure on the substrate formed with the sidewall structure includes: Forming the alternating stack of the isolation layer and the conductive layer on the substrate, and partial regions of the isolation layer and the conductive layer extend on the side surface of the sidewall structure, and partial regions of the isolation layer and the conductive layer extend on the substrate.

4. The preparation method according to claim 1, wherein, Further comprising: Forming a filling layer on a side of the stacked structure far from the substrate; Removing a part of the sidewall structure through a planarization process so that the top ends of the respective bit line lead-out structures are located on the same horizontal plane.

5. The preparation method according to claim 1, characterized in that, Performing a patterning process on the stacked structure to form a bit line structure located in different stacked layers, including: Forming a first isolation structure penetrating the stacked structure on the substrate. In a first direction, opposite sides of the first isolation structure are respectively adjacent to a bit line preset region and a capacitor connection region. One end of the bit line preset region is in contact with the sidewall structure. In a second direction, one side of the first isolation structure is adjacent to a transistor preset region, and a word line preset region is provided in the transistor preset region. In the first direction, one side of the transistor preset region is adjacent to the bit line preset region, and the other side of the transistor preset region is adjacent to a capacitor preset region. In the second direction, the capacitor preset region is adjacent to the capacitor connection region; Replacing at least a partial region of the isolation layer in the capacitor preset region with a capacitor dielectric layer and a first electrode, and the capacitor dielectric layer is located between the first electrode and the conductive layer; Replacing the conductive layer in the transistor preset region with a transistor, and forming a word line structure in the word line preset region, obtaining a bit line structure formed by the conductive layer in the bit line preset region and a second electrode formed by the conductive layer in the capacitor preset region, and the transistor is electrically connected to the bit line structure and the second electrode respectively; Wherein, the storage capacitor includes a first electrode, a second electrode, and a capacitor dielectric layer.

6. The preparation method according to claim 5, characterized in that, The replacing at least a partial region of the isolation layer in the capacitor preset region with the capacitor dielectric layer and the first electrode of the storage capacitor includes: Forming a first trench penetrating the stacked structure in the capacitor connection region, and the first trench exposes the first isolation structure; Remove the isolation layer based on the lateral etching of the first trench to form a first filling groove; Form the capacitor dielectric layer and the first electrode on the inner wall of the first filling groove in sequence.

7. The preparation method according to claim 6, characterized in that, The forming the capacitor dielectric layer and the first electrode on the inner wall of the first filling groove in sequence includes: Form the capacitor dielectric layer on the inner wall of the first filling groove, and the capacitor dielectric layer extends to cover the inner wall of the first trench; Form the first electrode on the capacitor dielectric layer, and the first electrode fills the first filling groove and the first trench.

8. The preparation method according to claim 5, characterized in that, The replacing the conductive layer in the transistor preset area with a transistor and forming a word line structure in the word line preset area includes: Form a word line through hole in the word line preset area; Remove the conductive layer in the transistor preset area based on the lateral etching of the word line through hole to form a second filling groove, and obtain the bit line structure and the second electrode; Form the transistor in the second filling groove; Form the word line structure in the word line through hole.

9. A semiconductor structure, characterized in that, Include: A substrate; A plurality of stacked bit line structures located on the substrate, each bit line structure includes an integrally formed first bit line and a bit line lead-out structure, each first bit line is stacked at intervals in a direction perpendicular to the substrate, the first bit line extends along a first direction parallel to the substrate, and each bit line lead-out structure extends from one end of the corresponding layer of the first bit line in a direction away from the substrate.

10. The semiconductor structure according to claim 9, wherein The tops of the respective bit line lead-out structures are in the same horizontal plane.

11. The semiconductor structure according to claim 9, wherein, Further include: A sidewall structure located on the substrate, the sidewall structure includes a bottom surface close to the substrate, a top surface far from the substrate, and a side surface connecting the bottom surface and the top surface, and each bit line lead-out structure extends in a direction perpendicular to the substrate and is stacked along a direction away from the side surface of the sidewall structure.

12. The semiconductor structure according to claim 11, wherein, The side surface of the sidewall structure is perpendicular to the substrate, and the bit line lead-out structures are sequentially formed on the side surface of the sidewall structure.

13. The semiconductor structure according to claim 9, wherein, Further include: A plurality of bit line contact structures, which are connected to the tops of the respective bit line lead-out structures in a one-to-one correspondence.

14. The semiconductor structure according to claim 13, wherein Further include a plurality of bit line contact holes, each bit line contact hole exposes the top of the bit line lead-out structure, and the bit line contact structure is located in the bit line contact hole.

15. The semiconductor structure according to claim 14, wherein The depths of the bit line contact holes are the same.

16. The semiconductor structure according to claim 9, wherein The plurality of first bit lines correspond to a plurality of stacked memory cells one-to-one, and the first bit line is a common bit line.

17. An electronic device, characterized in that, Include the semiconductor structure according to any one of claims 9-16.

Images