Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, the semiconductor structure comprises a substrate, active columns, word lines and bit lines, the active columns, the word lines and the bit lines are located on the substrate, the multiple active columns are arranged in an array mode in the second direction and the third direction, the multiple word lines are arranged in an array mode in the third direction, and each word line extends in the second direction. The plurality of bit lines are arranged in an array along a second direction, and each bit line extends along a third direction. At least part of the contact surface of the word line and the contact area of the vertical channel of the active column is not parallel to the second direction, so that a non-complete depletion channel is formed, and the problem of unstable threshold voltage can be solved. In addition, when the word lines and the bit lines partially surround the active columns, the distance between the adjacent word lines and the adjacent bit lines can be increased, and the coupling effect can be reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and particularly to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] With the continuous miniaturization of the feature size of semiconductor devices (such as below 10 nm), the density and integration of memory arrays have been significantly improved. However, the resulting signal interference problem affects the reliability of semiconductor structures. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in the present disclosure. This overview is not intended to limit the scope of protection of the claims.

[0004] In a first aspect of the present disclosure, a semiconductor structure is provided, including: A substrate; A plurality of active pillars disposed on the substrate, each active pillar extending along a first direction, the plurality of active pillars being arranged in an array along a second direction and a third direction. The active pillar includes a vertical channel, and a preset angle is formed between the second direction and the third direction, and both are perpendicular to the first direction; A plurality of word lines arranged in an array in the third direction, each word line extending along the second direction, and each word line connecting a plurality of the active pillars arranged in an array along the second direction. At least a partial contact surface of the contact area between the word line and the vertical channel of the active pillar is not parallel to the second direction; A plurality of bit lines arranged in an array in the second direction, each bit line extending along the third direction, and each bit line connecting a plurality of the active pillars arranged in an array along the third direction. At least a partial contact surface of the contact area between the bit line and the first end of the active pillar is not parallel to the third direction; For each active pillar, along the first direction, the bit line and the word line on the active pillar are arranged at intervals.

[0005] In some possible embodiments, a non-fully depleted channel is formed in the contact area between the vertical channel of the active pillar and the word line.

[0006] In some possible embodiments, each word line is provided with a plurality of first grooves along the second direction, each first groove corresponding to one active pillar, and the outer surface of the vertical channel is in contact connection with the inner wall surface of the first groove.

[0007] In some possible embodiments, each bit line is provided with a plurality of second grooves along the third direction, each second groove corresponding to one active pillar, and the outer surface of the first end of the active pillar is in contact connection with the inner wall surface of the second groove.

[0008] In some possible embodiments, a partial area of the first end of the active pillar is recessed to form a recess, and the inner surface of the second groove is in contact connection with the recess.

[0009] In some possible embodiments, the shape of any one of the first groove and the second groove includes an arc groove and a polygon groove.

[0010] In some possible embodiments, the projection of the polygon groove on the substrate includes at least two line segments connected in sequence; Some of the at least two line segments are parallel to the extension direction of the word line or the bit line where the polygon groove is located, or all of the at least two line segments are not parallel to the extension direction of the word line or the bit line where the polygon groove is located.

[0011] In some possible embodiments, the projection pattern of the active pillar on the substrate includes a square, the polygon groove includes a first segment, a second segment, and a third segment connected in sequence, the first segment and the third segment are perpendicular to the second segment respectively, and the second segment is parallel to the extension direction of the word line or the bit line where the polygon groove is located.

[0012] In some possible embodiments, for each active pillar, the bit line connected to the active pillar covers the outer surface of the entire circumferential direction of the first end.

[0013] In some possible embodiments, the semiconductor structure further includes a plurality of storage capacitors, and the plurality of storage capacitors are connected to the second ends of the plurality of active pillars in a one-to-one correspondence.

[0014] According to a second aspect of the present disclosure, there is provided a method for manufacturing a semiconductor structure, including: Providing a substrate, on which a plurality of active pillars are formed, each active pillar extends along a first direction, the plurality of active pillars are arranged in an array along a second direction and a third direction, the active pillar includes a vertical channel, a preset angle is provided between the second direction and the third direction, and both are perpendicular to the first direction; Forming a plurality of bit lines, the plurality of bit lines are arranged in an array in the second direction, each bit line extends along the third direction, each bit line is connected to a plurality of the active pillars arranged in an array along the third direction, and at least a part of the contact surface of the contact area between the bit line and the first end of the active pillar is not parallel to the third direction; A plurality of word lines are formed. For each of the active pillars, along the first direction, the bit lines and the word lines on the active pillar are arranged at intervals. The plurality of word lines are arranged in an array in the third direction. Each word line extends along the second direction. Each word line is connected to a plurality of the active pillars arranged in an array along the second direction. At least a part of the contact surface of the contact area between the word line and the vertical channel of the active pillar is not parallel to the second direction.

[0015] In some possible embodiments, the forming of the plurality of word lines includes: For each of the active pillars, a non-fully depleted channel is formed in the contact area between the vertical channel of the active pillar and the word line.

[0016] In some possible embodiments, the forming of the plurality of bit lines includes: A first mask layer is formed on the top surface of the substrate. The first mask layer exposes a first target area where the bit lines are to be formed. Among them, a first dielectric layer is filled between adjacent active pillars in the substrate; The first dielectric layer at a first depth along the first direction in the first target area is removed, exposing the outer surface of a first part of the active pillar. The remaining first dielectric layer in the first target area defines the bottom position of the bit line; A plurality of the bit lines are formed. The bit lines cover the outer surface of a second part of the active pillar exposed in the first target area. The second part is a part of the first part.

[0017] In some possible embodiments, the manufacturing method of the semiconductor structure further includes: The first dielectric layer at a second depth along the first direction in the first target area is removed, exposing the outer surface of a third part of the active pillar. The second depth is less than the first depth; A protective layer is formed on the sidewall of the third part of the active pillar; The first dielectric layer between the first depth and the second depth is removed, defining a first area along the first direction; A part of the structure of the active pillar in the first area is removed to form a recess.

[0018] In some possible embodiments, the forming of the word line includes: A second dielectric layer is formed above the plurality of bit lines. The second dielectric layer covers the top surface of the bit lines and fills the gap between the bottoms of the vertical channels of adjacent active pillars; A third dielectric layer is formed above the second dielectric layer. The third dielectric layer covers the surface of the vertical channel of the active pillar; Multiple word lines are formed, and each of the word lines is connected to a plurality of the active pillars arranged along the second direction. At least a part of the contact surface of the contact area between the word line and the third dielectric layer is not parallel to the second direction. The multiple word lines are disposed between adjacent ones of the active pillars arranged in an array along the third direction.

[0019] In some possible embodiments, after forming the third dielectric layer above the second dielectric layer, the manufacturing method further includes: Forming a fourth dielectric layer above the second dielectric layer, where the fourth dielectric layer covers the exposed surfaces of the second dielectric layer and the third dielectric layer; Forming a second mask layer on the top surface of the substrate, where the second mask layer exposes a second target area where the word lines are to be formed; Removing a partial structure of the fourth dielectric layer in the second target area to form a plurality of word line trenches arranged along the third direction. Each of the word line trenches extends along the second direction, and the word line trenches expose a partial top surface of the second dielectric layer and a partial side wall surface of the third dielectric layer; Forming multiple word lines in the multiple word line trenches.

[0020] In some possible embodiments, the manufacturing method further includes: Forming a plurality of storage capacitors, where the plurality of storage capacitors are respectively connected to second ends of the plurality of active pillars in one-to-one correspondence.

[0021] In the semiconductor structure provided by the present disclosure, at least a part of the contact surface of the contact area between the word line and the vertical channel of the active pillar is not parallel to the second direction, thereby forming a non-fully depleted channel, which is beneficial to solving the problem of unstable threshold voltage. In addition, when both the word line and the bit line partially surround the active pillar, the distance between adjacent word lines and adjacent bit lines can be increased, which is beneficial to reducing the coupling effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings incorporated into the specification and constituting a part of the specification illustrate embodiments of the present disclosure and, together with the description, are used to explain the principles of the embodiments of the present disclosure. In these drawings, like reference numerals are used to represent like elements. The following drawings are some embodiments of the present disclosure, not all embodiments. For those skilled in the art, other drawings can be obtained based on these drawings without creative efforts.

[0023] Figure 1 is a schematic diagram of a semiconductor structure shown according to an exemplary embodiment; Figure 2 is a top view of a semiconductor structure shown according to an exemplary embodiment; Figure 3 is a top view of a semiconductor structure shown according to an exemplary embodiment; Figure 4 is a top view of a semiconductor structure shown according to an exemplary embodiment; Figure 5 is a top view of a semiconductor structure shown according to an exemplary embodiment; Figure 6 is a top view of a semiconductor structure shown according to an exemplary embodiment; Figure 7 is a top view of a semiconductor structure shown according to an exemplary embodiment; Figure 8 is a flowchart of a method for fabricating a semiconductor structure shown according to an exemplary embodiment; Figure 9 is a schematic diagram of a substrate and a semiconductor structure formed with multiple active pillars shown according to an exemplary embodiment; Figure 10 is a schematic diagram of a semiconductor structure for forming a first mask layer shown according to an exemplary embodiment; Figure 11 is a schematic diagram of a semiconductor structure for forming a first mask layer shown according to an exemplary embodiment; Figure 12 is a schematic diagram of a semiconductor structure after removing a part of the first dielectric layer shown according to an exemplary embodiment; Figure 13 is a schematic diagram of a semiconductor structure after forming a protection layer shown according to an exemplary embodiment; Figure 14 is a schematic diagram of a semiconductor structure after removing a part of the first dielectric layer shown according to an exemplary embodiment; Figure 15 is a schematic diagram of a semiconductor structure after forming a recess shown according to an exemplary embodiment; Figure 16 is a schematic diagram of a semiconductor structure after forming multiple bit lines shown according to an exemplary embodiment; Figure 17 is a schematic diagram of a semiconductor structure after forming a second dielectric layer and a third dielectric layer shown according to an exemplary embodiment; Figure 18 is a schematic diagram of a semiconductor structure after forming a fourth dielectric layer shown according to an exemplary embodiment; Figure 19 is a schematic diagram of a semiconductor structure after forming a second mask layer shown according to an exemplary embodiment; Figure 20 is a schematic diagram of a semiconductor structure after forming word line trenches shown according to an exemplary embodiment; Figure 21Schematic diagram of a semiconductor structure after forming multiple word lines according to an exemplary embodiment; Figure 22 Schematic diagram of a semiconductor structure after forming multiple storage capacitors according to an exemplary embodiment; Figure 23 Top view of a semiconductor structure according to an exemplary embodiment.

[0024] Reference numerals: 10, substrate; 11, first dielectric layer; 12, isolation structure; 13, protective layer; 20, active pillar; 20a, depletion region; 20b, non - depletion region; 21, vertical channel; 22, first end; 221, recess; 30, bit line; 31, second groove; 40, word line; 41, first groove; 40’, word line trench; 50, storage capacitor; 60, second dielectric layer; 70, third dielectric layer; 80, fourth dielectric layer; 90, fifth dielectric layer; 100a, first mask layer; 100b, second mask layer. Detailed implementation manners

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present disclosure. It should be noted that, without conflict, the embodiments in the present disclosure and the features in the embodiments may be combined with each other arbitrarily.

[0026] To solve the problems existing in the related art, embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, and a plurality of active pillars, a plurality of word lines, and a plurality of bit lines located on the substrate. The plurality of active pillars are arranged in an array along a second direction and a third direction, the plurality of word lines are arranged in an array along the third direction, each word line extends along the second direction, the plurality of bit lines are arranged in an array along the second direction, and each bit line extends along the third direction. At least a partial contact surface of the contact area between the word line and the vertical channel of the active pillar is not parallel to the second direction, thereby forming a non - fully depleted channel, which is beneficial to solving the problem of unstable threshold voltage. In addition, when both the word line and the bit line partially surround the active pillar, the distance between adjacent word lines and adjacent bit lines can be increased, which is beneficial to reducing the coupling effect.

[0027] In exemplary embodiments of the present disclosure, as Figure 1 shown, this embodiment provides a semiconductor structure, which includes, but is not limited to, a dynamic random access memory (DRAM), a static random-access memory (SRAM), a non-volatile memory, etc.

[0028] As Figure 1 shown, the semiconductor structure includes a substrate 10, which serves as a support platform for the semiconductor structure to support other structures in the semiconductor structure. The material of the substrate 10 includes, but is not limited to, silicon (Si), and can also be any one of gallium nitride (GaN), gallium arsenide (GaAs), silicon carbide (SiC), and silicon-on-insulator (SOI), for example.

[0029] As Figure 1 shown, the semiconductor structure includes a plurality of discrete active columns 20. The adjacent active columns 20 can be separated by an isolation structure, so as to be arranged in an array above the substrate 10, which is beneficial to form a highly integrated transistor array. In some embodiments, referring to Figure 1 , the plurality of active columns 20 are arranged in an array along a second direction and a third direction. The second direction is parallel to the x direction shown in Figure 1 , and the third direction is parallel to the y direction shown in Figure 1 . There is a 90° angle between the second direction and the third direction, and the plurality of active columns 20 are arranged in a rectangular / square array. In other embodiments, the plurality of active columns 20 can also be arranged in other ways. For example, the angle between the second direction and the third direction is an acute angle, which will not be elaborated here. In this embodiment, a semiconductor structure with a 4F 2 structure is taken as an example for illustration. It can be understood that this does not limit the technical solution of the present disclosure. The semiconductor structure of the present disclosure can also be a 4.5F 2 , 6F 2 structure, or any one of 4.5F 2 to 6F 2 . Among them, the 4F 2 , 4.5F 2 , 6F 2 structures represent the minimum theoretical area occupied by a single memory cell (usually composed of a transistor and a capacitor, that is, a 1T1C cell) on the chip, where F represents the minimum feature size of the process node (such as the minimum line width or pitch of lithography).

[0030] Referring to Figure 1 and Figure 12 , each active column 20 is along a first direction ( Figure 1extends in the z - direction (as shown), the vertical channel 21 of the active pillar 20 (refer to Figure 21 ) is used to form the channel region of the vertical transistor, and the structures on both sides of the vertical channel 21 in the first direction in the active pillar 20 can be used to form the source region and the drain region of the vertical transistor. In the semiconductor structure provided in this embodiment, the semiconductor substrate can be etched, and the remaining semiconductor substrate forms the substrate 10 and a plurality of active pillars 20. Alternatively, the substrate 10 can be provided and a plurality of active pillars 20 can be formed on the substrate 10 through an epitaxial process. The shape of the active pillar 20 includes but is not limited to a cylinder (refer to Figure 7 ), a prism (refer to Figures 1 to 6 ).

[0031] As Figure 1 shown, the semiconductor structure includes a plurality of word lines 40, and the word lines 40 are in contact with the vertical channels 21 of the active pillars 20 (refer to Figure 21 ). The vertical channels 21 can be controlled through the word lines 40 to control the vertical transistor to turn on or off. Each word line 40 extends in the second direction (the x - direction as shown in Figure 1 ) to connect a plurality of active pillars 20 arranged in an array in the second direction. The plurality of word lines 40 are arranged in the third direction (the y - direction as shown in Figure 1 ), so that the plurality of word lines 40 are horizontally arranged in a parallel array on the same layer. Thus, the plurality of word lines 40 can form an orthogonal grid structure with the vertically arranged (in the z - direction as shown in Figure 1 ) active pillars 20, ensuring that each word line 40 cross - contacts the active pillar 20 at a specific node.

[0032] Refer to Figure 1 , at least a part of the contact surface of the contact area between the word line 40 and the vertical channel 21 of the active pillar 20 (refer to Figure 21 ) is not parallel to the second direction (the x - direction as shown in Figure 1 ). With such a setting, the word line 40 does not cover the entire outer peripheral surface of the vertical channel 21. Among them, the area where the vertical channel 21 is not in contact with the word line 40 will not be depleted by the electric field (see Figure 23 , a non - depleted region 20b is formed, also known as an electrically neutral region), and the area where the vertical channel 21 is in contact with the word line 40 can be completely depleted by the electric field (see Figure 23 , a depleted region 20a is formed), resulting in a non - fully depleted channel.

[0033] In one example, refer to Figure 23, an exemplary semiconductor structure with a non - fully depleted channel is shown. The active pillar 20 of this semiconductor structure includes a depletion region 20a and a non - depletion region 20b. Among them, the region of the active pillar 20 covered by the word line 40 and the region of the active pillar 20 covered by the bit line 30 together form the depletion region 20a. There is a partial region in the active pillar 20, that is, the non - depletion region 20b. This part of the region is neither covered by the word line 40 nor by the bit line 30. Carriers are retained in this non - depletion region 20b. The active pillar 20 can form a conductive path with the substrate 10 through the non - depletion region 20b. This conductivity helps to balance the potential of the substrate 10, avoid charge accumulation and potential drift caused by electrical floating, and further suppress the threshold voltage fluctuation or leakage current anomaly caused by the floating effect. In a transistor with a non - fully depleted channel, the carrier mobility is higher, and it has a higher saturation current under the same bias voltage compared with a fully depleted channel, which is beneficial for forming a high - speed circuit. The electrically neutral region in the non - fully depleted channel allows the threshold voltage to be adjusted through body - terminal biasing, which can be used to dynamically optimize power consumption and performance, improving the flexibility of threshold voltage control. Especially in a vertical - channel transistor, it can also reduce the influence of the floating body effect. The electrically neutral region in the non - fully depleted channel can serve as a collection area for radiation - induced charges, reducing the direct impact of charge accumulation on the channel and enhancing the reliability of the semiconductor structure in a radiation environment. The electrically neutral region can also provide an additional heat - conduction path, which is beneficial for improving the high - temperature stability of the semiconductor structure.

[0034] It should be noted that the shape of the non - depletion region 20b can be determined by simulation, and it changes with the shape of the active pillar 20 and the way the word line 40 and the bit line 30 cover the active pillar 20. In addition to the trapezoid - like shape shown in Figure 23 , the shape of the non - depletion region 20b can also be an arc or other shapes, which is not specifically limited in this disclosure.

[0035] In some embodiments, the cross - sectional shape of the active pillar 20 can be controlled so that at least part of the contact surface of the contact region between the word line 40 and the active pillar 20 is not parallel to the second direction. Exemplarily, the cross - sectional shape of the active pillar 20 is set to be a rhombus, a circle, an ellipse, a rectangle, a square, a pentagon, etc. When the cross - sectional shape of the active pillar 20 is a polygon, the polygon is an axisymmetric structure.

[0036] In some other embodiments, the formation region of the word line 40 can be defined to prevent the word line 40 from being formed on only one side of the active pillar 20, which may result in the contact surfaces between the word line 40 and the active pillar 20 being all parallel to the second direction. Exemplarily, the cross-sectional shape of the active pillar 20 is rectangular. A part of the structure of the word line 40 is formed on one side of the active pillar 20, and another part of the structure of the word line 40 is formed in contact with the active pillar 20 between two adjacent active pillars 20 along the second direction, thereby forming a contact surface that is not parallel to the second direction.

[0037] As Figure 1 shown, the semiconductor structure further includes a plurality of bit lines 30. The bit lines 30 are in contact with the first end portion 22 of the active pillar 20 (refer to Figure 16 ), and data signals can be transmitted to the storage capacitor 50 (detailed introduction later) connected to the second end of the active pillar 20 through the bit lines 30, and charge detection, writing, etc. can be achieved during read and write operations. Each bit line 30 extends along the third direction ( Figure 1 the y direction shown in Figure 1 ) to connect a plurality of active pillars 20 arranged in an array along the third direction. The plurality of bit lines 30 are arranged along the second direction ( Figure 1 the x direction shown in Figure 1 ), so that the plurality of bit lines 30 are horizontally arranged in a parallel array form on the same layer. Thus, the plurality of bit lines 30 can form an orthogonal grid structure with the vertically arranged active pillars 20 (extending along the Figure 1 z direction shown in Figure 21 ), ensuring that each bit line 30 cross-contacts the active pillar 20 at a specific node. For each active pillar 20, along the first direction, the bit lines 30 and the word lines 40 on the active pillar 20 are arranged at intervals. Exemplarily, an interlayer dielectric layer (such as Figure 21 the second dielectric layer 60 shown in

[0038] ) is arranged between the word line 40 and the bit line 30. The interlayer dielectric layer is used to electrically isolate the word line 40 from the bit line 30 to reduce the parasitic capacitance between the bit line 30 and the word line 40.

[0038] Refer to Figure 1 , at least part of the contact surface of the contact region between the bit line 30 and the first end portion 22 of the active pillar 20 (see Figure 21 ) is not parallel to the third direction (the extending direction of the bit line 30). The manner of making at least part of the contact surface in the contact region between the bit line 30 and the active pillar 20 not parallel to its extending direction is the same as the contact manner between the word line 40 and the active pillar 20 described above, and will not be elaborated here.

[0039] In some embodiments, referring to Figure 1 and Figure 21, the length of the word line 40 surrounding the circumferential direction of the vertical channel 21 of the active pillar 20 is greater than or equal to half of the circumference of the active pillar 20, and the length of the bit line 30 surrounding the circumferential direction of the first end portion 22 of the active pillar 20 is greater than or equal to half of the circumference of the first end portion 22 of the active pillar 20. Such a setting method can enable the word line 40 and the bit line 30 to form at least a semi-surrounding structure in the circumferential direction of the active pillar 20, thereby effectively improving the problem of unstable threshold voltage. In addition, when both the word line 40 and the bit line 30 partially surround the active pillar, the distance between adjacent word lines and the distance between adjacent bit lines can be increased, which is beneficial to reducing the coupling effect. Of course, it can be understood that in some cases, there may be a situation where the length of the bit line surrounding the circumferential direction of the active pillar is not equal to the length of the word line surrounding the circumferential direction of the active pillar. The surrounding length can be slightly less than half of the circumferential length of the active pillar, as long as the overall effect is not affected.

[0040] In the embodiments of the present disclosure, at least a part of the contact surface of the contact area between the word line and the vertical channel of the active pillar is not parallel to the second direction, thereby forming a non-fully depleted channel, which is beneficial to solving the problem of unstable threshold voltage. In addition, when both the word line and the bit line partially surround the active pillar, the distance between adjacent word lines and the distance between adjacent bit lines can be increased, which is beneficial to reducing the coupling effect.

[0041] In an exemplary embodiment, as Figure 1 shown, this embodiment provides a semiconductor structure, which includes a substrate 10, and a plurality of active pillars 20, a plurality of word lines 40, and a plurality of bit lines 30 located on the substrate 10. The plurality of active pillars 20 are arranged in an array in the second direction and the third direction. The plurality of word lines 40 are arranged in an array in the third direction. Each word line 40 extends in the second direction. The plurality of bit lines 30 are arranged in an array in the second direction. Each bit line 30 extends in the third direction. At least a part of the contact surface of the contact area between the word line 40 and the active pillar 20 is not parallel to the second direction, and at least a part of the contact surface of the contact area between the bit line 30 and the active pillar 20 is not parallel to the third direction.

[0042] Among them, as Figure 1 and Figure 2 shown, along the array direction of the plurality of word lines 40 (the third direction, Figure 1 the y direction shown in Figure 1 ), a plurality of first grooves 41 are provided on the same side of each word line 40. The plurality of first grooves 41 are spaced apart in the extending direction of the word line 40. Each first groove 41 corresponds to an active pillar 20 in contact with the word line 40. In this embodiment, in the third direction, the first grooves 41 on all the word lines 40 can be provided on the same side of the word line 40 (refer to

[0043] In some embodiments, as Figure 7 shown, the cross-section of the active column 20 is circular or elliptical, and the shape of the first groove 41 of the word line 40 is an arc groove. The arc curvature of the first groove 41 is the same as the curvature of the cross-section of the active column 20 (i.e., the plane perpendicular to the extending direction of the active column 20), so that the word line 40 fits with the active column 20 to form a contact connection. In this embodiment, the central angle of the arc is generally set to be greater than or equal to 180° and less than 360° (such as 180° - 270°), so that the word line 40 does not completely cover the outer peripheral surface of the vertical channel 21 of the active column 20 (see Figure 15 ), and at the same time has a sufficient contact area with the vertical channel 21 to ensure the channel control ability of the word line 40 for the vertical channel 21. In one example, referring to Figure 7 , the central angle of the arc of the arc groove is 180°, that is, the arc groove covers half of the outer peripheral surface of the vertical channel 21.

[0044] In other embodiments, as Figures 1 to 6 shown, the cross-section of the active column 20 is polygonal, and the shape of the first groove 41 of the word line 40 is an open polygonal groove. The projection of the polygonal groove on the substrate 10 includes at least two sequentially connected line segments. Some of the at least two line segments are parallel to the extending direction of the word line 40 where the polygonal groove is located, or all of the at least two line segments are not parallel to the extending direction of the word line 40 where the polygonal groove is located. Multiple line segments among the at least two line segments are connected end to end, but the whole is not closed, so that the word line 40 does not completely surround the outer peripheral surface of the vertical channel 21.

[0045] In one example, referring to Figure 1 and Figure 2 , the cross-section of the active column 20 is square (a special rectangle), and the projection of the polygonal groove on the substrate 10 includes three sequentially connected line segments. By adjusting the depth of the first groove 41 (the third direction, Figure 1 the y direction shown in Figure 21 ), the contact area between the word line 40 and the vertical channel 21 (see

[0046] In another example, referring to Figure 3 and Figure 4 , the cross-section of the active column 20 is rectangular, and the projection of the polygonal groove on the substrate 10 includes three sequentially connected line segments (in a U shape). By adjusting the depth of the first groove 41 (the third direction, Figure 3 the y direction shown in Figure 3, when the long side direction of the rectangle is parallel to the third direction (or has a small included angle), the depth of the first groove 41 can be set to be less than or equal to half of the length of the long side of the rectangle, so as to reduce the width of the word line 40, thereby reducing the overlapping area between the word line 40 and the bit line 30, and further reducing the parasitic capacitance between the bit line 30 and the word line 40. For another example, refer to Figure 4 , when the long side direction of the rectangle is parallel to the second direction (or has a small included angle), the depth of the second groove 31 (detailed introduction later) in the bit line 30 can be set to be less than or equal to half of the length of the long side of the rectangle.

[0047] In yet another example, refer to Figure 5 , the cross-section of the active column 20 is a rhombus, and the projection of the polygonal groove on the substrate 10 includes two line segments connected in sequence. In this example, in the opening direction of the first groove 41 (the third direction, Figure 5 the reverse of the y direction shown in), the depth of the first groove 41 is less than or equal to half of the size of the rhombus, so that the contact area between the word line 40 and the vertical channel 21 is less than or equal to half of the outer peripheral surface of the vertical channel 21 (refer to Figure 21 ).

[0048] In yet another example (not shown in the drawings), the cross-section of the active column is a rhombus, and the projection of the polygonal groove on the substrate includes four line segments connected in sequence. In this example, along the opening direction of the first groove (the third direction, Figure 1 the reverse of the y direction shown in), the depth of the first groove is greater than the size of the vertical channel, so that the contact area between the word line and the vertical channel is greater than half of the outer peripheral surface of the vertical channel. It should be noted that the covering area of the word line can be adaptively set according to factors such as the doping degree and the size of the active column to ensure that the word line has sufficient channel control ability.

[0049] In yet another example, refer to Figure 6 , the cross-section of the active column 20 is a hexagon, and the projection of the polygon on the substrate 10 includes four line segments connected in sequence. Based on the previous several examples, this example can be understood and will not be elaborated here.

[0050] In this embodiment, by setting the first groove 41 corresponding to the active column 20 on one side of the word line 40 in the third direction, the circumferential direction of the vertical channel 21 of the active column 20 is not completely surrounded by the word line 40, thereby forming a non-fully depleted channel. The non-fully depleted channel is beneficial to optimizing the electric field distribution, reducing the short-channel effect, and solving the problem of unstable threshold voltage (Threshold Voltage, abbreviated as VT) in the related art. Moreover, compared with the fully surrounded (channel region) type word line in the related art, the bit line 30 that only covers a part of the outer peripheral surface of the active column 20 in this embodiment is narrower ( Figure 1In the y - direction shown in [reference], it is possible to reduce the overlapping area between the word line 40 and the bit line 30. Based on the fact that the parasitic capacitance is proportional to the overlapping area of the parallel segments between conductors, it can be determined that the parasitic capacitance generated between the word line 40 and the bit line 30 in the semiconductor structure provided in this embodiment is smaller, thereby being able to reduce signal delay, power consumption, and improve the reliability and signal integrity of the semiconductor structure.

[0051] Among them, as Figure 1 , Figure 2 and Figure 6 shown, along the array direction of the plurality of bit lines 30 (the second direction, Figure 2 the x - direction shown in [reference]), on the first side of each bit line 30, a plurality of second grooves 31 are provided. The plurality of second grooves 31 are spaced along the third direction ( Figure 2 the y - direction shown in [reference]), and each second groove 31 corresponds to an active pillar 20 in contact with the bit line 30. In this embodiment, all the second grooves 31 can be provided on the same side of the bit line 30 in the second direction (refer to Figure 2 ), or can be provided on different sides (not shown in the drawings). When provided on different sides, the opening directions of the second grooves 31 of adjacent two bit lines 30 are opposite or back - to - back.

[0052] In some embodiments, the shape of the second groove 31 includes any one of an arc - shaped groove or a polygonal groove. The second groove 31 has the same setting method and principle as the first groove 41, and will not be elaborated here. Among them, when the cross - sectional shape of the active pillar 20 is set to have different sizes in the second direction and the third direction (such as being set to a rectangle or an ellipse), it is possible to make the bit line 30 have a larger contact area with the active pillar 20, reduce the contact resistance, and also be able to increase the distance between adjacent bit lines 30 and reduce the signal coupling generated between adjacent bit lines 30.

[0053] In this embodiment, by providing a second groove corresponding to the active pillar on one side of the bit line in the second direction, the circumferential direction of the first end portion (such as the source region) of the active pillar is not completely surrounded by the bit line, thereby reducing the contact resistance value between the bit line and the active pillar, reducing signal delay and power consumption, and improving the reliability and signal integrity of the semiconductor structure. And, setting like this can also reduce the size of the bit line in the second direction (the same principle as the word line becoming narrower, not elaborated again), so as to reduce the parasitic capacitance between the word line and the bit line.

[0054] Among them, as Figure 15 and Figure 16As shown, a partial area of the first end 22 of the active column 20 is recessed to form a recess 221, and a partial structure of the bit line 30 can extend into the recess 221 to form a contact connection with the first end 22 of the active column 20. In some embodiments, the first end 22 of the active column 20 can be wet-etched to remove a partial structure, so as to form a recess 221 on the surface of the first end 22. In some embodiments, the bit line 30 is provided with a second groove 31, and the inner surface of the second groove 31 is in contact connection with the recess 221.

[0055] Referring to Figure 15 and Figure 16 , it can be determined that extending a partial structure of the bit line 30 into the recess 221 can enable a partial top surface and a partial bottom surface of the bit line 30 to contact the active column 20, increasing the contact area between the bit line 30 and the active column 20, capable of reducing the contact resistance between the bit line 30 and the active column 20, and moreover, the bottom wall and the top wall of the recess 221 of the active column 20 can also provide support and limitation for the bit line 30, improving the connection reliability between the active column 20 and the bit line 30, and reducing the risk of contact failure of the bit line 30 caused by thermal stress or mechanical vibration, etc.

[0056] In an exemplary embodiment, as Figure 1 shown, this embodiment provides a semiconductor structure, which includes a substrate 10, and a plurality of active columns 20, a plurality of word lines 40, and a plurality of bit lines 30 located on the substrate 10. The plurality of active columns 20 are arranged in an array along a second direction and a third direction, the plurality of word lines 40 are arranged in an array along the third direction, each word line 40 extends along the second direction, the plurality of bit lines 30 are arranged in an array along the second direction, each bit line 30 extends along the third direction, at least part of the contact surface of the contact area between the word line 40 and the active column 20 is not parallel to the second direction, and at least part of the contact surface of the contact area between the bit line 30 and the active column 20 is not parallel to the third direction.

[0057] In this embodiment, referring to Figure 1 and Figure 2 , each of the word lines 40 is provided with a plurality of first grooves 41 along the second direction, each of the first grooves 41 corresponds to an active column 20, and the inner wall surface of the first groove 41 of the vertical channel 21 (referring to Figure 15 ) of the active column 20 is in contact connection.

[0058] In some embodiments (not shown in the drawings), the bit line connected to the active pillar wraps the surface of the first end portion of the active pillar in the entire circumferential direction. The bit line surrounding the entire outer peripheral surface of the source / drain region of the active pillar is a mature technology and will not be described in detail. In the semiconductor structure provided in this embodiment, when the bit line is arranged to completely surround the first end portion 22 of the active pillar 20, for example, a whole circle of recesses 221 can be provided at the first end portion 22 of the active pillar 20 to increase the contact area between the bit line 30 and the active pillar 20, thereby reducing the contact resistance.

[0059] Among them, as Figure 22 shown, the semiconductor structure further includes a plurality of storage capacitors 50. The plurality of storage capacitors 50 correspond one by one to the second end portions of the plurality of active pillars 20. By selecting the word line 40 (refer to Figure 1 ) and the bit line 30 (refer to Figure 1 ), the active pillar 20 located at the cross position of the selected word line 40 and bit line 30 can be controlled, and thus data can be read and written to the storage capacitor 50 connected to the active pillar 20. The storage capacitor 50 provided in this embodiment can be, for example, a common electrode plate capacitor in the related art, and its structure will not be further limited.

[0060] According to an exemplary embodiment of the present disclosure, as Figure 8 shown, this embodiment provides a manufacturing method of a semiconductor structure. The manufacturing method includes the following steps: Step S110: Provide a substrate, and form a plurality of active pillars on the substrate. Each active pillar extends along a first direction, and the plurality of active pillars are arranged in an array along a second direction and a third direction. The active pillar includes a vertical channel. There is a preset included angle between the second direction and the third direction, and both are perpendicular to the first direction.

[0061] In some embodiments, a semiconductor substrate can be provided, and part of the structure of the bulk substrate is removed by etching to obtain the substrate 10 and a plurality of active pillars 20 located on the substrate 10. Different regions of the semiconductor substrate can be doped with N-type impurity ions or P-type impurity ions according to the type of vertical transistor to be formed later. The P-type impurity ions include one or more of boron ions, gallium ions, or indium ions, and the N-type ions include one or more of phosphorus ions and arsenic ions.

[0062] In some other embodiments, the substrate 10 can be provided, and then an epitaxial growth process is used to form a plurality of active pillars 20 on the top surface of the substrate 10. Different regions of the active pillar 20 can be doped with N-type impurity ions or P-type impurity ions according to the type of vertical transistor to be formed later.

[0063] In some optional implementation manners, refer to Figure 9 , a plurality of isolation structures 12 are further formed on the substrate 10. The plurality of isolation structures 12 are arranged along the second direction (Figure 1 The median lines 30 are arranged at intervals in the arrangement direction), and each isolation structure 12 extends along the third direction ( Figure 1 the extending direction of the median line 30). The isolation structure 12 can isolate the signal crosstalk between two adjacent bit lines 30 and play the same role as the protective layer 13 (detailed introduction later) in some process steps (such as steps S330 and S340). The material of the isolation structure 12 includes but is not limited to silicon nitride and low-k dielectric materials.

[0064] Step S120: Form multiple bit lines. The multiple bit lines are arranged in an array in the second direction, each bit line extends along the third direction, each bit line is connected to multiple active columns arranged in an array along the third direction, and at least part of the contact surface of the contact area between the bit line and the first end of the active column is not parallel to the third direction.

[0065] In this step, referring to Figure 16 , a conductive material can be deposited in the bit line trench by a deposition process, and the conductive material is etched back to retain the conductive material to form the bit line 30. The conductive material is, for example, a metal such as aluminum, copper, or tungsten. The relationship between the contact surface of the contact area between the bit line 30 and the active column 20 and the third direction is affected by the shape of the active column 20 and the shape of the bit line 30.

[0066] Step S130: Form multiple word lines. For each active column, the bit line and the word line on the active column are arranged at intervals along the first direction. The multiple word lines are arranged in an array in the third direction, each word line extends along the second direction, and each word line is connected to multiple active columns arranged in an array along the second direction. At least part of the contact surface of the contact area between the word line and the vertical channel of the active column is not parallel to the second direction.

[0067] In this step, referring to Figure 20 and Figure 21 , a conductive material can be deposited in multiple word line trenches 40' by a deposition process, and the conductive material is etched back so that the top surface height of the conductive material is flush with the top surface of the vertical channel 21. The retained conductive material forms multiple word lines 40. The material of the word line 40 can be the same as or different from the material of the bit line 30, and there is no excessive limitation.

[0068] In the embodiment of the present disclosure, the word line is set such that at least part of the contact surface of the contact area with the active column is not parallel to the extending direction of the word line, so that the word line does not cover the entire outer peripheral surface of the vertical channel. Among them, the area where the vertical channel is not in contact with the word line will not be depleted by the electric field (forming an electrically neutral region), and the area where the vertical channel is in contact with the word line forms a non-fully depleted channel, which is beneficial to solving the problem of unstable threshold voltage. When both the word line and the bit line are in contact with part of the outer peripheral surface of the active column, the distance between adjacent word lines and adjacent bit lines can be increased, which is beneficial to reducing the coupling effect.

[0069] In an exemplary embodiment, this embodiment defines the formation of bit line 30 in the foregoing embodiment. As Figures 9 to 15 shown, a first dielectric layer 11 is filled between adjacent active pillars 20 on the substrate 10, and the first dielectric layer 11 covers the side wall surfaces of the active pillars 20. The manufacturing method of the semiconductor structure includes the following steps: Step S210: Provide a substrate, and form a plurality of active pillars on the substrate. Each active pillar extends along a first direction, and the plurality of active pillars are arranged in an array along a second direction and a third direction. The active pillars include vertical channels.

[0070] This step is the same as the implementation manner and principle of step S110 in the foregoing embodiment, and will not be described in detail.

[0071] Step S220: Form a first mask layer on the top surface of the substrate, and the first mask layer exposes a first target area where the bit line is to be formed.

[0072] In this step, referring to Figure 10 and Figure 11 , a mask material can be deposited on the top surface of the substrate 10 by a deposition process, and a photoresist layer is coated on the mask material. Then, the photoresist layer is exposed and developed to pattern the photoresist layer. Then, an etching process (such as reactive ion etching) is used to transfer the pattern in the photoresist layer to the mask material to obtain the first mask layer 100a.

[0073] The patterned first mask layer 100a can control the passing path of the etching medium, so that the etching medium only etches the material layer exposed in the first target area, which is convenient for forming the bit line 30 only in the first target area in the subsequent steps.

[0074] Step S230: Remove the first dielectric layer at a first depth along the first direction in the first target area, exposing the outer surface of the first part of the active pillar. The first dielectric layer retained in the first target area defines the bottom position of the bit line.

[0075] In this step, referring to Figures 10 to 15 , using the first mask layer 100a as a mask, an etching process is used to remove a partial structure of the material layer (the first dielectric layer 11) in the substrate 10 that is not covered by the first mask layer 100a. The first dielectric layer 11 retained in the first target area defines the bottom height of the bit line 30. By controlling the etching time, it is possible to etch and remove only the first dielectric layer 11 at the first depth, thereby exposing the outer surface of the first part of the active pillar 20.

[0076] Combined with FIG. Figure 1 and Figure 2, the projected pattern of the first target area on the substrate 10 is in the shape of a toothed strip, the strip part of the toothed strip corresponds to the area forming the main body of the bit line, and the tooth part of the toothed strip extends between adjacent active pillars 20, and the area between two adjacent tooth parts corresponds to the second groove 31 of the bit line 30.

[0077] Step S240, form a plurality of bit lines, the bit lines cover the outer surface of the second part of the exposed active pillar in the first target area, and the second part is a part of the first part.

[0078] In this step, referring to Figure 16 and Figure 14 , a conductive material can be deposited in the first target area by a deposition process, and the conductive material can be etched back to adjust the height of the conductive material to obtain the bit line 30. In some embodiments, referring to Figure 16 , when etching back the conductive material to form the bit line 30, the part of the protective layer 13 (introduced later), the first dielectric layer 11 and the isolation structure 12 that is higher than the bit line 30 will also be etched back and removed.

[0079] Referring to Figure 15 and Figure 16 , it can be understood that since part of the first target area is located between two adjacent active pillars 20, a part of the structure of the bit line 30 formed in step S240 extends between the adjacent active pillars 20, so that a second groove 31 is formed at the position of the bit line 30 corresponding to the active pillar 20.

[0080] Step S250, form a plurality of word lines. For each active pillar 20, along the first direction, the bit lines and the word lines on the active pillar 20 are arranged at intervals, the plurality of word lines are arranged in an array in the third direction, each word line extends along the second direction, and each word line connects a plurality of active pillars 20 arranged in an array along the second direction. At least part of the contact surface of the contact area between the word line and the vertical channel 21 of the active pillar 20 is not parallel to the second direction.

[0081] This step is the same as the implementation method and principle of step S130 in the foregoing example, and will not be described in detail.

[0082] In addition to the above steps, in some optional embodiments, the method of forming the bit line further includes: the topography and position of the mask layer can be adjusted to remove the first dielectric layer covered by the first mask layer to a first depth, and then a conductive material can be filled above the remaining first dielectric layer, and the conductive material can be patterned and etched back to obtain a plurality of bit lines corresponding to the first target area.

[0083] In an exemplary embodiment, before forming the bit line 30, the manufacturing method of the semiconductor structure further includes the following steps: Step S310: Remove the first dielectric layer with a second depth along the first direction in the first target area, exposing the outer surface of the third part of the active column, where the second depth is less than the first depth.

[0084] In this step, referring to Figures 10 to 12 (where Figure 11 is Figure 9 the view obtained by viewing in the reverse direction of the y direction in ), a first mask layer 100a can be formed on the top surface of the substrate 10. The area of the first dielectric layer 11 not covered by the first mask layer 100a is the first target area.

[0085] The first dielectric layer 11 in the first target area not covered by the first mask layer 100a can be removed by an etching process. By controlling the etching duration, only the first dielectric layer 11 with the second depth can be etched away to expose the outer surface of the third part of the active column 20.

[0086] Step S320: Form a protective layer on the sidewall of the third part of the active column.

[0087] In this step, referring to Figure 13 , processes such as deposition and epitaxial growth can be used to form a protective layer 13 on the exposed sidewall surface (i.e., the third part) of the active column 20. The material of the protective layer 13 has high etching resistance, and the material of the protective layer 13 includes nitrides, such as silicon nitride (Si3N4).

[0088] Step S330: Remove the first dielectric layer between the first depth and the second depth, and define a first area along the first direction.

[0089] In this step, referring to Figure 14 , the first dielectric layer 11 between the first depth and the second depth can be removed by using the processes described in Step S220 and Step S230 to expose a part of the outer peripheral surface (i.e., the first area) of the first end 22 of the active column 20.

[0090] Step S340: Remove a part of the structure of the active column in the first area to form a recess.

[0091] In this step, referring to Figure 15 , and combining Figure 13 and Figure 14 , it can be determined that since the second depth is less than the first depth, the protective layer 13 formed in Step S320 does not cover the first area of the active column 20. Furthermore, processes such as wet cleaning and etching can be used to process the first area of the active column 20 to remove a part of the structure of the first area of the active column 20, thereby forming a recess 221 on the outer peripheral surface of the active column 20.

[0092] In this embodiment, a protective layer covering only a part of the surface of the active pillar is formed by segmented etching of the first dielectric layer. The protective layer can protect the active pillar, and the surface of the active pillar not covered by the protective layer is convenient to be removed to form a recess. By forming the recess, not only the contact area between the active pillar and the bit line is increased, the contact resistance is reduced, but also the active pillar provides a limiting support for the bit line, enhancing the connection reliability between the active pillar and the bit line.

[0093] In an exemplary embodiment, this embodiment defines the formation of the word line 40 in the foregoing embodiment, and the manufacturing method includes the following steps: Step S410: Provide a substrate, and form a plurality of active pillars on the substrate. Each active pillar extends along a first direction, and the plurality of active pillars are arranged in an array along a second direction and a third direction. The active pillar includes a vertical channel. A preset angle is provided between the second direction and the third direction, and both are perpendicular to the first direction.

[0094] The implementation manner and principle of this step are the same as those of step S110 in the foregoing embodiment, and will not be described in detail.

[0095] Step S420: Form a plurality of bit lines. The plurality of bit lines are arranged in an array in the second direction. Each bit line extends along the third direction. Each bit line is connected to a plurality of active pillars arranged in an array along the third direction. At least a part of the contact surface of the contact area between the bit line and the first end of the active pillar is not parallel to the third direction.

[0096] The implementation manner and principle of this step are the same as those of step S120 in the foregoing embodiment, and will not be described in detail.

[0097] Step S430: Form a second dielectric layer above the plurality of bit lines. The second dielectric layer covers the top surface of the bit lines and fills the gap between the bottoms of the vertical channels of adjacent active pillars.

[0098] In this step, refer to Figure 17 A second dielectric layer 60 can be formed above the bit line 30 by a deposition process. The second dielectric layer 60 serves as an interlayer dielectric layer, and has the functions of providing a flat process support surface for the word line 40 and electrically isolating the bit line 30 and the word line 40. The material of the second dielectric layer 60 includes, but is not limited to, any one of silicon oxide, silicon nitride, silicon oxynitride, and low-k dielectric materials to form a single-layer structure, or a stacked structure composed of two or more of the above materials. In one example, the second dielectric layer can be a stacked structure composed of silicon oxide and silicon nitride materials. In another example, refer to Figure 17 , the material of the second dielectric layer 60 is the same as that of the first dielectric layer 11.

[0099] Step S440: Form a third dielectric layer above the second dielectric layer. The third dielectric layer covers the surface of the vertical channels of the active pillars.

[0100] In this step, referring to Figure 17 , a third dielectric layer 70 may be formed on the second dielectric layer 60 by a deposition process, and the third dielectric layer 70 covers the surface of the vertical channel 21 of the active pillar 20. The third dielectric layer 70 is used to form a gate dielectric layer (also known as a gate oxide layer), and the material of the gate dielectric layer includes but is not limited to silicon dioxide and high-k dielectric materials (such as hafnium oxide).

[0101] Step S450: Form a plurality of word lines. Each word line is connected to a plurality of active pillars arranged along the second direction. At least a part of the contact surface of the contact area between the word line and the third dielectric layer is not parallel to the second direction. The plurality of word lines are disposed between adjacent active pillars arranged in an array along the third direction.

[0102] In this step, referring to Figure 21 , a word line 40 may be formed on the side of the third dielectric layer 70 facing away from the active pillar 20 by a deposition process. The material of the word line 40 includes but is not limited to at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, nickel silicide, cobalt silicide, tantalum, aluminum, lanthanum, titanium, or tungsten.

[0103] In some embodiments, this embodiment further illustrates the formation of the word line 40 in the foregoing embodiments. After forming the third dielectric layer 70 above the second dielectric layer 60, the manufacturing method further includes: Step S510: Form a fourth dielectric layer above the second dielectric layer. The fourth dielectric layer covers the exposed surfaces of the second dielectric layer and the third dielectric layer.

[0104] In this step, referring to Figure 18 , a fourth dielectric layer 80 may be formed above the second dielectric layer 60 by a deposition process. The fourth dielectric layer 80 covers the exposed surfaces of the second dielectric layer 60 and the third dielectric layer 70. A part of the structure of the fourth dielectric layer 80 will be removed in subsequent steps to define the formation position and morphology of the word line 40. The material of the fourth dielectric layer 80 includes but is not limited to silicon dioxide and silicon nitride.

[0105] Step S520: Form a second mask layer on the top surface of the substrate. The second mask layer exposes a second target area where the word line is to be formed.

[0106] In this step, referring to Figure 19 , a second mask layer 100b may be formed on the top surface of the substrate 10. The second mask layer 100b exposes the second target area where the word line 40 is to be formed. The second mask layer 100b can provide protection to the structures covered by it, so that the fourth dielectric layer 80 not covered by it can be removed. The formation principle of the second mask layer 100b is the same as that of the first mask layer 100a in the foregoing embodiments, and will not be elaborated here.

[0107] Step S530: Remove partial structures of the fourth dielectric layer in the target area to form a plurality of word line trenches arranged in the third direction. Each word line trench extends in the second direction, exposing a partial top surface of the second dielectric layer and a partial side wall surface of the third dielectric layer.

[0108] In this step, refer to Figure 20 , and in combination with Figure 19 , use the second mask layer 100b as a mask, use the second dielectric layer 60 as an etch stop layer, and adopt an etching process to remove the structures of the fourth dielectric layer 80 located in the second target area, so as to form a plurality of word line trenches 40' arranged in the third direction in the substrate 10. The word line trenches 40' expose a partial top surface of the second dielectric layer 60, so that the top surface of the second dielectric layer 60 can define the bottom height of the word line 40. The word line trenches 40' also expose a partial side wall surface of the third dielectric layer 70 (gate oxide layer).

[0109] Step S540: Form a plurality of word lines in the plurality of word line trenches.

[0110] In this step, refer to Figure 20 and Figure 21 , a deposition process can be used to fill the word line trenches 40' with a conductive material, and the conductive material is etched back to adjust the top surface height of the conductive material to obtain the word line 40.

[0111] In some alternative embodiments, after step S440, the word line 40 can be formed in the following manner: form a conductive material on the top surface of the second dielectric layer 60, remove a part of the conductive material, retain the conductive material located in the second target area, and perform an etch back on the retained conductive material to form the word line.

[0112] In some embodiments, refer to Figure 22 , after forming the word line 40, the manufacturing method of the semiconductor structure further includes: forming a fifth dielectric layer 90, and the fifth dielectric layer 90 covers the word line 40 and the exposed top surface of the fourth dielectric layer 80.

[0113] After forming the fifth dielectric layer 90 (also known as the passivation layer), chemical mechanical polishing can be performed on the top surface of the fifth dielectric layer 90 to provide a flat process surface, which is convenient for forming the storage capacitor 50 on the top surface of the substrate 10 in subsequent steps. The material of the fifth dielectric layer 90 includes but is not limited to silicon dioxide, silicon nitride, and aluminum oxide, etc.

[0114] In some embodiments, after forming a plurality of word lines, the manufacturing method of the semiconductor structure further includes: forming a plurality of storage capacitors 50, and the plurality of storage capacitors 50 are connected to the second ends of the plurality of active pillars 20 in a one-to-one correspondence.

[0115] Forming the storage capacitor 50 is a mature technology, and this embodiment does not limit it too much.

[0116] In this specification, the embodiments or implementation manners are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0117] In the description of this specification, the descriptions with reference to terms such as "embodiment", "exemplary embodiment", "some implementation manners", "schematic implementation manners", "example", etc. mean that the specific features, structures, materials or characteristics described in connection with the implementation manner or example are included in at least one implementation manner or example of the present disclosure.

[0118] In this specification, the schematic expressions of the above terms do not necessarily refer to the same implementation manner or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more implementation manners or examples.

[0119] In the description of the present disclosure, it should be noted that the orientation or positional relationship indicated by terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to the present disclosure.

[0120] It can be understood that the terms "first", "second", etc. used in the present disclosure can be used in the present disclosure to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish the first structure from another structure.

[0121] In one or more drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the multiple parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the structure obtained after several steps can be described in one drawing. Many specific details of the present disclosure are described below, such as the structure, material, size, processing technology and technique of the device, in order to understand the present disclosure more clearly. But as those skilled in the art can understand, the present disclosure can be implemented without these specific details.

[0122] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate; A plurality of active pillars disposed on the substrate, each active pillar extending along a first direction, the plurality of active pillars being arranged in an array in a second direction and a third direction, the active pillar including a vertical channel, a preset angle being provided between the second direction and the third direction, and both being perpendicular to the first direction; A plurality of word lines arranged in an array in the third direction, each word line extending along the second direction, each word line connecting a plurality of the active pillars arranged in an array along the second direction, at least a partial contact surface of a contact area between the word line and the vertical channel of the active pillar being non-parallel to the second direction; A plurality of bit lines arranged in an array in the second direction, each bit line extending along the third direction, each bit line connecting a plurality of the active pillars arranged in an array along the third direction, at least a partial contact surface of a contact area between the bit line and a first end portion of the active pillar being non-parallel to the third direction; For each of the active pillars, along the first direction, the bit line and the word line on the active pillar are arranged at intervals.

2. The semiconductor structure according to claim 1, wherein A non-completely depleted channel is formed in a contact area between the vertical channel of the active pillar and the word line.

3. The semiconductor structure according to claim 1, characterized in that, Each word line is provided with a plurality of first grooves along the second direction, each first groove corresponding to one of the active pillars, and an outer surface of the vertical channel being in contact connection with an inner wall surface of the first groove.

4. The semiconductor structure according to claim 3, wherein Each bit line is provided with a plurality of second grooves along the third direction, each second groove corresponding to one of the active pillars, and an outer surface of the first end portion of the active pillar being in contact connection with an inner wall surface of the second groove.

5. The semiconductor structure according to claim 4, wherein A recessed portion is formed by recessing a partial area of the first end portion of the active pillar, and an inner surface of the second groove is in contact connection with the recessed portion.

6. The semiconductor structure according to claim 4, wherein, The shape of any one of the first groove and the second groove includes an arc groove and a polygon groove.

7. The semiconductor structure according to claim 6, wherein A projection of the polygon groove on the substrate includes at least two line segments connected in sequence; Some of the at least two line segments are parallel to an extending direction of the word line or the bit line where the polygon groove is located, or all of the at least two line segments are non-parallel to the extending direction of the word line or the bit line where the polygon groove is located.

8. The semiconductor structure according to claim 7, wherein A projection pattern of the active pillar on the substrate includes a square, the polygon groove includes a first segment, a second segment, and a third segment connected in sequence, the first segment and the third segment are respectively perpendicular to the second segment, and the second segment is parallel to the extending direction of the word line or the bit line where the polygon groove is located.

9. The semiconductor structure according to claim 3, characterized in that, For each of the active pillars, the bit line connected to the active pillar covers an outer surface of the entire circumferential direction of the first end portion.

10. The semiconductor structure according to any one of claims 1-9, characterized in that, The semiconductor structure further includes a plurality of storage capacitors, and the plurality of storage capacitors are connected to second end portions of the plurality of active pillars in a one-to-one correspondence.

11. A method for fabricating a semiconductor structure, characterized in that, Comprising: Provide a substrate, on which a plurality of active columns are formed. Each active column extends in a first direction, and the plurality of active columns are arranged in an array in a second direction and a third direction. The active column includes a vertical channel. A preset angle is provided between the second direction and the third direction, and both are perpendicular to the first direction; Form a plurality of bit lines. The plurality of bit lines are arranged in an array in the second direction. Each bit line extends in the third direction. Each bit line is connected to a plurality of the active columns arranged in an array in the third direction. At least a part of the contact surface of the contact area between the bit line and the first end of the active column is not parallel to the third direction; Form a plurality of word lines. For each active column, along the first direction, the bit lines and the word lines on the active column are arranged at intervals. The plurality of word lines are arranged in an array in the third direction. Each word line extends in the second direction. Each word line is connected to a plurality of the active columns arranged in an array in the second direction. At least a part of the contact surface of the contact area between the word line and the vertical channel of the active column is not parallel to the second direction.

12. The manufacturing method of the semiconductor structure according to claim 11, wherein The forming of the plurality of word lines includes: For each active column, a non-fully depleted channel is formed in the contact area between the vertical channel of the active column and the word line.

13. The manufacturing method of the semiconductor structure according to claim 11, wherein The forming of the plurality of bit lines includes: Form a first mask layer on the top surface of the substrate. The first mask layer exposes a first target area where the bit lines are to be formed. Among them, a first dielectric layer is filled between adjacent active columns in the substrate; Remove the first dielectric layer at a first depth along the first direction in the first target area, exposing the outer surface of the first part of the active column. The remaining first dielectric layer in the first target area defines the bottom position of the bit line; Form a plurality of the bit lines, and the bit lines cover the outer surface of the second part of the active column exposed in the first target area. The second part is a part of the first part.

14. The manufacturing method of the semiconductor structure according to claim 13, characterized in that, The method for manufacturing the semiconductor structure further includes: Remove the first dielectric layer at a second depth along the first direction in the first target area, exposing the outer surface of the third part of the active column. The second depth is less than the first depth; Form a protective layer on the sidewall of the third part of the active column; Remove the first dielectric layer between the first depth and the second depth, defining a first area along the first direction; Remove a part of the structure of the active column in the first area to form a recess.

15. The method for manufacturing a semiconductor structure according to claim 13, wherein, The forming of the word line includes: Form a second dielectric layer above the plurality of bit lines. The second dielectric layer covers the top surface of the bit lines and fills the gap between the bottoms of the vertical channels of adjacent active columns; Form a third dielectric layer above the second dielectric layer. The third dielectric layer covers the surface of the vertical channel of the active column; Form a plurality of word lines, each of the word lines connecting a plurality of the active pillars arranged along the second direction, at least a partial contact surface of the contact area between the word line and the third dielectric layer being non-parallel to the second direction, and the plurality of word lines being disposed between adjacent ones of the active pillars arranged in an array along the third direction.

16. The method for manufacturing a semiconductor structure according to claim 15, wherein After forming the third dielectric layer above the second dielectric layer, the manufacturing method further includes: Form a fourth dielectric layer above the second dielectric layer, the fourth dielectric layer covering the exposed surfaces of the second dielectric layer and the third dielectric layer; Form a second mask layer on the top surface of the substrate, the second mask layer exposing a second target area where the word lines are to be formed; Remove partial structures of the fourth dielectric layer in the second target area to form a plurality of word line trenches arranged along the third direction, each of the word line trenches extending along the second direction, the word line trenches exposing a partial top surface of the second dielectric layer and exposing a partial side wall surface of the third dielectric layer; Form a plurality of word lines in the plurality of word line trenches.

17. The method for manufacturing a semiconductor structure according to claim 11, wherein The manufacturing method further includes: Form a plurality of storage capacitors, the plurality of storage capacitors being connected to second ends of the plurality of active pillars in a one-to-one correspondence.

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