Semiconductor structure and manufacturing method thereof

Abstract

The present disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a substrate, and active pillars, word lines, and bit lines located on the substrate. A plurality of active pillars are arranged in an array along a second direction and a third direction, a plurality of word lines are arranged in an array along the third direction, each word line extending along the second direction, and a plurality of bit lines are arranged in an array along the second direction, each bit line extending along the third direction. At least a portion of the contact surface of the contact area between the word line and the vertical channel of the active pillar is not parallel to the second direction, thereby forming a non-completely depleted channel, which is beneficial for solving the problem of unstable threshold voltage. In addition, when both the word line and the bit line partially surround the active pillar, the distance between adjacent word lines and adjacent bit lines can be increased, which is beneficial for reducing the coupling effect.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] As the feature size of semiconductor devices continues to shrink (e.g., below 10nm), the density and integration of memory arrays have significantly increased, but the resulting signal interference problems affect the reliability of semiconductor structures. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] In a first aspect of the present disclosure, a semiconductor structure is provided, comprising:

[0005] substrate;

[0006] A plurality of active pillars are disposed on the substrate, each of the active pillars extending along a first direction, and the plurality of active pillars are arranged in an array along a second direction and a third direction, the active pillars including vertical channels, and the second direction and the third direction have a preset angle therebetween and are both perpendicular to the first direction;

[0007] a plurality of word lines arranged in an array in the third direction, each word line extending along the second direction, each word line connecting a plurality of active pillars arranged in an array along the second direction, and at least a portion of a contact surface between the word line and a vertical channel of the active pillar being non-parallel to the second direction;

[0008] a plurality of bit lines arranged in an array along the second direction, each of the bit lines extending along the third direction, each of the bit lines connecting the plurality of active pillars arranged in an array along the third direction, and at least a portion of a contact surface between the bit lines and the first end portions of the active pillars being non-parallel to the third direction;

[0009] For each of the active pillars, along the first direction, the bit line and the word line on the active pillar are spaced apart.

[0010] In some possible embodiments, the vertical channel of the active pillar and the contact region of the word line form a non-completely depleted channel.

[0011] In some possible embodiments, each word line is provided with a plurality of first grooves along the second direction, each first groove corresponds to one active pillar, and an outer surface of the vertical channel is in contact with an inner wall surface of the first groove.

[0012] In some possible embodiments, each bit line is provided with a plurality of second grooves along the third direction, each second groove corresponds to an active pillar, and an outer surface of a first end portion of the active pillar is in contact with an inner wall surface of the second groove.

[0013] In some possible embodiments, a portion of the first end portion of the active pillar is recessed to form a recessed portion, and an inner surface of the second groove is in contact with and connected to the recessed portion.

[0014] In some possible embodiments, the shape of any one of the first groove and the second groove includes an arc-shaped groove and a polygonal groove.

[0015] In some possible embodiments, the projection of the polygonal groove on the substrate includes at least two sequentially connected line segments;

[0016] Some of the at least two line segments are parallel to the extension direction of the word line or the bit line where the polygonal groove is located, or all of the at least two line segments are not parallel to the extension direction of the word line or the bit line where the polygonal groove is located.

[0017] In some possible embodiments, the projection pattern of the active column on the substrate includes a square, and the polygonal groove includes a first segment, a second segment and a third segment connected in sequence, the first segment and the third segment are respectively perpendicular to the second segment, and the second segment is parallel to the extension direction of the word line or the bit line where the polygonal groove is located.

[0018] In some possible embodiments, for each of the active pillars, the bit line connected to the active pillar covers the entire outer surface of the first end portion in the circumferential direction.

[0019] In some possible embodiments, the semiconductor structure further includes a plurality of storage capacitors, and the plurality of storage capacitors are connected to the second ends of the plurality of active pillars in a one-to-one correspondence.

[0020] According to a second aspect of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising:

[0021] Providing a substrate, on which a plurality of active pillars are formed, each of the active pillars extending along a first direction, the plurality of active pillars being arranged in an array along a second direction and a third direction, the active pillars including vertical channels, the second direction and the third direction having a preset angle therebetween, and both being perpendicular to the first direction;

[0022] forming a plurality of bit lines, the plurality of bit lines being arranged in an array in the second direction, each of the bit lines extending along the third direction, each of the bit lines connecting the plurality of active pillars arranged in an array along the third direction, and at least a portion of a contact surface between the bit lines and the first end portions of the active pillars being non-parallel to the third direction;

[0023] A plurality of word lines are formed, and for each of the active pillars, the bit lines and the word lines on the active pillar are spaced apart along the first direction, and the plurality of word lines are arranged in an array along the third direction, each word line extends along the second direction, and each word line connects the plurality of active pillars arranged in an array along the second direction, and at least a portion of a contact surface of a contact area between the word line and the vertical channel of the active pillar is not parallel to the second direction.

[0024] In some possible embodiments, forming a plurality of word lines includes:

[0025] For each of the active pillars, a vertical channel of the active pillar and a contact region of the word line form a non-completely depleted channel.

[0026] In some possible embodiments, forming a plurality of bit lines includes:

[0027] forming a first mask layer on the top surface of the substrate, wherein the first mask layer exposes a first target area where the bit line is to be formed, wherein a first dielectric layer is filled between adjacent active pillars in the substrate;

[0028] removing the first dielectric layer at a first depth along the first direction in the first target region to expose an outer surface of a first portion of the active pillar, wherein the first dielectric layer retained in the first target region defines a bottom position of the bit line;

[0029] A plurality of bit lines are formed, each bit line covering an outer surface of a second portion of the active pillar exposed in the first target region, wherein the second portion is a portion of the first portion.

[0030] In some possible embodiments, the method for manufacturing the semiconductor structure further includes:

[0031] removing the first dielectric layer to a second depth along the first direction in the first target region to expose an outer surface of a third portion of the active pillar, wherein the second depth is less than the first depth;

[0032] forming a protection layer on the sidewall of the third portion of the active pillar;

[0033] removing the first dielectric layer between the first depth and the second depth to define a first region along the first direction;

[0034] Part of the structure of the active pillar in the first region is removed to form a recessed portion.

[0035] In some possible embodiments, forming a word line includes:

[0036] forming a second dielectric layer above the plurality of bit lines, wherein the second dielectric layer covers top surfaces of the bit lines and fills gaps between bottoms of the vertical channels of adjacent active pillars;

[0037] forming a third dielectric layer above the second dielectric layer, wherein the third dielectric layer covers the surface of the vertical channel of the active pillar;

[0038] A plurality of word lines are formed, each of the word lines connecting the plurality of active pillars arranged along the second direction, at least a portion of a contact surface of a contact region between the word lines and the third dielectric layer is not parallel to the second direction, and the plurality of word lines are disposed between adjacent active pillars arranged in an array along the third direction.

[0039] In some possible embodiments, after forming the third dielectric layer above the second dielectric layer, the manufacturing method further includes:

[0040] forming a fourth dielectric layer above the second dielectric layer, wherein the fourth dielectric layer covers exposed surfaces of the second dielectric layer and the third dielectric layer;

[0041] forming a second mask layer on the top surface of the substrate, wherein the second mask layer exposes a second target area where the word line is to be formed;

[0042] removing a portion of the fourth dielectric layer in the second target area to form a plurality of word line trenches arranged along the third direction, each word line trench extending along the second direction, the word line trench exposing a portion of the top surface of the second dielectric layer and a portion of the sidewall surface of the third dielectric layer;

[0043] A plurality of word lines are formed in the plurality of word line trenches.

[0044] In some possible embodiments, the manufacturing method further includes:

[0045] A plurality of storage capacitors are formed, and the plurality of storage capacitors are connected to the second ends of the plurality of active pillars in a one-to-one correspondence.

[0046] In the semiconductor structure disclosed herein, at least a portion of the contact surface between the word line and the vertical channel of the active pillar is non-parallel to the second direction, thereby forming a non-completely depleted channel, which helps address the issue of unstable threshold voltage. Furthermore, when both the word line and the bit line partially surround the active pillar, the distance between adjacent word lines and bit lines can be increased, which helps reduce coupling effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The accompanying drawings, which are incorporated into and constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, are used to explain the principles of the embodiments of the present disclosure. In these drawings, similar reference numerals are used to represent similar elements. The drawings described below are some embodiments of the present disclosure, not all embodiments. For those skilled in the art, other drawings can be derived from these drawings without inventive effort.

[0048] Figure 1 is a schematic diagram of a semiconductor structure according to an exemplary embodiment;

[0049] Figure 2 is a top view of a semiconductor structure according to an exemplary embodiment;

[0050] Figure 3 is a top view of a semiconductor structure according to an exemplary embodiment;

[0051] Figure 4 is a top view of a semiconductor structure according to an exemplary embodiment;

[0052] Figure 5 is a top view of a semiconductor structure according to an exemplary embodiment;

[0053] Figure 6 is a top view of a semiconductor structure according to an exemplary embodiment;

[0054] Figure 7 is a top view of a semiconductor structure according to an exemplary embodiment;

[0055] Figure 8 is a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment;

[0056] Figure 9 is a schematic diagram showing a substrate and a semiconductor structure having a plurality of active pillars according to an exemplary embodiment;

[0057] Figure 10 is a schematic diagram of a semiconductor structure showing the formation of a first mask layer according to an exemplary embodiment;

[0058] Figure 11is a schematic diagram of a semiconductor structure showing the formation of a first mask layer according to an exemplary embodiment;

[0059] Figure 12 is a schematic diagram showing a semiconductor structure after a portion of the first dielectric layer is removed according to an exemplary embodiment;

[0060] Figure 13 is a schematic diagram showing a semiconductor structure after forming a protective layer according to an exemplary embodiment;

[0061] Figure 14 is a schematic diagram showing a semiconductor structure after a portion of the first dielectric layer is removed according to an exemplary embodiment;

[0062] Figure 15 is a schematic diagram showing a semiconductor structure after a recess is formed according to an exemplary embodiment;

[0063] Figure 16 is a schematic diagram showing a semiconductor structure after forming a plurality of bit lines according to an exemplary embodiment;

[0064] Figure 17 is a schematic diagram showing a semiconductor structure after forming a second dielectric layer and a third dielectric layer according to an exemplary embodiment;

[0065] Figure 18 is a schematic diagram showing a semiconductor structure after forming a fourth dielectric layer according to an exemplary embodiment;

[0066] Figure 19 is a schematic diagram showing a semiconductor structure after forming a second mask layer according to an exemplary embodiment;

[0067] Figure 20 is a schematic diagram showing a semiconductor structure after word line trenches are formed according to an exemplary embodiment;

[0068] Figure 21 is a schematic diagram showing a semiconductor structure after forming a plurality of word lines according to an exemplary embodiment;

[0069] Figure 22 is a schematic diagram showing a semiconductor structure after forming a plurality of storage capacitors according to an exemplary embodiment;

[0070] Figure 23 is a top view of a semiconductor structure according to an exemplary embodiment.

[0071] Reference numerals:

[0072] 10. substrate; 11. first dielectric layer; 12. isolation structure; 13. protective layer;

[0073] 20, active pillar; 20a, depletion region; 20b, non-depletion region; 21, vertical channel; 22, first end portion; 221, recessed portion;

[0074] 30. bit line; 31. second groove;

[0075] 40, word line; 41, first groove; 40', word line groove;

[0076] 50. Storage capacitor;

[0077] 60. second dielectric layer;

[0078] 70. The third dielectric layer;

[0079] 80. Fourth dielectric layer;

[0080] 90. Fifth dielectric layer;

[0081] 100a, a first mask layer; 100b, a second mask layer. DETAILED DESCRIPTION

[0082] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure. It should be noted that, in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0083] In order to improve the problems existing in the related art, the embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a substrate, and a plurality of active pillars, a plurality of word lines, and a plurality of bit lines located on the substrate. The plurality of active pillars are arranged in an array along the second direction and the third direction, the plurality of word lines are arranged in an array along the third direction, and each word line extends along the second direction. The plurality of bit lines are arranged in an array along the second direction, and each bit line extends along the third direction. At least part of the contact surface of the contact area between the word line and the vertical channel of the active pillar is not parallel to the second direction, thereby forming a non-completely depleted channel, which is beneficial to solving the problem of unstable threshold voltage. In addition, when both the word line and the bit line partially surround the active pillar, the distance between adjacent word lines and adjacent bit lines can be increased, which is beneficial to reducing the coupling effect.

[0084] In the exemplary embodiments of the present disclosure, Figure 1As shown, this embodiment provides a semiconductor structure, which includes but is not limited to dynamic random access memory (DRAM), static random access memory (SRAM), non-volatile memory, etc.

[0085] like Figure 1 As shown, the semiconductor structure includes a substrate 10, which serves as a supporting platform for the semiconductor structure and is used to support other structures within the semiconductor structure. The material of substrate 10 includes, but is not limited to, silicon (Si), and can also be any of gallium nitride (GaN), gallium arsenide (GaAs), silicon carbide (SiC), and silicon-on-insulator (SOI).

[0086] like Figure 1 As shown, the semiconductor structure includes a plurality of discrete active pillars 20, and adjacent active pillars 20 can be separated by an isolation structure, so that the array is arranged above the substrate 10, which is conducive to forming a highly integrated transistor array. In some embodiments, refer to Figure 1 , a plurality of active pillars 20 are arranged in an array along the second direction and the third direction, the second direction and Figure 1 The x direction is parallel to the Figure 1 The y direction is parallel to the second direction, and there is a 90° angle between the second direction and the third direction. The multiple active pillars 20 are arranged in a rectangular / square array. In other embodiments, the multiple active pillars 20 can also be arranged in other ways, such as an acute angle between the second direction and the third direction, which will not be described in detail. In this embodiment, 4F 2 The semiconductor structure of the structure is described as an example. It is understood that this does not limit the technical solution of the present invention. The semiconductor structure of the present invention can also be 4.5F 2 , 6F 2 structure, or 4.5F 2 ~6F 2 Any one of them. Among them, 4F 2 , 4.5F 2 , 6F 2 The structure represents the minimum theoretical area occupied by a single memory cell (usually consisting of a transistor and a capacitor, i.e. a 1T1C cell) on the chip, where F represents the minimum feature size of the process node (such as the minimum line width or spacing of lithography).

[0087] See Figure 1 and Figure 12 , each active pillar 20 is along the first direction ( Figure 1 The vertical channel 21 of the active pillar 20 (see Figure 21) is used to form the channel region of the vertical transistor. The structures on both sides of the vertical channel 21 in the first direction of the active pillar 20 can be used to form the source region and drain region of the vertical transistor. In the semiconductor structure provided in this embodiment, the semiconductor substrate can be etched, and the retained semiconductor substrate can be used to form the base 10 and multiple active pillars 20. Alternatively, a base 10 can be provided and multiple active pillars 20 can be formed on the base 10 through an epitaxial process. The shape of the active pillar 20 includes but is not limited to a cylinder (see Figure 7 ), prism (see Figures 1 to 6 ).

[0088] like Figure 1 As shown, the semiconductor structure includes a plurality of word lines 40, the word lines 40 and the vertical channels 21 of the active pillars 20 (see Figure 21 ) contact, the vertical channel 21 can be controlled by the word line 40 to control the vertical transistor to be turned on or off. Each word line 40 is along the second direction ( Figure 1 The word lines 40 extend in the x direction to connect the plurality of active pillars 20 arranged in an array along the second direction, and the plurality of word lines 40 extend in the third direction ( Figure 1 The word lines 40 are arranged in the y direction as shown in FIG. 4 , so that the word lines 40 are arranged horizontally in the same layer in a parallel array, so that the word lines 40 can be arranged vertically (along the y direction as shown in FIG. Figure 1 The active pillars 20 arranged in the z direction (as shown in FIG) form an orthogonal grid structure, ensuring that each word line 40 crosses and contacts the active pillar 20 at a specific node.

[0089] See Figure 1 , the word line 40 and the vertical channel 21 of the active pillar 20 (see Figure 21 ) of the contact area and the second direction ( Figure 1 The word line 40 is not parallel to the vertical channel 21 in the x direction, so that the word line 40 does not cover the entire peripheral surface of the vertical channel 21, wherein the area of ​​the vertical channel 21 not in contact with the word line 40 will not be depleted by the electric field (see Figure 23 , forming a non-depleted region 20b, also known as an electrically neutral region), the region where the vertical channel 21 contacts the word line 40 can be completely depleted by the electric field (see Figure 23 , forming a depletion region 20a), and obtaining a non-completely depleted channel.

[0090] In one example, see Figure 23, exemplarily showing a semiconductor structure with a non-completely depleted channel. The active pillar 20 of the semiconductor structure includes a depletion region 20a and a non-depletion region 20b. The region of the active pillar 20 covered by the word line 40 and the region of the active pillar 20 covered by the bit line 30 together form the depletion region 20a. A portion of the active pillar 20, namely the non-depletion region 20b, exists. This portion is neither covered by the word line 40 nor by the bit line 30. Carriers are retained in this portion of the non-depletion region 20b. The active pillar 20 can form a conductive path with the substrate 10 through the non-depletion region 20b. This conductivity helps balance the potential of the substrate 10, avoiding charge accumulation and potential drift caused by electrical dangling, thereby suppressing threshold voltage fluctuations or leakage current anomalies caused by the floating effect. Transistors with non-completely depleted channels have higher carrier mobility and higher saturation current at the same bias voltage compared to fully depleted channels, which is conducive to the formation of high-speed circuits. The electrically neutral region in a partially depleted channel allows for threshold voltage adjustment via body biasing, which can be used to dynamically optimize power consumption and performance, increasing threshold voltage control flexibility and mitigating the impact of the floating body effect, particularly in vertical channel transistors. The electrically neutral region in a partially depleted channel can serve as a collection area for radiation-induced charge, reducing the direct impact of charge accumulation on the channel and improving the reliability of the semiconductor structure in radiation environments. The electrically neutral region can also provide an additional heat conduction path, improving the high-temperature stability of the semiconductor structure.

[0091] It should be noted that the shape of the non-depleted region 20b can be determined by simulation and changes with the shape of the active pillar 20 and the way the word line 40 and the bit line 30 wrap around the active pillar 20. Figure 23 In addition to the trapezoidal shape shown in the figure, it can also be an arc shape or the like, which is not specifically limited in the present disclosure.

[0092] In some embodiments, the cross-sectional shape of the active pillar 20 can be controlled so that at least a portion of the contact surface between the word line 40 and the active pillar 20 is not parallel to the second direction. For example, the cross-sectional shape of the active pillar 20 is set to a diamond, circle, ellipse, rectangle, square, pentagon, etc. When the cross-sectional shape of the active pillar 20 is a polygon, the polygon is an axisymmetric structure.

[0093] In other embodiments, the formation region of the word line 40 can be limited to prevent the word line 40 from being formed on a single side of the active pillar 20, resulting in the contact surface between the word line 40 and the active pillar 20 being parallel to the second direction. For example, the cross-section of the active pillar 20 is rectangular, and a portion of the word line 40 is formed on one side of the active pillar 20. Another portion of the word line 40 is formed between two adjacent active pillars 20 along the second direction, forming contact with the active pillar 20, thereby forming a contact surface that is not parallel to the second direction.

[0094] like Figure 1 As shown, the semiconductor structure further includes a plurality of bit lines 30, the bit lines 30 and the first end portions 22 of the active pillars 20 (see FIG. Figure 16 ) contact, and can transmit data signals to the storage capacitor 50 (described in detail later) connected to the second end of the active pillar 20 through the bit line 30, and realize charge detection and writing in read and write operations. Each bit line 30 is along the third direction ( Figure 1 y direction shown in FIG) to connect the plurality of active pillars 20 arranged in an array along the third direction, and the plurality of bit lines 30 extend along the second direction ( Figure 1 The plurality of bit lines 30 are arranged horizontally in the same layer in a parallel array, so that the plurality of bit lines 30 can be aligned with the vertically arranged active pillars 20 (along the x direction shown in FIG. Figure 1 The active pillars 20 are formed into an orthogonal grid structure, which ensures that each bit line 30 crosses and contacts the active pillar 20 at a specific node. For each active pillar 20, along the first direction, the bit line 30 and the word line 40 on the active pillar 20 are arranged alternately. For example, an interlayer dielectric layer (such as Figure 21 As shown in the second dielectric layer 60 , the interlayer dielectric layer is used to electrically isolate the word line 40 from the bit line 30 to reduce the parasitic capacitance between the bit line 30 and the word line 40 .

[0095] See Figure 1 , the bit line 30 and the first end portion 22 of the active pillar 20 (see Figure 21 ) is not parallel to the third direction (the direction in which the bit line 30 extends). The method for achieving a portion of the contact surface in the contact region between the bit line 30 and the active pillar 20 being non-parallel to the extension direction is the same as the contact method between the word line 40 and the active pillar 20 described above, and will not be repeated here.

[0096] In some embodiments, reference Figure 1 and Figure 21, the length of the vertical channel 21 of the active pillar 20 surrounded by the word line 40 in the circumferential direction is greater than or equal to half of the circumference of the active pillar 20, and the length of the first end 22 of the active pillar 20 surrounded by the bit line 30 in the circumferential direction is greater than or equal to half of the circumference of the first end 22 of the active pillar 20. This arrangement allows the word line 40 and the bit line 30 to form at least a semi-enclosed structure in the circumferential direction of the active pillar 20, thereby effectively improving the problem of unstable threshold voltage. In addition, when both the word line 40 and the bit line 30 partially surround the active pillar, the distance between adjacent word lines and adjacent bit lines can be increased, which is conducive to reducing the coupling effect. Of course, it is understandable that in some cases, the length of the bit line surrounding the active pillar in the circumferential direction is not equal to the length of the active pillar surrounded by the word line in the circumferential direction. The surrounding length can be slightly less than half of the circumferential length of the active pillar, as long as it does not affect the overall effect.

[0097] In the disclosed embodiment, at least a portion of the contact surface between the word line and the vertical channel of the active pillar is non-parallel to the second direction, thereby forming a non-completely depleted channel, which helps address the issue of unstable threshold voltage. Furthermore, when both the word line and the bit line partially surround the active pillar, the distance between adjacent word lines and adjacent bit lines can be increased, which helps reduce coupling effects.

[0098] In an exemplary embodiment, Figure 1 As shown, this embodiment provides a semiconductor structure, which includes a substrate 10, and a plurality of active pillars 20, a plurality of word lines 40 and a plurality of bit lines 30 located on the substrate 10, the plurality of active pillars 20 are arranged in an array along the second direction and the third direction, the plurality of word lines 40 are arranged in an array along the third direction, each word line 40 extends along the second direction, the plurality of bit lines 30 are arranged in an array along the second direction, each bit line 30 extends along the third direction, at least a portion of the contact surface of the contact area between the word line 40 and the active pillar 20 is not parallel to the second direction, and at least a portion of the contact surface of the contact area between the bit line 30 and the active pillar 20 is not parallel to the third direction.

[0099] Among them, such as Figure 1 and Figure 2 As shown, along the array direction of the plurality of word lines 40 (the third direction, Figure 1 In the y direction shown in FIG, a plurality of first grooves 41 are provided on the same side of each word line 40. The plurality of first grooves 41 are provided at intervals in the extending direction of the word line 40. Each first groove 41 corresponds to an active pillar 20 in contact with the word line 40. In this embodiment, in the third direction, the first grooves 41 on all word lines 40 can be provided on the same side of the word line 40 (see FIG. Figure 1 ), or they may be arranged on different sides (not shown in the drawings). When arranged on different sides, the opening directions of the first grooves 41 of two adjacent word lines 40 are facing each other or facing each other.

[0100] In some embodiments, as Figure 7 As shown, the cross section of the active pillar 20 is circular or elliptical, and the first groove 41 of the word line 40 is in the shape of an arc groove. The curvature of the arc of the first groove 41 is the same as the curvature of the cross section of the active pillar 20 (i.e., the plane perpendicular to the extension direction of the active pillar 20), so that the word line 40 and the active pillar 20 are aligned to form a contact connection. In this embodiment, the central angle of the arc is generally set to be greater than or equal to 180° and less than 360° (for example, 180° to 270°) so that the word line 40 does not completely cover the vertical channel 21 of the active pillar 20 (see Figure 15 ) and has a sufficient contact area with the vertical channel 21 to ensure the channel control capability of the word line 40 on the vertical channel 21. In one example, see Figure 7 The arc center angle of the arc groove is 180°, that is, the arc groove covers half of the outer circumference of the vertical channel 21.

[0101] In other embodiments, Figures 1 to 6 As shown, the cross-section of the active pillar 20 is polygonal, and the first groove 41 of the word line 40 is in the shape of an open polygonal groove. The projection of the polygonal groove on the substrate 10 includes at least two sequentially connected line segments. Some of the at least two line segments are parallel to the extension direction of the word line 40 in which the polygonal groove is located, or all of the at least two line segments are not parallel to the extension direction of the word line 40 in which the polygonal groove is located. Multiple line segments of the at least two line segments are connected end to end, but are not closed as a whole, so that the word line 40 does not completely surround the outer peripheral surface of the vertical channel 21.

[0102] In one example, see Figure 1 and Figure 2 The cross section of the active pillar 20 is a square (special rectangle), and the projection of the polygonal groove on the substrate 10 includes three line segments connected in sequence. By adjusting the depth of the first groove 41 (the third direction, Figure 1 y direction as shown in FIG), the word line 40 and the vertical channel 21 (see Figure 21 ) to adjust the channel control ability of the word line 40 on the vertical channel 21.

[0103] In another example, see Figure 3 and Figure 4 The cross section of the active pillar 20 is rectangular, and the projection of the polygonal groove on the substrate 10 includes three line segments connected in sequence (in a U shape), which can be adjusted by adjusting the depth of the first groove 41 (the third direction, Figure 3 In the y direction shown in FIG), the contact area between the word line 40 and the vertical channel 21 is controlled. In this example, the depth of the first groove 41 can be adaptively set according to the direction of extension of the long side of the rectangle. For example, see Figure 3When the long side of the rectangle is parallel to the third direction (or there is a slight angle between them), the depth of the first groove 41 can be set to be less than or equal to half the length of the long side of the rectangle to reduce the width of the word line 40, thereby reducing the overlapping area between the word line 40 and the bit line 30, and further reducing the parasitic capacitance between the bit line 30 and the word line 40. For another example, see Figure 4 When the long side of the rectangle is parallel to the second direction (or there is a slight angle between them), the depth of the second groove 31 (described in detail later) in the bit line 30 can be set to be less than or equal to half the length of the long side of the rectangle.

[0104] In another example, see Figure 5 The cross section of the active pillar 20 is a rhombus, and the projection of the polygonal groove on the substrate 10 includes two line segments connected in sequence. In this example, in the opening direction of the first groove 41 (the third direction, Figure 5 In the direction opposite to the y direction shown in FIG, the depth of the first groove 41 is less than or equal to half the size of the rhombus, so that the contact area between the word line 40 and the vertical channel 21 is less than or equal to the vertical channel 21 (see FIG. Figure 21 ) half of the outer circumference.

[0105] In another example (not shown in the drawings), the cross section of the active pillar is a rhombus, and the projection of the polygonal groove on the substrate includes four line segments connected in sequence. In this example, along the opening direction of the first groove (the third direction, Figure 1 (In the opposite direction of the y-direction shown in FIG), the depth of the first groove is greater than the size of the vertical channel, so that the contact area between the word line and the vertical channel is greater than half of the outer perimeter of the vertical channel. It should be noted that the word line coverage area can be adaptively set based on factors such as the doping level and the size of the active pillar to ensure sufficient channel control capability of the word line.

[0106] In another example, see Figure 6 The cross section of the active pillar 20 is a hexagon, and the projection of the polygon on the substrate 10 includes four sequentially connected line segments. This example can be understood based on the aforementioned examples and will not be described in detail here.

[0107] In this embodiment, by providing a first groove 41 corresponding to the active pillar 20 on one side of the word line 40 in the third direction, the vertical channel 21 of the active pillar 20 is not completely surrounded by the word line 40 in the circumferential direction, thereby forming a non-completely depleted channel. The non-completely depleted channel is conducive to optimizing the electric field distribution, reducing the short channel effect, and solving the problem of unstable threshold voltage (VT) in the related art. In addition, compared with the fully surrounded (channel area) word line in the related art, the bit line 30 in this embodiment, which only covers a portion of the outer circumference of the active pillar 20, is narrower ( Figure 1y direction as shown in ), the overlapping area between the word line 40 and the bit line 30 can be reduced. Since the parasitic capacitance is proportional to the overlapping area of ​​the parallel segments between the conductors, it can be determined that the parasitic capacitance generated between the word line 40 and the bit line 30 in the semiconductor structure provided by this embodiment is smaller, thereby reducing signal delay and power consumption, and improving the reliability and signal integrity of the semiconductor structure.

[0108] Among them, such as Figure 1 、 Figure 2 and Figure 6 As shown, along the array direction of the plurality of bit lines 30 (the second direction, Figure 2 ), a plurality of second grooves 31 are provided on the first side of each bit line 30, and the plurality of second grooves 31 are provided along the third direction ( Figure 2 The second grooves 31 are arranged at intervals along the y direction shown in FIG. 1 , and each second groove 31 corresponds to an active pillar 20 in contact with the bit line 30. In this embodiment, all the second grooves 31 can be arranged on the same side of the bit line 30 in the second direction (see FIG. 1 ). Figure 2 ), or may be arranged on different sides (not shown in the drawings). When arranged on different sides, the opening directions of the second grooves 31 of two adjacent bit lines 30 are opposite or back-to-back.

[0109] In some embodiments, the shape of the second groove 31 includes either an arcuate groove or a polygonal groove. The second groove 31 and the first groove 41 have the same configuration and principle, and will not be described in detail. Specifically, when the cross-sectional shape of the active pillar 20 is configured to have different dimensions in the second direction and the third direction (for example, configured to be rectangular or elliptical), the contact area between the bit line 30 and the active pillar 20 can be increased, reducing contact resistance. Furthermore, the spacing between adjacent bit lines 30 can be increased, reducing signal coupling between adjacent bit lines 30.

[0110] In this embodiment, by providing a second recess corresponding to the active pillar on one side of the bit line in the second direction, the first end portion (e.g., the source region) of the active pillar is not completely surrounded by the bit line in the circumferential direction. This reduces the contact resistance between the bit line and the active pillar, lowering signal delay and power consumption, and improving the reliability and signal integrity of the semiconductor structure. Furthermore, this arrangement reduces the size of the bit line in the second direction (using the same principle as word line narrowing, which will not be further described), thereby reducing parasitic capacitance between the word line and the bit line.

[0111] Among them, such as Figure 15 and Figure 16As shown, a portion of the first end portion 22 of the active pillar 20 is recessed to form a recessed portion 221, and a portion of the structure of the bit line 30 can extend into the recessed portion 221 to form a contact connection with the first end portion 22 of the active pillar 20. In some embodiments, the first end portion 22 of the active pillar 20 can be wet-etched to remove a portion of the structure to form the recessed portion 221 on the surface of the first end portion 22. In some embodiments, the bit line 30 is provided with a second groove 31, and the inner surface of the second groove 31 is in contact with the recessed portion 221.

[0112] See Figure 15 and Figure 16 It can be determined that extending part of the structure of the bit line 30 into the recessed portion 221 can make part of the top surface and part of the bottom surface of the bit line 30 contact the active pillar 20, thereby increasing the contact area between the bit line 30 and the active pillar 20 and reducing the contact resistance between the bit line 30 and the active pillar 20. In addition, the bottom wall and the top wall of the recessed portion 221 of the active pillar 20 can also provide support and limitation for the bit line 30, thereby improving the connection reliability between the active pillar 20 and the bit line 30 and reducing the risk of contact failure of the bit line 30 due to thermal stress or mechanical vibration.

[0113] In an exemplary embodiment, Figure 1 As shown, this embodiment provides a semiconductor structure, which includes a substrate 10, and a plurality of active pillars 20, a plurality of word lines 40 and a plurality of bit lines 30 located on the substrate 10, the plurality of active pillars 20 are arranged in an array along the second direction and the third direction, the plurality of word lines 40 are arranged in an array along the third direction, each word line 40 extends along the second direction, the plurality of bit lines 30 are arranged in an array along the second direction, each bit line 30 extends along the third direction, at least a portion of the contact surface of the contact area between the word line 40 and the active pillar 20 is not parallel to the second direction, and at least a portion of the contact surface of the contact area between the bit line 30 and the active pillar 20 is not parallel to the third direction.

[0114] In this embodiment, refer to Figure 1 and Figure 2 Each word line 40 is provided with a plurality of first grooves 41 along the second direction, each first groove 41 corresponds to an active pillar 20, and the vertical channel 21 of the active pillar 20 (see Figure 15 ) is in contact with the inner wall surface of the first groove 41.

[0115] In some embodiments (not shown in the figures), the bit line connected to the active pillar covers the entire circumferential surface of the first end portion of the active pillar. The bit line surrounding the entire outer circumference of the source / drain region of the active pillar is a mature technology and will not be described in detail. In the semiconductor structure provided in this embodiment, when the bit line is arranged to fully surround the first end portion 22 of the active pillar 20, for example, a full circle of recessed portions 221 can be provided at the first end portion 22 of the active pillar 20 to increase the contact area between the bit line 30 and the active pillar 20, thereby reducing contact resistance.

[0116] Among them, such as Figure 22 As shown, the semiconductor structure further includes a plurality of storage capacitors 50, and the plurality of storage capacitors 50 correspond to the second ends of the plurality of active pillars 20 one by one. Figure 1 ) and bit line 30 (see Figure 1 ), can control the active pillar 20 located at the intersection of the selected word line 40 and the bit line 30, and thus can read and write data to the storage capacitor 50 connected to the active pillar 20. The storage capacitor 50 provided in this embodiment can be, for example, a common electrode plate capacitor in the related art, and its structure is not further limited.

[0117] According to an exemplary embodiment of the present disclosure, Figure 8 As shown, this embodiment provides a method for manufacturing a semiconductor structure, and the manufacturing method includes the following steps:

[0118] Step S110: providing a substrate, forming a plurality of active pillars on the substrate, each active pillar extending along a first direction, and the plurality of active pillars are arranged in an array along a second direction and a third direction, the active pillars including vertical channels, and a preset angle between the second direction and the third direction, and both being perpendicular to the first direction.

[0119] In some embodiments, a semiconductor substrate may be provided, and a portion of the bulk substrate structure may be removed by etching to obtain a base 10 and a plurality of active pillars 20 located on the base 10. Depending on the type of vertical transistor to be formed subsequently, different regions of the semiconductor substrate may be doped with N-type impurity ions or P-type impurity ions, where the P-type impurity ions include one or more of boron ions, gallium ions, or indium ions, and the N-type ions include one or more of phosphorus ions and arsenic ions.

[0120] In other embodiments, a substrate 10 may be provided, and then an epitaxial growth process may be used to form a plurality of active pillars 20 on the top surface of the substrate 10. Different regions of the active pillars 20 may be doped with N-type impurity ions or P-type impurity ions according to the type of vertical transistor to be formed subsequently.

[0121] In some optional embodiments, see Figure 9, a plurality of isolation structures 12 are further formed on the substrate 10, and the plurality of isolation structures 12 are arranged along the second direction ( Figure 1 The center line 30 is arranged in a spaced manner, and each isolation structure 12 is arranged along the third direction ( Figure 1 Isolation structure 12 extends in the direction of the mid-bit line 30. Isolation structure 12 can isolate signal crosstalk between two adjacent bit lines 30 and, in some process steps (e.g., steps S330 and S340), perform the same function as protective layer 13 (described in detail later). Materials for isolation structure 12 include, but are not limited to, silicon nitride and low-k dielectric materials.

[0122] Step S120: forming a plurality of bit lines, wherein the plurality of bit lines are arranged in an array in the second direction, each bit line extends along a third direction, each bit line connects a plurality of active pillars arranged in an array along the third direction, and at least a portion of a contact surface between the bit line and the first end portion of the active pillar is not parallel to the third direction.

[0123] In this step, refer to Figure 16 A deposition process can be used to deposit a conductive material in the bit line trench, and the conductive material is then etched back. The remaining conductive material forms the bit line 30. Conductive materials include metals such as aluminum, copper, and tungsten. The relationship between the contact surface of the contact area between the bit line 30 and the active pillar 20 and the third direction is affected by the shapes of the active pillar 20 and the bit line 30.

[0124] Step S130: forming a plurality of word lines. For each active pillar, the bit lines and word lines on the active pillar are spaced apart along the first direction. The plurality of word lines are arranged in an array in the third direction. Each word line extends along the second direction. Each word line connects the plurality of active pillars arranged in the array along the second direction. At least a portion of the contact surface of the contact area between the word line and the vertical channel of the active pillar is not parallel to the second direction.

[0125] In this step, refer to Figure 20 and Figure 21 A deposition process can be used to deposit a conductive material in the plurality of word line trenches 40', and the conductive material is etched back so that the top surface of the conductive material is flush with the top surface of the vertical channel 21. The remaining conductive material forms a plurality of word lines 40. The material of the word lines 40 can be the same as or different from that of the bit lines 30, without further limitation.

[0126] In the disclosed embodiments, the word lines are arranged so that at least a portion of their contact surface with the active pillars is non-parallel to the direction of their extension. This prevents the word lines from covering the entire perimeter of the vertical channels. This prevents the vertical channels from being depleted by the electric field (forming an electrically neutral region) in areas not in contact with the word lines. The areas in contact with the word lines form partially depleted channels, which helps address the issue of unstable threshold voltages. When both word lines and bit lines contact portions of the perimeter of the active pillars, the spacing between adjacent word lines and bit lines can be increased, reducing coupling effects.

[0127] In an exemplary embodiment, this embodiment defines the formation of the bit line 30 in the above embodiment. Figures 9 to 15 As shown, a first dielectric layer 11 is filled between adjacent active pillars 20 on the substrate 10, and the first dielectric layer 11 covers the sidewalls of the active pillars 20. The method for manufacturing the semiconductor structure includes the following steps:

[0128] Step S210: providing a substrate, forming a plurality of active pillars on the substrate, each active pillar extending along a first direction, and the plurality of active pillars arranged in an array along a second direction and a third direction, wherein the active pillars include vertical channels.

[0129] This step is implemented in the same manner and on the same principle as step S110 in the aforementioned embodiment, and will not be described in detail.

[0130] Step S220 , forming a first mask layer on the top surface of the substrate, wherein the first mask layer exposes a first target area where a bit line is to be formed.

[0131] In this step, refer to Figure 10 and Figure 11 A deposition process can be used to deposit a mask material on the top surface of the substrate 10, and a photoresist can be coated on the mask material to form a photoresist layer. The photoresist layer is then exposed and developed to pattern the photoresist layer. Then, an etching process (such as reactive ion etching) is used to transfer the pattern in the photoresist layer to the mask material to obtain a first mask layer 100a.

[0132] The patterned first mask layer 100a can control the path of the etching medium so that the etching medium etches only the material layer exposed in the first target area, thereby facilitating the formation of the bit line 30 only in the first target area in subsequent steps.

[0133] Step S230 : removing the first dielectric layer at a first depth along a first direction in the first target region to expose the outer surface of the first portion of the active pillar. The first dielectric layer retained in the first target region defines the bottom position of the bit line.

[0134] In this step, refer to Figures 10 to 15Using first mask layer 100a as a mask, an etching process is performed to remove the portion of the material layer (first dielectric layer 11) in substrate 10 not covered by first mask layer 100a. The first dielectric layer 11 retained in the first target area defines the bottom height of bit line 30. By controlling the etching time, only the first dielectric layer 11 is etched and removed to a first depth, thereby exposing the first portion of the outer surface of active pillar 20.

[0135] Combined diagram Figure 1 and Figure 2 The projection pattern of the first target area on the substrate 10 is in a rack shape, the strip portion of the rack shape corresponds to the area forming the bit line body, the teeth of the rack shape extend between adjacent active pillars 20, and the area between two adjacent teeth corresponds to the second groove 31 of the bit line 30.

[0136] Step S240 : forming a plurality of bit lines, wherein the bit lines cover the outer surface of the second portion of the active pillar exposed in the first target region, where the second portion is a portion of the first portion.

[0137] In this step, refer to Figure 16 and Figure 14 , a deposition process may be used to deposit a conductive material in the first target area, and the conductive material may be etched back to adjust the height of the conductive material to obtain the bit line 30. In some embodiments, refer to Figure 16 When the conductive material is etched back to form the bit line 30 , the protection layer 13 (described later), the first dielectric layer 11 and the isolation structure 12 portions above the bit line 30 will also be etched back and removed.

[0138] See Figure 15 and Figure 16 It can be understood that, since part of the first target area is located between two adjacent active pillars 20, part of the structure of the bit line 30 formed in step S240 extends between the adjacent active pillars 20, so that the second groove 31 is formed at the position of the bit line 30 corresponding to the active pillar 20.

[0139] Step S250: forming a plurality of word lines. For each active pillar 20, the bit lines and word lines on the active pillar 20 are spaced apart along the first direction, and the plurality of word lines are arranged in an array in the third direction. Each word line extends along the second direction, and each word line connects the plurality of active pillars 20 arranged in an array along the second direction. At least a portion of the contact surface of the contact area between the word line and the vertical channel 21 of the active pillar 20 is not parallel to the second direction.

[0140] This step is implemented in the same manner and on the same principle as step S130 in the aforementioned example and will not be described in detail.

[0141] In addition to the above steps, in some optional embodiments, the method of forming the bit lines also includes: adjusting the morphology and position of the mask layer to remove the first dielectric layer covered by the first mask layer to a first depth, and then filling the retained first dielectric layer with a conductive material, and patterning and etching back the conductive material to obtain a plurality of bit lines corresponding to the first target area.

[0142] In an exemplary embodiment, before forming the bit line 30, the method for manufacturing the semiconductor structure further includes the following steps:

[0143] Step S310 : removing the first dielectric layer to a second depth along the first direction in the first target region to expose the outer surface of the third portion of the active pillar, wherein the second depth is less than the first depth.

[0144] In this step, refer to Figures 10 to 12 (in, Figure 11 for Figure 9 As shown in the figure (view obtained by looking in the reverse direction along the y direction), a first mask layer 100a can be formed on the top surface of the substrate 10, and the area of ​​the first dielectric layer 11 not covered by the first mask layer 100a is the first target area.

[0145] An etching process can be used to remove the first dielectric layer 11 in the first target area that is not covered by the first mask layer 100a. By controlling the etching time, only the first dielectric layer 11 at the second depth can be etched away to expose the outer surface of the third portion of the active pillar 20.

[0146] Step S320 , forming a protection layer on the sidewall of the third portion of the active pillar.

[0147] In this step, refer to Figure 13 A protective layer 13 can be formed on the exposed sidewall surface (ie, the third portion) of the active pillar 20 by deposition, epitaxial growth, or other processes. The protective layer 13 is made of a material with high etching resistance, such as nitride, such as silicon nitride (Si3N4).

[0148] Step S330 : removing the first dielectric layer between the first depth and the second depth to define a first region along the first direction.

[0149] In this step, refer to Figure 14 The first dielectric layer 11 between the first depth and the second depth may be removed by the processes described in step S220 and step S230 to expose a portion of the outer circumference (ie, the first region) of the first end portion 22 of the active pillar 20 .

[0150] Step S340 : removing a portion of the active pillar structure in the first region to form a recessed portion.

[0151] In this step, refer to Figure 15 , and combined with Figure 13 and Figure 14 It can be determined that since the second depth is less than the first depth, the protective layer 13 formed in step S320 does not cover the first area of ​​the active pillar 20. Then, the first area of ​​the active pillar 20 can be processed by wet cleaning, etching and other processes to remove part of the structure of the first area of ​​the active pillar 20, thereby forming a recessed portion 221 on the outer peripheral surface of the active pillar 20.

[0152] In this embodiment, a protective layer covering only a portion of the active pillar surface is formed by etching the first dielectric layer in sections. This protective layer protects the active pillar, while the surface of the active pillar not covered by the protective layer is easily removed to form a recessed portion. The recessed portion not only increases the contact area between the active pillar and the bit line, reducing contact resistance, but also enables the active pillar to provide positional support for the bit line, enhancing the connection reliability between the active pillar and the bit line.

[0153] In an exemplary embodiment, this embodiment defines the formation of the word line 40 in the above embodiment, and the manufacturing method includes the following steps:

[0154] Step S410: Provide a substrate, form a plurality of active pillars on the substrate, each active pillar extends along a first direction, and the plurality of active pillars are arranged in an array along a second direction and a third direction, the active pillars include vertical channels, and there is a preset angle between the second direction and the third direction, and both are perpendicular to the first direction.

[0155] This step is implemented in the same manner and on the same principle as step S110 in the aforementioned embodiment, and will not be described in detail.

[0156] Step S420: forming a plurality of bit lines, wherein the plurality of bit lines are arranged in an array in the second direction, each bit line extends along a third direction, and each bit line connects a plurality of active pillars arranged in an array along the third direction, wherein at least a portion of a contact surface between the bit line and the first end portion of the active pillar is not parallel to the third direction.

[0157] This step is implemented in the same manner and on the same principle as step S120 in the aforementioned embodiment and will not be described in detail.

[0158] Step S430 , forming a second dielectric layer above the plurality of bit lines, wherein the second dielectric layer covers top surfaces of the bit lines and fills gaps between bottoms of the vertical trenches of adjacent active pillars.

[0159] In this step, refer to Figure 17A second dielectric layer 60 can be formed above the bit line 30 using a deposition process. The second dielectric layer 60 serves as an interlayer dielectric layer, providing a flat process support surface for the word line 40 and electrically isolating the bit line 30 from the word line 40. The material of the second dielectric layer 60 includes, but is not limited to, a single-layer structure formed by any one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material, or a stacked structure of two or more of the above materials. In one example, the second dielectric layer can be a stacked structure composed of silicon oxide and silicon nitride. In another example, see Figure 17 The material of the second dielectric layer 60 is the same as that of the first dielectric layer 11 .

[0160] Step S440 , forming a third dielectric layer on the second dielectric layer, wherein the third dielectric layer covers the surface of the vertical channel of the active pillar.

[0161] In this step, refer to Figure 17 A third dielectric layer 70 can be formed on the second dielectric layer 60 using a deposition process. The third dielectric layer 70 covers the surface of the vertical channel 21 of the active pillar 20. The third dielectric layer 70 is used to form a gate dielectric layer (also known as a gate oxide layer). The material of the gate dielectric layer includes but is not limited to silicon dioxide and a high-k dielectric material (such as hafnium oxide).

[0162] Step S450: forming a plurality of word lines, each word line connecting a plurality of active pillars arranged along the second direction, at least a portion of a contact surface between the word line and the third dielectric layer is not parallel to the second direction, and the plurality of word lines are disposed between adjacent active pillars arranged in an array along the third direction.

[0163] In this step, refer to Figure 21 A deposition process can be used to form word lines 40 on a side of the third dielectric layer 70 facing away from the active pillars 20. The material of the word lines 40 includes, but is not limited to, at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, nickel silicide, cobalt silicide, tantalum, aluminum, lanthanum, titanium, or tungsten.

[0164] In some embodiments, this embodiment further illustrates the formation of the word line 40 in the aforementioned embodiment. After forming the third dielectric layer 70 on the second dielectric layer 60 , the manufacturing method further includes:

[0165] Step S510 : forming a fourth dielectric layer on the second dielectric layer, wherein the fourth dielectric layer covers exposed surfaces of the second dielectric layer and the third dielectric layer.

[0166] In this step, refer to Figure 18A fourth dielectric layer 80 can be formed on the second dielectric layer 60 using a deposition process. The fourth dielectric layer 80 covers the exposed surfaces of the second dielectric layer 60 and the third dielectric layer 70. Part of the fourth dielectric layer 80 will be removed in subsequent steps to define the formation position and morphology of the word lines 40. Materials for the fourth dielectric layer 80 include, but are not limited to, silicon oxide and silicon nitride.

[0167] Step S520 , forming a second mask layer on the top surface of the substrate, wherein the second mask layer exposes a second target area where a word line is to be formed.

[0168] In this step, refer to Figure 19 A second mask layer 100b can be formed on the top surface of the substrate 10. The second mask layer 100b exposes the second target area where the word line 40 is to be formed. The second mask layer 100b protects the structure covered by it, allowing the fourth dielectric layer 80 not covered by it to be removed. The formation principle of the second mask layer 100b is the same as that of the first mask layer 100a in the aforementioned embodiment and will not be further described.

[0169] Step S530: remove a portion of the fourth dielectric layer in the target area to form a plurality of word line trenches arranged along the third direction, each word line trench extending along the second direction, and exposing a portion of the top surface of the second dielectric layer and a portion of the sidewall surface of the third dielectric layer.

[0170] In this step, refer to Figure 20 , and combined with Figure 19 Using the second mask layer 100 b as a mask and the second dielectric layer 60 as an etch stop layer, an etching process is employed to remove the structure of the fourth dielectric layer 80 located in the second target region, thereby forming a plurality of word line trenches 40 ′ arranged along the third direction in the substrate 10 . The word line trenches 40 ′ expose a portion of the top surface of the second dielectric layer 60 , so that the top surface of the second dielectric layer 60 can define the bottom height of the word line 40 . The word line trenches 40 ′ also expose a portion of the sidewall surface of the third dielectric layer 70 (gate oxide layer).

[0171] Step S540: forming a plurality of word lines in the plurality of word line trenches.

[0172] In this step, refer to Figure 20 and Figure 21 A deposition process may be used to fill the word line trench 40 ′ with a conductive material, and the conductive material may be etched back to adjust the top surface height of the conductive material, thereby obtaining the word line 40 .

[0173] In some optional embodiments, after step S440, the word line 40 can be formed in the following manner: a conductive material is formed on the top surface of the second dielectric layer 60, a portion of the conductive material is removed, the conductive material located in the second target area is retained, and the retained conductive material is etched back to form the word line.

[0174] In some embodiments, see Figure 22 After forming the word line 40 , the method for manufacturing the semiconductor structure further includes: forming a fifth dielectric layer 90 , where the fifth dielectric layer 90 covers the word line 40 and the exposed top surface of the fourth dielectric layer 80 .

[0175] After forming the fifth dielectric layer 90 (also known as the passivation layer), the top surface of the fifth dielectric layer 90 can be chemically mechanically polished to provide a flat surface to facilitate subsequent formation of the storage capacitor 50 on the top surface of the substrate 10. Materials for the fifth dielectric layer 90 include, but are not limited to, silicon dioxide, silicon nitride, and aluminum oxide.

[0176] In some embodiments, after forming the plurality of word lines, the method for manufacturing the semiconductor structure further includes: forming a plurality of storage capacitors 50 , wherein the plurality of storage capacitors 50 are connected to the second ends of the plurality of active pillars 20 in a one-to-one correspondence.

[0177] Forming the storage capacitor 50 is a mature technology and is not limited in this embodiment.

[0178] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0179] In the description of this specification, reference to the terms "embodiment", "exemplary embodiment", "some embodiments", "illustrative embodiment", "example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure.

[0180] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any suitable manner in any one or more embodiments or examples.

[0181] In the description of the present disclosure, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present disclosure.

[0182] It is to be understood that the terms "first", "second", etc. used in the present disclosure can be used to describe various structures in the present disclosure, but these structures are not limited by these terms. These terms are only used to distinguish a first structure from another structure.

[0183] In one or more of the accompanying drawings, identical elements are represented by similar reference numerals. For clarity, many parts in the accompanying drawings are not drawn to scale. In addition, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be described in a single figure. Many specific details of the present disclosure, such as device structure, materials, dimensions, processing techniques, and technologies, are described below to facilitate a clearer understanding of the present disclosure. However, as will be appreciated by those skilled in the art, the present disclosure may be practiced without following these specific details.

[0184] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A semiconductor structure, characterized in that include: substrate; A plurality of active pillars are disposed on the substrate, each of the active pillars extending along a first direction, and the plurality of active pillars are arranged in an array along a second direction and a third direction, the active pillars including vertical channels, and the second direction and the third direction have a preset angle therebetween and are both perpendicular to the first direction; a plurality of word lines arranged in an array in the third direction, each word line extending along the second direction, each word line connecting a plurality of active pillars arranged in an array along the second direction, and at least a portion of a contact surface between the word line and a vertical channel of the active pillar being non-parallel to the second direction; a plurality of bit lines arranged in an array along the second direction, each of the bit lines extending along the third direction, each of the bit lines connecting the plurality of active pillars arranged in an array along the third direction, and at least a portion of a contact surface between the bit lines and the first end portions of the active pillars being non-parallel to the third direction; For each of the active pillars, along the first direction, the bit line and the word line on the active pillar are arranged alternately; The vertical channel of the active pillar and the contact region of the word line form a non-completely depleted channel.

2. The semiconductor structure according to claim 1, wherein: Each word line is provided with a plurality of first grooves along the second direction, each first groove corresponds to one active pillar, and an outer surface of the vertical channel is in contact with an inner wall surface of the first groove.

3. The semiconductor structure according to claim 2, wherein: Each bit line is provided with a plurality of second grooves along the third direction, each second groove corresponds to one active pillar, and an outer surface of a first end portion of the active pillar is in contact with an inner wall surface of the second groove.

4. The semiconductor structure according to claim 3, wherein: A partial area of ​​the first end portion of the active pillar is recessed to form a recessed portion, and an inner surface of the second groove is in contact with and connected to the recessed portion.

5. The semiconductor structure according to claim 3, wherein: The shape of any one of the first groove and the second groove includes an arc groove and a polygonal groove.

6. The semiconductor structure according to claim 5, wherein: The projection of the polygonal groove on the substrate includes at least two line segments connected in sequence; Some of the at least two line segments are parallel to the extension direction of the word line or the bit line where the polygonal groove is located, or all of the at least two line segments are not parallel to the extension direction of the word line or the bit line where the polygonal groove is located.

7. The semiconductor structure according to claim 6, wherein: The projection pattern of the active column on the substrate includes a square, and the polygonal groove includes a first segment, a second segment and a third segment connected in sequence, the first segment and the third segment are respectively perpendicular to the second segment, and the second segment is parallel to the extension direction of the word line or the bit line where the polygonal groove is located.

8. The semiconductor structure according to claim 2, wherein: For each of the active pillars, the bit line connected to the active pillar covers the entire outer surface of the first end portion in the circumferential direction.

9. The semiconductor structure according to any one of claims 1 to 8, wherein: The semiconductor structure further includes a plurality of storage capacitors, and the plurality of storage capacitors are connected to the second ends of the plurality of active pillars in a one-to-one correspondence.

10. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, on which a plurality of active pillars are formed, each of the active pillars extending along a first direction, the plurality of active pillars being arranged in an array along a second direction and a third direction, the active pillars including vertical channels, the second direction and the third direction having a preset angle therebetween, and both being perpendicular to the first direction; forming a plurality of bit lines, the plurality of bit lines being arranged in an array in the second direction, each of the bit lines extending along the third direction, each of the bit lines connecting the plurality of active pillars arranged in an array along the third direction, and at least a portion of a contact surface between the bit lines and the first end portions of the active pillars being non-parallel to the third direction; forming a plurality of word lines, wherein for each active pillar, the bit lines and the word lines on the active pillar are spaced apart along the first direction, the plurality of word lines are arranged in an array along the third direction, each word line extends along the second direction, each word line connects the plurality of active pillars arranged in an array along the second direction, and at least a portion of a contact surface between the word line and the vertical channel of the active pillar is not parallel to the second direction; For each of the active pillars, a vertical channel of the active pillar and a contact region of the word line form a non-completely depleted channel.

11. The method for manufacturing a semiconductor structure according to claim 10, wherein: The forming of the plurality of bit lines comprises: forming a first mask layer on the top surface of the substrate, wherein the first mask layer exposes a first target area where the bit line is to be formed, wherein a first dielectric layer is filled between adjacent active pillars in the substrate; removing the first dielectric layer at a first depth along the first direction in the first target region to expose an outer surface of a first portion of the active pillar, wherein the first dielectric layer retained in the first target region defines a bottom position of the bit line; A plurality of bit lines are formed, each bit line covering an outer surface of a second portion of the active pillar exposed in the first target region, wherein the second portion is a portion of the first portion.

12. The method for manufacturing a semiconductor structure according to claim 11, wherein: The method for manufacturing the semiconductor structure further includes: removing the first dielectric layer to a second depth along the first direction in the first target region to expose an outer surface of a third portion of the active pillar, wherein the second depth is less than the first depth; forming a protection layer on the sidewall of the third portion of the active pillar; removing the first dielectric layer between the first depth and the second depth to define a first region along the first direction; Part of the structure of the active pillar in the first region is removed to form a recessed portion.

13. The method for manufacturing a semiconductor structure according to claim 11, wherein: The forming of the word line comprises: forming a second dielectric layer above the plurality of bit lines, wherein the second dielectric layer covers top surfaces of the bit lines and fills gaps between bottoms of the vertical channels of adjacent active pillars; forming a third dielectric layer above the second dielectric layer, wherein the third dielectric layer covers the surface of the vertical channel of the active pillar; A plurality of word lines are formed, each of the word lines connecting the plurality of active pillars arranged along the second direction, at least a portion of a contact surface of a contact region between the word lines and the third dielectric layer is not parallel to the second direction, and the plurality of word lines are disposed between adjacent active pillars arranged in an array along the third direction.

14. The method for manufacturing a semiconductor structure according to claim 13, wherein: After forming the third dielectric layer above the second dielectric layer, the manufacturing method further includes: forming a fourth dielectric layer above the second dielectric layer, wherein the fourth dielectric layer covers exposed surfaces of the second dielectric layer and the third dielectric layer; forming a second mask layer on the top surface of the substrate, wherein the second mask layer exposes a second target area where the word line is to be formed; removing a portion of the fourth dielectric layer in the second target area to form a plurality of word line trenches arranged along the third direction, each word line trench extending along the second direction, the word line trench exposing a portion of the top surface of the second dielectric layer and a portion of the sidewall surface of the third dielectric layer; A plurality of word lines are formed in the plurality of word line trenches.

15. The method for manufacturing a semiconductor structure according to claim 10, wherein: The production method further comprises: A plurality of storage capacitors are formed, and the plurality of storage capacitors are connected to the second ends of the plurality of active pillars in a one-to-one correspondence.

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