Manufacturing method of semiconductor structure
By etching the grooves in the semiconductor structure and growing the sacrificial layer, and repeated growth and etching, the impurity concentration between the barrier layer and the p-type semiconductor is reduced, the interface quality problem is solved, and the stability and reliability of the device are improved.
Patent Information
- Application Number
- CN202311850137.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-29
- Publication Date
- 2025-07-08
AI Technical Summary
The prior art is difficult to effectively reduce the impurities between the barrier layer and the p-type semiconductor in the enhanced semiconductor device, resulting in a decrease in interface quality and affecting device performance and reliability.
The grooves are etched on the n-type semiconductor layer and the sacrificial layer is grown, and the growth and etching are repeated multiple times until the concentration of impurity elements is lower than the preset value, reducing the concentration of impurity in the surface of the barrier layer and the epitaxial cavity, and improving the interface quality.
By growing and etching the sacrificial layer multiple times, the concentration of impurity elements is significantly reduced, the interface quality between the barrier layer and the p-type semiconductor layer is improved, and the stability and reliability of the device are enhanced.
Smart Images
Figure CN120282468A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and particularly to a manufacturing method of a semiconductor structure. Background Art
[0002] A high electron mobility transistor (HEMT) is a heterojunction field effect transistor. Taking the AlGaN / GaN heterostructure as an example, due to the presence of a strong two-dimensional electron gas in the AlGaN / GaN heterostructure, usually the AlGaN / GaN HEMT is a depletion-type device, making it difficult to implement an enhancement-type device. However, the application of depletion-type devices has certain limitations in many places. For example, in the application of power switch devices, an enhancement-type (normally-off) switch device is required. The enhancement-type gallium nitride switch device is mainly used in high-frequency devices, power switch devices, digital circuits, etc., and its research is of great significance.
[0003] There are many ways to implement an enhancement-type device. For example, a p-type semiconductor is disposed on the barrier layer in the gate region to deplete the two-dimensional electron gas. However, there are usually a large number of impurities at the contact interface between the barrier layer and the p-type semiconductor, reducing the interface quality between the barrier layer and the p-type semiconductor, resulting in current leakage, reducing the gate reliability, and ultimately affecting the device performance. Summary of the Invention
[0004] In view of this, an embodiment of the present disclosure provides a manufacturing method of a semiconductor structure to reduce the impurities between the barrier layer and the p-type semiconductor in the enhancement-type device and improve the device reliability.
[0005] According to one aspect of the present disclosure, an embodiment of the present disclosure provides a manufacturing method of a semiconductor structure, characterized by including the following steps:
[0006] S1. Provide a substrate, and sequentially grow a channel layer, a barrier layer, and an n-type semiconductor layer on the substrate;
[0007] S2. Etch a groove on the n-type semiconductor layer, and the groove penetrates through the n-type semiconductor layer;
[0008] S3. Grow a sacrificial layer on the n-type semiconductor layer and in the groove;
[0009] S4. Etch the sacrificial layer;
[0010] S5. Grow a p-type semiconductor layer on the n-type semiconductor layer and in the groove;
[0011] Wherein, before entering step S5, steps S3 and S4 are repeated N times until the concentration of impurity elements on the surface of the barrier layer below the groove is lower than a preset value.
[0012] As an alternative embodiment, the groove penetrates through the n-type semiconductor layer and partially penetrates through the barrier layer.
[0013] As an alternative embodiment, the method for etching the groove in step S2 is in-situ etching.
[0014] As an alternative embodiment, the in-situ etching is dry etching.
[0015] As an alternative embodiment, the gas environment for etching includes a combination of one or more of Cl2, H2, HCl, and TBCl.
[0016] As an alternative embodiment, after the in-situ etching to form the groove in step S2, it further includes:
[0017] Etching the groove a second time to etch and form a plurality of V-grooves or hexagonal prisms arranged at intervals on the bottom surface of the groove.
[0018] As an alternative embodiment, a first insertion layer is further provided on the n-type semiconductor layer before etching the groove in the n-type semiconductor layer, and the material of the first insertion layer is AlGaN.
[0019] As an alternative embodiment, a second insertion layer is further provided between the barrier layer and the n-type semiconductor layer, and the second insertion layer is an unintentionally doped layer.
[0020] As an alternative embodiment, the material of the n-type semiconductor layer includes at least one of n-type GaN, n-type AlGaN, or n-type AlInGaN.
[0021] As an alternative embodiment, the sacrificial layer is conformally grown on the n-type semiconductor layer and in the groove, or, the surface of the sacrificial layer on the side away from the substrate is planar.
[0022] As an alternative embodiment, the method for etching the sacrificial layer in step S4 is in-situ etching.
[0023] As an alternative embodiment, the material of the sacrificial layer includes a combination of one or more of AlN, InN, InGaN, InAlN, InAlGaN, and GaN.
[0024] As an alternative embodiment, the sacrificial layer is an unintentionally doped layer.
[0025] As an alternative embodiment, the sacrificial layer is a carbon-doped layer, an iron-doped layer, or an iron-carbon co-doped layer.
[0026] As an alternative embodiment, the p-type semiconductor layer conformally grows on the n-type semiconductor layer and in the groove, or the surface of the p-type semiconductor layer on the side away from the substrate is planar.
[0027] As an alternative embodiment, the material of the p-type semiconductor layer includes at least one of p-type diamond, p-type NiO, p-type GaN or p-type polycrystalline GaN.
[0028] As an alternative embodiment, the method for manufacturing the semiconductor structure further includes:
[0029] S6. Etch the n-type semiconductor layer to expose the barrier layer, form a source region and a drain region, set a source electrode in the source region, set a drain electrode in the drain region, and set a gate electrode on the p-type semiconductor layer above the groove.
[0030] The present disclosure provides a method for manufacturing a semiconductor structure, in which a channel layer, a barrier layer and an n-type semiconductor layer are sequentially grown on a substrate; a groove is etched in the n-type semiconductor layer, and the groove penetrates the n-type semiconductor layer; a sacrificial layer is grown on the n-type semiconductor layer and in the groove; the sacrificial layer is etched; a p-type semiconductor layer is grown on the n-type semiconductor layer and in the groove; the growth and etching of the sacrificial layer are repeated multiple times until the concentration of impurity elements on the surface of the barrier layer below the groove is lower than a preset value.
[0031] The present disclosure reduces the concentration of impurity elements on the surface of the barrier layer below the groove by the method of growing and etching the sacrificial layer multiple times, and also reduces the concentration of impurity elements in the epitaxial cavity, improves the interface quality between the barrier layer and the p-type semiconductor layer, further improves the crystal quality of the p-type semiconductor layer, thereby reducing the gate leakage current and further improving the stability and reliability of the device. Description of the Drawings
[0032] Figure 1 Shown is a flowchart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.
[0033] Figures 2 to 11 Shown as Figure 1 Shown is a schematic diagram of an intermediate structure corresponding to the shown process.
[0034] Figures 12a to 12c Shown is a schematic diagram of the structure of a semiconductor structure provided by an embodiment of the present disclosure. Detailed Embodiments
[0035] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present disclosure.
[0036] In order to reduce the impurities between the barrier layer and the p-type semiconductor in the enhanced device and improve the device reliability, the present disclosure provides a manufacturing method of a semiconductor structure. A channel layer, a barrier layer, and an n-type semiconductor layer are sequentially grown on a substrate; a groove is etched in the n-type semiconductor layer, and the groove penetrates through the n-type semiconductor layer; a sacrificial layer is grown on the n-type semiconductor layer and in the groove; the sacrificial layer is etched; a p-type semiconductor layer is grown on the n-type semiconductor layer and in the groove; the growth and etching of the sacrificial layer are repeated multiple times until the concentration of impurity elements on the surface of the barrier layer below the groove is lower than a preset value. The present disclosure reduces the concentration of impurity elements on the surface of the barrier layer below the groove by growing and etching the sacrificial layer multiple times, and also reduces the concentration of impurity elements in the epitaxial cavity, improves the interface quality between the barrier layer and the p-type semiconductor layer, further improves the crystal quality of the p-type semiconductor layer, thereby reducing the gate leakage current and further improving the stability and reliability of the device.
[0037] The following combines Figures 1 to 12c to further illustrate by way of example a manufacturing method of a semiconductor structure mentioned in the present disclosure.
[0038] Figure 1 The flowchart of the manufacturing method of the semiconductor structure provided by an embodiment of the present disclosure is shown; Figures 2 to 11 As shown Figure 1 The intermediate structure schematic diagram corresponding to the shown process is shown. As Figure 1 shown, the manufacturing method of the semiconductor structure provided by an embodiment of the present disclosure includes the following steps:
[0039] Step S1: Provide a substrate, and sequentially grow a channel layer, a barrier layer, and an n-type semiconductor layer on the substrate.
[0040] Specifically, as Figure 2As shown, a substrate 10 is provided, and a channel layer 20, a barrier layer 30, and an n-type semiconductor layer 40 are sequentially grown on the substrate 10. The material of the substrate 10 includes any one or a combination of Si, Al2O3, GaN, SiC, or AlN. The bandgap width of the material of the barrier layer 30 is greater than that of the material of the channel layer 20. The material of the channel layer 20 and the material of the barrier layer 30 may include group III nitride materials, and a two-dimensional electron gas can be formed at the interface between the channel layer 20 and the barrier layer 30. In an alternative embodiment, the channel layer 20 is a GaN layer and the barrier layer 30 is an AlGaN layer. In other alternative embodiments, the material combinations of the channel layer 20 and the barrier layer 30 may also be GaN / AlN, GaN / InN, GaN / InAlGaN, GaAs / AlGaAs, GaN / InAlN, or InN / InAlN. The material of the n-type semiconductor layer 40 includes at least one of n-type GaN, n-type AlGaN, or n-type AlInGaN.
[0041] Step S2: Etch a groove in the n-type semiconductor layer, and the groove penetrates through the n-type semiconductor layer.
[0042] Specifically, as Figure 3 shown, a groove 41 is etched in the n-type semiconductor layer 40, and the groove 41 penetrates through the n-type semiconductor layer 40. The method for etching the groove 41 is in-situ etching. The in-situ etching method is dry etching, and the etching gas environment includes one or a combination of Cl2, H2, HCl, and TBCl. The in-situ etching method does not introduce impurities, can reduce the interface state density, and is beneficial to reducing the current collapse effect and leakage current of the device prepared subsequently. Optionally, as Figure 4 shown, the groove 41 penetrates through the n-type semiconductor layer 40 and partially penetrates the barrier layer 30. Reducing the thickness of the barrier layer 30 can further improve the depletion effect of the p-type semiconductor material grown in the groove 41 on the two-dimensional electron gas, thereby increasing the device threshold voltage. Optionally, after the groove 41 is formed by in-situ etching, the groove 41 is etched again to form a plurality of V-shaped pits (as Figure 5 shown) or hexagonal prisms (as Figure 6 shown) arranged at intervals on the bottom surface of the groove 41. In the case of forming crystal planes, such as (1-100) crystal plane or (11-20) crystal plane, the crystal quality of the p-type semiconductor material grown in the groove 41 can be further improved.
[0043] Step S3: Grow a sacrificial layer on the n-type semiconductor layer and in the groove.
[0044] Specifically, a sacrificial layer 50 is grown on the n-type semiconductor layer 40 and in the groove 41. As Figure 7 shown, the sacrificial layer 50 conformally grows on the n-type semiconductor layer 40 and in the groove 41; as Figure 8As shown, the surface of the sacrificial layer 50 on the side away from the substrate 10 is a plane. The material of the sacrificial layer 50 includes one or more combinations of AlN, InN, InGaN, InAlN, InAlGaN, and GaN. The sacrificial layer 50 is an unintentionally doped layer. Impurity elements on the surface of the barrier layer 30 below the groove 41 will diffuse into the sacrificial layer 50, and impurity elements in the epitaxial cavity can also diffuse into the sacrificial layer 50, thereby reducing the impurity elements on the surface of the barrier layer 30 below the groove 41 and in the epitaxial cavity. Optionally, the sacrificial layer 50 is a carbon-doped layer, an iron-doped layer, or an iron-carbon co-doped layer. Further, the carbon doping, iron doping, or iron-carbon co-doping of the sacrificial layer 50 is a graded doping. Doping iron or carbon in the sacrificial layer 50 can form deep-level traps, thereby providing recombination centers to capture holes or electrons on the surface of the barrier layer 30 below the groove 41, thereby reducing the concentration of impurity elements on the surface of the barrier layer 30 below the groove 41 and at the same time reducing the concentration of impurity elements in the epitaxial cavity.
[0045] Step S4: Etch the sacrificial layer.
[0046] Specifically, etch the sacrificial layer 50 to form an intermediate structure as shown in Figure 3 or Figure 4 shown. The method for etching the sacrificial layer 50 is in-situ etching. The in-situ etching method will not introduce impurities, can reduce the interface state density, and is beneficial to reducing the current collapse effect of the device prepared subsequently and reducing the leakage current.
[0047] Repeat steps S3 and S4 N times until the concentration of impurity elements on the surface of the barrier layer 30 below the groove 41 is lower than the preset value. Repeating steps S3 and S4 N times reduces the concentration of impurity elements on the surface of the barrier layer 30 below the groove 41, and at the same time reduces the concentration of impurity elements in the epitaxial cavity, improves the interface quality between the barrier layer 30 and the p-type semiconductor layer 60, further improves the crystal quality of the p-type semiconductor layer 60, thereby reducing the gate leakage current and further improving the stability and reliability of the device.
[0048] Step S5: Grow a p-type semiconductor layer on the n-type semiconductor layer and in the groove.
[0049] Specifically, grow a p-type semiconductor layer 60 on the n-type semiconductor layer 40 and in the groove 41. As shown in Figure 9 shown, the p-type semiconductor layer 60 conformally grows on the n-type semiconductor layer 40 and in the groove 41; as shown in Figure 10As shown, the surface of the p-type semiconductor layer 60 on the side away from the substrate 10 is planar. The p-type semiconductor layer 60 completely covers the n-type semiconductor layer 40. Since the n-type semiconductor layer 40 can perform electron compensation on the channel layer 20, avoiding the influence of surface states on the two-dimensional electron gas, it is not necessary to selectively etch away all parts of the p-type semiconductor material except the gate region, and the device conduction requirements can still be met. The material of the p-type semiconductor layer 60 includes at least one of p-type diamond, p-type NiO, p-type GaN, or p-type polycrystalline GaN.
[0050] Step S6: Etch the n-type semiconductor layer to expose the barrier layer, form a source region and a drain region, set a source electrode in the source region, set a drain electrode in the drain region, and set a gate electrode on the p-type semiconductor layer above the groove.
[0051] Specifically, etch the n-type semiconductor layer 40 to expose the barrier layer 30, form a source region and a drain region, set a source electrode 81 in the source region, set a drain electrode 82 in the drain region, and set a gate electrode 83 on the p-type semiconductor layer 60 above the groove 41 to form a semiconductor structure as Figure 11 shown.
[0052] In the semiconductor structure of the present disclosure, an n-type semiconductor layer 40 is formed on the barrier layer 30, a groove structure 41 is formed in the gate region of the n-type semiconductor layer 40, and a p-type semiconductor layer 60 is provided at the groove 41, so as to achieve the purpose of pinching off the n-type conductive layer under the gate and realize an enhancement-mode switching device. Since the n-type semiconductor layer 40 can perform electron compensation on the channel layer 20, avoiding the influence of surface states on the two-dimensional electron gas, it is not necessary to selectively etch away all parts of the p-type semiconductor material except the gate region, and the device conduction requirements can still be met, reducing the process difficulty and improving the stability and reliability of the device.
[0053] Figures 12a to 12c The following shows a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure. In one embodiment, as Figure 12aAs shown, a first insertion layer 71 can be further disposed on the n-type semiconductor layer 40 before etching the groove 41 in the n-type semiconductor layer 40. The material of the first insertion layer 71 is AlGaN. Optionally, the first insertion layer 71 is an unintentionally doped layer. At the same time, a second insertion layer 72 is disposed between the barrier layer 30 and the n-type semiconductor layer 40, and the second insertion layer 72 is an unintentionally doped layer. The setting of the first insertion layer 71 can, on the one hand, add a discrete energy level between the p-type semiconductor layer 60 and the n-type semiconductor layer 40, adjust the energy band structure, avoid the accumulation of carriers in the device, make the carrier distribution more uniform, and on the other hand, further prevent the holes in the p-type semiconductor layer 60 from affecting the two-dimensional electron gas in the channel layer of the non-gate region, enhance the on-state property of the device, and on the third hand, passivate the surface of the n-type semiconductor layer 40 to play a protective role. The second insertion layer 72 can, on the one hand, further play a role in protecting the underlying barrier layer 30, and on the other hand, also further prevent the holes in the p-type semiconductor layer 60 from affecting the two-dimensional electron gas in the channel layer of the non-gate region, enhance the on-state property of the device. However, it should be understood that in an embodiment of the present invention, according to actual design requirements, it may also only include the first insertion layer 71 (as Figure 12b shown), or only include the second insertion layer 72 (as Figure 12c shown). Optionally, as Figure 12b shown, when only the first insertion layer 71 is included, the method of etching the groove 41 is two-step etching. First, the first insertion layer 71 is dry-etched, and then the n-type semiconductor layer 40 is in-situ etched to form the groove 41. The two-step etching method can further improve the crystal quality of the surface of the groove 41, thereby improving the crystal quality of the p-type semiconductor layer 60 grown in the groove.
[0054] The present disclosure provides a method for manufacturing a semiconductor structure. A channel layer, a barrier layer, and an n-type semiconductor layer are sequentially grown on a substrate; a groove is etched in the n-type semiconductor layer, and the groove penetrates the n-type semiconductor layer; a sacrificial layer is grown on the n-type semiconductor layer and in the groove; the sacrificial layer is etched; a p-type semiconductor layer is grown on the n-type semiconductor layer and in the groove; the growth and etching of the sacrificial layer are repeated multiple times until the concentration of impurity elements on the surface of the barrier layer below the groove is lower than a preset value.
[0055] The present disclosure reduces the concentration of impurity elements on the surface of the barrier layer below the groove by growing and etching the sacrificial layer multiple times, and also reduces the concentration of impurity elements in the epitaxial cavity, improves the interface quality between the barrier layer and the p-type semiconductor layer, further improves the crystal quality of the p-type semiconductor layer, thereby reducing the gate leakage current and further improving the stability and reliability of the device.
[0056] It should be understood that the term "including" and its variants used in this disclosure are open-ended, that is, "including but not limited to". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment". In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.
[0057] The above are only the preferred embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent replacements, etc. made within the spirit and principle of the present disclosure shall be included within the protection scope of the present disclosure.
Claims
1. A manufacturing method of a semiconductor structure, characterized in that, It includes the following steps: S1. Provide a substrate (10), and sequentially grow a channel layer (20), a barrier layer (30), and an n-type semiconductor layer (40) on the substrate (10); S2. Etch a groove (41) on the n-type semiconductor layer (40), and the groove (41) penetrates through the n-type semiconductor layer (40); S3. Grow a sacrificial layer (50) on the n-type semiconductor layer (40) and in the groove (41); S4. Etch the sacrificial layer (50); S5. Grow a p-type semiconductor layer (60) on the n-type semiconductor layer (40) and in the groove (41); Wherein, before entering step S5, repeat steps S3 and S4 for N times until the impurity element concentration on the surface of the barrier layer (30) below the groove (41) is lower than a preset value.
2. The manufacturing method of the semiconductor structure according to claim 1, wherein The groove (41) penetrates through the n-type semiconductor layer (40) and partially penetrates the barrier layer (30).
3. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, The method for etching the groove (41) in step S2 is in-situ etching.
4. The manufacturing method of the semiconductor structure according to claim 3, characterized in that, The in-situ etching is dry etching.
5. The manufacturing method of the semiconductor structure according to claim 3, characterized in that, The gas environment for the etching includes one or a combination of more of Cl2, H2, HCl, and TBCl.
6. The manufacturing method of the semiconductor structure according to claim 3, characterized in that, After in-situ etching to form the groove (41) in step S2, it further includes: Etch the groove (41) a second time, and form a plurality of V-grooves or hexagonal prisms arranged at intervals on the bottom surface of the groove (41).
7. The manufacturing method of the semiconductor structure according to claim 1, wherein, Before etching the groove (41) on the n-type semiconductor layer (40), further provide a first insertion layer (71) on the n-type semiconductor layer (40), and the material of the first insertion layer (71) is AlGaN.
8. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, Further provide a second insertion layer (72) between the barrier layer (30) and the n-type semiconductor layer (40), and the second insertion layer (72) is an unintentionally doped layer.
9. The manufacturing method of the semiconductor structure according to claim 1, wherein, The material of the n-type semiconductor layer (40) includes at least one of n-type GaN, n-type AlGaN, or n-type AlInGaN.
10. The manufacturing method of the semiconductor structure according to claim 1, wherein, The sacrificial layer (50) conformally grows on the n-type semiconductor layer (40) and in the groove (41), or, the surface of the sacrificial layer (50) on the side away from the substrate (10) is a plane.
11. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, The method for etching the sacrificial layer (50) in step S4 is in-situ etching.
12. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, The material of the sacrificial layer (50) includes one or a combination of more of AlN, InN, InGaN, InAlN, InAlGaN, and GaN.
13. The manufacturing method of the semiconductor structure according to claim 12, wherein, The sacrificial layer (50) is an unintentionally doped layer.
14. The manufacturing method of the semiconductor structure according to claim 12, characterized in that, The sacrificial layer (50) is a carbon-doped layer, an iron-doped layer, or an iron-carbon co-doped layer.
15. The manufacturing method of the semiconductor structure according to claim 1, wherein, The p-type semiconductor layer (60) conformally grows on the n-type semiconductor layer (40) and in the groove (41), or, the surface of the p-type semiconductor layer (60) on the side away from the substrate (10) is a plane.
16. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, The material of the p-type semiconductor layer (60) includes at least one of p-type diamond, p-type NiO, p-type GaN, or p-type polycrystalline GaN.
17. The manufacturing method of the semiconductor structure according to claim 1, wherein, The manufacturing method of the semiconductor structure further includes: S6. Etch the n-type semiconductor layer (40) to expose the barrier layer (30), form a source region and a drain region, provide a source electrode (81) in the source region, provide a drain electrode (82) in the drain region, and provide a gate electrode (83) on the p-type semiconductor layer (60) above the groove (41).