Semiconductor device and manufacturing method thereof

Abstract

A manufacturing method includes forming a first anti-reflection pattern on a substrate, forming a photoresist pattern on the first anti-reflection pattern, forming a first polymer pattern on the photoresist pattern, forming a copolymer layer on the first anti-reflection pattern and the first polymer pattern, and performing an annealing process on the copolymer layer, the copolymer layer includes a first polymer and a second polymer different from the first polymer, and the first polymer pattern includes the first polymer.

Description

[0001] This patent application claims priority to Korean Patent Application No. 10-2024-0001697, filed with the Korean Intellectual Property Office on January 4, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The inventive concept relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a field effect transistor and a method of manufacturing the same. Background Art

[0003] A semiconductor device may include an integrated circuit including a metal oxide semiconductor field effect transistor (MOSFET). To meet the growing demand for semiconductor devices with small pattern sizes and reduced design rules, MOSFETs are being aggressively scaled down. The scaling down of MOSFETs may lead to a degradation in the operating performance of semiconductor devices. Various studies are underway to overcome the technical limitations associated with the scaling down of semiconductor devices and to achieve high-performance semiconductor devices. Summary of the Invention

[0004] Some aspects of the inventive concept provide a semiconductor device having improved reliability and electrical characteristics.

[0005] Some aspects of the inventive concept provide a method of manufacturing a semiconductor device having improved reliability and electrical characteristics.

[0006] According to some embodiments of the inventive concept, a method of manufacturing a semiconductor device includes: forming a first anti-reflection pattern on a substrate; forming a photoresist pattern on the first anti-reflection pattern; forming a first polymer pattern on the photoresist pattern; forming a copolymer layer on the first anti-reflection pattern and the first polymer pattern; and performing an annealing process on the copolymer layer, wherein the copolymer layer includes a first polymer and a second polymer different from the first polymer, and the first polymer pattern includes the first polymer.

[0007] According to some embodiments of the inventive concept, a method of manufacturing a semiconductor device includes: forming an anti-reflection pattern and a photoresist layer sequentially stacked on a substrate; irradiating the photoresist layer with extreme ultraviolet light to form a photoresist pattern; forming a first polymer pattern on the photoresist pattern; forming a copolymer layer covering a first material region on the first polymer pattern and a second material region on the anti-reflection pattern; and performing an annealing process on the copolymer layer, wherein one of the first material region and the second material region is polar and the other is non-polar.

[0008] According to some embodiments of the inventive concept, a method of manufacturing a semiconductor device includes: forming a transistor on a substrate and forming a first wiring layer on the transistor, wherein forming the first wiring layer includes: forming an interlayer insulating layer, a first anti-reflection pattern, and a photoresist pattern that are sequentially stacked on the transistor; forming a first polymer pattern on the photoresist pattern; forming a copolymer layer on the first anti-reflection pattern and the first polymer pattern, the copolymer layer including a first polymer and a second polymer that are different from each other; and performing phase separation on the copolymer layer, performing phase separation on the copolymer layer including aligning the first polymer vertically on the first polymer pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Example embodiments will be understood more clearly from the following brief description taken in conjunction with the accompanying drawings. The drawings represent non-limiting example embodiments described herein.

[0010] Figure 1 is a schematic diagram showing an EUV exposure apparatus according to an embodiment of the inventive concept.

[0011] Figures 2 to 8 is a cross-sectional view for explaining a lithography process according to an embodiment of the inventive concept.

[0012] Figures 9A to 9D is a cross-sectional view for explaining a lithography process according to another embodiment of the inventive concept.

[0013] Figure 10 is a plan view of a semiconductor device according to an embodiment of the inventive concept.

[0014] Figures 11A to 11D are cross-sectional views taken along lines A-A', B-B', C-C', and D-D' of Figure 10 respectively.

[0015] Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figures 14A to 14C , Figures 15A to 15D , Figures 16A to 16C and Figures 17A to 17C are cross-sectional views for explaining a method of manufacturing a semiconductor device according to an embodiment of the inventive concept.

[0016] Figures 18 to 25 is a cross-sectional view for explaining a method of forming a Figure 11D semiconductor device. DETAILED DESCRIPTION

[0017] Hereinafter, to describe the inventive concept in detail, embodiments according to the inventive concept will be described with reference to the accompanying drawings.

[0018] Throughout this specification, when a component is described as "including" a particular element or group of elements, it should be understood that the component is formed only by that element or group of elements, or that the element or group of elements may be combined with other elements to form the component, unless the context clearly and / or expressly describes the contrary. On the other hand, the term "consisting of" means that the component is formed only by the listed elements.

[0019] Ordinal numbers such as "first", "second", "third", etc. may simply be used as labels for certain elements, steps, etc. to distinguish these elements, steps, etc. from each other. Terms not described using "first", "second", etc. in the specification may still be referred to as "first" or "second" in the claims. Additionally, a term referred to by a particular ordinal number (e.g., "first" in a particular claim) may be described elsewhere by a different ordinal number (e.g., "second" in the specification or another claim).

[0020] It will be understood that when an element is referred to as "connected" or "coupled" to another element or "on" another element, the element may be directly connected or coupled to the other element or directly on the other element, or there may be intervening elements. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element or "contacting" another element or "in contact with" another element (or any form of the word "contact"), there are no intervening elements at the point of contact. Other words used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" and "directly between", "adjacent" and "directly adjacent", etc.).

[0021] Figure 1 is a schematic diagram showing an EUV exposure apparatus according to an embodiment of the inventive concept. Refer to Figure 1 , the EUV exposure apparatus EPA may include a light source unit 10, a condenser unit 20, a projection unit 40, and a control unit 90. The light source unit 10, also referred to as a light source, may generate extreme ultraviolet (EUV) light, such as light having a wavelength of 4 nm to 124 nm. In one embodiment, the light source unit 10 may generate EUV light, such as light having a wavelength of 13.5 nm. The light source unit 10 may generate light having an energy of 6.21 eV to 124 eV (particularly 90 eV to 95 eV).

[0022] The light source unit 10 generates EUV light, but may undesirably generate DUV light, such as light having a wavelength of 100 nm or greater and 300 nm or less. The condenser unit 20 is configured to guide the light 11 generated by the light source unit 10 such that the light is reflected by a reflective mask MA mounted on a mask stage 32.

[0023] The condenser unit 20 includes a condenser optical device 22, such as a lens or a mirror. The condenser optical device 22 collects and reflects the light 11 and guides the light 11 to the reflection mask MA. The light 11 may be incident obliquely on the reflection mask MA through the condenser unit 20. The mask stage 32 may move the reflection mask MA according to the scanning direction of the reflection mask MA. The light source unit 10 and the mask stage 32 may be controlled by the control unit 90.

[0024] The light 11 incident on the reflection mask MA may be reflected by the reflection mask MA and may be incident obliquely on the projection unit 40. The projection unit 40 is configured to project a mask pattern (absorption pattern) of the reflection mask MA onto a substrate SUB located on the substrate stage 52. For example, the substrate SUB may be a silicon wafer on which an integrated circuit is formed. The substrate SUB is coated with a photoresist capable of reacting to light. The substrate stage 52 may move the substrate SUB to change the exposure area (or exposure position) of the substrate SUB.

[0025] The projection unit 40 includes a reflective projection optical device 42, such as a lens. The reflective projection optical device 42 reduces the mask pattern on the reflection mask MA by a certain magnification, such as 4 times, 6 times, or 8 times, using the light 11 obliquely reflected from the reflection mask MA and projects it onto the substrate SUB.

[0026] In this case, a patterning process may be performed using the mask pattern of the reflection mask MA to form a desired pattern on the wafer. According to an embodiment of the inventive concept, the patterning process may include a lithography process using extreme ultraviolet (EUV). In the present specification, extreme ultraviolet (EUV) may refer to ultraviolet light having a wavelength of 4 nm to 124 nm (specifically 4 nm to 20 nm, and more specifically 13.5 nm). Extreme ultraviolet (EUV) may refer to light having an energy of 6.21 eV to 124 eV (specifically 90 eV to 95 eV).

[0027] The lithography process using extreme ultraviolet (EUV) may include an exposure and development process using extreme ultraviolet (EUV) irradiated onto the photoresist layer. As an example, the photoresist layer may include a metal oxide.

[0028] The photoresist layer may be formed to have a relatively thin thickness. The photoresist pattern may be formed by developing the photoresist layer exposed to extreme ultraviolet (EUV). The photoresist pattern may be a metal oxide resist (MOR). When observed in a two-dimensional perspective view, the photoresist pattern may have a linear shape, an island shape, a zigzag shape, a honeycomb shape, or a circular shape extending in one direction, but is not limited thereto.

[0029] A mask pattern may be formed by patterning a photoresist pattern into an etch mask and one or more mask layers stacked thereunder. The mask pattern may be used as an etch mask to pattern a target layer, whereby a desired pattern may be formed on a wafer.

[0030] Figures 2 to 8 is a cross-sectional view for explaining a lithography process according to an embodiment of the inventive concept.

[0031] Reference Figure 2 , a substrate 10 may be provided. The substrate 10 is not particularly limited, but may be a semiconductor wafer, such as a silicon wafer. A first anti-reflection pattern AF1 and a second anti-reflection pattern AF2 may be formed on the substrate 10. The second anti-reflection pattern AF2 may be interposed between the substrate 10 and the first anti-reflection pattern AF1. For example, the first anti-reflection pattern may be a bottom anti-reflection coating (BARC). The second anti-reflection pattern may be spin-on carbon (SOC).

[0032] The first anti-reflection pattern AF1 and the second anti-reflection pattern AF2 are disposed under the photoresist pattern PR to prevent diffuse reflection of light passing through the photoresist pattern PR and to prevent collapse of the photoresist pattern PR. The first anti-reflection pattern AF1 and the second anti-reflection pattern AF2 may be omitted.

[0033] A photoresist layer PRF may be formed on the first anti-reflection pattern AF1. The photoresist layer PRF may include a photosensitive compound and a synthetic resin capable of being exposed and developed by extreme ultraviolet (EUV) exposure. The photoresist layer PRF may include a metal oxide. The thickness of the photoresist layer PRF may be greater than the respective thicknesses of the first anti-reflection pattern AF1 and the second anti-reflection pattern AF2, and may be greater than the total thickness of the first anti-reflection pattern AF1 and the second anti-reflection pattern AF2.

[0034] An exposure process using extreme ultraviolet (EUV) may be performed on the photoresist layer PRF. As an example, the extreme ultraviolet (EUV) may have a wavelength of about 13.5 nm, which allows for the implementation of fine pitch patterns.

[0035] Reference Figure 3 , the photoresist layer PRF exposed to extreme ultraviolet (EUV) may be developed to form a photoresist pattern PR. The photoresist pattern PR may have the same line width LW for each other. The same spacing SPA may be provided between the photoresist patterns PR.

[0036] The photoresist patterns PR may be arranged in a first direction D1 at a constant pitch PI. The sum of the line width LW and the spacing SPA is defined as the pitch PI. For example, the pitch PI may be 22 nm to 26 nm. The line width LW and the pitch PI may vary differently depending on the type of illumination system used in the EUV lithography process.

[0037] ReferenceFigure 4 A first polymer layer PMF1 can be formed on the photoresist pattern PR and the first anti-reflection pattern AF1. The first polymer layer PMF1 can cover the upper surface and sidewalls of the photoresist pattern PR. The first polymer layer PMF1 can cover the upper surface of the first anti-reflection pattern AF1 exposed by the photoresist pattern PR.

[0038] Reference Figure 5 The first polymer layer PMF1 can be etched to form a first polymer pattern PM1 on the upper surface of the photoresist pattern PR. The line width of the first polymer pattern PM1 can be substantially the same as the line width of the photoresist pattern PR. A first material region can be formed on the surface of the first polymer pattern PM1. A second material region can be formed on the surface of the first anti-reflection pattern AF1. One of the first material region and the second material region can be polar, while the other can be non-polar. For example, since the first polymer pattern PM1 is non-polar, the first material region can be non-polar, and since the photoresist pattern PR is polar, the second material region can be polar.

[0039] The first polymer pattern PM1 can include a first upper surface UW1. As the first polymer layer PMF1 is etched, a second upper surface UW2 of the first anti-reflection pattern can be exposed. The first polymer layer PMF1 can include a material having a selective etching rate relative to the first anti-reflection pattern. The second upper surface UW2 can be disposed between adjacent photoresist patterns PR.

[0040] The level of the first upper surface UW1 (e.g., the vertical height above the top surface of the substrate 10) can be higher than the level of the second upper surface UW2. One of the first upper surface UW1 and the second upper surface UW2 can be polar, and the other can be non-polar. For example, the first upper surface UW1 can be non-polar, and the second upper surface UW2 can be polar. The first polymer pattern PM1 can include a first polymer. The first polymer can be a hydrophobic polymer. When the first polymer is a non-polar polymer, the first upper surface UW1 can be non-polar.

[0041] Reference Figure 6 A copolymer layer BCP can be formed on the first polymer pattern PM1 and the first anti-reflection pattern AF1. The copolymer layer BCP can cover the first upper surface UW1, the second upper surface UW2, and the sidewalls of the photoresist pattern PR.

[0042] The copolymer layer BCP may include a first polymer and a second polymer. The first polymer and the second polymer may be different polymers. For example, one of the first polymer and the second polymer may be polar and the other may be non-polar. For example, the first polymer may be polystyrene (PS), and the second polymer may be polymethyl methacrylate (PMMA).

[0043] Reference Figure 7 , the copolymer layer BCP can be phase-separated by performing an annealing process on the copolymer layer BCP. A directed self-assembly (DSA) process can be performed on the copolymer layer BCP. The copolymer layer BCP can be separated into the first polymer and the second polymer by the annealing process. The first extended pattern EP1 and the second extended pattern EP2 can be formed by the annealing process. Specifically, the first polymer can be aligned in the vertical direction D3 on the first upper surface UW1 of the first polymer pattern PM1 to form the first extended pattern EP1. The second polymer can be aligned in the vertical direction D3 on the second upper surface UW2 to form the second extended pattern EP2. Aligning each polymer means changing the structure of the polymer to have a more crystalline arrangement, which can result in a reduction in stress within the material.

[0044] The first extended pattern EP1 may include the first polymer, and the second extended pattern EP2 may include the second polymer. During the annealing process, the first polymer of the copolymer layer BCP can be aligned on the first upper surface UW1, and the second polymer can be aligned on the second upper surface UW2. For example, since the second extended pattern EP2 includes the polar second polymer, the second extended pattern EP2 can be aligned on the polar second upper surface UW2.

[0045] The line width of the first extended pattern EP1 may be substantially the same as the line width of the photoresist pattern PR and the line width of the first polymer pattern PM1. The second extended pattern EP2 can be formed between adjacent photoresist patterns PR.

[0046] Reference Figure 8 , the second extended pattern EP2 can be selectively removed by performing an etching process. The etching process may have different etching rates for the first polymer and the second polymer. The pitch of the first extended pattern EP1 may be substantially the same as the pitch SPA of the photoresist pattern PR.

[0047] According to an aspect of the inventive concept, the first polymer pattern PM1 and the first extended pattern EP1 can be formed on the photoresist pattern PR, such that the photoresist pattern PR extends in the vertical direction D3. Thus, even when some of the photoresist patterns PR are damaged or tilted, they can be corrected by the first extended pattern EP1.

[0048] In addition, according to an aspect of the inventive concept, by forming the first polymer pattern PM1, the first extension pattern EP1 and the second extension pattern EP2 can be more stably aligned during the annealing process. Since the first polymer pattern PM1 is formed on the photoresist pattern PR, the DSA process can be performed without a process of etching the photoresist pattern PR.

[0049] Figures 9A to 9D is a cross-sectional view for explaining a photolithography process according to another embodiment of the inventive concept. After the process according to Figures 1 to 5 , the process according to Figures 9A to 9D can be subsequently performed.

[0050] Referring to Figure 9A , the second polymer layer PMF2 can be formed on the first polymer pattern PM1 and the first antireflection pattern AF1. The second polymer layer PMF2 can cover the first upper surface UW1, the second upper surface UW2, and the sidewalls of the photoresist pattern PR.

[0051] The second polymer layer PMF2 can include a second polymer. The second polymer can be a polymer different from the first polymer of the first polymer pattern PM1. For example, the first polymer can be polystyrene (PS), and the second polymer can be polymethyl methacrylate (PMMA).

[0052] Referring to Figure 9B , the second polymer layer PMF2 can be etched to form the second polymer pattern PM2. As the second polymer layer PMF2 is etched, the first upper surface UW1 can be exposed again. The second polymer pattern PM2 can be formed on the Figure 9A second upper surface UW2. The second polymer pattern PM2 can be formed between the photoresist patterns PR.

[0053] The second polymer pattern PM2 can include a third upper surface UW3. The level of the third upper surface UW3 can be lower than or equal to the level of the first upper surface UW1. One of the first upper surface UW1 and the third upper surface UW3 can be polar, and the other can be nonpolar. For example, since the first polymer pattern PM1 includes the first polymer as a nonpolar polymer, the first upper surface UW1 can be nonpolar. Since the second polymer pattern PM2 includes the second polymer as a polar polymer, the third upper surface UW3 can be polar.

[0054] Referring to Figure 9C , the copolymer layer BCP can be formed on the first polymer pattern PM1 and the second polymer pattern PM2. The copolymer layer BCP can cover the first upper surface UW1, the third upper surface UW3, and the sidewalls of the photoresist pattern PR. Figure 9CThe formation of the copolymer layer BCP can be the same as that of Figure 6 the copolymer layer BCP.

[0055] Refer to Figure 9D , and the copolymer layer BCP can be phase-separated by performing an annealing process on the BCP. Figure 9D The annealing process of Figure 7 can be substantially the same as that of Figure 7 . Through the annealing process, the first polymer can be aligned in the vertical direction D3 on the first upper surface UW1 of the first polymer pattern PM1 to form the first extended pattern EP1. Through the annealing process, the second polymer can be aligned in the vertical direction D3 on the third upper surface UW3 to form the second extended pattern EP2.

[0056] Refer to Figures 9A to 9D , and the second polymer pattern PM2 can be further formed between the photoresist patterns PR. This is to form both the first polymer pattern PM1 and the second polymer pattern PM2 to further improve the alignment of each of the first polymer and the second polymer during the annealing process.

[0057] Figure 10 is a plan view of a semiconductor device for explaining an embodiment according to the inventive concept. Figures 11A to 11D are cross-sectional views taken along lines A-A', B-B', C-C', and D-D' of Figure 10 respectively. Figure 10 and Figures 11A to 11D are examples showing the semiconductor device in detail.

[0058] Refer to Figure 10 and Figures 11A to 11D , a single-height cell SHC is provided on the substrate 100. Logic transistors constituting a logic circuit can be provided on the single-height cell SHC. The substrate 100 can be a semiconductor substrate including silicon, germanium, silicon germanium, etc., or a compound semiconductor substrate. As an example, the substrate 100 can be a silicon substrate.

[0059] The substrate 100 can include a first active region AR1 and a second active region AR2. Each of the first active region AR1 and the second active region AR2 can extend along the second direction D2. In one embodiment, the first active region AR1 can be an NMOSFET region, and the second active region AR2 can be a PMOSFET region.

[0060] The first active pattern AP1 and the second active pattern AP2 may be defined by a trench TR formed on top of a substrate 100. The first active pattern AP1 may be disposed on a first active region AR1, and the second active pattern AP2 may be disposed on a second active region AR2. The first active pattern AP1 and the second active pattern AP2 may extend in a second direction D2. The first active pattern AP1 and the second active pattern AP2 may be part of the substrate 100 and may be vertically protruding portions.

[0061] A device isolation layer ST may be disposed on the substrate 100. The device isolation layer ST may fill the trench TR. The device isolation layer ST may include a silicon oxide layer. In one embodiment, the device isolation layer ST does not cover a first channel pattern CH1 and a second channel pattern CH2, which will be described later.

[0062] The first channel pattern CH1 may be disposed on the first active pattern AP1. The second channel pattern CH2 may be disposed on the second active pattern AP2. Each of the first channel pattern CH1 and the second channel pattern CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 stacked in sequence. The first semiconductor pattern to the third semiconductor pattern SP1, SP2, and SP3 may be spaced apart from each other in a vertical direction (i.e., a third direction D3).

[0063] Each of the first semiconductor pattern to the third semiconductor pattern SP1, SP2, and SP3 may include silicon (Si), germanium (Ge), or silicon germanium (SiGe). For example, each of the first semiconductor pattern to the third semiconductor pattern SP1, SP2, and SP3 may include crystalline silicon. In one embodiment of the inventive concept, the first semiconductor pattern to the third semiconductor pattern SP1, SP2, and SP3 may be stacked nanosheets.

[0064] A plurality of first source / drain patterns SD1 may be disposed on the first active pattern AP1. A plurality of first recesses RS1 may be formed on the first active pattern AP1. The first source / drain patterns SD1 may be respectively disposed in the first recesses RS1. The first source / drain patterns SD1 may be impurity regions of a second conductivity type (e.g., p-type). The first channel pattern CH1 may be interposed between a pair of first source / drain patterns SD1. For example, the stacked first semiconductor pattern to the third semiconductor pattern SP1, SP2, and SP3 may connect a pair of first source / drain patterns SD1 to each other.

[0065] A plurality of second source / drain patterns SD2 may be disposed on the second active pattern AP2. A plurality of second recesses RS2 may be formed on the second active pattern AP2. The second source / drain patterns SD2 may be respectively disposed in the second recesses RS2. The second source / drain patterns SD2 may be impurity regions of a first conductivity type (e.g., n-type). The second channel pattern CH2 may be interposed between a pair of second source / drain patterns SD2. For example, the stacked first semiconductor pattern to the third semiconductor pattern SP1, SP2, and SP3 may connect a pair of second source / drain patterns SD2 to each other.

[0066] The first source / drain pattern SD1 and the second source / drain pattern SD2 may be epitaxial patterns formed by a selective epitaxial growth (SEG) process. For example, the upper surface of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be higher than the upper surface of the third semiconductor pattern SP3. As another example, the upper surface of at least one of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be located at substantially the same level as the upper surface of the third semiconductor pattern SP3.

[0067] In an embodiment of the inventive concept, the first source / drain pattern SD1 may include a semiconductor element (e.g., SiGe) having a lattice constant greater than that of the semiconductor element of the substrate 100. Accordingly, a pair of first source / drain patterns SD1 may provide compressive stress to the first channel pattern CH1 therebetween. The second source / drain pattern SD2 may include the same semiconductor element as the semiconductor element of the substrate 100 (e.g., Si).

[0068] The sidewalls of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may have an uneven relief shape. For example, the sidewalls of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may have a wavy profile. The sidewalls of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may protrude toward the first to third portions PO1, PO2, and PO3 of the gate electrode GE to be described later.

[0069] The gate electrode GE may be disposed to cross the first channel pattern CH1 and the second channel pattern CH2 and extend along the first direction D1. The gate electrode GE may be arranged along the second direction D2 and may have a first pitch. Each gate electrode GE may vertically overlap the first channel pattern CH1 and the second channel pattern CH2.

[0070] The gate electrode GE may include a first portion PO1 between the active pattern AP1 or AP2 and the first semiconductor pattern SP1, a second portion PO2 between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a third portion PO3 between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and a fourth portion PO4 on the third semiconductor pattern SP3.

[0071] Referring to Figure 11D , the gate electrode GE may be disposed on the top surface TS, the bottom surface BS, and the two sidewalls SW of each of the first to third semiconductor patterns SP1, SP2, and SP3. For example, the transistor according to the present embodiment may be a three-dimensional field-effect transistor in which the gate electrode GE surrounds the channel three-dimensionally (e.g., MBCFET or GAAFET).

[0072] Referring again to Figure 10 and Figures 11A to 11D , a pair of gate spacers GS may be disposed on opposite sidewalls of the fourth portion PO4 of each gate electrode GE. The gate spacer GS may extend along the gate electrode GE in the first direction D1. The upper surface of the gate spacer GS may be higher than the upper surface of the gate electrode GE. The upper surface of the gate spacer GS may be coplanar with the upper surface of the first interlayer insulating layer 110 to be described later. In one embodiment, the gate spacer GS may include at least one of SiCN, SiCON, and SiN. In another embodiment, the gate spacer GS may include a multi-layer formed of at least two of SiCN, SiCON, and SiN.

[0073] The gate capping pattern GP may be disposed on the gate electrode GE. The gate capping pattern GP may extend along the gate electrode GE in the first direction D1. The gate capping pattern GP may include a material having an etching selectivity with respect to the first interlayer insulating layer 110 and the second interlayer insulating layer 120 to be described later. Specifically, the gate capping pattern GP may include at least one of SiON, SiCN, SiCON, and SiN.

[0074] The gate insulating layer GI may be interposed between the gate electrode GE and the first channel pattern CH1 and between the gate electrode GE and the second channel pattern CH2. The gate insulating layer GI may cover the top surface TS, the bottom surface BS, and the two sidewalls SW of each of the first to third semiconductor patterns SP1, SP2, and SP3. The gate insulating layer GI may cover the upper surface of the device isolation layer ST under the gate electrode GE.

[0075] Referring again to Figure 10 and Figures 11A to 11D, the gate electrode GE may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern may be disposed on the gate insulating layer GI and adjacent to the first semiconductor pattern to the third semiconductor patterns SP1, SP2, and SP3. The first metal pattern may include a work function metal for adjusting the threshold voltage of the transistor. By adjusting the thickness and composition of the first metal pattern, a desired threshold voltage of the transistor can be achieved. For example, the first part to the third part PO1, PO2, and PO3 of the gate electrode GE may be constituted by the first metal pattern as the work function metal.

[0076] The first metal pattern may include a metal nitride layer. For example, the first metal pattern may include nitrogen (N) and at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo). In addition, the first metal pattern may further include carbon (C). The first metal pattern may include a plurality of stacked work function metal layers.

[0077] The second metal pattern may include a metal having a lower resistance than the first metal pattern. For example, the second metal pattern may include at least one metal selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta). For example, the fourth part PO4 of the gate electrode GE may include the first metal pattern and the second metal pattern on the first metal pattern.

[0078] A first interlayer insulating layer 110 may be disposed on the substrate 100. The first interlayer insulating layer 110 may cover the gate spacer GS and the first source / drain pattern SD1 and the second source / drain pattern SD2. The upper surface of the first interlayer insulating layer 110 may be substantially coplanar with the upper surface of the gate capping pattern GP and the upper surface of the gate spacer GS. A second interlayer insulating layer 120 may be disposed on the first interlayer insulating layer 110 to cover the gate capping pattern GP. A third interlayer insulating layer 130 may be disposed on the second interlayer insulating layer 120. A fourth interlayer insulating layer 140 may be disposed on the third interlayer insulating layer 130. As an example, the first interlayer insulating layer 110 to the fourth interlayer insulating layer 140 may include a silicon oxide layer.

[0079] The single-height cell SHC may have a first boundary BD1 and a second boundary BD2 that are opposite to each other in the second direction D2. The first boundary BD1 and the second boundary BD2 may extend along the first direction D1. The single-height cell SHC may have a third boundary BD3 and a fourth boundary BD4 that are opposite to each other in the first direction D1. The third boundary BD3 and the fourth boundary BD4 may extend along the second direction D2.

[0080] A pair of isolation structures DB that face each other in the second direction D2 may be provided on opposite sides of the single-height cell SHC. For example, the pair of isolation structures DB may be provided on the first boundary BD1 and the second boundary BD2 of the single-height cell SHC, respectively. The isolation structure DB may extend in the first direction D1 parallel to the first gate electrode GE1 and the second gate electrode GE2. The pitch between the isolation structure DB and the adjacent first gate electrode GE1 and second gate electrode GE2 may be the same as the first pitch.

[0081] The isolation structure DB may pass through the first interlayer insulating layer 110 and the second interlayer insulating layer 120 and extend into the first active pattern AP1 and the second active pattern AP2. The isolation structure DB may penetrate the upper portions of each of the first active pattern AP1 and the second active pattern AP2. The isolation structure DB may electrically isolate the active region of the single-height cell SHC from the active regions of other adjacent cells.

[0082] The active contact AC may be provided to pass through the first interlayer insulating layer 110 and the second interlayer insulating layer 120, and may be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively. A pair of active contacts AC may be provided on both sides of the gate electrode GE. When observed in a plan view, the active contact AC may have a bar shape extending in the first direction D1.

[0083] The active contact AC may be a self-aligned contact. That is, the active contact AC may be formed in a self-aligned manner using the gate capping pattern GP and the gate spacer GS. For example, the active contact AC may cover at least a part of the sidewall of the gate spacer GS. Although not shown, the active contact AC may cover a part of the upper surface of the gate capping pattern GP.

[0084] A metal-semiconductor compound layer SC, such as a silicide layer, may be inserted between the active contact AC and the first source / drain pattern SD1 and between the active contact AC and the second source / drain pattern SD2, respectively. The active contact AC may be electrically connected to the source / drain patterns SD1 and SD2 through the metal-semiconductor compound layer SC. For example, the metal-semiconductor compound layer SC may include at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

[0085] The gate contact GC may be provided to pass through the second interlayer insulating layer 120 and the gate capping pattern GP, and may be electrically connected to the gate electrode GE, respectively. When observed in a plan view, the gate contact GC may be arranged to overlap the first active region AR1 and the second active region AR2, respectively. As an example, the gate contact GC may be provided on the second active pattern AP2 (see Figure 11B ).

[0086] In one embodiment of the inventive concept, referring to Figure 11B , the upper portion of the active contact AC directly adjacent to the gate contact GC may be filled with an upper insulating pattern UIP. The bottom surface of the upper insulating pattern UIP may be lower than the bottom surface of the gate contact GC. The upper surface of the active contact AC adjacent to the gate contact GC may be lower than the bottom surface of the gate contact GC, and the upper insulating pattern UIP fills the vertical space therebetween. Accordingly, a short circuit may be prevented when the gate contact GC contacts the adjacent active contact AC.

[0087] Each of the active contact AC and the gate contact GC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM may include at least one metal selected from aluminum, copper, tungsten, molybdenum, and cobalt. The barrier pattern BM may cover sidewalls and a bottom surface of the conductive pattern FM. The barrier pattern BM may include a metal layer / metal nitride layer. The metal layer may include at least one of titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer may include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0088] A first metal layer M1 may be disposed in the third interlayer insulating layer 130. For example, the first metal layer M1 may include a first power supply wiring M1_R1, a second power supply wiring M1_R2, and a first wiring M1_I. Each of the wirings M1_R1, M1_R2, and M1_I of the first metal layer M1 may extend parallel to each other in a second direction D2.

[0089] Specifically, the first power supply wiring M1_R1 and the second power supply wiring M1_R2 may be disposed on a third boundary BD3 and a fourth boundary BD4 of a single-height unit SHC, respectively. The first power supply wiring M1_R1 may extend in the second direction D2 in the third boundary BD3. The second power supply wiring M1_R2 may extend in the second direction D2 in the fourth boundary BD4.

[0090] The first wiring M1_I of the first metal layer M1 may be disposed between the first power supply wiring M1_R1 and the second power supply wiring M1_R2. The first wiring M1_I of the first metal layer M1 may be arranged at a second pitch in a first direction D1. The second pitch may be smaller than the first pitch. The line width of each of the first wirings M1_I may be smaller than the line width of each of the first power supply wiring M1_R1 and the second power supply wiring M1_R2.

[0091] The first metal layer M1 may further include a first via VI. The first via VI may be respectively disposed below the wirings M1_R1, M1_R2, and M1_I of the first metal layer M1. The active contact AC and the wirings of the first metal layer M1 may be electrically connected to each other through the first via VI. The gate contact GC and the wirings of the first metal layer M1 may be electrically connected to each other through the first via VI.

[0092] The second metal layer M2 may be disposed in the fourth interlayer insulating layer 140. The second metal layer M2 may include a plurality of second wirings M2_I. Each second wiring M2_I of the second metal layer M2 may have a linear or strip shape extending along the first direction D1. The second wirings M2_I may extend parallel to each other along the first direction D1.

[0093] The second metal layer M2 may further include second vias VI2 respectively disposed below the second wirings M2_I. The wirings of the first metal layer M1 and the wirings of the second metal layer M2 may be electrically connected to each other through the second vias VI2. For example, the wirings of the second metal layer M2 and the second vias VI2 therebelow may be formed together by a dual damascene process.

[0094] The wirings of the first metal layer M1 and the wirings of the second metal layer M2 may include the same or different conductive materials. For example, the wirings of the first metal layer M1 and the wirings of the second metal layer M2 may include at least one metal material selected from aluminum, copper, tungsten, molybdenum, ruthenium, and cobalt. Although not shown, metal layers (e.g., M3, M4, M5...) stacked on the fourth interlayer insulating layer 140 may be additionally provided. Each of the stacked metal layers may include wirings for constructing lines between cells.

[0095] Figures 12A to 17C is for illustrating a cross-sectional view of a method of manufacturing a semiconductor device as shown Figure 10 in accordance with an embodiment of the inventive concept. Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A and Figure 17A is a cross-sectional view taken along line A-A'. Figure 15B is a cross-sectional view taken along line B-B'. Figure 14B , Figure 15C , Figure 16B and Figure 17B is a cross-sectional view taken along line C-C'. Figure 12B , Figure 13B , Figure 14C , Figure 15D , Figure 16C and Figure 17C is a cross-sectional view taken along line D-D'.

[0096] Refer toFigure 12A and Figure 12B A substrate 100 including a first active region AR1 and a second active region AR2 can be provided. An active layer ACL and a sacrificial layer SAL can be alternately stacked on the substrate 100. The active layer ACL can include one of silicon (Si), germanium (Ge), and silicon germanium (SiGe), and the sacrificial layer SAL can include the other of silicon (Si), germanium (Ge), and silicon germanium (SiGe).

[0097] The sacrificial layer SAL can include a material having an etching selectivity with respect to the active layer ACL. For example, the active layer ACL can include silicon (Si), and the sacrificial layer SAL can include silicon germanium (SiGe). The germanium (Ge) concentration in each sacrificial layer SAL can be 10 at% to 30 at%.

[0098] Mask patterns can be respectively formed on the first active region AR1 and the second active region AR2 of the substrate 100. A patterning process can be performed using the mask patterns as an etching mask to form trenches TR defining a first active pattern AP1 and a second active pattern AP2. A detailed description of the patterning process will be described later. The first active pattern AP1 can be formed on the first active region AR1. The second active pattern AP2 can be formed on the second active region AR2.

[0099] A stacked pattern STP can be formed on each of the first active pattern AP1 and the second active pattern AP2. The stacked pattern STP can include an active layer ACL and a sacrificial layer SAL alternately stacked with each other. The stacked pattern STP can be formed together with the first active pattern AP1 and the second active pattern AP2 during the patterning process.

[0100] A device isolation layer ST can be formed to fill the trenches TR. Specifically, an insulating layer can be formed on the entire surface of the substrate 100 to cover the first active pattern AP1, the second active pattern AP2, and the stacked pattern STP. The insulating layer can be recessed until the stacked pattern (STP) is exposed to form the device isolation layer ST.

[0101] The device isolation layer ST can include an insulating material, such as a silicon oxide layer. The stacked pattern STP can be exposed on the device isolation layer ST. The stacked pattern STP can protrude vertically above the device isolation layer ST.

[0102] Reference Figure 13A and Figure 13B A sacrificial pattern PP can be formed across the stacked pattern STP on the substrate 100. Each sacrificial pattern PP can be formed in a linear or strip shape extending along a first direction D1. The sacrificial patterns PP can be arranged at a first pitch along a second direction D2.

[0103] Specifically, forming the sacrificial pattern PP may include forming a sacrificial layer on the entire surface of the substrate 100, forming a hard mask pattern MP on the sacrificial layer, and patterning the sacrificial layer using the hard mask pattern MP as an etch mask. The sacrificial layer may include polysilicon.

[0104] A pair of gate spacers GS may be formed on opposite sidewalls of each sacrificial pattern PP. Forming the gate spacers GS may include conformally forming a gate spacer layer on the entire surface of the substrate 100 and anisotropically etching the gate spacer layer.

[0105] Reference Figures 14A to 14C , a first recess RS1 may be formed in the stacked pattern STP on the first active pattern AP1. A second recess RS2 may be formed in the stacked pattern STP on the second active pattern AP2. While forming the first recess RS1 and the second recess RS2, the device isolation layer ST on both sides of the first active pattern AP1 and the second active pattern AP2 may be further recessed (reference Figure 14B ).

[0106] Specifically, the stacked pattern STP on the first active pattern AP1 may be etched using the hard mask pattern MP and the gate spacers GS as etch masks to form the first recess RS1. The first recess RS1 may be formed between a pair of sacrificial patterns PP. Forming the first recess RS1 may include additionally performing a selective etching process on the exposed sacrificial layer SAL. Accordingly, the first recess RS1 may have a wavy inner wall.

[0107] The second recess RS2 in the stacked pattern STP on the second active pattern AP2 may be formed in the same manner as the first recess RS1. However, forming the second recess RS2 may further include forming an inner spacer IP in the region where the sacrificial layer SAL is recessed. As a result, the inner wall of the second recess RS2 may not have a wavy shape like the inner wall of the first recess RS1.

[0108] The first semiconductor pattern to the third semiconductor patterns SP1, SP2, and SP3 sequentially stacked between adjacent first recesses RS1 may be formed of the active layer ACL, respectively. The first semiconductor pattern to the third semiconductor patterns SP1, SP2, and SP3 sequentially stacked between adjacent second recesses RS2 may be formed of the active layer ACL, respectively. The first semiconductor pattern to the third semiconductor patterns SP1, SP2, and SP3 between adjacent first recesses RS1 may form a first channel pattern CH1. The first semiconductor pattern to the third semiconductor patterns SP1, SP2, and SP3 between adjacent second recesses RS2 may form a second channel pattern CH2.

[0109] Reference Figures 15A to 15D, the first source / drain pattern SD1 may be respectively formed in the first recess RS1. Specifically, a SEG process using the inner wall of the first recess RS1 as a seed layer may be performed to form an epitaxial layer filling the first recess RS1. The epitaxial layer may be grown using the first semiconductor pattern to the third semiconductor patterns SP1, SP2, and SP3 and the substrate 100 exposed by the first recess RS1 as seeds. As an example, the SEG process may include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

[0110] In an embodiment of the inventive concept, the first source / drain pattern SD1 may include a semiconductor element (e.g., SiGe) having a lattice constant greater than that of the semiconductor element of the substrate 100. While forming the first source / drain pattern SD1, impurities (e.g., boron, gallium, or indium) that make the first source / drain pattern SD1 p-type may be in-situ implanted. As another example, after forming the first source / drain pattern SD1, impurities may be implanted into the first source / drain pattern SD1.

[0111] The second source / drain pattern SD2 may be respectively formed in the second recess RS2. Specifically, a SEG process may be performed using the inner wall of the second recess RS2 as a seed layer to form the second source / drain pattern SD2.

[0112] In an embodiment of the inventive concept, the second source / drain pattern SD2 may include the same semiconductor element as the substrate 100 (e.g., Si). While forming the second source / drain pattern SD2, impurities (e.g., phosphorus, arsenic, or antimony) that make the second source / drain pattern SD2 n-type may be in-situ implanted. As another example, after forming the second source / drain pattern SD2, impurities may be implanted into the second source / drain pattern SD2.

[0113] Reference Figures 16A to 16C , a first interlayer insulating layer 110 may be formed to cover the first source / drain pattern SD1 and the second source / drain pattern SD2, the hard mask pattern MP, and the gate spacer GS. As an example, the first interlayer insulating layer 110 may include a silicon oxide layer.

[0114] The first interlayer insulating layer 110 may be planarized until the upper surface of the sacrificial pattern PP is exposed. The first interlayer insulating layer 110 may be planarized using an etch-back or a chemical mechanical polishing (CMP) process. During the planarization process, all of the hard mask pattern MP may be removed. Thus, the upper surface of the first interlayer insulating layer 110 may be coplanar with the upper surfaces of the sacrificial pattern PP and the gate spacer GS.

[0115] A region of the sacrificial pattern (PP) can be selectively opened using a lithography technique. For example, a region of the sacrificial pattern PP on the third boundary BD3 and the fourth boundary BD4 of the first single-height cell SHC1 can be selectively opened. The opened region of the sacrificial pattern PP can be removed by selective etching. A gate cut pattern CT can be formed by filling the space from which the sacrificial pattern PP has been removed with an insulating material.

[0116] The exposed sacrificial pattern PP can be selectively removed. The sacrificial pattern PP can be removed so that an external region ORG exposing the first channel pattern CH1 and the second channel pattern CH2 can be formed (see Figure 16C ). Removing the sacrificial pattern PP can include wet etching using an etchant that selectively etches polysilicon.

[0117] The sacrificial layer SAL exposed through the external region ORG can be selectively removed to form an internal region IRG (see Figure 16C ). Specifically, an etching process can be performed to selectively etch the sacrificial layer SAL, so that only the sacrificial layer SAL can be removed while keeping the first semiconductor pattern to the third semiconductor pattern SP1, SP2, and SP3 intact. The etching process can have a high etching rate for silicon germanium with a relatively high germanium concentration. For example, the etching process can have a high etching rate for silicon germanium with a germanium concentration greater than 10 at%.

[0118] During the etching process, the sacrificial layer SAL on the first active region AR1 and the second active region AR2 can be removed. The etching process can be wet etching. The etching material used in the etching process can quickly remove the sacrificial layer SAL with a relatively high germanium concentration.

[0119] Due to the selective removal of the sacrificial layer SAL, only the first semiconductor pattern to the third semiconductor pattern SP1, SP2, and SP3 stacked on the first active pattern AP1 and the second active pattern AP2 can be retained. The first internal region to the third internal region IRG1, IRG2, and IRG3 can be formed by removing the region of the sacrificial layer SAL.

[0120] Specifically, the first internal region IRG1 can be formed between the active pattern AP1 or AP2 and the first semiconductor pattern SP1, the second internal region IRG2 can be formed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, and the third internal region IRG3 can be formed between the second semiconductor pattern SP2 and the third semiconductor pattern SP3.

[0121] Refer to Figures 17A to 17C, a gate insulating layer GI can be conformally formed on the exposed first to third semiconductor patterns SP1, SP2, and SP3. The gate electrode GE can include first to third portions PO1, PO2, and PO3 respectively formed in first to third internal regions IRG1, IRG2, and IRG3, and a fourth region PO4 formed in the external region ORG. The gate electrode GE can be recessed to reduce its height. A gate capping pattern GP can be formed on the recessed gate electrode GE.

[0122] Referring again to Figure 10 and Figures 11A to 11D , a second interlayer insulating layer 120 can be formed on the first interlayer insulating layer 110. The second interlayer insulating layer 120 can include a silicon oxide layer. Active contacts AC can be formed through the second interlayer insulating layer 120 and the first interlayer insulating layer 110 and electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2. Gate contacts GC can be formed to penetrate the second interlayer insulating layer 120 and the gate capping pattern GP and electrically connected to the gate electrode GE.

[0123] Forming each of the active contacts AC and the gate contacts GC can include forming a barrier pattern BM and forming a conductive pattern FM on the barrier pattern BM. The barrier pattern BM can be conformally formed and can include a metal layer / metal nitride layer. The conductive pattern FM can include a low-resistance metal.

[0124] A pair of isolation structures DB can be formed on both sides of each of the first single-height cell SHC1 and the second single-height cell SHC2. The isolation structures DB can extend from the second interlayer insulating layer 120 through the gate electrode GE into the active patterns AP1 or AP2. The isolation structures DB can include an insulating material such as a silicon oxide layer or a silicon nitride layer.

[0125] A third interlayer insulating layer 130 can be formed on the active contacts AC and the gate contacts GC. A first metal layer M1 can be formed in the third interlayer insulating layer 130. A fourth interlayer insulating layer 140 can be formed on the third interlayer insulating layer 130. A second metal layer M2 can be formed in the fourth interlayer insulating layer 140.

[0126] Referring to Figures 18 to 25 , a semiconductor device and a method of manufacturing the same according to an embodiment of the inventive concept will be described in detail.

[0127] Figures 18 to 25 is a cross-sectional view for explaining a method of forming Figure 11D . Referring to Figures 18 to 25 , a method of forming the first metal layer M1 will be described in more detail. Forming the first metal layer M1 can include a photolithography process described with reference to Figures 2 to 9D .

[0128] Reference Figure 18 , a first anti-reflection pattern AF1 and a second anti-reflection pattern AF2 can be formed on the third interlayer insulating layer 130. The second anti-reflection pattern AF2 can be interposed between the third interlayer insulating layer 130 and the first anti-reflection pattern AF1. A photoresist pattern PR can be formed on the first anti-reflection pattern AF1. The photoresist pattern PR can be formed by a lithography process using extreme ultraviolet (EUV) as previously described in Figure 2 and Figure 3 . As another example, the line width of the photoresist pattern PR can be different.

[0129] Reference Figure 19 , a first polymer layer PMF1 can be formed on the photoresist pattern PR and the first anti-reflection pattern AF1. The first polymer layer PMF1 can be formed on the entire surface of the substrate 100. The first polymer layer PMF1 can cover the upper surface and sidewalls of the photoresist pattern PR. The first polymer layer PMF1 can cover the upper surface of the first anti-reflection pattern AF1 exposed by the photoresist pattern PR.

[0130] Reference Figure 20 , the first polymer layer PMF1 can be etched to form a first polymer pattern PM1 on the upper surface of the photoresist pattern PR. The line width of the first polymer pattern PM1 can be substantially the same as the line width of the photoresist pattern PR. The first polymer pattern PM1 can include a first upper surface UW1. As the first polymer layer PMF1 is etched, a second upper surface UW2 of the first anti-reflection pattern can be exposed.

[0131] Reference Figure 21 , a copolymer layer BCP can be formed on the entire surface of the substrate 100. Specifically, the copolymer layer BCP can cover the first upper surface UW1, the second upper surface UW2, and the sidewalls of the photoresist pattern PR. The copolymer layer BCP can include different first and second polymers.

[0132] Reference Figure 22 , an annealing process can be performed on the copolymer layer BCP to separate the copolymer layer BCP into a first extended pattern EP1 and a second extended pattern EP2. The first extended pattern EP1 can be formed by aligning the first polymer in the vertical direction D3. The second extended pattern EP2 can be formed by aligning the second polymer in the vertical direction D3.

[0133] For example, the first polymer of the first polymer pattern PM1 can be non-polar, and the second polymer can be polar. Thus, during the annealing process, the first polymer of the copolymer layer BCP can be aligned on the first upper surface UW1 of the first polymer pattern PM1, and the second polymer of the copolymer layer BCP can be aligned on the second upper surface UW2. The first upper surface UW1 can be more friendly to the first polymer than to the second polymer, resulting in the alignment of the first polymer. The second upper surface UW2 can be more friendly to the second polymer than to the first polymer, resulting in the alignment of the second polymer.

[0134] Reference Figure 23 , the second extension pattern EP2 can be selectively removed by performing an etching process. The etching process can have different etching rates for the first polymer and the second polymer. The second extension pattern EP2 can be removed and the upper surface of the first anti-reflection pattern AF1 can be exposed again.

[0135] Due to the formation of the first polymer pattern PM1 and the first extension pattern EP1 on the photoresist pattern PR, the first height HE1 of the photoresist pattern PR extends to the second height HE2. The first height HE1 can be the vertical height of the photoresist pattern PR. The second height HE2 can be the sum of the heights of the photoresist pattern, the first polymer pattern PM1, and the first extension pattern EP1.

[0136] Reference Figure 24 , the third interlayer insulating layer 130 can be patterned using the photoresist pattern PR and the first extension pattern EP1 as an etching mask. Through the patterning process, the upper portion of the third interlayer insulating layer 130 can be etched. According to an aspect of the inventive concept, since the first polymer pattern PM1 is formed on the photoresist pattern PR, the first extension pattern EP1 can be precisely aligned on the photoresist pattern PR. In addition, the DSA process can be performed on the photoresist pattern PR without a process of etching the photoresist pattern PR.

[0137] Reference Figure 25 , the first metal layer M1 can be formed by filling the etched third interlayer insulating layer 130 with a metal material. For example, the metal material can include at least one selected from aluminum, copper, tungsten, molybdenum, ruthenium, and cobalt. A via VI can be formed to vertically connect to the first metal layer M1 and the gate contact GC.

[0138] In a method of manufacturing a semiconductor device according to an aspect of the inventive concept, before performing a directed self-assembly (DSA) process, a polymer pattern may be formed on a photoresist pattern. By forming the polymer pattern, the DSA process may be performed on the photoresist pattern without etching the photoresist pattern. In addition, the photoresist pattern may include a metal oxide, thereby allowing a finer pattern to be implemented on a wafer. Accordingly, electrical characteristics and reliability of the semiconductor device according to the inventive concept may be improved.

[0139] Although embodiments have been described above, those skilled in the art will understand that many modifications and variations can be made without departing from the spirit and scope of the inventive concept defined in the appended claims. Accordingly, the exemplary embodiments of the inventive concept should be considered illustrative rather than restrictive in all respects, and the scope of the present invention is indicated by the appended claims.

Claims

1. A method of manufacturing a semiconductor device, the method comprising: forming a first anti-reflection pattern on a substrate; forming a photoresist pattern on the first anti-reflection pattern; forming a first polymer pattern on the photoresist pattern; forming a copolymer layer on the first anti-reflection pattern and the first polymer pattern; and performing an annealing process on the copolymer layer, wherein the copolymer layer includes a first polymer and a second polymer different from the first polymer, and wherein the first polymer pattern includes the first polymer.

2. The method according to claim 1, wherein The photoresist pattern includes a metal oxide.

3. The method according to claim 1, wherein The first polymer pattern includes a first upper surface, wherein the formation of the first polymer pattern includes: forming a first polymer layer on the first anti-reflection pattern and the photoresist pattern; and etching the first polymer layer to expose a second upper surface of the first anti-reflection pattern.

4. The method according to claim 3, wherein The annealing process includes: aligning the first polymer in a vertical direction on the first polymer pattern to form a first extension pattern; and aligning the second polymer in the vertical direction on the second upper surface to form a second extension pattern.

5. The method according to claim 3, wherein, The photoresist pattern is one of a plurality of photoresist patterns, and the method further includes: forming a second polymer layer on the first upper surface and the second upper surface; and etching the second polymer layer to form a second polymer pattern between adjacent photoresist patterns, wherein the second polymer pattern includes a third upper surface, and wherein the third upper surface is polar.

6. The method according to claim 5, wherein, The second polymer pattern includes the second polymer.

7. The method according to claim 1, wherein, One of the first polymer and the second polymer is polar and the other is non-polar.

8. The method according to claim 1, further comprising forming a second anti-reflection pattern between the substrate and the first anti-reflection pattern, Among them, wherein the second anti-reflection pattern includes a spin-on carbon (SOC) layer or an amorphous carbon layer.

9. The method according to claim 1, wherein, The photoresist pattern is one of a plurality of photoresist patterns, and further includes a first pitch, the first pitch being the pitch between adjacent photoresist patterns, wherein each photoresist pattern has a first line width, and wherein the sum of the first line width and the first pitch is 22 nm to 26 nm.

10. A method of manufacturing a semiconductor device, the method comprising: forming an anti-reflection pattern and a photoresist layer stacked in sequence on a substrate; irradiating the photoresist layer with extreme ultraviolet light to form a photoresist pattern; forming a first polymer pattern on the photoresist pattern; forming a copolymer layer covering a first material region on the first polymer pattern and a second material region on the anti-reflection pattern; and performing an annealing process on the copolymer layer, wherein one of the first material region and the second material region is polar and the other is non-polar.

11. The method according to claim 10, wherein, The photoresist pattern includes a metal oxide.

12. The method according to claim 10, wherein, The copolymer layer includes a first polymer and a second polymer different from each other, and wherein the first polymer pattern includes the first polymer.

13. The method according to claim 12, wherein, When irradiating the photoresist layer with extreme ultraviolet light to form a photoresist pattern, a plurality of photoresist patterns are formed, and the method further includes forming a second polymer pattern between adjacent photoresist patterns among the plurality of photoresist patterns, wherein the second polymer pattern includes the second polymer.

14. The method according to claim 13, wherein, The annealing process includes: Aligning the first polymer vertically on the first polymer pattern; and Aligning the second polymer vertically on the second polymer pattern.

15. The method according to claim 12, wherein, One of the first polymer and the second polymer is polar and the other is non-polar.

16. A method of manufacturing a semiconductor device, the method including: Forming a transistor on a substrate; And Forming a first wiring layer on the transistor, wherein the formation of the first wiring layer includes: Forming an interlayer insulating layer, a first anti-reflection pattern, and a photoresist pattern that are sequentially stacked on the transistor; Forming a first polymer pattern on the photoresist pattern; Forming a copolymer layer on the first anti-reflection pattern and the first polymer pattern, the copolymer layer including a first polymer and a second polymer that are different from each other; and Performing phase separation on the copolymer layer, wherein performing phase separation on the copolymer layer includes aligning the first polymer vertically on the first polymer pattern.

17. The method according to claim 16, wherein, The first polymer pattern includes the first polymer.

18. The method according to claim 16, wherein, One of the first polymer and the second polymer is polar and the other is non-polar.

19. The method according to claim 16, wherein, The photoresist pattern is one of a plurality of photoresist patterns, and the method further includes forming a second polymer pattern between the photoresist patterns, wherein the second polymer pattern includes the second polymer.

20. The method according to claim 16, wherein, The photoresist pattern is one of a plurality of photoresist patterns, and further includes a first pitch, the first pitch being the pitch between adjacent photoresist patterns, wherein each photoresist pattern has a first line width, and wherein the sum of the first line width and the first pitch is 22 nm to 26 nm.

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